51void AMDGPUInstPrinter::printU4ImmOperand(
const MCInst *
MI,
unsigned OpNo,
54 O <<
formatHex(
MI->getOperand(OpNo).getImm() & 0xf);
57void AMDGPUInstPrinter::printU16ImmOperand(
const MCInst *
MI,
unsigned OpNo,
62 int64_t Imm =
MI->getOperand(OpNo).getImm();
63 if (isInt<16>(Imm) || isUInt<16>(Imm))
64 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
66 printU32ImmOperand(
MI, OpNo, STI, O);
69void AMDGPUInstPrinter::printU4ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
74void AMDGPUInstPrinter::printU8ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
79void AMDGPUInstPrinter::printU16ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
84void AMDGPUInstPrinter::printU32ImmOperand(
const MCInst *
MI,
unsigned OpNo,
87 O <<
formatHex(
MI->getOperand(OpNo).getImm() & 0xffffffff);
90void AMDGPUInstPrinter::printNamedBit(
const MCInst *
MI,
unsigned OpNo,
92 if (
MI->getOperand(OpNo).getImm()) {
97void AMDGPUInstPrinter::printOffset(
const MCInst *
MI,
unsigned OpNo,
103 printU16ImmDecOperand(
MI, OpNo, O);
107void AMDGPUInstPrinter::printFlatOffset(
const MCInst *
MI,
unsigned OpNo,
115 bool IsFlatSeg = !(
Desc.TSFlags &
119 printU16ImmDecOperand(
MI, OpNo, O);
125void AMDGPUInstPrinter::printOffset0(
const MCInst *
MI,
unsigned OpNo,
128 if (
MI->getOperand(OpNo).getImm()) {
130 printU8ImmDecOperand(
MI, OpNo, O);
134void AMDGPUInstPrinter::printOffset1(
const MCInst *
MI,
unsigned OpNo,
137 if (
MI->getOperand(OpNo).getImm()) {
139 printU8ImmDecOperand(
MI, OpNo, O);
143void AMDGPUInstPrinter::printSMRDOffset8(
const MCInst *
MI,
unsigned OpNo,
146 printU32ImmOperand(
MI, OpNo, STI, O);
149void AMDGPUInstPrinter::printSMEMOffset(
const MCInst *
MI,
unsigned OpNo,
155void AMDGPUInstPrinter::printSMEMOffsetMod(
const MCInst *
MI,
unsigned OpNo,
159 printSMEMOffset(
MI, OpNo, STI, O);
162void AMDGPUInstPrinter::printSMRDLiteralOffset(
const MCInst *
MI,
unsigned OpNo,
165 printU32ImmOperand(
MI, OpNo, STI, O);
168void AMDGPUInstPrinter::printCPol(
const MCInst *
MI,
unsigned OpNo,
170 auto Imm =
MI->getOperand(OpNo).getImm();
182 O <<
" /* unexpected cache policy bit */";
185void AMDGPUInstPrinter::printDMask(
const MCInst *
MI,
unsigned OpNo,
187 if (
MI->getOperand(OpNo).getImm()) {
189 printU16ImmOperand(
MI, OpNo, STI, O);
193void AMDGPUInstPrinter::printDim(
const MCInst *
MI,
unsigned OpNo,
195 unsigned Dim =
MI->getOperand(OpNo).getImm();
196 O <<
" dim:SQ_RSRC_IMG_";
205void AMDGPUInstPrinter::printR128A16(
const MCInst *
MI,
unsigned OpNo,
208 printNamedBit(
MI, OpNo, O,
"a16");
210 printNamedBit(
MI, OpNo, O,
"r128");
213void AMDGPUInstPrinter::printFORMAT(
const MCInst *
MI,
unsigned OpNo,
218void AMDGPUInstPrinter::printSymbolicFormat(
const MCInst *
MI,
227 unsigned Val =
MI->getOperand(OpNo).getImm();
229 if (Val == UFMT_DEFAULT)
234 O <<
" format:" << Val;
237 if (Val == DFMT_NFMT_DEFAULT)
244 if (Dfmt != DFMT_DEFAULT) {
246 if (Nfmt != NFMT_DEFAULT) {
250 if (Nfmt != NFMT_DEFAULT) {
255 O <<
" format:" << Val;
266 case AMDGPU::PRIVATE_RSRC_REG:
278void AMDGPUInstPrinter::printVOPDst(
const MCInst *
MI,
unsigned OpNo,
280 auto Opcode =
MI->getOpcode();
298 printRegularOperand(
MI, OpNo, STI, O);
304 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
305 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
306 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
307 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
308 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
309 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
310 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
311 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
312 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
313 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
314 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
315 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
316 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
317 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
318 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
319 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
320 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
321 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
322 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
323 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
324 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
325 printDefaultVccOperand(
false, STI, O);
330void AMDGPUInstPrinter::printVINTRPDst(
const MCInst *
MI,
unsigned OpNo,
337 printRegularOperand(
MI, OpNo, STI, O);
340void AMDGPUInstPrinter::printImmediateInt16(
uint32_t Imm,
343 int16_t SImm =
static_cast<int16_t
>(
Imm);
352void AMDGPUInstPrinter::printImmediate16(
uint32_t Imm,
355 int16_t SImm =
static_cast<int16_t
>(
Imm);
363 else if (Imm == 0xBC00)
365 else if (Imm == 0x3800)
367 else if (Imm == 0xB800)
369 else if (Imm == 0x4000)
371 else if (Imm == 0xC000)
373 else if (Imm == 0x4400)
375 else if (Imm == 0xC400)
377 else if (Imm == 0x3118 &&
378 STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm)) {
386void AMDGPUInstPrinter::printImmediateV216(
uint32_t Imm,
390 printImmediate16(Lo16, STI, O);
393void AMDGPUInstPrinter::printImmediate32(
uint32_t Imm,
396 int32_t SImm =
static_cast<int32_t
>(
Imm);
397 if (SImm >= -16 && SImm <= 64) {
402 if (Imm == llvm::bit_cast<uint32_t>(0.0f))
404 else if (Imm == llvm::bit_cast<uint32_t>(1.0f))
406 else if (Imm == llvm::bit_cast<uint32_t>(-1.0f))
408 else if (Imm == llvm::bit_cast<uint32_t>(0.5f))
410 else if (Imm == llvm::bit_cast<uint32_t>(-0.5f))
412 else if (Imm == llvm::bit_cast<uint32_t>(2.0f))
414 else if (Imm == llvm::bit_cast<uint32_t>(-2.0f))
416 else if (Imm == llvm::bit_cast<uint32_t>(4.0f))
418 else if (Imm == llvm::bit_cast<uint32_t>(-4.0f))
420 else if (Imm == 0x3e22f983 &&
421 STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm))
424 O << formatHex(static_cast<uint64_t>(Imm));
427void AMDGPUInstPrinter::printImmediate64(
uint64_t Imm,
430 int64_t SImm =
static_cast<int64_t
>(
Imm);
431 if (SImm >= -16 && SImm <= 64) {
436 if (Imm == llvm::bit_cast<uint64_t>(0.0))
438 else if (Imm == llvm::bit_cast<uint64_t>(1.0))
440 else if (Imm == llvm::bit_cast<uint64_t>(-1.0))
442 else if (Imm == llvm::bit_cast<uint64_t>(0.5))
444 else if (Imm == llvm::bit_cast<uint64_t>(-0.5))
446 else if (Imm == llvm::bit_cast<uint64_t>(2.0))
448 else if (Imm == llvm::bit_cast<uint64_t>(-2.0))
450 else if (Imm == llvm::bit_cast<uint64_t>(4.0))
452 else if (Imm == llvm::bit_cast<uint64_t>(-4.0))
454 else if (Imm == 0x3fc45f306dc9c882 &&
455 STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm))
456 O <<
"0.15915494309189532";
458 assert(isUInt<32>(Imm) || isInt<32>(Imm));
462 O << formatHex(static_cast<uint64_t>(Imm));
466void AMDGPUInstPrinter::printBLGP(
const MCInst *
MI,
unsigned OpNo,
469 unsigned Imm =
MI->getOperand(OpNo).getImm();
474 switch (
MI->getOpcode()) {
475 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
476 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
477 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
478 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
479 O <<
" neg:[" << (
Imm & 1) <<
',' << ((Imm >> 1) & 1) <<
','
480 << ((Imm >> 2) & 1) <<
']';
485 O <<
" blgp:" <<
Imm;
488void AMDGPUInstPrinter::printCBSZ(
const MCInst *
MI,
unsigned OpNo,
491 unsigned Imm =
MI->getOperand(OpNo).getImm();
495 O <<
" cbsz:" <<
Imm;
498void AMDGPUInstPrinter::printABID(
const MCInst *
MI,
unsigned OpNo,
501 unsigned Imm =
MI->getOperand(OpNo).getImm();
505 O <<
" abid:" <<
Imm;
508void AMDGPUInstPrinter::printDefaultVccOperand(
bool FirstOperand,
521void AMDGPUInstPrinter::printWaitVDST(
const MCInst *
MI,
unsigned OpNo,
525 printU4ImmDecOperand(
MI, OpNo, O);
528void AMDGPUInstPrinter::printWaitEXP(
const MCInst *
MI,
unsigned OpNo,
532 printU4ImmDecOperand(
MI, OpNo, O);
536 unsigned OpNo)
const {
539 (
Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
540 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO));
544void AMDGPUInstPrinter::printOperand(
const MCInst *
MI,
unsigned OpNo,
547 unsigned Opc =
MI->getOpcode();
556 (
Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
557 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
558 printDefaultVccOperand(
true, STI, O);
560 printRegularOperand(
MI, OpNo, STI, O);
564void AMDGPUInstPrinter::printRegularOperand(
const MCInst *
MI,
unsigned OpNo,
569 if (OpNo >=
MI->getNumOperands()) {
570 O <<
"/*Missing OP" << OpNo <<
"*/";
581 int RCID =
Desc.operands()[OpNo].RegClass;
587 <<
"\' register class*/";
590 }
else if (
Op.isImm()) {
591 const uint8_t OpTy =
Desc.operands()[OpNo].OperandType;
605 printImmediate32(
Op.getImm(), STI, O);
612 printImmediate64(
Op.getImm(), STI, O);
617 printImmediateInt16(
Op.getImm(), STI, O);
623 printImmediate16(
Op.getImm(), STI, O);
627 if (!isUInt<16>(
Op.getImm()) &&
629 printImmediate32(
Op.getImm(), STI, O);
635 printImmediate16(
static_cast<uint16_t>(
Op.getImm()), STI, O);
641 printImmediateInt16(
static_cast<uint16_t>(
Op.getImm()), STI, O);
645 printImmediateV216(
Op.getImm(), STI, O);
654 printImmediate32(
Op.getImm(), STI, O);
655 O <<
"/*Invalid immediate*/";
662 }
else if (
Op.isDFPImm()) {
663 double Value = bit_cast<double>(
Op.getDFPImm());
669 int RCID =
Desc.operands()[OpNo].RegClass;
672 printImmediate32(llvm::bit_cast<uint32_t>((
float)
Value), STI, O);
673 else if (RCBits == 64)
674 printImmediate64(llvm::bit_cast<uint64_t>(
Value), STI, O);
678 }
else if (
Op.isExpr()) {
686 switch (
MI->getOpcode()) {
689 case AMDGPU::V_CNDMASK_B32_e32_gfx10:
690 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
691 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
692 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
693 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
694 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
695 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
696 case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
697 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
698 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
699 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
700 case AMDGPU::V_CNDMASK_B32_e32_gfx11:
701 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
702 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
703 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
704 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
705 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
706 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
707 case AMDGPU::V_CNDMASK_B32_dpp8_gfx11:
708 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
709 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
710 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
712 case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
713 case AMDGPU::V_CNDMASK_B32_e32_vi:
715 AMDGPU::OpName::src1))
716 printDefaultVccOperand(OpNo == 0, STI, O);
724 if ((
int)OpNo == SOffsetIdx)
725 printSymbolicFormat(
MI, STI, O);
729void AMDGPUInstPrinter::printOperandAndFPInputMods(
const MCInst *
MI,
734 if (needsImpliedVcc(
Desc, OpNo))
735 printDefaultVccOperand(
true, STI, O);
737 unsigned InputModifiers =
MI->getOperand(OpNo).getImm();
742 bool NegMnemo =
false;
745 if (OpNo + 1 <
MI->getNumOperands() &&
748 NegMnemo =
Op.isImm() ||
Op.isDFPImm();
759 printRegularOperand(
MI, OpNo + 1, STI, O);
768 switch (
MI->getOpcode()) {
772 case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
773 case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
774 case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
777 printDefaultVccOperand(OpNo == 0, STI, O);
782void AMDGPUInstPrinter::printOperandAndIntInputMods(
const MCInst *
MI,
787 if (needsImpliedVcc(
Desc, OpNo))
788 printDefaultVccOperand(
true, STI, O);
790 unsigned InputModifiers =
MI->getOperand(OpNo).getImm();
793 printRegularOperand(
MI, OpNo + 1, STI, O);
798 switch (
MI->getOpcode()) {
801 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
802 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
803 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
805 AMDGPU::OpName::src1))
806 printDefaultVccOperand(OpNo == 0, STI, O);
811void AMDGPUInstPrinter::printDPP8(
const MCInst *
MI,
unsigned OpNo,
817 unsigned Imm =
MI->getOperand(OpNo).getImm();
819 for (
size_t i = 1; i < 8; ++i) {
820 O <<
',' <<
formatDec((Imm >> (3 * i)) & 0x7);
825void AMDGPUInstPrinter::printDPPCtrl(
const MCInst *
MI,
unsigned OpNo,
828 using namespace AMDGPU::DPP;
830 unsigned Imm =
MI->getOperand(OpNo).getImm();
834 O <<
" /* DP ALU dpp only supports row_newbcast */";
836 }
else if (Imm <= DppCtrl::QUAD_PERM_LAST) {
842 }
else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
843 (Imm <= DppCtrl::ROW_SHL_LAST)) {
845 printU4ImmDecOperand(
MI, OpNo, O);
846 }
else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
847 (Imm <= DppCtrl::ROW_SHR_LAST)) {
849 printU4ImmDecOperand(
MI, OpNo, O);
850 }
else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
851 (Imm <= DppCtrl::ROW_ROR_LAST)) {
853 printU4ImmDecOperand(
MI, OpNo, O);
854 }
else if (Imm == DppCtrl::WAVE_SHL1) {
856 O <<
"/* wave_shl is not supported starting from GFX10 */";
860 }
else if (Imm == DppCtrl::WAVE_ROL1) {
862 O <<
"/* wave_rol is not supported starting from GFX10 */";
866 }
else if (Imm == DppCtrl::WAVE_SHR1) {
868 O <<
"/* wave_shr is not supported starting from GFX10 */";
872 }
else if (Imm == DppCtrl::WAVE_ROR1) {
874 O <<
"/* wave_ror is not supported starting from GFX10 */";
878 }
else if (Imm == DppCtrl::ROW_MIRROR) {
880 }
else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
881 O <<
"row_half_mirror";
882 }
else if (Imm == DppCtrl::BCAST15) {
884 O <<
"/* row_bcast is not supported starting from GFX10 */";
888 }
else if (Imm == DppCtrl::BCAST31) {
890 O <<
"/* row_bcast is not supported starting from GFX10 */";
894 }
else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
895 (Imm <= DppCtrl::ROW_SHARE_LAST)) {
897 O <<
"row_newbcast:";
901 O <<
" /* row_newbcast/row_share is not supported on ASICs earlier "
902 "than GFX90A/GFX10 */";
905 printU4ImmDecOperand(
MI, OpNo, O);
906 }
else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
907 (Imm <= DppCtrl::ROW_XMASK_LAST)) {
909 O <<
"/* row_xmask is not supported on ASICs earlier than GFX10 */";
913 printU4ImmDecOperand(
MI, OpNo, O);
915 O <<
"/* Invalid dpp_ctrl value */";
919void AMDGPUInstPrinter::printDppRowMask(
const MCInst *
MI,
unsigned OpNo,
923 printU4ImmOperand(
MI, OpNo, STI, O);
926void AMDGPUInstPrinter::printDppBankMask(
const MCInst *
MI,
unsigned OpNo,
930 printU4ImmOperand(
MI, OpNo, STI, O);
933void AMDGPUInstPrinter::printDppBoundCtrl(
const MCInst *
MI,
unsigned OpNo,
936 unsigned Imm =
MI->getOperand(OpNo).getImm();
938 O <<
" bound_ctrl:1";
942void AMDGPUInstPrinter::printDppFI(
const MCInst *
MI,
unsigned OpNo,
945 unsigned Imm =
MI->getOperand(OpNo).getImm();
946 if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
951void AMDGPUInstPrinter::printSDWASel(
const MCInst *
MI,
unsigned OpNo,
955 unsigned Imm =
MI->getOperand(OpNo).getImm();
957 case SdwaSel::BYTE_0:
O <<
"BYTE_0";
break;
958 case SdwaSel::BYTE_1:
O <<
"BYTE_1";
break;
959 case SdwaSel::BYTE_2:
O <<
"BYTE_2";
break;
960 case SdwaSel::BYTE_3:
O <<
"BYTE_3";
break;
961 case SdwaSel::WORD_0:
O <<
"WORD_0";
break;
962 case SdwaSel::WORD_1:
O <<
"WORD_1";
break;
963 case SdwaSel::DWORD:
O <<
"DWORD";
break;
968void AMDGPUInstPrinter::printSDWADstSel(
const MCInst *
MI,
unsigned OpNo,
972 printSDWASel(
MI, OpNo, O);
975void AMDGPUInstPrinter::printSDWASrc0Sel(
const MCInst *
MI,
unsigned OpNo,
979 printSDWASel(
MI, OpNo, O);
982void AMDGPUInstPrinter::printSDWASrc1Sel(
const MCInst *
MI,
unsigned OpNo,
986 printSDWASel(
MI, OpNo, O);
989void AMDGPUInstPrinter::printSDWADstUnused(
const MCInst *
MI,
unsigned OpNo,
995 unsigned Imm =
MI->getOperand(OpNo).getImm();
997 case DstUnused::UNUSED_PAD:
O <<
"UNUSED_PAD";
break;
998 case DstUnused::UNUSED_SEXT:
O <<
"UNUSED_SEXT";
break;
999 case DstUnused::UNUSED_PRESERVE:
O <<
"UNUSED_PRESERVE";
break;
1004void AMDGPUInstPrinter::printExpSrcN(
const MCInst *
MI,
unsigned OpNo,
1007 unsigned Opc =
MI->getOpcode();
1009 unsigned En =
MI->getOperand(EnIdx).getImm();
1014 if (
MI->getOperand(ComprIdx).getImm())
1015 OpNo = OpNo -
N +
N / 2;
1023void AMDGPUInstPrinter::printExpSrc0(
const MCInst *
MI,
unsigned OpNo,
1026 printExpSrcN(
MI, OpNo, STI, O, 0);
1029void AMDGPUInstPrinter::printExpSrc1(
const MCInst *
MI,
unsigned OpNo,
1032 printExpSrcN(
MI, OpNo, STI, O, 1);
1035void AMDGPUInstPrinter::printExpSrc2(
const MCInst *
MI,
unsigned OpNo,
1038 printExpSrcN(
MI, OpNo, STI, O, 2);
1041void AMDGPUInstPrinter::printExpSrc3(
const MCInst *
MI,
unsigned OpNo,
1044 printExpSrcN(
MI, OpNo, STI, O, 3);
1047void AMDGPUInstPrinter::printExpTgt(
const MCInst *
MI,
unsigned OpNo,
1053 unsigned Id =
MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1058 O <<
' ' << TgtName;
1062 O <<
" invalid_target_" <<
Id;
1067 bool IsPacked,
bool HasDstSel) {
1070 for (
int I = 0;
I < NumOps; ++
I) {
1071 if (!!(Ops[
I] &
Mod) != DefaultValue)
1081void AMDGPUInstPrinter::printPackedModifier(
const MCInst *
MI,
1085 unsigned Opc =
MI->getOpcode();
1089 for (
int OpName : { AMDGPU::OpName::src0_modifiers,
1090 AMDGPU::OpName::src1_modifiers,
1091 AMDGPU::OpName::src2_modifiers }) {
1096 Ops[NumOps++] =
MI->getOperand(
Idx).getImm();
1099 const bool HasDstSel =
1111 for (
int I = 0;
I < NumOps; ++
I) {
1115 O << !!(Ops[
I] &
Mod);
1125void AMDGPUInstPrinter::printOpSel(
const MCInst *
MI,
unsigned,
1128 unsigned Opc =
MI->getOpcode();
1135 O <<
" op_sel:[" << FI <<
',' << BC <<
']';
1142void AMDGPUInstPrinter::printOpSelHi(
const MCInst *
MI,
unsigned OpNo,
1148void AMDGPUInstPrinter::printNegLo(
const MCInst *
MI,
unsigned OpNo,
1154void AMDGPUInstPrinter::printNegHi(
const MCInst *
MI,
unsigned OpNo,
1160void AMDGPUInstPrinter::printInterpSlot(
const MCInst *
MI,
unsigned OpNum,
1163 unsigned Imm =
MI->getOperand(OpNum).getImm();
1175 O <<
"invalid_param_" <<
Imm;
1179void AMDGPUInstPrinter::printInterpAttr(
const MCInst *
MI,
unsigned OpNum,
1182 unsigned Attr =
MI->getOperand(OpNum).getImm();
1183 O <<
"attr" << Attr;
1186void AMDGPUInstPrinter::printInterpAttrChan(
const MCInst *
MI,
unsigned OpNum,
1189 unsigned Chan =
MI->getOperand(OpNum).getImm();
1190 O <<
'.' <<
"xyzw"[Chan & 0x3];
1193void AMDGPUInstPrinter::printGPRIdxMode(
const MCInst *
MI,
unsigned OpNo,
1197 unsigned Val =
MI->getOperand(OpNo).getImm();
1199 if ((Val & ~ENABLE_MASK) != 0) {
1200 O << formatHex(static_cast<uint64_t>(Val));
1203 bool NeedComma =
false;
1204 for (
unsigned ModeId = ID_MIN; ModeId <=
ID_MAX; ++ModeId) {
1205 if (Val & (1 << ModeId)) {
1216void AMDGPUInstPrinter::printMemOperand(
const MCInst *
MI,
unsigned OpNo,
1219 printRegularOperand(
MI, OpNo, STI, O);
1221 printRegularOperand(
MI, OpNo + 1, STI, O);
1229 if (
Op.getImm() == 1) {
1240 if (
Op.getImm() == 1)
1247 int Imm =
MI->getOperand(OpNo).getImm();
1261 const unsigned Imm16 =
MI->getOperand(OpNo).getImm();
1266 decodeMsg(Imm16, MsgId, OpId,
StreamId, STI);
1268 StringRef MsgName = getMsgName(MsgId, STI);
1270 if (!MsgName.
empty() && isValidMsgOp(MsgId, OpId, STI) &&
1271 isValidMsgStream(MsgId, OpId,
StreamId, STI)) {
1272 O <<
"sendmsg(" << MsgName;
1273 if (msgRequiresOp(MsgId, STI)) {
1274 O <<
", " << getMsgOpName(MsgId, OpId, STI);
1275 if (msgSupportsStream(MsgId, OpId, STI)) {
1280 }
else if (encodeMsg(MsgId, OpId,
StreamId) == Imm16) {
1281 O <<
"sendmsg(" << MsgId <<
", " << OpId <<
", " <<
StreamId <<
')';
1293 uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask;
1294 uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1298 for (
unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1325 uint16_t Imm =
MI->getOperand(OpNo).getImm();
1332 if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1334 O <<
"swizzle(" << IdSymbolic[ID_QUAD_PERM];
1335 for (
unsigned I = 0;
I < LANE_NUM; ++
I) {
1342 }
else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1344 uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1345 uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK;
1346 uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1348 if (AndMask == BITMASK_MAX && OrMask == 0 &&
llvm::popcount(XorMask) == 1) {
1350 O <<
"swizzle(" << IdSymbolic[ID_SWAP];
1355 }
else if (AndMask == BITMASK_MAX && OrMask == 0 && XorMask > 0 &&
1358 O <<
"swizzle(" << IdSymbolic[ID_REVERSE];
1365 uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1366 if (GroupSize > 1 &&
1368 OrMask < GroupSize &&
1371 O <<
"swizzle(" << IdSymbolic[ID_BROADCAST];
1379 O <<
"swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1386 printU16ImmDecOperand(
MI, OpNo, O);
1395 unsigned SImm16 =
MI->getOperand(OpNo).getImm();
1396 unsigned Vmcnt, Expcnt, Lgkmcnt;
1402 bool PrintAll = IsDefaultVmcnt && IsDefaultExpcnt && IsDefaultLgkmcnt;
1404 bool NeedSpace =
false;
1406 if (!IsDefaultVmcnt || PrintAll) {
1407 O <<
"vmcnt(" << Vmcnt <<
')';
1411 if (!IsDefaultExpcnt || PrintAll) {
1414 O <<
"expcnt(" << Expcnt <<
')';
1418 if (!IsDefaultLgkmcnt || PrintAll) {
1421 O <<
"lgkmcnt(" << Lgkmcnt <<
')';
1430 uint64_t Imm16 =
MI->getOperand(OpNo).getImm() & 0xffff;
1432 bool HasNonDefaultVal =
false;
1433 if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) {
1438 bool NeedSpace =
false;
1439 while (decodeDepCtr(Imm16,
Id,
Name, Val, IsDefault, STI)) {
1440 if (!IsDefault || !HasNonDefaultVal) {
1443 O <<
Name <<
'(' << Val <<
')';
1455 const char *BadInstId =
"/* invalid instid value */";
1456 static const std::array<const char *, 12> InstIds = {
1457 "NO_DEP",
"VALU_DEP_1",
"VALU_DEP_2",
1458 "VALU_DEP_3",
"VALU_DEP_4",
"TRANS32_DEP_1",
1459 "TRANS32_DEP_2",
"TRANS32_DEP_3",
"FMA_ACCUM_CYCLE_1",
1460 "SALU_CYCLE_1",
"SALU_CYCLE_2",
"SALU_CYCLE_3"};
1462 const char *BadInstSkip =
"/* invalid instskip value */";
1463 static const std::array<const char *, 6> InstSkips = {
1464 "SAME",
"NEXT",
"SKIP_1",
"SKIP_2",
"SKIP_3",
"SKIP_4"};
1466 unsigned SImm16 =
MI->getOperand(OpNo).getImm();
1467 const char *Prefix =
"";
1469 unsigned Value = SImm16 & 0xF;
1471 const char *
Name =
Value < InstIds.size() ? InstIds[
Value] : BadInstId;
1472 O << Prefix <<
"instid0(" <<
Name <<
')';
1476 Value = (SImm16 >> 4) & 7;
1479 Value < InstSkips.size() ? InstSkips[
Value] : BadInstSkip;
1480 O << Prefix <<
"instskip(" <<
Name <<
')';
1484 Value = (SImm16 >> 7) & 0xF;
1486 const char *
Name =
Value < InstIds.size() ? InstIds[
Value] : BadInstId;
1487 O << Prefix <<
"instid1(" <<
Name <<
')';
1502 unsigned Val =
MI->getOperand(OpNo).getImm();
1507 if (!HwRegName.
empty()) {
1512 if (
Width != WIDTH_DEFAULT_ ||
Offset != OFFSET_DEFAULT_) {
1521 uint16_t Imm =
MI->getOperand(OpNo).getImm();
1529#include "AMDGPUGenAsmWriter.inc"
unsigned const MachineRegisterInfo * MRI
static void printSwizzleBitmask(const uint16_t AndMask, const uint16_t OrMask, const uint16_t XorMask, raw_ostream &O)
static bool allOpsDefaultValue(const int *Ops, int NumOps, int Mod, bool IsPacked, bool HasDstSel)
Provides AMDGPU specific target descriptions.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printEndpgm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getRegisterName(MCRegister Reg)
static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, StringRef Asm, StringRef Default="")
void printDepCtr(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printSendMsg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, MCRegister Reg) const override
Print the assembler register name.
static void printRegOperand(unsigned RegNo, raw_ostream &O, const MCRegisterInfo &MRI)
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printSWaitCnt(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printOModSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printSDelayALU(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
This class represents an Operation in the Expression.
Base class for the full range of assembler expressions which are needed for parsing.
format_object< int64_t > formatHex(int64_t Value) const
format_object< int64_t > formatDec(int64_t Value) const
Utility functions to print decimal/hexadecimal values.
const MCRegisterInfo & MRI
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
MCRegisterClass - Base class of TargetRegisterClass.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const char * getRegClassName(const MCRegisterClass *Class) const
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
const char *const IdSymbolic[]
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
LLVM_READNONE bool isLegalDPALU_DPPControl(unsigned DC)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool isGFX940(const MCSubtargetInfo &STI)
IsaVersion getIsaVersion(StringRef GPU)
bool isDPALU_DPP(const MCInstrDesc &OpDesc)
bool isSI(const MCSubtargetInfo &STI)
bool getVOP3IsSingle(unsigned Opc)
bool getVOP1IsSingle(unsigned Opc)
bool isGFX90A(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
unsigned getVmcntBitMask(const IsaVersion &Version)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool isInlineValue(unsigned Reg)
bool isGFX10Plus(const MCSubtargetInfo &STI)
@ OPERAND_REG_INLINE_C_V2INT32
@ OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
@ OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
@ OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
bool isCI(const MCSubtargetInfo &STI)
bool getVOP2IsSingle(unsigned Opc)
bool isPermlane16(unsigned Opc)
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
int popcount(T Value) noexcept
Count the number of set bits in a value.
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
@ Mod
The access may modify the value stored in memory.
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
@ Default
The result values are uniform if and only if all operands are uniform.
Instruction set architecture version.
Description of the encoding of one expression Op.