28 "amdgpu-keep-16-bit-reg-suffixes",
29 cl::desc(
"Keep .l and .h suffixes in asm for debugging purposes"),
57void AMDGPUInstPrinter::printU4ImmOperand(
const MCInst *
MI,
unsigned OpNo,
60 O <<
formatHex(
MI->getOperand(OpNo).getImm() & 0xf);
63void AMDGPUInstPrinter::printU8ImmOperand(
const MCInst *
MI,
unsigned OpNo,
65 O <<
formatHex(
MI->getOperand(OpNo).getImm() & 0xff);
68void AMDGPUInstPrinter::printU16ImmOperand(
const MCInst *
MI,
unsigned OpNo,
73 int64_t
Imm =
MI->getOperand(OpNo).getImm();
74 if (isInt<16>(Imm) || isUInt<16>(Imm))
75 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
77 printU32ImmOperand(
MI, OpNo, STI, O);
80void AMDGPUInstPrinter::printU4ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
85void AMDGPUInstPrinter::printU8ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
90void AMDGPUInstPrinter::printU16ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
95void AMDGPUInstPrinter::printU32ImmOperand(
const MCInst *
MI,
unsigned OpNo,
98 O <<
formatHex(
MI->getOperand(OpNo).getImm() & 0xffffffff);
101void AMDGPUInstPrinter::printNamedBit(
const MCInst *
MI,
unsigned OpNo,
103 if (
MI->getOperand(OpNo).getImm()) {
108void AMDGPUInstPrinter::printOffen(
const MCInst *
MI,
unsigned OpNo,
110 printNamedBit(
MI, OpNo, O,
"offen");
113void AMDGPUInstPrinter::printIdxen(
const MCInst *
MI,
unsigned OpNo,
115 printNamedBit(
MI, OpNo, O,
"idxen");
118void AMDGPUInstPrinter::printAddr64(
const MCInst *
MI,
unsigned OpNo,
120 printNamedBit(
MI, OpNo, O,
"addr64");
123void AMDGPUInstPrinter::printOffset(
const MCInst *
MI,
unsigned OpNo,
129 printU16ImmDecOperand(
MI, OpNo, O);
133void AMDGPUInstPrinter::printFlatOffset(
const MCInst *
MI,
unsigned OpNo,
141 bool IsFlatSeg = !(Desc.
TSFlags &
145 printU16ImmDecOperand(
MI, OpNo, O);
151void AMDGPUInstPrinter::printOffset0(
const MCInst *
MI,
unsigned OpNo,
154 if (
MI->getOperand(OpNo).getImm()) {
156 printU8ImmDecOperand(
MI, OpNo, O);
160void AMDGPUInstPrinter::printOffset1(
const MCInst *
MI,
unsigned OpNo,
163 if (
MI->getOperand(OpNo).getImm()) {
165 printU8ImmDecOperand(
MI, OpNo, O);
169void AMDGPUInstPrinter::printSMRDOffset8(
const MCInst *
MI,
unsigned OpNo,
172 printU32ImmOperand(
MI, OpNo, STI, O);
175void AMDGPUInstPrinter::printSMEMOffset(
const MCInst *
MI,
unsigned OpNo,
181void AMDGPUInstPrinter::printSMEMOffsetMod(
const MCInst *
MI,
unsigned OpNo,
185 printSMEMOffset(
MI, OpNo, STI, O);
188void AMDGPUInstPrinter::printSMRDLiteralOffset(
const MCInst *
MI,
unsigned OpNo,
191 printU32ImmOperand(
MI, OpNo, STI, O);
194void AMDGPUInstPrinter::printGDS(
const MCInst *
MI,
unsigned OpNo,
196 printNamedBit(
MI, OpNo, O,
"gds");
199void AMDGPUInstPrinter::printCPol(
const MCInst *
MI,
unsigned OpNo,
201 auto Imm =
MI->getOperand(OpNo).getImm();
213 O <<
" /* unexpected cache policy bit */";
216void AMDGPUInstPrinter::printSWZ(
const MCInst *
MI,
unsigned OpNo,
220void AMDGPUInstPrinter::printTFE(
const MCInst *
MI,
unsigned OpNo,
222 printNamedBit(
MI, OpNo, O,
"tfe");
225void AMDGPUInstPrinter::printDMask(
const MCInst *
MI,
unsigned OpNo,
227 if (
MI->getOperand(OpNo).getImm()) {
229 printU16ImmOperand(
MI, OpNo, STI, O);
233void AMDGPUInstPrinter::printDim(
const MCInst *
MI,
unsigned OpNo,
235 unsigned Dim =
MI->getOperand(OpNo).getImm();
236 O <<
" dim:SQ_RSRC_IMG_";
245void AMDGPUInstPrinter::printUNorm(
const MCInst *
MI,
unsigned OpNo,
247 printNamedBit(
MI, OpNo, O,
"unorm");
250void AMDGPUInstPrinter::printDA(
const MCInst *
MI,
unsigned OpNo,
252 printNamedBit(
MI, OpNo, O,
"da");
255void AMDGPUInstPrinter::printR128A16(
const MCInst *
MI,
unsigned OpNo,
258 printNamedBit(
MI, OpNo, O,
"a16");
260 printNamedBit(
MI, OpNo, O,
"r128");
263void AMDGPUInstPrinter::printA16(
const MCInst *
MI,
unsigned OpNo,
265 printNamedBit(
MI, OpNo, O,
"a16");
268void AMDGPUInstPrinter::printLWE(
const MCInst *
MI,
unsigned OpNo,
270 printNamedBit(
MI, OpNo, O,
"lwe");
273void AMDGPUInstPrinter::printD16(
const MCInst *
MI,
unsigned OpNo,
275 printNamedBit(
MI, OpNo, O,
"d16");
278void AMDGPUInstPrinter::printExpCompr(
const MCInst *
MI,
unsigned OpNo,
281 printNamedBit(
MI, OpNo, O,
"compr");
284void AMDGPUInstPrinter::printExpVM(
const MCInst *
MI,
unsigned OpNo,
287 printNamedBit(
MI, OpNo, O,
"vm");
290void AMDGPUInstPrinter::printFORMAT(
const MCInst *
MI,
unsigned OpNo,
295void AMDGPUInstPrinter::printSymbolicFormat(
const MCInst *
MI,
304 unsigned Val =
MI->getOperand(OpNo).getImm();
306 if (Val == UFMT_DEFAULT)
311 O <<
" format:" << Val;
314 if (Val == DFMT_NFMT_DEFAULT)
321 if (Dfmt != DFMT_DEFAULT) {
323 if (Nfmt != NFMT_DEFAULT) {
327 if (Nfmt != NFMT_DEFAULT) {
332 O <<
" format:" << Val;
343 case AMDGPU::PRIVATE_RSRC_REG:
354 if (!
RegName.consume_back(
".l"))
360void AMDGPUInstPrinter::printVOPDst(
const MCInst *
MI,
unsigned OpNo,
362 auto Opcode =
MI->getOpcode();
380 printRegularOperand(
MI, OpNo, STI, O);
386 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
387 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
388 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
389 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
390 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
391 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
392 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
393 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
394 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
395 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
396 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
397 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
398 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
399 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
400 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
401 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
402 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
403 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
404 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
405 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
406 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
407 printDefaultVccOperand(
false, STI, O);
412void AMDGPUInstPrinter::printVINTRPDst(
const MCInst *
MI,
unsigned OpNo,
419 printRegularOperand(
MI, OpNo, STI, O);
422void AMDGPUInstPrinter::printImmediateInt16(
uint32_t Imm,
425 int16_t SImm =
static_cast<int16_t
>(
Imm);
434void AMDGPUInstPrinter::printImmediate16(
uint32_t Imm,
437 int16_t SImm =
static_cast<int16_t
>(
Imm);
445 else if (Imm == 0xBC00)
447 else if (Imm == 0x3800)
449 else if (Imm == 0xB800)
451 else if (Imm == 0x4000)
453 else if (Imm == 0xC000)
455 else if (Imm == 0x4400)
457 else if (Imm == 0xC400)
459 else if (Imm == 0x3118 &&
468void AMDGPUInstPrinter::printImmediateV216(
uint32_t Imm,
472 printImmediate16(Lo16, STI, O);
475void AMDGPUInstPrinter::printImmediate32(
uint32_t Imm,
478 int32_t SImm =
static_cast<int32_t
>(
Imm);
479 if (SImm >= -16 && SImm <= 64) {
502 else if (Imm == 0x3e22f983 &&
506 O << formatHex(static_cast<uint64_t>(Imm));
509void AMDGPUInstPrinter::printImmediate64(
uint64_t Imm,
512 int64_t SImm =
static_cast<int64_t
>(
Imm);
513 if (SImm >= -16 && SImm <= 64) {
536 else if (Imm == 0x3fc45f306dc9c882 &&
538 O <<
"0.15915494309189532";
540 assert(isUInt<32>(Imm) || isInt<32>(Imm));
544 O << formatHex(static_cast<uint64_t>(Imm));
548void AMDGPUInstPrinter::printBLGP(
const MCInst *
MI,
unsigned OpNo,
551 unsigned Imm =
MI->getOperand(OpNo).getImm();
556 switch (
MI->getOpcode()) {
557 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
558 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
559 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
560 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
561 O <<
" neg:[" << (
Imm & 1) <<
',' << ((Imm >> 1) & 1) <<
','
562 << ((Imm >> 2) & 1) <<
']';
567 O <<
" blgp:" <<
Imm;
570void AMDGPUInstPrinter::printCBSZ(
const MCInst *
MI,
unsigned OpNo,
573 unsigned Imm =
MI->getOperand(OpNo).getImm();
577 O <<
" cbsz:" <<
Imm;
580void AMDGPUInstPrinter::printABID(
const MCInst *
MI,
unsigned OpNo,
583 unsigned Imm =
MI->getOperand(OpNo).getImm();
587 O <<
" abid:" <<
Imm;
590void AMDGPUInstPrinter::printDefaultVccOperand(
bool FirstOperand,
603void AMDGPUInstPrinter::printWaitVDST(
const MCInst *
MI,
unsigned OpNo,
606 uint8_t
Imm =
MI->getOperand(OpNo).getImm();
609 printU4ImmDecOperand(
MI, OpNo, O);
613void AMDGPUInstPrinter::printWaitEXP(
const MCInst *
MI,
unsigned OpNo,
616 uint8_t
Imm =
MI->getOperand(OpNo).getImm();
619 printU4ImmDecOperand(
MI, OpNo, O);
623bool AMDGPUInstPrinter::needsImpliedVcc(
const MCInstrDesc &Desc,
624 unsigned OpNo)
const {
632void AMDGPUInstPrinter::printOperand(
const MCInst *
MI,
unsigned OpNo,
635 unsigned Opc =
MI->getOpcode();
646 printDefaultVccOperand(
true, STI, O);
648 printRegularOperand(
MI, OpNo, STI, O);
652void AMDGPUInstPrinter::printRegularOperand(
const MCInst *
MI,
unsigned OpNo,
657 if (OpNo >=
MI->getNumOperands()) {
658 O <<
"/*Missing OP" << OpNo <<
"*/";
669 int RCID = Desc.
operands()[OpNo].RegClass;
675 <<
"\' register class*/";
678 }
else if (
Op.isImm()) {
679 const uint8_t OpTy = Desc.
operands()[OpNo].OperandType;
693 printImmediate32(
Op.getImm(), STI, O);
700 printImmediate64(
Op.getImm(), STI, O);
705 printImmediateInt16(
Op.getImm(), STI, O);
711 printImmediate16(
Op.getImm(), STI, O);
715 if (!isUInt<16>(
Op.getImm()) &&
717 printImmediate32(
Op.getImm(), STI, O);
723 printImmediate16(
static_cast<uint16_t>(
Op.getImm()), STI, O);
729 printImmediateInt16(
static_cast<uint16_t>(
Op.getImm()), STI, O);
733 printImmediateV216(
Op.getImm(), STI, O);
742 printImmediate32(
Op.getImm(), STI, O);
743 O <<
"/*Invalid immediate*/";
750 }
else if (
Op.isDFPImm()) {
751 double Value = bit_cast<double>(
Op.getDFPImm());
757 int RCID = Desc.
operands()[OpNo].RegClass;
761 else if (RCBits == 64)
766 }
else if (
Op.isExpr()) {
774 switch (
MI->getOpcode()) {
777 case AMDGPU::V_CNDMASK_B32_e32_gfx10:
778 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
779 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
780 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
781 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
782 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
783 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
784 case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
785 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
786 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
787 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
788 case AMDGPU::V_CNDMASK_B32_e32_gfx11:
789 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
790 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
791 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
792 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
793 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
794 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
795 case AMDGPU::V_CNDMASK_B32_dpp8_gfx11:
796 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
797 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
798 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
800 case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
801 case AMDGPU::V_CNDMASK_B32_e32_vi:
803 AMDGPU::OpName::src1))
804 printDefaultVccOperand(OpNo == 0, STI, O);
812 if ((
int)OpNo == SOffsetIdx)
813 printSymbolicFormat(
MI, STI, O);
817void AMDGPUInstPrinter::printOperandAndFPInputMods(
const MCInst *
MI,
822 if (needsImpliedVcc(Desc, OpNo))
823 printDefaultVccOperand(
true, STI, O);
825 unsigned InputModifiers =
MI->getOperand(OpNo).getImm();
830 bool NegMnemo =
false;
833 if (OpNo + 1 <
MI->getNumOperands() &&
836 NegMnemo =
Op.isImm() ||
Op.isDFPImm();
847 printRegularOperand(
MI, OpNo + 1, STI, O);
856 switch (
MI->getOpcode()) {
860 case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
861 case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
862 case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
865 printDefaultVccOperand(OpNo == 0, STI, O);
870void AMDGPUInstPrinter::printOperandAndIntInputMods(
const MCInst *
MI,
875 if (needsImpliedVcc(Desc, OpNo))
876 printDefaultVccOperand(
true, STI, O);
878 unsigned InputModifiers =
MI->getOperand(OpNo).getImm();
881 printRegularOperand(
MI, OpNo + 1, STI, O);
886 switch (
MI->getOpcode()) {
889 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
890 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
891 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
893 AMDGPU::OpName::src1))
894 printDefaultVccOperand(OpNo == 0, STI, O);
899void AMDGPUInstPrinter::printDPP8(
const MCInst *
MI,
unsigned OpNo,
905 unsigned Imm =
MI->getOperand(OpNo).getImm();
907 for (
size_t i = 1; i < 8; ++i) {
908 O <<
',' <<
formatDec((Imm >> (3 * i)) & 0x7);
913void AMDGPUInstPrinter::printDPPCtrl(
const MCInst *
MI,
unsigned OpNo,
916 using namespace AMDGPU::DPP;
918 unsigned Imm =
MI->getOperand(OpNo).getImm();
921 AMDGPU::OpName::src0);
924 Desc.
operands()[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID &&
926 O <<
" /* 64 bit dpp only supports row_newbcast */";
928 }
else if (Imm <= DppCtrl::QUAD_PERM_LAST) {
934 }
else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
935 (Imm <= DppCtrl::ROW_SHL_LAST)) {
937 printU4ImmDecOperand(
MI, OpNo, O);
938 }
else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
939 (Imm <= DppCtrl::ROW_SHR_LAST)) {
941 printU4ImmDecOperand(
MI, OpNo, O);
942 }
else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
943 (Imm <= DppCtrl::ROW_ROR_LAST)) {
945 printU4ImmDecOperand(
MI, OpNo, O);
946 }
else if (Imm == DppCtrl::WAVE_SHL1) {
948 O <<
"/* wave_shl is not supported starting from GFX10 */";
952 }
else if (Imm == DppCtrl::WAVE_ROL1) {
954 O <<
"/* wave_rol is not supported starting from GFX10 */";
958 }
else if (Imm == DppCtrl::WAVE_SHR1) {
960 O <<
"/* wave_shr is not supported starting from GFX10 */";
964 }
else if (Imm == DppCtrl::WAVE_ROR1) {
966 O <<
"/* wave_ror is not supported starting from GFX10 */";
970 }
else if (Imm == DppCtrl::ROW_MIRROR) {
972 }
else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
973 O <<
"row_half_mirror";
974 }
else if (Imm == DppCtrl::BCAST15) {
976 O <<
"/* row_bcast is not supported starting from GFX10 */";
980 }
else if (Imm == DppCtrl::BCAST31) {
982 O <<
"/* row_bcast is not supported starting from GFX10 */";
986 }
else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
987 (Imm <= DppCtrl::ROW_SHARE_LAST)) {
989 O <<
"row_newbcast:";
993 O <<
" /* row_newbcast/row_share is not supported on ASICs earlier "
994 "than GFX90A/GFX10 */";
997 printU4ImmDecOperand(
MI, OpNo, O);
998 }
else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
999 (Imm <= DppCtrl::ROW_XMASK_LAST)) {
1001 O <<
"/* row_xmask is not supported on ASICs earlier than GFX10 */";
1005 printU4ImmDecOperand(
MI, OpNo, O);
1007 O <<
"/* Invalid dpp_ctrl value */";
1011void AMDGPUInstPrinter::printRowMask(
const MCInst *
MI,
unsigned OpNo,
1015 printU4ImmOperand(
MI, OpNo, STI, O);
1018void AMDGPUInstPrinter::printBankMask(
const MCInst *
MI,
unsigned OpNo,
1022 printU4ImmOperand(
MI, OpNo, STI, O);
1025void AMDGPUInstPrinter::printDppBoundCtrl(
const MCInst *
MI,
unsigned OpNo,
1028 unsigned Imm =
MI->getOperand(OpNo).getImm();
1030 O <<
" bound_ctrl:1";
1034void AMDGPUInstPrinter::printFI(
const MCInst *
MI,
unsigned OpNo,
1038 unsigned Imm =
MI->getOperand(OpNo).getImm();
1039 if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
1044void AMDGPUInstPrinter::printSDWASel(
const MCInst *
MI,
unsigned OpNo,
1048 unsigned Imm =
MI->getOperand(OpNo).getImm();
1050 case SdwaSel::BYTE_0:
O <<
"BYTE_0";
break;
1051 case SdwaSel::BYTE_1:
O <<
"BYTE_1";
break;
1052 case SdwaSel::BYTE_2:
O <<
"BYTE_2";
break;
1053 case SdwaSel::BYTE_3:
O <<
"BYTE_3";
break;
1054 case SdwaSel::WORD_0:
O <<
"WORD_0";
break;
1055 case SdwaSel::WORD_1:
O <<
"WORD_1";
break;
1056 case SdwaSel::DWORD:
O <<
"DWORD";
break;
1061void AMDGPUInstPrinter::printSDWADstSel(
const MCInst *
MI,
unsigned OpNo,
1065 printSDWASel(
MI, OpNo, O);
1068void AMDGPUInstPrinter::printSDWASrc0Sel(
const MCInst *
MI,
unsigned OpNo,
1072 printSDWASel(
MI, OpNo, O);
1075void AMDGPUInstPrinter::printSDWASrc1Sel(
const MCInst *
MI,
unsigned OpNo,
1079 printSDWASel(
MI, OpNo, O);
1082void AMDGPUInstPrinter::printSDWADstUnused(
const MCInst *
MI,
unsigned OpNo,
1088 unsigned Imm =
MI->getOperand(OpNo).getImm();
1090 case DstUnused::UNUSED_PAD:
O <<
"UNUSED_PAD";
break;
1091 case DstUnused::UNUSED_SEXT:
O <<
"UNUSED_SEXT";
break;
1092 case DstUnused::UNUSED_PRESERVE:
O <<
"UNUSED_PRESERVE";
break;
1097void AMDGPUInstPrinter::printExpSrcN(
const MCInst *
MI,
unsigned OpNo,
1100 unsigned Opc =
MI->getOpcode();
1102 unsigned En =
MI->getOperand(EnIdx).getImm();
1107 if (
MI->getOperand(ComprIdx).getImm())
1108 OpNo = OpNo -
N +
N / 2;
1116void AMDGPUInstPrinter::printExpSrc0(
const MCInst *
MI,
unsigned OpNo,
1119 printExpSrcN(
MI, OpNo, STI, O, 0);
1122void AMDGPUInstPrinter::printExpSrc1(
const MCInst *
MI,
unsigned OpNo,
1125 printExpSrcN(
MI, OpNo, STI, O, 1);
1128void AMDGPUInstPrinter::printExpSrc2(
const MCInst *
MI,
unsigned OpNo,
1131 printExpSrcN(
MI, OpNo, STI, O, 2);
1134void AMDGPUInstPrinter::printExpSrc3(
const MCInst *
MI,
unsigned OpNo,
1137 printExpSrcN(
MI, OpNo, STI, O, 3);
1140void AMDGPUInstPrinter::printExpTgt(
const MCInst *
MI,
unsigned OpNo,
1146 unsigned Id =
MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1151 O <<
' ' << TgtName;
1155 O <<
" invalid_target_" <<
Id;
1160 bool IsPacked,
bool HasDstSel) {
1163 for (
int I = 0;
I < NumOps; ++
I) {
1164 if (!!(Ops[
I] &
Mod) != DefaultValue)
1174void AMDGPUInstPrinter::printPackedModifier(
const MCInst *
MI,
1178 unsigned Opc =
MI->getOpcode();
1182 for (
int OpName : { AMDGPU::OpName::src0_modifiers,
1183 AMDGPU::OpName::src1_modifiers,
1184 AMDGPU::OpName::src2_modifiers }) {
1189 Ops[NumOps++] =
MI->getOperand(
Idx).getImm();
1192 const bool HasDstSel =
1204 for (
int I = 0;
I < NumOps; ++
I) {
1208 O << !!(Ops[
I] &
Mod);
1218void AMDGPUInstPrinter::printOpSel(
const MCInst *
MI,
unsigned,
1221 unsigned Opc =
MI->getOpcode();
1228 O <<
" op_sel:[" << FI <<
',' << BC <<
']';
1235void AMDGPUInstPrinter::printOpSelHi(
const MCInst *
MI,
unsigned OpNo,
1241void AMDGPUInstPrinter::printNegLo(
const MCInst *
MI,
unsigned OpNo,
1247void AMDGPUInstPrinter::printNegHi(
const MCInst *
MI,
unsigned OpNo,
1253void AMDGPUInstPrinter::printInterpSlot(
const MCInst *
MI,
unsigned OpNum,
1256 unsigned Imm =
MI->getOperand(OpNum).getImm();
1268 O <<
"invalid_param_" <<
Imm;
1272void AMDGPUInstPrinter::printInterpAttr(
const MCInst *
MI,
unsigned OpNum,
1275 unsigned Attr =
MI->getOperand(OpNum).getImm();
1276 O <<
"attr" << Attr;
1279void AMDGPUInstPrinter::printInterpAttrChan(
const MCInst *
MI,
unsigned OpNum,
1282 unsigned Chan =
MI->getOperand(OpNum).getImm();
1283 O <<
'.' <<
"xyzw"[Chan & 0x3];
1286void AMDGPUInstPrinter::printVGPRIndexMode(
const MCInst *
MI,
unsigned OpNo,
1290 unsigned Val =
MI->getOperand(OpNo).getImm();
1292 if ((Val & ~ENABLE_MASK) != 0) {
1293 O << formatHex(static_cast<uint64_t>(Val));
1296 bool NeedComma =
false;
1297 for (
unsigned ModeId = ID_MIN; ModeId <=
ID_MAX; ++ModeId) {
1298 if (Val & (1 << ModeId)) {
1309void AMDGPUInstPrinter::printMemOperand(
const MCInst *
MI,
unsigned OpNo,
1312 printRegularOperand(
MI, OpNo, STI, O);
1314 printRegularOperand(
MI, OpNo + 1, STI, O);
1322 if (Op.getImm() == 1) {
1333 if (Op.getImm() == 1)
1340 printNamedBit(
MI, OpNo, O,
"high");
1346 printNamedBit(
MI, OpNo, O,
"clamp");
1352 int Imm =
MI->getOperand(OpNo).getImm();
1366 const unsigned Imm16 =
MI->getOperand(OpNo).getImm();
1371 decodeMsg(Imm16, MsgId, OpId,
StreamId, STI);
1373 StringRef MsgName = getMsgName(MsgId, STI);
1375 if (!MsgName.
empty() && isValidMsgOp(MsgId, OpId, STI) &&
1376 isValidMsgStream(MsgId, OpId,
StreamId, STI)) {
1377 O <<
"sendmsg(" << MsgName;
1378 if (msgRequiresOp(MsgId, STI)) {
1379 O <<
", " << getMsgOpName(MsgId, OpId, STI);
1380 if (msgSupportsStream(MsgId, OpId, STI)) {
1385 }
else if (encodeMsg(MsgId, OpId,
StreamId) == Imm16) {
1386 O <<
"sendmsg(" << MsgId <<
", " << OpId <<
", " <<
StreamId <<
')';
1398 uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask;
1399 uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1403 for (
unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1430 uint16_t Imm =
MI->getOperand(OpNo).getImm();
1437 if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1439 O <<
"swizzle(" << IdSymbolic[ID_QUAD_PERM];
1440 for (
unsigned I = 0;
I < LANE_NUM; ++
I) {
1447 }
else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1449 uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1450 uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK;
1451 uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1453 if (AndMask == BITMASK_MAX && OrMask == 0 &&
llvm::popcount(XorMask) == 1) {
1455 O <<
"swizzle(" << IdSymbolic[ID_SWAP];
1460 }
else if (AndMask == BITMASK_MAX && OrMask == 0 && XorMask > 0 &&
1463 O <<
"swizzle(" << IdSymbolic[ID_REVERSE];
1470 uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1471 if (GroupSize > 1 &&
1473 OrMask < GroupSize &&
1476 O <<
"swizzle(" << IdSymbolic[ID_BROADCAST];
1484 O <<
"swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1491 printU16ImmDecOperand(
MI, OpNo, O);
1500 unsigned SImm16 =
MI->getOperand(OpNo).getImm();
1501 unsigned Vmcnt, Expcnt, Lgkmcnt;
1507 bool PrintAll = IsDefaultVmcnt && IsDefaultExpcnt && IsDefaultLgkmcnt;
1509 bool NeedSpace =
false;
1511 if (!IsDefaultVmcnt || PrintAll) {
1512 O <<
"vmcnt(" << Vmcnt <<
')';
1516 if (!IsDefaultExpcnt || PrintAll) {
1519 O <<
"expcnt(" << Expcnt <<
')';
1523 if (!IsDefaultLgkmcnt || PrintAll) {
1526 O <<
"lgkmcnt(" << Lgkmcnt <<
')';
1535 uint64_t Imm16 =
MI->getOperand(OpNo).getImm() & 0xffff;
1537 bool HasNonDefaultVal =
false;
1538 if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) {
1543 bool NeedSpace =
false;
1544 while (decodeDepCtr(Imm16,
Id,
Name, Val, IsDefault, STI)) {
1545 if (!IsDefault || !HasNonDefaultVal) {
1548 O <<
Name <<
'(' << Val <<
')';
1560 const char *BadInstId =
"/* invalid instid value */";
1561 static const std::array<const char *, 12> InstIds = {
1562 "NO_DEP",
"VALU_DEP_1",
"VALU_DEP_2",
1563 "VALU_DEP_3",
"VALU_DEP_4",
"TRANS32_DEP_1",
1564 "TRANS32_DEP_2",
"TRANS32_DEP_3",
"FMA_ACCUM_CYCLE_1",
1565 "SALU_CYCLE_1",
"SALU_CYCLE_2",
"SALU_CYCLE_3"};
1567 const char *BadInstSkip =
"/* invalid instskip value */";
1568 static const std::array<const char *, 6> InstSkips = {
1569 "SAME",
"NEXT",
"SKIP_1",
"SKIP_2",
"SKIP_3",
"SKIP_4"};
1571 unsigned SImm16 =
MI->getOperand(OpNo).getImm();
1572 const char *Prefix =
"";
1574 unsigned Value = SImm16 & 0xF;
1576 const char *
Name =
Value < InstIds.size() ? InstIds[
Value] : BadInstId;
1577 O << Prefix <<
"instid0(" <<
Name <<
')';
1581 Value = (SImm16 >> 4) & 7;
1584 Value < InstSkips.size() ? InstSkips[
Value] : BadInstSkip;
1585 O << Prefix <<
"instskip(" <<
Name <<
')';
1589 Value = (SImm16 >> 7) & 0xF;
1591 const char *
Name =
Value < InstIds.size() ? InstIds[
Value] : BadInstId;
1592 O << Prefix <<
"instid1(" <<
Name <<
')';
1607 unsigned Val =
MI->getOperand(OpNo).getImm();
1612 if (!HwRegName.
empty()) {
1617 if (
Width != WIDTH_DEFAULT_ ||
Offset != OFFSET_DEFAULT_) {
1626 uint16_t Imm =
MI->getOperand(OpNo).getImm();
1634#include "AMDGPUGenAsmWriter.inc"
unsigned const MachineRegisterInfo * MRI
static void printSwizzleBitmask(const uint16_t AndMask, const uint16_t OrMask, const uint16_t XorMask, raw_ostream &O)
static bool allOpsDefaultValue(const int *Ops, int NumOps, int Mod, bool IsPacked, bool HasDstSel)
static cl::opt< bool > Keep16BitSuffixes("amdgpu-keep-16-bit-reg-suffixes", cl::desc("Keep .l and .h suffixes in asm for debugging purposes"), cl::init(false), cl::ReallyHidden)
Provides AMDGPU specific target descriptions.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Interface definition for SIRegisterInfo.
This header is deprecated in favour of llvm/TargetParser/TargetParser.h.
void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printClampSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printDelayFlag(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printEndpgm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getRegisterName(MCRegister Reg)
static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, StringRef Asm, StringRef Default="")
void printDepCtr(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printSendMsg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, MCRegister Reg) const override
Print the assembler register name.
static void printRegOperand(unsigned RegNo, raw_ostream &O, const MCRegisterInfo &MRI)
void printWaitFlag(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printOModSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printHigh(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Base class for the full range of assembler expressions which are needed for parsing.
format_object< int64_t > formatHex(int64_t Value) const
format_object< int64_t > formatDec(int64_t Value) const
Utility functions to print decimal/hexadecimal values.
const MCRegisterInfo & MRI
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
ArrayRef< MCOperandInfo > operands() const
bool hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
Return true if this instruction implicitly defines the specified physical register.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
MCRegisterClass - Base class of TargetRegisterClass.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const char * getRegClassName(const MCRegisterClass *Class) const
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const FeatureBitset & getFeatureBits() const
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
const char *const IdSymbolic[]
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
LLVM_READNONE bool isLegal64BitDPPControl(unsigned DC)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool isGFX940(const MCSubtargetInfo &STI)
IsaVersion getIsaVersion(StringRef GPU)
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
bool isSI(const MCSubtargetInfo &STI)
bool getVOP3IsSingle(unsigned Opc)
bool getVOP1IsSingle(unsigned Opc)
bool isGFX90A(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
unsigned getVmcntBitMask(const IsaVersion &Version)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool isInlineValue(unsigned Reg)
bool isGFX10Plus(const MCSubtargetInfo &STI)
@ OPERAND_REG_INLINE_C_V2INT32
@ OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
@ OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
@ OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
bool isCI(const MCSubtargetInfo &STI)
bool getVOP2IsSingle(unsigned Opc)
bool isPermlane16(unsigned Opc)
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
int popcount(T Value) noexcept
Count the number of set bits in a value.
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
@ Mod
The access may modify the value stored in memory.
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
@ Default
The result values are uniform if and only if all operands are uniform.
Instruction set architecture version.