51void AMDGPUInstPrinter::printU4ImmOperand(
const MCInst *
MI,
unsigned OpNo,
54 O <<
formatHex(
MI->getOperand(OpNo).getImm() & 0xf);
57void AMDGPUInstPrinter::printU16ImmOperand(
const MCInst *
MI,
unsigned OpNo,
62 int64_t Imm =
MI->getOperand(OpNo).getImm();
63 if (isInt<16>(Imm) || isUInt<16>(Imm))
64 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
66 printU32ImmOperand(
MI, OpNo, STI, O);
69void AMDGPUInstPrinter::printU4ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
74void AMDGPUInstPrinter::printU8ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
79void AMDGPUInstPrinter::printU16ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
84void AMDGPUInstPrinter::printU32ImmOperand(
const MCInst *
MI,
unsigned OpNo,
87 O <<
formatHex(
MI->getOperand(OpNo).getImm() & 0xffffffff);
90void AMDGPUInstPrinter::printNamedBit(
const MCInst *
MI,
unsigned OpNo,
92 if (
MI->getOperand(OpNo).getImm()) {
97void AMDGPUInstPrinter::printOffset(
const MCInst *
MI,
unsigned OpNo,
110 printU16ImmDecOperand(
MI, OpNo, O);
114void AMDGPUInstPrinter::printFlatOffset(
const MCInst *
MI,
unsigned OpNo,
129 printU16ImmDecOperand(
MI, OpNo, O);
133void AMDGPUInstPrinter::printOffset0(
const MCInst *
MI,
unsigned OpNo,
136 if (
MI->getOperand(OpNo).getImm()) {
138 printU8ImmDecOperand(
MI, OpNo, O);
142void AMDGPUInstPrinter::printOffset1(
const MCInst *
MI,
unsigned OpNo,
145 if (
MI->getOperand(OpNo).getImm()) {
147 printU8ImmDecOperand(
MI, OpNo, O);
151void AMDGPUInstPrinter::printSMRDOffset8(
const MCInst *
MI,
unsigned OpNo,
154 printU32ImmOperand(
MI, OpNo, STI, O);
157void AMDGPUInstPrinter::printSMEMOffset(
const MCInst *
MI,
unsigned OpNo,
163void AMDGPUInstPrinter::printSMEMOffsetMod(
const MCInst *
MI,
unsigned OpNo,
167 printSMEMOffset(
MI, OpNo, STI, O);
170void AMDGPUInstPrinter::printSMRDLiteralOffset(
const MCInst *
MI,
unsigned OpNo,
173 printU32ImmOperand(
MI, OpNo, STI, O);
176void AMDGPUInstPrinter::printCPol(
const MCInst *
MI,
unsigned OpNo,
178 auto Imm =
MI->getOperand(OpNo).getImm();
184 printTH(
MI, TH, Scope, O);
185 printScope(Scope, O);
201 O <<
" /* unexpected cache policy bit */";
204void AMDGPUInstPrinter::printTH(
const MCInst *
MI, int64_t TH, int64_t Scope,
210 const unsigned Opcode =
MI->getOpcode();
238 O << (IsStore ?
"TH_STORE_" :
"TH_LOAD_");
248 : (IsStore ?
"RT_WB" :
"LU"));
269void AMDGPUInstPrinter::printScope(int64_t Scope,
raw_ostream &O) {
287void AMDGPUInstPrinter::printDMask(
const MCInst *
MI,
unsigned OpNo,
289 if (
MI->getOperand(OpNo).getImm()) {
291 printU16ImmOperand(
MI, OpNo, STI, O);
295void AMDGPUInstPrinter::printDim(
const MCInst *
MI,
unsigned OpNo,
297 unsigned Dim =
MI->getOperand(OpNo).getImm();
298 O <<
" dim:SQ_RSRC_IMG_";
307void AMDGPUInstPrinter::printR128A16(
const MCInst *
MI,
unsigned OpNo,
310 printNamedBit(
MI, OpNo, O,
"a16");
312 printNamedBit(
MI, OpNo, O,
"r128");
315void AMDGPUInstPrinter::printFORMAT(
const MCInst *
MI,
unsigned OpNo,
320void AMDGPUInstPrinter::printSymbolicFormat(
const MCInst *
MI,
329 unsigned Val =
MI->getOperand(OpNo).getImm();
331 if (Val == UFMT_DEFAULT)
336 O <<
" format:" << Val;
339 if (Val == DFMT_NFMT_DEFAULT)
346 if (Dfmt != DFMT_DEFAULT) {
348 if (Nfmt != NFMT_DEFAULT) {
352 if (Nfmt != NFMT_DEFAULT) {
357 O <<
" format:" << Val;
368 case AMDGPU::PRIVATE_RSRC_REG:
380void AMDGPUInstPrinter::printVOPDst(
const MCInst *
MI,
unsigned OpNo,
382 auto Opcode =
MI->getOpcode();
400 printRegularOperand(
MI, OpNo, STI, O);
406 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
407 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
408 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
409 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
410 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
411 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
412 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
413 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
414 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
415 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
416 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
417 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
418 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
419 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
420 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
421 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
422 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
423 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
424 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
425 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
426 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
427 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12:
428 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12:
429 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12:
430 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12:
431 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12:
432 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12:
433 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12:
434 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12:
435 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12:
436 printDefaultVccOperand(
false, STI, O);
441void AMDGPUInstPrinter::printVINTRPDst(
const MCInst *
MI,
unsigned OpNo,
448 printRegularOperand(
MI, OpNo, STI, O);
451void AMDGPUInstPrinter::printImmediateInt16(
uint32_t Imm,
454 int32_t SImm =
static_cast<int32_t
>(
Imm);
460 if (printImmediateFloat32(Imm, STI, O))
463 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
470 else if (Imm == 0xBC00)
472 else if (Imm == 0x3800)
474 else if (Imm == 0xB800)
476 else if (Imm == 0x4000)
478 else if (Imm == 0xC000)
480 else if (Imm == 0x4400)
482 else if (Imm == 0xC400)
484 else if (Imm == 0x3118 && STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm))
496 else if (Imm == 0xBF80)
498 else if (Imm == 0x3F00)
500 else if (Imm == 0xBF00)
502 else if (Imm == 0x4000)
504 else if (Imm == 0xC000)
506 else if (Imm == 0x4080)
508 else if (Imm == 0xC080)
510 else if (Imm == 0x3E22 && STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm))
518void AMDGPUInstPrinter::printImmediateBF16(
uint32_t Imm,
521 int16_t SImm =
static_cast<int16_t
>(
Imm);
530 O << formatHex(static_cast<uint64_t>(Imm));
533void AMDGPUInstPrinter::printImmediateF16(
uint32_t Imm,
536 int16_t SImm =
static_cast<int16_t
>(
Imm);
550void AMDGPUInstPrinter::printImmediateV216(
uint32_t Imm, uint8_t OpType,
553 int32_t SImm =
static_cast<int32_t
>(
Imm);
563 if (printImmediateFloat32(Imm, STI, O))
569 if (isUInt<16>(Imm) &&
576 if (isUInt<16>(Imm) &&
584 O << formatHex(static_cast<uint64_t>(Imm));
587bool AMDGPUInstPrinter::printImmediateFloat32(
uint32_t Imm,
590 if (Imm == llvm::bit_cast<uint32_t>(0.0f))
592 else if (Imm == llvm::bit_cast<uint32_t>(1.0f))
594 else if (Imm == llvm::bit_cast<uint32_t>(-1.0f))
596 else if (Imm == llvm::bit_cast<uint32_t>(0.5f))
598 else if (Imm == llvm::bit_cast<uint32_t>(-0.5f))
600 else if (Imm == llvm::bit_cast<uint32_t>(2.0f))
602 else if (Imm == llvm::bit_cast<uint32_t>(-2.0f))
604 else if (Imm == llvm::bit_cast<uint32_t>(4.0f))
606 else if (Imm == llvm::bit_cast<uint32_t>(-4.0f))
608 else if (Imm == 0x3e22f983 &&
609 STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm))
617void AMDGPUInstPrinter::printImmediate32(
uint32_t Imm,
620 int32_t SImm =
static_cast<int32_t
>(
Imm);
626 if (printImmediateFloat32(Imm, STI, O))
629 O << formatHex(static_cast<uint64_t>(Imm));
632void AMDGPUInstPrinter::printImmediate64(
uint64_t Imm,
635 int64_t SImm =
static_cast<int64_t
>(
Imm);
636 if (SImm >= -16 && SImm <= 64) {
641 if (Imm == llvm::bit_cast<uint64_t>(0.0))
643 else if (Imm == llvm::bit_cast<uint64_t>(1.0))
645 else if (Imm == llvm::bit_cast<uint64_t>(-1.0))
647 else if (Imm == llvm::bit_cast<uint64_t>(0.5))
649 else if (Imm == llvm::bit_cast<uint64_t>(-0.5))
651 else if (Imm == llvm::bit_cast<uint64_t>(2.0))
653 else if (Imm == llvm::bit_cast<uint64_t>(-2.0))
655 else if (Imm == llvm::bit_cast<uint64_t>(4.0))
657 else if (Imm == llvm::bit_cast<uint64_t>(-4.0))
659 else if (Imm == 0x3fc45f306dc9c882 &&
660 STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm))
661 O <<
"0.15915494309189532";
664 O << formatHex(static_cast<uint64_t>(
Hi_32(Imm)));
666 assert(isUInt<32>(Imm) || isInt<32>(Imm));
670 O << formatHex(static_cast<uint64_t>(Imm));
674void AMDGPUInstPrinter::printBLGP(
const MCInst *
MI,
unsigned OpNo,
677 unsigned Imm =
MI->getOperand(OpNo).getImm();
682 switch (
MI->getOpcode()) {
683 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
684 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
685 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
686 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
687 O <<
" neg:[" << (
Imm & 1) <<
',' << ((Imm >> 1) & 1) <<
','
688 << ((Imm >> 2) & 1) <<
']';
693 O <<
" blgp:" <<
Imm;
696void AMDGPUInstPrinter::printCBSZ(
const MCInst *
MI,
unsigned OpNo,
699 unsigned Imm =
MI->getOperand(OpNo).getImm();
703 O <<
" cbsz:" <<
Imm;
706void AMDGPUInstPrinter::printABID(
const MCInst *
MI,
unsigned OpNo,
709 unsigned Imm =
MI->getOperand(OpNo).getImm();
713 O <<
" abid:" <<
Imm;
716void AMDGPUInstPrinter::printDefaultVccOperand(
bool FirstOperand,
729void AMDGPUInstPrinter::printWaitVDST(
const MCInst *
MI,
unsigned OpNo,
733 printU4ImmDecOperand(
MI, OpNo, O);
736void AMDGPUInstPrinter::printWaitVAVDst(
const MCInst *
MI,
unsigned OpNo,
739 O <<
" wait_va_vdst:";
740 printU4ImmDecOperand(
MI, OpNo, O);
743void AMDGPUInstPrinter::printWaitVMVSrc(
const MCInst *
MI,
unsigned OpNo,
746 O <<
" wait_vm_vsrc:";
747 printU4ImmDecOperand(
MI, OpNo, O);
750void AMDGPUInstPrinter::printWaitEXP(
const MCInst *
MI,
unsigned OpNo,
754 printU4ImmDecOperand(
MI, OpNo, O);
758 unsigned OpNo)
const {
762 (
Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
763 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO));
767void AMDGPUInstPrinter::printOperand(
const MCInst *
MI,
unsigned OpNo,
770 unsigned Opc =
MI->getOpcode();
779 (
Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
780 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
781 printDefaultVccOperand(
true, STI, O);
783 printRegularOperand(
MI, OpNo, STI, O);
787void AMDGPUInstPrinter::printRegularOperand(
const MCInst *
MI,
unsigned OpNo,
792 if (OpNo >=
MI->getNumOperands()) {
793 O <<
"/*Missing OP" << OpNo <<
"*/";
804 int RCID =
Desc.operands()[OpNo].RegClass;
810 <<
"\' register class*/";
813 }
else if (
Op.isImm()) {
814 const uint8_t OpTy =
Desc.operands()[OpNo].OperandType;
829 printImmediate32(
Op.getImm(), STI, O);
833 printImmediate64(
Op.getImm(), STI, O,
false);
838 printImmediate64(
Op.getImm(), STI, O,
true);
843 printImmediateInt16(
Op.getImm(), STI, O);
849 printImmediateF16(
Op.getImm(), STI, O);
855 printImmediateBF16(
Op.getImm(), STI, O);
866 printImmediateV216(
Op.getImm(), OpTy, STI, O);
875 printImmediate32(
Op.getImm(), STI, O);
876 O <<
"/*Invalid immediate*/";
883 }
else if (
Op.isDFPImm()) {
884 double Value = bit_cast<double>(
Op.getDFPImm());
890 int RCID =
Desc.operands()[OpNo].RegClass;
893 printImmediate32(llvm::bit_cast<uint32_t>((
float)
Value), STI, O);
894 else if (RCBits == 64)
895 printImmediate64(llvm::bit_cast<uint64_t>(
Value), STI, O,
true);
899 }
else if (
Op.isExpr()) {
907 switch (
MI->getOpcode()) {
910 case AMDGPU::V_CNDMASK_B32_e32_gfx10:
911 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
912 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
913 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
914 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
915 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
916 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
917 case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
918 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
919 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
920 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
921 case AMDGPU::V_CNDMASK_B32_e32_gfx11:
922 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
923 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
924 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
925 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
926 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
927 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
928 case AMDGPU::V_CNDMASK_B32_dpp8_gfx11:
929 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
930 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
931 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
932 case AMDGPU::V_CNDMASK_B32_e32_gfx12:
933 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12:
934 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12:
935 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12:
936 case AMDGPU::V_CNDMASK_B32_dpp_gfx12:
937 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12:
938 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12:
939 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12:
940 case AMDGPU::V_CNDMASK_B32_dpp8_gfx12:
941 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12:
942 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12:
943 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12:
945 case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
946 case AMDGPU::V_CNDMASK_B32_e32_vi:
948 AMDGPU::OpName::src1))
949 printDefaultVccOperand(OpNo == 0, STI, O);
957 if ((
int)OpNo == SOffsetIdx)
958 printSymbolicFormat(
MI, STI, O);
962void AMDGPUInstPrinter::printOperandAndFPInputMods(
const MCInst *
MI,
967 if (needsImpliedVcc(
Desc, OpNo))
968 printDefaultVccOperand(
true, STI, O);
970 unsigned InputModifiers =
MI->getOperand(OpNo).getImm();
975 bool NegMnemo =
false;
978 if (OpNo + 1 <
MI->getNumOperands() &&
981 NegMnemo =
Op.isImm() ||
Op.isDFPImm();
992 printRegularOperand(
MI, OpNo + 1, STI, O);
1001 switch (
MI->getOpcode()) {
1005 case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
1006 case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
1007 case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
1008 if ((
int)OpNo + 1 ==
1010 printDefaultVccOperand(OpNo == 0, STI, O);
1015void AMDGPUInstPrinter::printOperandAndIntInputMods(
const MCInst *
MI,
1020 if (needsImpliedVcc(
Desc, OpNo))
1021 printDefaultVccOperand(
true, STI, O);
1023 unsigned InputModifiers =
MI->getOperand(OpNo).getImm();
1026 printRegularOperand(
MI, OpNo + 1, STI, O);
1031 switch (
MI->getOpcode()) {
1034 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
1035 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
1036 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
1038 AMDGPU::OpName::src1))
1039 printDefaultVccOperand(OpNo == 0, STI, O);
1044void AMDGPUInstPrinter::printDPP8(
const MCInst *
MI,
unsigned OpNo,
1050 unsigned Imm =
MI->getOperand(OpNo).getImm();
1052 for (
size_t i = 1; i < 8; ++i) {
1053 O <<
',' <<
formatDec((Imm >> (3 * i)) & 0x7);
1058void AMDGPUInstPrinter::printDPPCtrl(
const MCInst *
MI,
unsigned OpNo,
1061 using namespace AMDGPU::DPP;
1063 unsigned Imm =
MI->getOperand(OpNo).getImm();
1067 O <<
" /* DP ALU dpp only supports row_newbcast */";
1069 }
else if (Imm <= DppCtrl::QUAD_PERM_LAST) {
1075 }
else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
1076 (Imm <= DppCtrl::ROW_SHL_LAST)) {
1078 printU4ImmDecOperand(
MI, OpNo, O);
1079 }
else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
1080 (Imm <= DppCtrl::ROW_SHR_LAST)) {
1082 printU4ImmDecOperand(
MI, OpNo, O);
1083 }
else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
1084 (Imm <= DppCtrl::ROW_ROR_LAST)) {
1086 printU4ImmDecOperand(
MI, OpNo, O);
1087 }
else if (Imm == DppCtrl::WAVE_SHL1) {
1089 O <<
"/* wave_shl is not supported starting from GFX10 */";
1093 }
else if (Imm == DppCtrl::WAVE_ROL1) {
1095 O <<
"/* wave_rol is not supported starting from GFX10 */";
1099 }
else if (Imm == DppCtrl::WAVE_SHR1) {
1101 O <<
"/* wave_shr is not supported starting from GFX10 */";
1105 }
else if (Imm == DppCtrl::WAVE_ROR1) {
1107 O <<
"/* wave_ror is not supported starting from GFX10 */";
1111 }
else if (Imm == DppCtrl::ROW_MIRROR) {
1113 }
else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
1114 O <<
"row_half_mirror";
1115 }
else if (Imm == DppCtrl::BCAST15) {
1117 O <<
"/* row_bcast is not supported starting from GFX10 */";
1120 O <<
"row_bcast:15";
1121 }
else if (Imm == DppCtrl::BCAST31) {
1123 O <<
"/* row_bcast is not supported starting from GFX10 */";
1126 O <<
"row_bcast:31";
1127 }
else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
1128 (Imm <= DppCtrl::ROW_SHARE_LAST)) {
1130 O <<
"row_newbcast:";
1134 O <<
" /* row_newbcast/row_share is not supported on ASICs earlier "
1135 "than GFX90A/GFX10 */";
1138 printU4ImmDecOperand(
MI, OpNo, O);
1139 }
else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
1140 (Imm <= DppCtrl::ROW_XMASK_LAST)) {
1142 O <<
"/* row_xmask is not supported on ASICs earlier than GFX10 */";
1146 printU4ImmDecOperand(
MI, OpNo, O);
1148 O <<
"/* Invalid dpp_ctrl value */";
1152void AMDGPUInstPrinter::printDppRowMask(
const MCInst *
MI,
unsigned OpNo,
1156 printU4ImmOperand(
MI, OpNo, STI, O);
1159void AMDGPUInstPrinter::printDppBankMask(
const MCInst *
MI,
unsigned OpNo,
1163 printU4ImmOperand(
MI, OpNo, STI, O);
1166void AMDGPUInstPrinter::printDppBoundCtrl(
const MCInst *
MI,
unsigned OpNo,
1169 unsigned Imm =
MI->getOperand(OpNo).getImm();
1171 O <<
" bound_ctrl:1";
1175void AMDGPUInstPrinter::printDppFI(
const MCInst *
MI,
unsigned OpNo,
1178 unsigned Imm =
MI->getOperand(OpNo).getImm();
1179 if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
1184void AMDGPUInstPrinter::printSDWASel(
const MCInst *
MI,
unsigned OpNo,
1188 unsigned Imm =
MI->getOperand(OpNo).getImm();
1190 case SdwaSel::BYTE_0:
O <<
"BYTE_0";
break;
1191 case SdwaSel::BYTE_1:
O <<
"BYTE_1";
break;
1192 case SdwaSel::BYTE_2:
O <<
"BYTE_2";
break;
1193 case SdwaSel::BYTE_3:
O <<
"BYTE_3";
break;
1194 case SdwaSel::WORD_0:
O <<
"WORD_0";
break;
1195 case SdwaSel::WORD_1:
O <<
"WORD_1";
break;
1196 case SdwaSel::DWORD:
O <<
"DWORD";
break;
1201void AMDGPUInstPrinter::printSDWADstSel(
const MCInst *
MI,
unsigned OpNo,
1205 printSDWASel(
MI, OpNo, O);
1208void AMDGPUInstPrinter::printSDWASrc0Sel(
const MCInst *
MI,
unsigned OpNo,
1212 printSDWASel(
MI, OpNo, O);
1215void AMDGPUInstPrinter::printSDWASrc1Sel(
const MCInst *
MI,
unsigned OpNo,
1219 printSDWASel(
MI, OpNo, O);
1222void AMDGPUInstPrinter::printSDWADstUnused(
const MCInst *
MI,
unsigned OpNo,
1228 unsigned Imm =
MI->getOperand(OpNo).getImm();
1230 case DstUnused::UNUSED_PAD:
O <<
"UNUSED_PAD";
break;
1231 case DstUnused::UNUSED_SEXT:
O <<
"UNUSED_SEXT";
break;
1232 case DstUnused::UNUSED_PRESERVE:
O <<
"UNUSED_PRESERVE";
break;
1237void AMDGPUInstPrinter::printExpSrcN(
const MCInst *
MI,
unsigned OpNo,
1240 unsigned Opc =
MI->getOpcode();
1242 unsigned En =
MI->getOperand(EnIdx).getImm();
1247 if (
MI->getOperand(ComprIdx).getImm())
1248 OpNo = OpNo -
N +
N / 2;
1256void AMDGPUInstPrinter::printExpSrc0(
const MCInst *
MI,
unsigned OpNo,
1259 printExpSrcN(
MI, OpNo, STI, O, 0);
1262void AMDGPUInstPrinter::printExpSrc1(
const MCInst *
MI,
unsigned OpNo,
1265 printExpSrcN(
MI, OpNo, STI, O, 1);
1268void AMDGPUInstPrinter::printExpSrc2(
const MCInst *
MI,
unsigned OpNo,
1271 printExpSrcN(
MI, OpNo, STI, O, 2);
1274void AMDGPUInstPrinter::printExpSrc3(
const MCInst *
MI,
unsigned OpNo,
1277 printExpSrcN(
MI, OpNo, STI, O, 3);
1280void AMDGPUInstPrinter::printExpTgt(
const MCInst *
MI,
unsigned OpNo,
1286 unsigned Id =
MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1291 O <<
' ' << TgtName;
1295 O <<
" invalid_target_" <<
Id;
1300 bool IsPacked,
bool HasDstSel) {
1303 for (
int I = 0;
I < NumOps; ++
I) {
1304 if (!!(Ops[
I] &
Mod) != DefaultValue)
1314void AMDGPUInstPrinter::printPackedModifier(
const MCInst *
MI,
1318 unsigned Opc =
MI->getOpcode();
1322 std::pair<int, int> MOps[] = {
1323 {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src0},
1324 {AMDGPU::OpName::src1_modifiers, AMDGPU::OpName::src1},
1325 {AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::src2}};
1328 for (
auto [SrcMod, Src] : MOps) {
1334 (ModIdx != -1) ?
MI->getOperand(ModIdx).getImm() : DefaultValue;
1344 {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers,
1345 AMDGPU::OpName::src2_modifiers}) {
1348 Ops[NumOps++] =
MI->getOperand(
Idx).getImm();
1350 Ops[NumOps++] = DefaultValue;
1354 const bool HasDstSel =
1366 for (
int I = 0;
I < NumOps; ++
I) {
1370 O << !!(Ops[
I] &
Mod);
1380void AMDGPUInstPrinter::printOpSel(
const MCInst *
MI,
unsigned,
1383 unsigned Opc =
MI->getOpcode();
1387 unsigned Mod =
MI->getOperand(SrcMod).getImm();
1390 if (Index0 || Index1)
1391 O <<
" op_sel:[" << Index0 <<
',' << Index1 <<
']';
1400 O <<
" op_sel:[" << FI <<
',' << BC <<
']';
1407void AMDGPUInstPrinter::printOpSelHi(
const MCInst *
MI,
unsigned OpNo,
1413void AMDGPUInstPrinter::printNegLo(
const MCInst *
MI,
unsigned OpNo,
1419void AMDGPUInstPrinter::printNegHi(
const MCInst *
MI,
unsigned OpNo,
1425void AMDGPUInstPrinter::printIndexKey8bit(
const MCInst *
MI,
unsigned OpNo,
1428 auto Imm =
MI->getOperand(OpNo).getImm() & 0x7;
1432 O <<
" index_key:" <<
Imm;
1435void AMDGPUInstPrinter::printIndexKey16bit(
const MCInst *
MI,
unsigned OpNo,
1438 auto Imm =
MI->getOperand(OpNo).getImm() & 0x7;
1442 O <<
" index_key:" <<
Imm;
1445void AMDGPUInstPrinter::printInterpSlot(
const MCInst *
MI,
unsigned OpNum,
1448 unsigned Imm =
MI->getOperand(OpNum).getImm();
1460 O <<
"invalid_param_" <<
Imm;
1464void AMDGPUInstPrinter::printInterpAttr(
const MCInst *
MI,
unsigned OpNum,
1467 unsigned Attr =
MI->getOperand(OpNum).getImm();
1468 O <<
"attr" << Attr;
1471void AMDGPUInstPrinter::printInterpAttrChan(
const MCInst *
MI,
unsigned OpNum,
1474 unsigned Chan =
MI->getOperand(OpNum).getImm();
1475 O <<
'.' <<
"xyzw"[Chan & 0x3];
1478void AMDGPUInstPrinter::printGPRIdxMode(
const MCInst *
MI,
unsigned OpNo,
1482 unsigned Val =
MI->getOperand(OpNo).getImm();
1484 if ((Val & ~ENABLE_MASK) != 0) {
1485 O << formatHex(static_cast<uint64_t>(Val));
1488 bool NeedComma =
false;
1489 for (
unsigned ModeId = ID_MIN; ModeId <=
ID_MAX; ++ModeId) {
1490 if (Val & (1 << ModeId)) {
1501void AMDGPUInstPrinter::printMemOperand(
const MCInst *
MI,
unsigned OpNo,
1504 printRegularOperand(
MI, OpNo, STI, O);
1506 printRegularOperand(
MI, OpNo + 1, STI, O);
1514 if (
Op.getImm() == 1) {
1525 if (
Op.getImm() == 1)
1532 int Imm =
MI->getOperand(OpNo).getImm();
1546 const unsigned Imm16 =
MI->getOperand(OpNo).getImm();
1551 decodeMsg(Imm16, MsgId, OpId,
StreamId, STI);
1553 StringRef MsgName = getMsgName(MsgId, STI);
1555 if (!MsgName.
empty() && isValidMsgOp(MsgId, OpId, STI) &&
1556 isValidMsgStream(MsgId, OpId,
StreamId, STI)) {
1557 O <<
"sendmsg(" << MsgName;
1558 if (msgRequiresOp(MsgId, STI)) {
1559 O <<
", " << getMsgOpName(MsgId, OpId, STI);
1560 if (msgSupportsStream(MsgId, OpId, STI)) {
1565 }
else if (encodeMsg(MsgId, OpId,
StreamId) == Imm16) {
1566 O <<
"sendmsg(" << MsgId <<
", " << OpId <<
", " <<
StreamId <<
')';
1578 uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask;
1579 uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1583 for (
unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1610 uint16_t Imm =
MI->getOperand(OpNo).getImm();
1617 if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1619 O <<
"swizzle(" << IdSymbolic[ID_QUAD_PERM];
1620 for (
unsigned I = 0;
I < LANE_NUM; ++
I) {
1627 }
else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1629 uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1630 uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK;
1631 uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1633 if (AndMask == BITMASK_MAX && OrMask == 0 &&
llvm::popcount(XorMask) == 1) {
1635 O <<
"swizzle(" << IdSymbolic[ID_SWAP];
1640 }
else if (AndMask == BITMASK_MAX && OrMask == 0 && XorMask > 0 &&
1643 O <<
"swizzle(" << IdSymbolic[ID_REVERSE];
1650 uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1651 if (GroupSize > 1 &&
1653 OrMask < GroupSize &&
1656 O <<
"swizzle(" << IdSymbolic[ID_BROADCAST];
1664 O <<
"swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1671 printU16ImmDecOperand(
MI, OpNo, O);
1680 unsigned SImm16 =
MI->getOperand(OpNo).getImm();
1681 unsigned Vmcnt, Expcnt, Lgkmcnt;
1687 bool PrintAll = IsDefaultVmcnt && IsDefaultExpcnt && IsDefaultLgkmcnt;
1689 bool NeedSpace =
false;
1691 if (!IsDefaultVmcnt || PrintAll) {
1692 O <<
"vmcnt(" << Vmcnt <<
')';
1696 if (!IsDefaultExpcnt || PrintAll) {
1699 O <<
"expcnt(" << Expcnt <<
')';
1703 if (!IsDefaultLgkmcnt || PrintAll) {
1706 O <<
"lgkmcnt(" << Lgkmcnt <<
')';
1715 uint64_t Imm16 =
MI->getOperand(OpNo).getImm() & 0xffff;
1717 bool HasNonDefaultVal =
false;
1718 if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) {
1723 bool NeedSpace =
false;
1724 while (decodeDepCtr(Imm16,
Id,
Name, Val, IsDefault, STI)) {
1725 if (!IsDefault || !HasNonDefaultVal) {
1728 O <<
Name <<
'(' << Val <<
')';
1740 const char *BadInstId =
"/* invalid instid value */";
1741 static const std::array<const char *, 12> InstIds = {
1742 "NO_DEP",
"VALU_DEP_1",
"VALU_DEP_2",
1743 "VALU_DEP_3",
"VALU_DEP_4",
"TRANS32_DEP_1",
1744 "TRANS32_DEP_2",
"TRANS32_DEP_3",
"FMA_ACCUM_CYCLE_1",
1745 "SALU_CYCLE_1",
"SALU_CYCLE_2",
"SALU_CYCLE_3"};
1747 const char *BadInstSkip =
"/* invalid instskip value */";
1748 static const std::array<const char *, 6> InstSkips = {
1749 "SAME",
"NEXT",
"SKIP_1",
"SKIP_2",
"SKIP_3",
"SKIP_4"};
1751 unsigned SImm16 =
MI->getOperand(OpNo).getImm();
1752 const char *Prefix =
"";
1754 unsigned Value = SImm16 & 0xF;
1756 const char *
Name =
Value < InstIds.size() ? InstIds[
Value] : BadInstId;
1757 O << Prefix <<
"instid0(" <<
Name <<
')';
1761 Value = (SImm16 >> 4) & 7;
1764 Value < InstSkips.size() ? InstSkips[
Value] : BadInstSkip;
1765 O << Prefix <<
"instskip(" <<
Name <<
')';
1769 Value = (SImm16 >> 7) & 0xF;
1771 const char *
Name =
Value < InstIds.size() ? InstIds[
Value] : BadInstId;
1772 O << Prefix <<
"instid1(" <<
Name <<
')';
1783 unsigned Val =
MI->getOperand(OpNo).getImm();
1784 auto [
Id,
Offset, Width] = HwregEncoding::decode(Val);
1788 if (!HwRegName.
empty()) {
1793 if (Width != HwregSize::Default ||
Offset != HwregOffset::Default)
1794 O <<
", " <<
Offset <<
", " << Width;
1801 uint16_t Imm =
MI->getOperand(OpNo).getImm();
1809#include "AMDGPUGenAsmWriter.inc"
unsigned const MachineRegisterInfo * MRI
static void printSwizzleBitmask(const uint16_t AndMask, const uint16_t OrMask, const uint16_t XorMask, raw_ostream &O)
static bool printImmediateBFloat16(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O)
static bool allOpsDefaultValue(const int *Ops, int NumOps, int Mod, bool IsPacked, bool HasDstSel)
static bool printImmediateFP16(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O)
Provides AMDGPU specific target descriptions.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printEndpgm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getRegisterName(MCRegister Reg)
static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, StringRef Asm, StringRef Default="")
void printDepCtr(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printSendMsg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, MCRegister Reg) const override
Print the assembler register name.
static void printRegOperand(unsigned RegNo, raw_ostream &O, const MCRegisterInfo &MRI)
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printSWaitCnt(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printOModSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printSDelayALU(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
This class represents an Operation in the Expression.
Base class for the full range of assembler expressions which are needed for parsing.
format_object< int64_t > formatHex(int64_t Value) const
format_object< int64_t > formatDec(int64_t Value) const
Utility functions to print decimal/hexadecimal values.
const MCRegisterInfo & MRI
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
bool mayStore() const
Return true if this instruction could possibly modify memory.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
MCRegisterClass - Base class of TargetRegisterClass.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const char * getRegClassName(const MCRegisterClass *Class) const
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
const char *const IdSymbolic[]
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
bool isVOPCAsmOnly(unsigned Opc)
LLVM_READNONE bool isLegalDPALU_DPPControl(unsigned DC)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool isGFX12Plus(const MCSubtargetInfo &STI)
bool isGFX940(const MCSubtargetInfo &STI)
IsaVersion getIsaVersion(StringRef GPU)
bool isValid32BitLiteral(uint64_t Val, bool IsFP64)
bool isDPALU_DPP(const MCInstrDesc &OpDesc)
bool isSI(const MCSubtargetInfo &STI)
bool getVOP3IsSingle(unsigned Opc)
bool getVOP1IsSingle(unsigned Opc)
bool isGFX90A(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
bool isGFX12(const MCSubtargetInfo &STI)
unsigned getVmcntBitMask(const IsaVersion &Version)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool isInlineValue(unsigned Reg)
bool isGFX10Plus(const MCSubtargetInfo &STI)
@ OPERAND_REG_INLINE_C_V2INT32
@ OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_BF16
@ OPERAND_REG_INLINE_C_V2BF16
@ OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
@ OPERAND_REG_IMM_BF16_DEFERRED
@ OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_AC_BF16
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
@ OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_V2BF16
@ OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_INLINE_SPLIT_BARRIER_INT32
@ OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc)
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
bool isCI(const MCSubtargetInfo &STI)
bool getVOP2IsSingle(unsigned Opc)
bool isPermlane16(unsigned Opc)
Reg
All possible values of the reg field in the ModR/M byte.
Scope
Defines the scope in which this symbol should be visible: Default – Visible in the public interface o...
This is an optimization pass for GlobalISel generic memory operations.
int popcount(T Value) noexcept
Count the number of set bits in a value.
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
constexpr uint32_t Hi_32(uint64_t Value)
Return the high 32 bits of a 64 bit value.
@ Mod
The access may modify the value stored in memory.
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
@ Default
The result values are uniform if and only if all operands are uniform.
Instruction set architecture version.
Description of the encoding of one expression Op.