LLVM  14.0.0git
AMDGPUInstPrinter.cpp
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1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 // \file
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPUInstPrinter.h"
12 #include "SIDefines.h"
13 #include "SIRegisterInfo.h"
14 #include "Utils/AMDGPUAsmUtils.h"
15 #include "Utils/AMDGPUBaseInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCInstrInfo.h"
23 
24 using namespace llvm;
25 using namespace llvm::AMDGPU;
26 
28  "amdgpu-keep-16-bit-reg-suffixes",
29  cl::desc("Keep .l and .h suffixes in asm for debugging purposes"),
30  cl::init(false),
32 
33 void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
34  // FIXME: The current implementation of
35  // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
36  // as an integer or we provide a name which represents a physical register.
37  // For CFI instructions we really want to emit a name for the DWARF register
38  // instead, because there may be multiple DWARF registers corresponding to a
39  // single physical register. One case where this problem manifests is with
40  // wave32/wave64 where using the physical register name is ambiguous: if we
41  // write e.g. `.cfi_undefined v0` we lose information about the wavefront
42  // size which we need to encode the register in the final DWARF. Ideally we
43  // would extend MC to support parsing DWARF register names so we could do
44  // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with
45  // non-pretty DWARF register names in assembly text.
46  OS << RegNo;
47 }
48 
50  StringRef Annot, const MCSubtargetInfo &STI,
51  raw_ostream &OS) {
52  OS.flush();
53  printInstruction(MI, Address, STI, OS);
54  printAnnotation(OS, Annot);
55 }
56 
57 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
58  const MCSubtargetInfo &STI,
59  raw_ostream &O) {
60  O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
61 }
62 
63 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
64  raw_ostream &O) {
65  O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
66 }
67 
68 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
69  const MCSubtargetInfo &STI,
70  raw_ostream &O) {
71  // It's possible to end up with a 32-bit literal used with a 16-bit operand
72  // with ignored high bits. Print as 32-bit anyway in that case.
73  int64_t Imm = MI->getOperand(OpNo).getImm();
74  if (isInt<16>(Imm) || isUInt<16>(Imm))
75  O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
76  else
77  printU32ImmOperand(MI, OpNo, STI, O);
78 }
79 
80 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
81  raw_ostream &O) {
82  O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
83 }
84 
85 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
86  raw_ostream &O) {
87  O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
88 }
89 
90 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
91  raw_ostream &O) {
92  O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
93 }
94 
95 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
96  const MCSubtargetInfo &STI,
97  raw_ostream &O) {
98  O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
99 }
100 
101 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
102  raw_ostream &O, StringRef BitName) {
103  if (MI->getOperand(OpNo).getImm()) {
104  O << ' ' << BitName;
105  }
106 }
107 
108 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
109  raw_ostream &O) {
110  printNamedBit(MI, OpNo, O, "offen");
111 }
112 
113 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
114  raw_ostream &O) {
115  printNamedBit(MI, OpNo, O, "idxen");
116 }
117 
118 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
119  raw_ostream &O) {
120  printNamedBit(MI, OpNo, O, "addr64");
121 }
122 
123 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
124  raw_ostream &O) {
125  if (MI->getOperand(OpNo).getImm()) {
126  O << " offset:";
127  printU16ImmDecOperand(MI, OpNo, O);
128  }
129 }
130 
131 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
132  const MCSubtargetInfo &STI,
133  raw_ostream &O) {
134  uint16_t Imm = MI->getOperand(OpNo).getImm();
135  if (Imm != 0) {
136  O << " offset:";
137  printU16ImmDecOperand(MI, OpNo, O);
138  }
139 }
140 
141 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
142  const MCSubtargetInfo &STI,
143  raw_ostream &O) {
144  uint16_t Imm = MI->getOperand(OpNo).getImm();
145  if (Imm != 0) {
146  O << " offset:";
147 
148  const MCInstrDesc &Desc = MII.get(MI->getOpcode());
149  bool IsFlatSeg = !(Desc.TSFlags &
151 
152  if (IsFlatSeg) { // Unsigned offset
153  printU16ImmDecOperand(MI, OpNo, O);
154  } else { // Signed offset
155  if (AMDGPU::isGFX10Plus(STI)) {
156  O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
157  } else {
158  O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
159  }
160  }
161  }
162 }
163 
164 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
165  const MCSubtargetInfo &STI,
166  raw_ostream &O) {
167  if (MI->getOperand(OpNo).getImm()) {
168  O << " offset0:";
169  printU8ImmDecOperand(MI, OpNo, O);
170  }
171 }
172 
173 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
174  const MCSubtargetInfo &STI,
175  raw_ostream &O) {
176  if (MI->getOperand(OpNo).getImm()) {
177  O << " offset1:";
178  printU8ImmDecOperand(MI, OpNo, O);
179  }
180 }
181 
182 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
183  const MCSubtargetInfo &STI,
184  raw_ostream &O) {
185  printU32ImmOperand(MI, OpNo, STI, O);
186 }
187 
188 void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
189  const MCSubtargetInfo &STI,
190  raw_ostream &O) {
191  O << formatHex(MI->getOperand(OpNo).getImm());
192 }
193 
194 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
195  const MCSubtargetInfo &STI,
196  raw_ostream &O) {
197  printU32ImmOperand(MI, OpNo, STI, O);
198 }
199 
200 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
201  const MCSubtargetInfo &STI, raw_ostream &O) {
202  printNamedBit(MI, OpNo, O, "gds");
203 }
204 
205 void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
206  const MCSubtargetInfo &STI, raw_ostream &O) {
207  auto Imm = MI->getOperand(OpNo).getImm();
208  if (Imm & CPol::GLC)
209  O << " glc";
210  if (Imm & CPol::SLC)
211  O << " slc";
212  if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
213  O << " dlc";
214  if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
215  O << " scc";
216  if (Imm & ~CPol::ALL)
217  O << " /* unexpected cache policy bit */";
218 }
219 
220 void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo,
221  const MCSubtargetInfo &STI, raw_ostream &O) {
222 }
223 
224 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
225  const MCSubtargetInfo &STI, raw_ostream &O) {
226  printNamedBit(MI, OpNo, O, "tfe");
227 }
228 
229 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
230  const MCSubtargetInfo &STI, raw_ostream &O) {
231  if (MI->getOperand(OpNo).getImm()) {
232  O << " dmask:";
233  printU16ImmOperand(MI, OpNo, STI, O);
234  }
235 }
236 
237 void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
238  const MCSubtargetInfo &STI, raw_ostream &O) {
239  unsigned Dim = MI->getOperand(OpNo).getImm();
240  O << " dim:SQ_RSRC_IMG_";
241 
242  const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
243  if (DimInfo)
244  O << DimInfo->AsmSuffix;
245  else
246  O << Dim;
247 }
248 
249 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
250  const MCSubtargetInfo &STI, raw_ostream &O) {
251  printNamedBit(MI, OpNo, O, "unorm");
252 }
253 
254 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
255  const MCSubtargetInfo &STI, raw_ostream &O) {
256  printNamedBit(MI, OpNo, O, "da");
257 }
258 
259 void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
260  const MCSubtargetInfo &STI, raw_ostream &O) {
261  if (STI.hasFeature(AMDGPU::FeatureR128A16))
262  printNamedBit(MI, OpNo, O, "a16");
263  else
264  printNamedBit(MI, OpNo, O, "r128");
265 }
266 
267 void AMDGPUInstPrinter::printGFX10A16(const MCInst *MI, unsigned OpNo,
268  const MCSubtargetInfo &STI, raw_ostream &O) {
269  printNamedBit(MI, OpNo, O, "a16");
270 }
271 
272 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
273  const MCSubtargetInfo &STI, raw_ostream &O) {
274  printNamedBit(MI, OpNo, O, "lwe");
275 }
276 
277 void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo,
278  const MCSubtargetInfo &STI, raw_ostream &O) {
279  printNamedBit(MI, OpNo, O, "d16");
280 }
281 
282 void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
283  const MCSubtargetInfo &STI,
284  raw_ostream &O) {
285  printNamedBit(MI, OpNo, O, "compr");
286 }
287 
288 void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
289  const MCSubtargetInfo &STI,
290  raw_ostream &O) {
291  printNamedBit(MI, OpNo, O, "vm");
292 }
293 
294 void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
295  const MCSubtargetInfo &STI,
296  raw_ostream &O) {
297 }
298 
299 void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
300  const MCSubtargetInfo &STI,
301  raw_ostream &O) {
302  using namespace llvm::AMDGPU::MTBUFFormat;
303 
304  int OpNo =
306  assert(OpNo != -1);
307 
308  unsigned Val = MI->getOperand(OpNo).getImm();
309  if (AMDGPU::isGFX10Plus(STI)) {
310  if (Val == UFMT_DEFAULT)
311  return;
312  if (isValidUnifiedFormat(Val)) {
313  O << " format:[" << getUnifiedFormatName(Val) << ']';
314  } else {
315  O << " format:" << Val;
316  }
317  } else {
318  if (Val == DFMT_NFMT_DEFAULT)
319  return;
320  if (isValidDfmtNfmt(Val, STI)) {
321  unsigned Dfmt;
322  unsigned Nfmt;
323  decodeDfmtNfmt(Val, Dfmt, Nfmt);
324  O << " format:[";
325  if (Dfmt != DFMT_DEFAULT) {
326  O << getDfmtName(Dfmt);
327  if (Nfmt != NFMT_DEFAULT) {
328  O << ',';
329  }
330  }
331  if (Nfmt != NFMT_DEFAULT) {
332  O << getNfmtName(Nfmt, STI);
333  }
334  O << ']';
335  } else {
336  O << " format:" << Val;
337  }
338  }
339 }
340 
342  const MCRegisterInfo &MRI) {
343 #if !defined(NDEBUG)
344  switch (RegNo) {
345  case AMDGPU::FP_REG:
346  case AMDGPU::SP_REG:
347  case AMDGPU::PRIVATE_RSRC_REG:
348  llvm_unreachable("pseudo-register should not ever be emitted");
349  case AMDGPU::SCC:
350  llvm_unreachable("pseudo scc should not ever be emitted");
351  default:
352  break;
353  }
354 #endif
355 
357  if (!Keep16BitSuffixes)
358  if (!RegName.consume_back(".l"))
359  RegName.consume_back(".h");
360 
361  O << RegName;
362 }
363 
364 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
365  const MCSubtargetInfo &STI,
366  raw_ostream &O) {
367  auto Opcode = MI->getOpcode();
368  auto Flags = MII.get(Opcode).TSFlags;
369 
370  if (OpNo == 0) {
371  if (Flags & SIInstrFlags::VOP3) {
372  if (!getVOP3IsSingle(Opcode))
373  O << "_e64";
374  } else if (Flags & SIInstrFlags::DPP) {
375  O << "_dpp";
376  } else if (Flags & SIInstrFlags::SDWA) {
377  O << "_sdwa";
378  } else if (((Flags & SIInstrFlags::VOP1) && !getVOP1IsSingle(Opcode)) ||
379  ((Flags & SIInstrFlags::VOP2) && !getVOP2IsSingle(Opcode))) {
380  O << "_e32";
381  }
382  O << " ";
383  }
384 
385  printOperand(MI, OpNo, STI, O);
386 
387  // Print default vcc/vcc_lo operand.
388  switch (Opcode) {
389  default: break;
390 
391  case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
392  case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
393  case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
394  case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
395  case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
396  case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
397  case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
398  case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
399  case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
400  case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
401  case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
402  case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
403  printDefaultVccOperand(1, STI, O);
404  break;
405  }
406 }
407 
408 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
409  const MCSubtargetInfo &STI, raw_ostream &O) {
410  if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
411  O << " ";
412  else
413  O << "_e32 ";
414 
415  printOperand(MI, OpNo, STI, O);
416 }
417 
418 void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
419  const MCSubtargetInfo &STI,
420  raw_ostream &O) {
421  int16_t SImm = static_cast<int16_t>(Imm);
422  if (isInlinableIntLiteral(SImm)) {
423  O << SImm;
424  } else {
425  uint64_t Imm16 = static_cast<uint16_t>(Imm);
426  O << formatHex(Imm16);
427  }
428 }
429 
430 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm,
431  const MCSubtargetInfo &STI,
432  raw_ostream &O) {
433  int16_t SImm = static_cast<int16_t>(Imm);
434  if (isInlinableIntLiteral(SImm)) {
435  O << SImm;
436  return;
437  }
438 
439  if (Imm == 0x3C00)
440  O<< "1.0";
441  else if (Imm == 0xBC00)
442  O<< "-1.0";
443  else if (Imm == 0x3800)
444  O<< "0.5";
445  else if (Imm == 0xB800)
446  O<< "-0.5";
447  else if (Imm == 0x4000)
448  O<< "2.0";
449  else if (Imm == 0xC000)
450  O<< "-2.0";
451  else if (Imm == 0x4400)
452  O<< "4.0";
453  else if (Imm == 0xC400)
454  O<< "-4.0";
455  else if (Imm == 0x3118 &&
456  STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) {
457  O << "0.15915494";
458  } else {
459  uint64_t Imm16 = static_cast<uint16_t>(Imm);
460  O << formatHex(Imm16);
461  }
462 }
463 
464 void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm,
465  const MCSubtargetInfo &STI,
466  raw_ostream &O) {
467  uint16_t Lo16 = static_cast<uint16_t>(Imm);
468  printImmediate16(Lo16, STI, O);
469 }
470 
471 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
472  const MCSubtargetInfo &STI,
473  raw_ostream &O) {
474  int32_t SImm = static_cast<int32_t>(Imm);
475  if (SImm >= -16 && SImm <= 64) {
476  O << SImm;
477  return;
478  }
479 
480  if (Imm == FloatToBits(0.0f))
481  O << "0.0";
482  else if (Imm == FloatToBits(1.0f))
483  O << "1.0";
484  else if (Imm == FloatToBits(-1.0f))
485  O << "-1.0";
486  else if (Imm == FloatToBits(0.5f))
487  O << "0.5";
488  else if (Imm == FloatToBits(-0.5f))
489  O << "-0.5";
490  else if (Imm == FloatToBits(2.0f))
491  O << "2.0";
492  else if (Imm == FloatToBits(-2.0f))
493  O << "-2.0";
494  else if (Imm == FloatToBits(4.0f))
495  O << "4.0";
496  else if (Imm == FloatToBits(-4.0f))
497  O << "-4.0";
498  else if (Imm == 0x3e22f983 &&
499  STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
500  O << "0.15915494";
501  else
502  O << formatHex(static_cast<uint64_t>(Imm));
503 }
504 
505 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
506  const MCSubtargetInfo &STI,
507  raw_ostream &O) {
508  int64_t SImm = static_cast<int64_t>(Imm);
509  if (SImm >= -16 && SImm <= 64) {
510  O << SImm;
511  return;
512  }
513 
514  if (Imm == DoubleToBits(0.0))
515  O << "0.0";
516  else if (Imm == DoubleToBits(1.0))
517  O << "1.0";
518  else if (Imm == DoubleToBits(-1.0))
519  O << "-1.0";
520  else if (Imm == DoubleToBits(0.5))
521  O << "0.5";
522  else if (Imm == DoubleToBits(-0.5))
523  O << "-0.5";
524  else if (Imm == DoubleToBits(2.0))
525  O << "2.0";
526  else if (Imm == DoubleToBits(-2.0))
527  O << "-2.0";
528  else if (Imm == DoubleToBits(4.0))
529  O << "4.0";
530  else if (Imm == DoubleToBits(-4.0))
531  O << "-4.0";
532  else if (Imm == 0x3fc45f306dc9c882 &&
533  STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
534  O << "0.15915494309189532";
535  else {
536  assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
537 
538  // In rare situations, we will have a 32-bit literal in a 64-bit
539  // operand. This is technically allowed for the encoding of s_mov_b64.
540  O << formatHex(static_cast<uint64_t>(Imm));
541  }
542 }
543 
544 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
545  const MCSubtargetInfo &STI,
546  raw_ostream &O) {
547  unsigned Imm = MI->getOperand(OpNo).getImm();
548  if (!Imm)
549  return;
550 
551  O << " blgp:" << Imm;
552 }
553 
554 void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
555  const MCSubtargetInfo &STI,
556  raw_ostream &O) {
557  unsigned Imm = MI->getOperand(OpNo).getImm();
558  if (!Imm)
559  return;
560 
561  O << " cbsz:" << Imm;
562 }
563 
564 void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
565  const MCSubtargetInfo &STI,
566  raw_ostream &O) {
567  unsigned Imm = MI->getOperand(OpNo).getImm();
568  if (!Imm)
569  return;
570 
571  O << " abid:" << Imm;
572 }
573 
574 void AMDGPUInstPrinter::printDefaultVccOperand(unsigned OpNo,
575  const MCSubtargetInfo &STI,
576  raw_ostream &O) {
577  if (OpNo > 0)
578  O << ", ";
579  printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
580  AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI);
581  if (OpNo == 0)
582  O << ", ";
583 }
584 
585 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
586  const MCSubtargetInfo &STI,
587  raw_ostream &O) {
588  // Print default vcc/vcc_lo operand of VOPC.
589  const MCInstrDesc &Desc = MII.get(MI->getOpcode());
590  if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
591  (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
592  Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
593  printDefaultVccOperand(OpNo, STI, O);
594 
595  if (OpNo >= MI->getNumOperands()) {
596  O << "/*Missing OP" << OpNo << "*/";
597  return;
598  }
599 
600  const MCOperand &Op = MI->getOperand(OpNo);
601  if (Op.isReg()) {
602  printRegOperand(Op.getReg(), O, MRI);
603  } else if (Op.isImm()) {
604  const uint8_t OpTy = Desc.OpInfo[OpNo].OperandType;
605  switch (OpTy) {
618  printImmediate32(Op.getImm(), STI, O);
619  break;
625  printImmediate64(Op.getImm(), STI, O);
626  break;
630  printImmediateInt16(Op.getImm(), STI, O);
631  break;
636  printImmediate16(Op.getImm(), STI, O);
637  break;
640  if (!isUInt<16>(Op.getImm()) &&
641  STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) {
642  printImmediate32(Op.getImm(), STI, O);
643  break;
644  }
645 
646  // Deal with 16-bit FP inline immediates not working.
647  if (OpTy == AMDGPU::OPERAND_REG_IMM_V2FP16) {
648  printImmediate16(static_cast<uint16_t>(Op.getImm()), STI, O);
649  break;
650  }
654  printImmediateInt16(static_cast<uint16_t>(Op.getImm()), STI, O);
655  break;
658  printImmediateV216(Op.getImm(), STI, O);
659  break;
661  case MCOI::OPERAND_PCREL:
662  O << formatDec(Op.getImm());
663  break;
665  // FIXME: This should be removed and handled somewhere else. Seems to come
666  // from a disassembler bug.
667  O << "/*invalid immediate*/";
668  break;
669  default:
670  // We hit this for the immediate instruction bits that don't yet have a
671  // custom printer.
672  llvm_unreachable("unexpected immediate operand type");
673  }
674  } else if (Op.isDFPImm()) {
675  double Value = bit_cast<double>(Op.getDFPImm());
676  // We special case 0.0 because otherwise it will be printed as an integer.
677  if (Value == 0.0)
678  O << "0.0";
679  else {
680  const MCInstrDesc &Desc = MII.get(MI->getOpcode());
681  int RCID = Desc.OpInfo[OpNo].RegClass;
682  unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
683  if (RCBits == 32)
684  printImmediate32(FloatToBits(Value), STI, O);
685  else if (RCBits == 64)
686  printImmediate64(DoubleToBits(Value), STI, O);
687  else
688  llvm_unreachable("Invalid register class size");
689  }
690  } else if (Op.isExpr()) {
691  const MCExpr *Exp = Op.getExpr();
692  Exp->print(O, &MAI);
693  } else {
694  O << "/*INV_OP*/";
695  }
696 
697  // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
698  switch (MI->getOpcode()) {
699  default: break;
700 
701  case AMDGPU::V_CNDMASK_B32_e32_gfx10:
702  case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
703  case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
704  case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
705  case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
706  case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
707  case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
708  case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
709  case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
710  case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
711  case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
712  case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
713 
714  case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
715  case AMDGPU::V_CNDMASK_B32_e32_vi:
716  if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
717  AMDGPU::OpName::src1))
718  printDefaultVccOperand(OpNo, STI, O);
719  break;
720  }
721 
722  if (Desc.TSFlags & SIInstrFlags::MTBUF) {
723  int SOffsetIdx =
724  AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
725  assert(SOffsetIdx != -1);
726  if ((int)OpNo == SOffsetIdx)
727  printSymbolicFormat(MI, STI, O);
728  }
729 }
730 
731 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
732  unsigned OpNo,
733  const MCSubtargetInfo &STI,
734  raw_ostream &O) {
735  unsigned InputModifiers = MI->getOperand(OpNo).getImm();
736 
737  // Use 'neg(...)' instead of '-' to avoid ambiguity.
738  // This is important for integer literals because
739  // -1 is not the same value as neg(1).
740  bool NegMnemo = false;
741 
742  if (InputModifiers & SISrcMods::NEG) {
743  if (OpNo + 1 < MI->getNumOperands() &&
744  (InputModifiers & SISrcMods::ABS) == 0) {
745  const MCOperand &Op = MI->getOperand(OpNo + 1);
746  NegMnemo = Op.isImm() || Op.isDFPImm();
747  }
748  if (NegMnemo) {
749  O << "neg(";
750  } else {
751  O << '-';
752  }
753  }
754 
755  if (InputModifiers & SISrcMods::ABS)
756  O << '|';
757  printOperand(MI, OpNo + 1, STI, O);
758  if (InputModifiers & SISrcMods::ABS)
759  O << '|';
760 
761  if (NegMnemo) {
762  O << ')';
763  }
764 }
765 
766 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
767  unsigned OpNo,
768  const MCSubtargetInfo &STI,
769  raw_ostream &O) {
770  unsigned InputModifiers = MI->getOperand(OpNo).getImm();
771  if (InputModifiers & SISrcMods::SEXT)
772  O << "sext(";
773  printOperand(MI, OpNo + 1, STI, O);
774  if (InputModifiers & SISrcMods::SEXT)
775  O << ')';
776 
777  // Print default vcc/vcc_lo operand of VOP2b.
778  switch (MI->getOpcode()) {
779  default: break;
780 
781  case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
782  case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
783  case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
784  case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
785  if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
786  AMDGPU::OpName::src1))
787  printDefaultVccOperand(OpNo, STI, O);
788  break;
789  }
790 }
791 
792 void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
793  const MCSubtargetInfo &STI,
794  raw_ostream &O) {
795  if (!AMDGPU::isGFX10Plus(STI))
796  llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
797 
798  unsigned Imm = MI->getOperand(OpNo).getImm();
799  O << "dpp8:[" << formatDec(Imm & 0x7);
800  for (size_t i = 1; i < 8; ++i) {
801  O << ',' << formatDec((Imm >> (3 * i)) & 0x7);
802  }
803  O << ']';
804 }
805 
806 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
807  const MCSubtargetInfo &STI,
808  raw_ostream &O) {
809  using namespace AMDGPU::DPP;
810 
811  unsigned Imm = MI->getOperand(OpNo).getImm();
812  const MCInstrDesc &Desc = MII.get(MI->getOpcode());
813  int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
814  AMDGPU::OpName::src0);
815 
816  if (Src0Idx >= 0 &&
817  Desc.OpInfo[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID &&
819  O << " /* 64 bit dpp only supports row_newbcast */";
820  return;
821  } else if (Imm <= DppCtrl::QUAD_PERM_LAST) {
822  O << "quad_perm:[";
823  O << formatDec(Imm & 0x3) << ',';
824  O << formatDec((Imm & 0xc) >> 2) << ',';
825  O << formatDec((Imm & 0x30) >> 4) << ',';
826  O << formatDec((Imm & 0xc0) >> 6) << ']';
827  } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
828  (Imm <= DppCtrl::ROW_SHL_LAST)) {
829  O << "row_shl:";
830  printU4ImmDecOperand(MI, OpNo, O);
831  } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
832  (Imm <= DppCtrl::ROW_SHR_LAST)) {
833  O << "row_shr:";
834  printU4ImmDecOperand(MI, OpNo, O);
835  } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
836  (Imm <= DppCtrl::ROW_ROR_LAST)) {
837  O << "row_ror:";
838  printU4ImmDecOperand(MI, OpNo, O);
839  } else if (Imm == DppCtrl::WAVE_SHL1) {
840  if (AMDGPU::isGFX10Plus(STI)) {
841  O << "/* wave_shl is not supported starting from GFX10 */";
842  return;
843  }
844  O << "wave_shl:1";
845  } else if (Imm == DppCtrl::WAVE_ROL1) {
846  if (AMDGPU::isGFX10Plus(STI)) {
847  O << "/* wave_rol is not supported starting from GFX10 */";
848  return;
849  }
850  O << "wave_rol:1";
851  } else if (Imm == DppCtrl::WAVE_SHR1) {
852  if (AMDGPU::isGFX10Plus(STI)) {
853  O << "/* wave_shr is not supported starting from GFX10 */";
854  return;
855  }
856  O << "wave_shr:1";
857  } else if (Imm == DppCtrl::WAVE_ROR1) {
858  if (AMDGPU::isGFX10Plus(STI)) {
859  O << "/* wave_ror is not supported starting from GFX10 */";
860  return;
861  }
862  O << "wave_ror:1";
863  } else if (Imm == DppCtrl::ROW_MIRROR) {
864  O << "row_mirror";
865  } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
866  O << "row_half_mirror";
867  } else if (Imm == DppCtrl::BCAST15) {
868  if (AMDGPU::isGFX10Plus(STI)) {
869  O << "/* row_bcast is not supported starting from GFX10 */";
870  return;
871  }
872  O << "row_bcast:15";
873  } else if (Imm == DppCtrl::BCAST31) {
874  if (AMDGPU::isGFX10Plus(STI)) {
875  O << "/* row_bcast is not supported starting from GFX10 */";
876  return;
877  }
878  O << "row_bcast:31";
879  } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
880  (Imm <= DppCtrl::ROW_SHARE_LAST)) {
881  if (AMDGPU::isGFX90A(STI)) {
882  O << "row_newbcast:";
883  } else if (AMDGPU::isGFX10Plus(STI)) {
884  O << "row_share:";
885  } else {
886  O << " /* row_newbcast/row_share is not supported on ASICs earlier "
887  "than GFX90A/GFX10 */";
888  return;
889  }
890  printU4ImmDecOperand(MI, OpNo, O);
891  } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
892  (Imm <= DppCtrl::ROW_XMASK_LAST)) {
893  if (!AMDGPU::isGFX10Plus(STI)) {
894  O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
895  return;
896  }
897  O << "row_xmask:";
898  printU4ImmDecOperand(MI, OpNo, O);
899  } else {
900  O << "/* Invalid dpp_ctrl value */";
901  }
902 }
903 
904 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo,
905  const MCSubtargetInfo &STI,
906  raw_ostream &O) {
907  O << " row_mask:";
908  printU4ImmOperand(MI, OpNo, STI, O);
909 }
910 
911 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
912  const MCSubtargetInfo &STI,
913  raw_ostream &O) {
914  O << " bank_mask:";
915  printU4ImmOperand(MI, OpNo, STI, O);
916 }
917 
918 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
919  const MCSubtargetInfo &STI,
920  raw_ostream &O) {
921  unsigned Imm = MI->getOperand(OpNo).getImm();
922  if (Imm) {
923  O << " bound_ctrl:1";
924  }
925 }
926 
927 void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo,
928  const MCSubtargetInfo &STI,
929  raw_ostream &O) {
930  using namespace llvm::AMDGPU::DPP;
931  unsigned Imm = MI->getOperand(OpNo).getImm();
932  if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
933  O << " fi:1";
934  }
935 }
936 
937 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
938  raw_ostream &O) {
939  using namespace llvm::AMDGPU::SDWA;
940 
941  unsigned Imm = MI->getOperand(OpNo).getImm();
942  switch (Imm) {
943  case SdwaSel::BYTE_0: O << "BYTE_0"; break;
944  case SdwaSel::BYTE_1: O << "BYTE_1"; break;
945  case SdwaSel::BYTE_2: O << "BYTE_2"; break;
946  case SdwaSel::BYTE_3: O << "BYTE_3"; break;
947  case SdwaSel::WORD_0: O << "WORD_0"; break;
948  case SdwaSel::WORD_1: O << "WORD_1"; break;
949  case SdwaSel::DWORD: O << "DWORD"; break;
950  default: llvm_unreachable("Invalid SDWA data select operand");
951  }
952 }
953 
954 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
955  const MCSubtargetInfo &STI,
956  raw_ostream &O) {
957  O << "dst_sel:";
958  printSDWASel(MI, OpNo, O);
959 }
960 
961 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
962  const MCSubtargetInfo &STI,
963  raw_ostream &O) {
964  O << "src0_sel:";
965  printSDWASel(MI, OpNo, O);
966 }
967 
968 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
969  const MCSubtargetInfo &STI,
970  raw_ostream &O) {
971  O << "src1_sel:";
972  printSDWASel(MI, OpNo, O);
973 }
974 
975 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
976  const MCSubtargetInfo &STI,
977  raw_ostream &O) {
978  using namespace llvm::AMDGPU::SDWA;
979 
980  O << "dst_unused:";
981  unsigned Imm = MI->getOperand(OpNo).getImm();
982  switch (Imm) {
983  case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
984  case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
985  case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
986  default: llvm_unreachable("Invalid SDWA dest_unused operand");
987  }
988 }
989 
990 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
991  const MCSubtargetInfo &STI, raw_ostream &O,
992  unsigned N) {
993  unsigned Opc = MI->getOpcode();
994  int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en);
995  unsigned En = MI->getOperand(EnIdx).getImm();
996 
997  int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);
998 
999  // If compr is set, print as src0, src0, src1, src1
1000  if (MI->getOperand(ComprIdx).getImm())
1001  OpNo = OpNo - N + N / 2;
1002 
1003  if (En & (1 << N))
1004  printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
1005  else
1006  O << "off";
1007 }
1008 
1009 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
1010  const MCSubtargetInfo &STI,
1011  raw_ostream &O) {
1012  printExpSrcN(MI, OpNo, STI, O, 0);
1013 }
1014 
1015 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
1016  const MCSubtargetInfo &STI,
1017  raw_ostream &O) {
1018  printExpSrcN(MI, OpNo, STI, O, 1);
1019 }
1020 
1021 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
1022  const MCSubtargetInfo &STI,
1023  raw_ostream &O) {
1024  printExpSrcN(MI, OpNo, STI, O, 2);
1025 }
1026 
1027 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
1028  const MCSubtargetInfo &STI,
1029  raw_ostream &O) {
1030  printExpSrcN(MI, OpNo, STI, O, 3);
1031 }
1032 
1033 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
1034  const MCSubtargetInfo &STI,
1035  raw_ostream &O) {
1036  using namespace llvm::AMDGPU::Exp;
1037 
1038  // This is really a 6 bit field.
1039  unsigned Id = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1040 
1041  int Index;
1042  StringRef TgtName;
1043  if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) {
1044  O << ' ' << TgtName;
1045  if (Index >= 0)
1046  O << Index;
1047  } else {
1048  O << " invalid_target_" << Id;
1049  }
1050 }
1051 
1052 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
1053  bool IsPacked, bool HasDstSel) {
1054  int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
1055 
1056  for (int I = 0; I < NumOps; ++I) {
1057  if (!!(Ops[I] & Mod) != DefaultValue)
1058  return false;
1059  }
1060 
1061  if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
1062  return false;
1063 
1064  return true;
1065 }
1066 
1067 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
1068  StringRef Name,
1069  unsigned Mod,
1070  raw_ostream &O) {
1071  unsigned Opc = MI->getOpcode();
1072  int NumOps = 0;
1073  int Ops[3];
1074 
1075  for (int OpName : { AMDGPU::OpName::src0_modifiers,
1076  AMDGPU::OpName::src1_modifiers,
1077  AMDGPU::OpName::src2_modifiers }) {
1078  int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);
1079  if (Idx == -1)
1080  break;
1081 
1082  Ops[NumOps++] = MI->getOperand(Idx).getImm();
1083  }
1084 
1085  const bool HasDstSel =
1086  NumOps > 0 &&
1087  Mod == SISrcMods::OP_SEL_0 &&
1088  MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
1089 
1090  const bool IsPacked =
1091  MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
1092 
1093  if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
1094  return;
1095 
1096  O << Name;
1097  for (int I = 0; I < NumOps; ++I) {
1098  if (I != 0)
1099  O << ',';
1100 
1101  O << !!(Ops[I] & Mod);
1102  }
1103 
1104  if (HasDstSel) {
1105  O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
1106  }
1107 
1108  O << ']';
1109 }
1110 
1111 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1112  const MCSubtargetInfo &STI,
1113  raw_ostream &O) {
1114  unsigned Opc = MI->getOpcode();
1115  if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
1116  Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) {
1117  auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1118  auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
1119  unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
1120  unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0);
1121  if (FI || BC)
1122  O << " op_sel:[" << FI << ',' << BC << ']';
1123  return;
1124  }
1125 
1126  printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O);
1127 }
1128 
1129 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1130  const MCSubtargetInfo &STI,
1131  raw_ostream &O) {
1132  printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O);
1133 }
1134 
1135 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1136  const MCSubtargetInfo &STI,
1137  raw_ostream &O) {
1138  printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
1139 }
1140 
1141 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1142  const MCSubtargetInfo &STI,
1143  raw_ostream &O) {
1144  printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
1145 }
1146 
1147 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1148  const MCSubtargetInfo &STI,
1149  raw_ostream &O) {
1150  unsigned Imm = MI->getOperand(OpNum).getImm();
1151  switch (Imm) {
1152  case 0:
1153  O << "p10";
1154  break;
1155  case 1:
1156  O << "p20";
1157  break;
1158  case 2:
1159  O << "p0";
1160  break;
1161  default:
1162  O << "invalid_param_" << Imm;
1163  }
1164 }
1165 
1166 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1167  const MCSubtargetInfo &STI,
1168  raw_ostream &O) {
1169  unsigned Attr = MI->getOperand(OpNum).getImm();
1170  O << "attr" << Attr;
1171 }
1172 
1173 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1174  const MCSubtargetInfo &STI,
1175  raw_ostream &O) {
1176  unsigned Chan = MI->getOperand(OpNum).getImm();
1177  O << '.' << "xyzw"[Chan & 0x3];
1178 }
1179 
1180 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
1181  const MCSubtargetInfo &STI,
1182  raw_ostream &O) {
1183  using namespace llvm::AMDGPU::VGPRIndexMode;
1184  unsigned Val = MI->getOperand(OpNo).getImm();
1185 
1186  if ((Val & ~ENABLE_MASK) != 0) {
1187  O << formatHex(static_cast<uint64_t>(Val));
1188  } else {
1189  O << "gpr_idx(";
1190  bool NeedComma = false;
1191  for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
1192  if (Val & (1 << ModeId)) {
1193  if (NeedComma)
1194  O << ',';
1195  O << IdSymbolic[ModeId];
1196  NeedComma = true;
1197  }
1198  }
1199  O << ')';
1200  }
1201 }
1202 
1203 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1204  const MCSubtargetInfo &STI,
1205  raw_ostream &O) {
1206  printOperand(MI, OpNo, STI, O);
1207  O << ", ";
1208  printOperand(MI, OpNo + 1, STI, O);
1209 }
1210 
1211 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1213  StringRef Default) {
1214  const MCOperand &Op = MI->getOperand(OpNo);
1215  assert(Op.isImm());
1216  if (Op.getImm() == 1) {
1217  O << Asm;
1218  } else {
1219  O << Default;
1220  }
1221 }
1222 
1223 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1224  raw_ostream &O, char Asm) {
1225  const MCOperand &Op = MI->getOperand(OpNo);
1226  assert(Op.isImm());
1227  if (Op.getImm() == 1)
1228  O << Asm;
1229 }
1230 
1231 void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
1232  const MCSubtargetInfo &STI,
1233  raw_ostream &O) {
1234  printNamedBit(MI, OpNo, O, "high");
1235 }
1236 
1237 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
1238  const MCSubtargetInfo &STI,
1239  raw_ostream &O) {
1240  printNamedBit(MI, OpNo, O, "clamp");
1241 }
1242 
1243 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
1244  const MCSubtargetInfo &STI,
1245  raw_ostream &O) {
1246  int Imm = MI->getOperand(OpNo).getImm();
1247  if (Imm == SIOutMods::MUL2)
1248  O << " mul:2";
1249  else if (Imm == SIOutMods::MUL4)
1250  O << " mul:4";
1251  else if (Imm == SIOutMods::DIV2)
1252  O << " div:2";
1253 }
1254 
1255 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1256  const MCSubtargetInfo &STI,
1257  raw_ostream &O) {
1258  using namespace llvm::AMDGPU::SendMsg;
1259 
1260  const unsigned Imm16 = MI->getOperand(OpNo).getImm();
1261 
1262  uint16_t MsgId;
1263  uint16_t OpId;
1265  decodeMsg(Imm16, MsgId, OpId, StreamId);
1266 
1267  if (isValidMsgId(MsgId, STI) &&
1268  isValidMsgOp(MsgId, OpId, STI) &&
1269  isValidMsgStream(MsgId, OpId, StreamId, STI)) {
1270  O << "sendmsg(" << getMsgName(MsgId);
1271  if (msgRequiresOp(MsgId)) {
1272  O << ", " << getMsgOpName(MsgId, OpId);
1273  if (msgSupportsStream(MsgId, OpId)) {
1274  O << ", " << StreamId;
1275  }
1276  }
1277  O << ')';
1278  } else if (encodeMsg(MsgId, OpId, StreamId) == Imm16) {
1279  O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')';
1280  } else {
1281  O << Imm16; // Unknown imm16 code.
1282  }
1283 }
1284 
1285 static void printSwizzleBitmask(const uint16_t AndMask,
1286  const uint16_t OrMask,
1287  const uint16_t XorMask,
1288  raw_ostream &O) {
1289  using namespace llvm::AMDGPU::Swizzle;
1290 
1291  uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask;
1292  uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1293 
1294  O << "\"";
1295 
1296  for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1297  uint16_t p0 = Probe0 & Mask;
1298  uint16_t p1 = Probe1 & Mask;
1299 
1300  if (p0 == p1) {
1301  if (p0 == 0) {
1302  O << "0";
1303  } else {
1304  O << "1";
1305  }
1306  } else {
1307  if (p0 == 0) {
1308  O << "p";
1309  } else {
1310  O << "i";
1311  }
1312  }
1313  }
1314 
1315  O << "\"";
1316 }
1317 
1318 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1319  const MCSubtargetInfo &STI,
1320  raw_ostream &O) {
1321  using namespace llvm::AMDGPU::Swizzle;
1322 
1323  uint16_t Imm = MI->getOperand(OpNo).getImm();
1324  if (Imm == 0) {
1325  return;
1326  }
1327 
1328  O << " offset:";
1329 
1330  if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1331 
1332  O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
1333  for (unsigned I = 0; I < LANE_NUM; ++I) {
1334  O << ",";
1335  O << formatDec(Imm & LANE_MASK);
1336  Imm >>= LANE_SHIFT;
1337  }
1338  O << ")";
1339 
1340  } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1341 
1342  uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1343  uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK;
1344  uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1345 
1346  if (AndMask == BITMASK_MAX &&
1347  OrMask == 0 &&
1348  countPopulation(XorMask) == 1) {
1349 
1350  O << "swizzle(" << IdSymbolic[ID_SWAP];
1351  O << ",";
1352  O << formatDec(XorMask);
1353  O << ")";
1354 
1355  } else if (AndMask == BITMASK_MAX &&
1356  OrMask == 0 && XorMask > 0 &&
1357  isPowerOf2_64(XorMask + 1)) {
1358 
1359  O << "swizzle(" << IdSymbolic[ID_REVERSE];
1360  O << ",";
1361  O << formatDec(XorMask + 1);
1362  O << ")";
1363 
1364  } else {
1365 
1366  uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1367  if (GroupSize > 1 &&
1368  isPowerOf2_64(GroupSize) &&
1369  OrMask < GroupSize &&
1370  XorMask == 0) {
1371 
1372  O << "swizzle(" << IdSymbolic[ID_BROADCAST];
1373  O << ",";
1374  O << formatDec(GroupSize);
1375  O << ",";
1376  O << formatDec(OrMask);
1377  O << ")";
1378 
1379  } else {
1380  O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1381  O << ",";
1382  printSwizzleBitmask(AndMask, OrMask, XorMask, O);
1383  O << ")";
1384  }
1385  }
1386  } else {
1387  printU16ImmDecOperand(MI, OpNo, O);
1388  }
1389 }
1390 
1391 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
1392  const MCSubtargetInfo &STI,
1393  raw_ostream &O) {
1395 
1396  unsigned SImm16 = MI->getOperand(OpNo).getImm();
1397  unsigned Vmcnt, Expcnt, Lgkmcnt;
1398  decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt);
1399 
1400  bool NeedSpace = false;
1401 
1402  if (Vmcnt != getVmcntBitMask(ISA)) {
1403  O << "vmcnt(" << Vmcnt << ')';
1404  NeedSpace = true;
1405  }
1406 
1407  if (Expcnt != getExpcntBitMask(ISA)) {
1408  if (NeedSpace)
1409  O << ' ';
1410  O << "expcnt(" << Expcnt << ')';
1411  NeedSpace = true;
1412  }
1413 
1414  if (Lgkmcnt != getLgkmcntBitMask(ISA)) {
1415  if (NeedSpace)
1416  O << ' ';
1417  O << "lgkmcnt(" << Lgkmcnt << ')';
1418  }
1419 }
1420 
1421 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1422  const MCSubtargetInfo &STI, raw_ostream &O) {
1423  unsigned Id;
1424  unsigned Offset;
1425  unsigned Width;
1426 
1427  using namespace llvm::AMDGPU::Hwreg;
1428  unsigned Val = MI->getOperand(OpNo).getImm();
1429  decodeHwreg(Val, Id, Offset, Width);
1430  StringRef HwRegName = getHwreg(Id, STI);
1431 
1432  O << "hwreg(";
1433  if (!HwRegName.empty()) {
1434  O << HwRegName;
1435  } else {
1436  O << Id;
1437  }
1438  if (Width != WIDTH_DEFAULT_ || Offset != OFFSET_DEFAULT_) {
1439  O << ", " << Offset << ", " << Width;
1440  }
1441  O << ')';
1442 }
1443 
1444 void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
1445  const MCSubtargetInfo &STI,
1446  raw_ostream &O) {
1447  uint16_t Imm = MI->getOperand(OpNo).getImm();
1448  if (Imm == 0) {
1449  return;
1450  }
1451 
1452  O << ' ' << formatDec(Imm);
1453 }
1454 
1455 #include "AMDGPUGenAsmWriter.inc"
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:164
llvm::AMDGPU::MTBUFFormat::DFMT_DEFAULT
@ DFMT_DEFAULT
Definition: SIDefines.h:466
i
i
Definition: README.txt:29
llvm::AMDGPU::SendMsg::getMsgName
StringRef getMsgName(int64_t MsgId)
Definition: AMDGPUBaseInfo.cpp:1252
llvm::AMDGPU::DPP::ROW_SHL_LAST
@ ROW_SHL_LAST
Definition: SIDefines.h:693
llvm::AMDGPU::DPP::ROW_SHR_FIRST
@ ROW_SHR_FIRST
Definition: SIDefines.h:696
llvm::AMDGPU::DPP::ROW_ROR_FIRST
@ ROW_ROR_FIRST
Definition: SIDefines.h:700
llvm::AMDGPU::getMIMGDimInfoByEncoding
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
llvm::AMDGPU::DPP::QUAD_PERM_LAST
@ QUAD_PERM_LAST
Definition: SIDefines.h:689
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::SIInstrFlags::VOPC
@ VOPC
Definition: SIDefines.h:42
llvm::AMDGPU::Hwreg::getHwreg
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1044
llvm::SIOutMods::DIV2
@ DIV2
Definition: SIDefines.h:225
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:159
allOpsDefaultValue
static bool allOpsDefaultValue(const int *Ops, int NumOps, int Mod, bool IsPacked, bool HasDstSel)
Definition: AMDGPUInstPrinter.cpp:1052
llvm::AMDGPU::DPP::BCAST31
@ BCAST31
Definition: SIDefines.h:717
llvm::AMDGPU::SDWA::BYTE_1
@ BYTE_1
Definition: SIDefines.h:652
llvm::AMDGPU::MTBUFFormat::getDfmtName
StringRef getDfmtName(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:1131
llvm::AMDGPU::SendMsg::encodeMsg
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
Definition: AMDGPUBaseInfo.cpp:1331
llvm::AMDGPU::getIsaVersion
IsaVersion getIsaVersion(StringRef GPU)
Definition: TargetParser.cpp:189
MCInstrDesc.h
llvm::MCOI::OPERAND_IMMEDIATE
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:58
llvm::AMDGPU::Swizzle::BITMASK_OR_SHIFT
@ BITMASK_OR_SHIFT
Definition: SIDefines.h:642
llvm::AMDGPU::OPERAND_REG_IMM_V2FP16
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:153
llvm::AMDGPUInstPrinter::printWaitFlag
void printWaitFlag(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AMDGPUInstPrinter.cpp:1391
llvm::AMDGPU::isLegal64BitDPPControl
LLVM_READNONE bool isLegal64BitDPPControl(unsigned DC)
Definition: AMDGPUBaseInfo.h:907
llvm::AMDGPU::Swizzle::QUAD_PERM_ENC
@ QUAD_PERM_ENC
Definition: SIDefines.h:622
llvm::AMDGPU::getVOP2IsSingle
bool getVOP2IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:304
llvm::AMDGPU::DPP
Definition: SIDefines.h:683
llvm::AMDGPU::DPP::DPP8_FI_1
@ DPP8_FI_1
Definition: SIDefines.h:736
llvm::SIInstrFlags::VOP2
@ VOP2
Definition: SIDefines.h:41
llvm::AMDGPU::Swizzle::LANE_MASK
@ LANE_MASK
Definition: SIDefines.h:630
llvm::AMDGPU::SDWA::BYTE_0
@ BYTE_0
Definition: SIDefines.h:651
llvm::AMDGPU::OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:155
llvm::FloatToBits
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
Definition: MathExtras.h:663
printOperand
static bool printOperand(raw_ostream &OS, const SelectionDAG *G, const SDValue Value)
Definition: SelectionDAGDumper.cpp:946
llvm::AMDGPU::VGPRIndexMode::IdSymbolic
const char *const IdSymbolic[]
Definition: AMDGPUAsmUtils.cpp:353
llvm::AMDGPUInstPrinter::printOModSI
void printOModSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AMDGPUInstPrinter.cpp:1243
llvm::AMDGPU::MTBUFFormat::NFMT_DEFAULT
@ NFMT_DEFAULT
Definition: SIDefines.h:487
llvm::AMDGPU::SDWA::UNUSED_PRESERVE
@ UNUSED_PRESERVE
Definition: SIDefines.h:663
llvm::AMDGPU::Swizzle::BITMASK_XOR_SHIFT
@ BITMASK_XOR_SHIFT
Definition: SIDefines.h:643
llvm::AMDGPU::DPP::ROW_MIRROR
@ ROW_MIRROR
Definition: SIDefines.h:714
llvm::AMDGPU::Swizzle::BITMASK_WIDTH
@ BITMASK_WIDTH
Definition: SIDefines.h:639
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:80
llvm::SIInstrFlags::FlatScratch
@ FlatScratch
Definition: SIDefines.h:117
llvm::AMDGPU::SendMsg
Definition: SIDefines.h:302
AMDGPUAsmUtils.h
llvm::AMDGPU::getVmcntBitMask
unsigned getVmcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:894
llvm::SISrcMods::DST_OP_SEL
@ DST_OP_SEL
Definition: SIDefines.h:216
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
TargetParser.h
llvm::AMDGPU::getNamedOperandIdx
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
llvm::AMDGPU::DPP::ROW_SHL_FIRST
@ ROW_SHL_FIRST
Definition: SIDefines.h:692
llvm::AMDGPUInstPrinter::printHigh
void printHigh(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AMDGPUInstPrinter.cpp:1231
llvm::AMDGPU::SendMsg::getMsgOpName
StringRef getMsgOpName(int64_t MsgId, int64_t OpId)
Definition: AMDGPUBaseInfo.cpp:1289
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::cl::ReallyHidden
@ ReallyHidden
Definition: CommandLine.h:144
llvm::AMDGPU::MTBUFFormat::isValidDfmtNfmt
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1158
llvm::AMDGPU::SDWA::UNUSED_SEXT
@ UNUSED_SEXT
Definition: SIDefines.h:662
llvm::AMDGPU::Hwreg::decodeHwreg
void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width)
Definition: AMDGPUBaseInfo.cpp:1048
llvm::AMDGPU::IsaVersion
Instruction set architecture version.
Definition: TargetParser.h:106
llvm::AMDGPU::Swizzle::BITMASK_PERM_ENC_MASK
@ BITMASK_PERM_ENC_MASK
Definition: SIDefines.h:626
CommandLine.h
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
llvm::AMDGPU::isGFX90A
bool isGFX90A(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1475
llvm::AMDGPU::OPERAND_REG_IMM_FP32
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:148
llvm::AMDGPUInstPrinter::printSendMsg
void printSendMsg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AMDGPUInstPrinter.cpp:1255
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:203
llvm::AMDGPU::SDWA::UNUSED_PAD
@ UNUSED_PAD
Definition: SIDefines.h:661
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:160
llvm::AMDGPU::VGPRIndexMode::ENABLE_MASK
@ ENABLE_MASK
Definition: SIDefines.h:248
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:118
llvm::AMDGPU::MTBUFFormat::UFMT_DEFAULT
@ UFMT_DEFAULT
Definition: SIDefines.h:603
llvm::AMDGPU::CPol::DLC
@ DLC
Definition: SIDefines.h:295
llvm::AMDGPU::Swizzle::BITMASK_MAX
@ BITMASK_MAX
Definition: SIDefines.h:638
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:177
llvm::AMDGPU::DPP::ROW_XMASK_FIRST
@ ROW_XMASK_FIRST
Definition: SIDefines.h:726
llvm::AMDGPUInstPrinter::printRegName
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
Definition: AMDGPUInstPrinter.cpp:33
MCInstrInfo.h
llvm::DoubleToBits
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
Definition: MathExtras.h:653
llvm::AMDGPU::Hwreg::Id
Id
Definition: SIDefines.h:362
llvm::AMDGPU::SDWA::BYTE_2
@ BYTE_2
Definition: SIDefines.h:653
MCInst.h
llvm::AMDGPU::MTBUFFormat
Definition: SIDefines.h:442
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::AMDGPU
Definition: AMDGPUMetadataVerifier.h:22
llvm::AMDGPU::OPERAND_REG_IMM_FP64
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:149
OpName
Definition: R600Defines.h:62
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::raw_ostream::flush
void flush()
Definition: raw_ostream.h:186
llvm::AMDGPU::decodeWaitcnt
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
Definition: AMDGPUBaseInfo.cpp:945
llvm::AMDGPU::OPERAND_REG_IMM_V2FP32
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:156
llvm::SIInstrFlags::FlatGlobal
@ FlatGlobal
Definition: SIDefines.h:102
llvm::AMDGPUInstPrinter::printClampSI
void printClampSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AMDGPUInstPrinter.cpp:1237
llvm::MCOI::OPERAND_PCREL
@ OPERAND_PCREL
Definition: MCInstrDesc.h:61
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:89
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT32
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:167
llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat
bool isValidUnifiedFormat(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:1190
llvm::AMDGPU::isCI
bool isCI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1437
llvm::AMDGPU::SendMsg::StreamId
StreamId
Definition: SIDefines.h:348
llvm::AMDGPU::isGFX10Plus
bool isGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1457
llvm::AMDGPU::Swizzle::ID_REVERSE
@ ID_REVERSE
Definition: SIDefines.h:614
llvm::AMDGPUInstPrinter::printSwizzle
void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AMDGPUInstPrinter.cpp:1318
llvm::AMDGPUInstPrinter::printIfSet
static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, StringRef Asm, StringRef Default="")
Definition: AMDGPUInstPrinter.cpp:1211
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::MCInstrDesc::hasImplicitDefOfPhysReg
bool hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
Return true if this instruction implicitly defines the specified physical register.
Definition: MCInstrDesc.cpp:33
llvm::M68kBeads::Imm16
@ Imm16
Definition: M68kBaseInfo.h:64
llvm::SIInstrFlags::DPP
@ DPP
Definition: SIDefines.h:50
llvm::AMDGPU::Swizzle::QUAD_PERM_ENC_MASK
@ QUAD_PERM_ENC_MASK
Definition: SIDefines.h:623
llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:151
llvm::SIInstrFlags::MTBUF
@ MTBUF
Definition: SIDefines.h:55
llvm::cl::opt< bool >
llvm::AMDGPU::Swizzle::IdSymbolic
const char *const IdSymbolic[]
Definition: AMDGPUAsmUtils.cpp:340
llvm::AMDGPU::getRegBitWidth
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
Definition: AMDGPUBaseInfo.cpp:1610
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:206
llvm::AMDGPU::getExpcntBitMask
unsigned getExpcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:903
llvm::AMDGPU::Swizzle::LANE_NUM
@ LANE_NUM
Definition: SIDefines.h:633
llvm::countPopulation
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:567
llvm::AMDGPU::VGPRIndexMode::ID_MIN
@ ID_MIN
Definition: SIDefines.h:238
llvm::AMDGPU::isInlinableIntLiteral
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
Definition: AMDGPUBaseInfo.h:840
AMDGPUMCTargetDesc.h
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:391
llvm::SIInstrFlags::VOP1
@ VOP1
Definition: SIDefines.h:40
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:161
llvm::isUInt< 16 >
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:408
llvm::SIInstrFlags::IsPacked
@ IsPacked
Definition: SIDefines.h:96
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:152
llvm::AMDGPU::CPol::GLC
@ GLC
Definition: SIDefines.h:293
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
uint64_t
llvm::AMDGPU::Hwreg
Definition: SIDefines.h:360
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:163
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:95
llvm::MCSubtargetInfo::getCPU
StringRef getCPU() const
Definition: MCSubtargetInfo.h:108
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::AMDGPU::Swizzle::ID_BROADCAST
@ ID_BROADCAST
Definition: SIDefines.h:615
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:59
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::AMDGPU::DPP::WAVE_SHL1
@ WAVE_SHL1
Definition: SIDefines.h:702
llvm::AMDGPU::Swizzle::ID_QUAD_PERM
@ ID_QUAD_PERM
Definition: SIDefines.h:611
llvm::AMDGPU::SDWA::DWORD
@ DWORD
Definition: SIDefines.h:657
AMDGPUInstPrinter.h
llvm::HighlightColor::Address
@ Address
llvm::isUInt< 32 >
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:411
llvm::SISrcMods::NEG
@ NEG
Definition: SIDefines.h:210
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AMDGPU::DPP::BCAST15
@ BCAST15
Definition: SIDefines.h:716
llvm::AMDGPU::SendMsg::msgRequiresOp
bool msgRequiresOp(int64_t MsgId)
Definition: AMDGPUBaseInfo.cpp:1314
llvm::AMDGPUInstPrinter::printEndpgm
void printEndpgm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AMDGPUInstPrinter.cpp:1444
llvm::AMDGPU::Hwreg::OFFSET_DEFAULT_
@ OFFSET_DEFAULT_
Definition: SIDefines.h:392
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT16
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:175
llvm::AMDGPU::Swizzle::BITMASK_MASK
@ BITMASK_MASK
Definition: SIDefines.h:637
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:206
llvm::AMDGPU::Exp::isSupportedTgtId
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1111
llvm::AMDGPU::CPol::ALL
@ ALL
Definition: SIDefines.h:297
llvm::AMDGPU::Swizzle
Definition: SIDefines.h:608
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:165
llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:152
llvm::AMDGPU::Swizzle::BITMASK_AND_SHIFT
@ BITMASK_AND_SHIFT
Definition: SIDefines.h:641
llvm::SIInstrFlags::SDWA
@ SDWA
Definition: SIDefines.h:49
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:178
llvm::AMDGPU::Exp
Definition: SIDefines.h:741
llvm::SISrcMods::SEXT
@ SEXT
Definition: SIDefines.h:212
llvm::AMDGPU::OPERAND_REG_IMM_INT16
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:147
llvm::AMDGPU::CPol::SCC
@ SCC
Definition: SIDefines.h:296
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:176
llvm::AMDGPU::SendMsg::msgSupportsStream
bool msgSupportsStream(int64_t MsgId, int64_t OpId)
Definition: AMDGPUBaseInfo.cpp:1318
llvm::MSP430Attrs::ISA
ISA
Definition: MSP430Attributes.h:36
llvm::AMDGPU::Hwreg::WIDTH_DEFAULT_
@ WIDTH_DEFAULT_
Definition: SIDefines.h:415
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::AMDGPU::DPP::ROW_HALF_MIRROR
@ ROW_HALF_MIRROR
Definition: SIDefines.h:715
llvm::AMDGPU::getVOP3IsSingle
bool getVOP3IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:309
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
uint32_t
llvm::AMDGPU::VGPRIndexMode::ID_MAX
@ ID_MAX
Definition: SIDefines.h:239
llvm::SIInstrFlags::VOP3_OPSEL
@ VOP3_OPSEL
Definition: SIDefines.h:78
llvm::AMDGPU::Exp::getTgtName
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
Definition: AMDGPUBaseInfo.cpp:1077
llvm::format
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:290
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPU::SDWA
Definition: SIDefines.h:648
llvm::SISrcMods::NEG_HI
@ NEG_HI
Definition: SIDefines.h:213
llvm::AMDGPU::DPP::ROW_XMASK_LAST
@ ROW_XMASK_LAST
Definition: SIDefines.h:727
llvm::AMDGPU::SendMsg::isValidMsgOp
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1269
llvm::isInt< 16 >
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:370
llvm::AMDGPU::isSI
bool isSI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1433
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:179
llvm::AMDGPU::SDWA::WORD_1
@ WORD_1
Definition: SIDefines.h:656
llvm::SIOutMods::MUL4
@ MUL4
Definition: SIDefines.h:224
llvm::AMDGPU::DPP::WAVE_ROL1
@ WAVE_ROL1
Definition: SIDefines.h:705
llvm::SISrcMods::ABS
@ ABS
Definition: SIDefines.h:211
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::SIOutMods::MUL2
@ MUL2
Definition: SIDefines.h:223
llvm::AMDGPU::OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:154
uint16_t
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_DEFAULT
@ DFMT_NFMT_DEFAULT
Definition: SIDefines.h:495
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
SIDefines.h
Keep16BitSuffixes
static cl::opt< bool > Keep16BitSuffixes("amdgpu-keep-16-bit-reg-suffixes", cl::desc("Keep .l and .h suffixes in asm for debugging purposes"), cl::init(false), cl::ReallyHidden)
llvm::SIInstrFlags::VOP3
@ VOP3
Definition: SIDefines.h:45
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:166
llvm::AMDGPU::CPol::SLC
@ SLC
Definition: SIDefines.h:294
llvm::AMDGPU::DPP::ROW_SHR_LAST
@ ROW_SHR_LAST
Definition: SIDefines.h:697
llvm::AMDGPU::Swizzle::ID_SWAP
@ ID_SWAP
Definition: SIDefines.h:613
llvm::AMDGPU::DPP::ROW_SHARE_LAST
@ ROW_SHARE_LAST
Definition: SIDefines.h:724
llvm::AMDGPU::getVOP1IsSingle
bool getVOP1IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:299
llvm::AMDGPU::MTBUFFormat::decodeDfmtNfmt
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
Definition: AMDGPUBaseInfo.cpp:1173
llvm::AMDGPUInstPrinter::printHwreg
void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AMDGPUInstPrinter.cpp:1421
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:168
llvm::AMDGPU::SendMsg::decodeMsg
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId)
Definition: AMDGPUBaseInfo.cpp:1322
llvm::AMDGPU::SendMsg::isValidMsgStream
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1294
llvm::AMDGPU::Swizzle::LANE_SHIFT
@ LANE_SHIFT
Definition: SIDefines.h:632
llvm::AMDGPUInstPrinter::printInst
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
Definition: AMDGPUInstPrinter.cpp:49
llvm::AMDGPU::MTBUFFormat::getNfmtName
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1153
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:414
llvm::AMDGPU::getLgkmcntBitMask
unsigned getLgkmcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:907
llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName
StringRef getUnifiedFormatName(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:1186
llvm::AMDGPU::SDWA::WORD_0
@ WORD_0
Definition: SIDefines.h:655
llvm::AMDGPU::DPP::ROW_ROR_LAST
@ ROW_ROR_LAST
Definition: SIDefines.h:701
llvm::SISrcMods::OP_SEL_0
@ OP_SEL_0
Definition: SIDefines.h:214
llvm::AMDGPU::Swizzle::ID_BITMASK_PERM
@ ID_BITMASK_PERM
Definition: SIDefines.h:612
printSwizzleBitmask
static void printSwizzleBitmask(const uint16_t AndMask, const uint16_t OrMask, const uint16_t XorMask, raw_ostream &O)
Definition: AMDGPUInstPrinter.cpp:1285
N
#define N
llvm::SISrcMods::OP_SEL_1
@ OP_SEL_1
Definition: SIDefines.h:215
llvm::codeview::CompileSym3Flags::Exp
@ Exp
llvm::AMDGPU::OPERAND_REG_IMM_INT32
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:145
llvm::MCOI::OPERAND_UNKNOWN
@ OPERAND_UNKNOWN
Definition: MCInstrDesc.h:57
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:162
RegName
#define RegName(no)
llvm::HexStyle::Asm
@ Asm
0ffh
Definition: MCInstPrinter.h:34
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::AMDGPU::DPP::DPP_FI_1
@ DPP_FI_1
Definition: SIDefines.h:734
llvm::AMDGPU::OPERAND_REG_IMM_FP16
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:150
llvm::cl::desc
Definition: CommandLine.h:412
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:180
Mod
Module * Mod
Definition: PassBuilderBindings.cpp:54
llvm::AMDGPU::SDWA::BYTE_3
@ BYTE_3
Definition: SIDefines.h:654
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:232
llvm::isPowerOf2_64
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
Definition: MathExtras.h:496
llvm::AMDGPU::SendMsg::isValidMsgId
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1229
llvm::AMDGPU::VGPRIndexMode
Definition: SIDefines.h:230
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::AMDGPU::Swizzle::BITMASK_PERM_ENC
@ BITMASK_PERM_ENC
Definition: SIDefines.h:625
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
SIRegisterInfo.h
llvm::AMDGPU::OPERAND_REG_IMM_INT64
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:146
llvm::AMDGPU::DPP::WAVE_ROR1
@ WAVE_ROR1
Definition: SIDefines.h:711
llvm::AMDGPUInstPrinter::printRegOperand
static void printRegOperand(unsigned RegNo, raw_ostream &O, const MCRegisterInfo &MRI)
Definition: AMDGPUInstPrinter.cpp:341
llvm::AMDGPU::DPP::WAVE_SHR1
@ WAVE_SHR1
Definition: SIDefines.h:708
AMDGPUBaseInfo.h
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:181
getRegisterName
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)
Definition: MIParser.cpp:1328
llvm::AMDGPU::DPP::ROW_SHARE_FIRST
@ ROW_SHARE_FIRST
Definition: SIDefines.h:723