56 void getMachineOpValueT16Lo128(
const MCInst &
MI,
unsigned OpNo,
APInt &
Op,
83 uint64_t getImplicitOpSelHiEncoding(
int Opcode)
const;
90 std::optional<uint32_t> getLitEncoding(
const MCOperand &MO,
108template <
typename IntTy>
110 if (Imm >= 0 && Imm <= 64)
113 if (Imm >= -16 && Imm <= -1)
114 return 192 + std::abs(Imm);
121 return IntImm == 0 ? 255 : IntImm;
154 STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm))
165 if (Val == llvm::bit_cast<uint32_t>(0.5f))
168 if (Val == llvm::bit_cast<uint32_t>(-0.5f))
171 if (Val == llvm::bit_cast<uint32_t>(1.0f))
174 if (Val == llvm::bit_cast<uint32_t>(-1.0f))
177 if (Val == llvm::bit_cast<uint32_t>(2.0f))
180 if (Val == llvm::bit_cast<uint32_t>(-2.0f))
183 if (Val == llvm::bit_cast<uint32_t>(4.0f))
186 if (Val == llvm::bit_cast<uint32_t>(-4.0f))
189 if (Val == 0x3e22f983 &&
190 STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm))
201 if (Val == llvm::bit_cast<uint64_t>(0.5))
204 if (Val == llvm::bit_cast<uint64_t>(-0.5))
207 if (Val == llvm::bit_cast<uint64_t>(1.0))
210 if (Val == llvm::bit_cast<uint64_t>(-1.0))
213 if (Val == llvm::bit_cast<uint64_t>(2.0))
216 if (Val == llvm::bit_cast<uint64_t>(-2.0))
219 if (Val == llvm::bit_cast<uint64_t>(4.0))
222 if (Val == llvm::bit_cast<uint64_t>(-4.0))
225 if (Val == 0x3fc45f306dc9c882 &&
226 STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm))
232std::optional<uint32_t>
233AMDGPUMCCodeEmitter::getLitEncoding(
const MCOperand &MO,
238 const auto *
C = dyn_cast<MCConstantExpr>(MO.
getExpr());
287 if (!isUInt<16>(Imm) && STI.
hasFeature(AMDGPU::FeatureVOP3Literal))
310uint64_t AMDGPUMCCodeEmitter::getImplicitOpSelHiEncoding(
int Opcode)
const {
311 using namespace AMDGPU::VOP3PEncoding;
312 using namespace AMDGPU::OpName;
327 Desc.hasImplicitDefOfPhysReg(AMDGPU::EXEC);
330void AMDGPUMCCodeEmitter::encodeInstruction(
const MCInst &
MI,
334 int Opcode =
MI.getOpcode();
335 APInt Encoding, Scratch;
336 getBinaryCodeForInstr(
MI, Fixups, Encoding, Scratch, STI);
338 unsigned bytes =
Desc.getSize();
343 Opcode == AMDGPU::V_ACCVGPR_READ_B32_vi ||
344 Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_vi) {
345 Encoding |= getImplicitOpSelHiEncoding(Opcode);
355 assert((Encoding & 0xFF) == 0);
356 Encoding |=
MRI.getEncodingValue(AMDGPU::EXEC_LO);
359 for (
unsigned i = 0; i < bytes; i++) {
366 AMDGPU::OpName::vaddr0);
368 AMDGPU::OpName::srsrc);
369 assert(vaddr0 >= 0 && srsrc > vaddr0);
370 unsigned NumExtraAddrs = srsrc - vaddr0 - 1;
371 unsigned NumPadding = (-NumExtraAddrs) & 3;
373 for (
unsigned i = 0; i < NumExtraAddrs; ++i) {
374 getMachineOpValue(
MI,
MI.getOperand(vaddr0 + 1 + i), Encoding, Fixups,
381 if ((bytes > 8 && STI.
hasFeature(AMDGPU::FeatureVOP3Literal)) ||
382 (bytes > 4 && !STI.
hasFeature(AMDGPU::FeatureVOP3Literal)))
390 for (
unsigned i = 0, e =
Desc.getNumOperands(); i < e; ++i) {
398 auto Enc = getLitEncoding(
Op,
Desc.operands()[i], STI);
399 if (!Enc || *Enc != 255)
407 else if (
Op.isExpr()) {
408 if (
const auto *
C = dyn_cast<MCConstantExpr>(
Op.getExpr()))
411 }
else if (!
Op.isExpr())
414 support::endian::write<uint32_t>(CB, Imm, support::endianness::little);
421void AMDGPUMCCodeEmitter::getSOPPBrEncoding(
const MCInst &
MI,
unsigned OpNo,
433 getMachineOpValue(
MI, MO,
Op, Fixups, STI);
437void AMDGPUMCCodeEmitter::getSMEMOffsetEncoding(
440 auto Offset =
MI.getOperand(OpNo).getImm();
446void AMDGPUMCCodeEmitter::getSDWASrcEncoding(
const MCInst &
MI,
unsigned OpNo,
450 using namespace AMDGPU::SDWA;
458 RegEnc |=
MRI.getEncodingValue(Reg);
459 RegEnc &= SDWA9EncValues::SRC_VGPR_MASK;
461 RegEnc |= SDWA9EncValues::SRC_SGPR_MASK;
467 auto Enc = getLitEncoding(MO,
Desc.operands()[OpNo], STI);
468 if (Enc && *Enc != 255) {
469 Op = *Enc | SDWA9EncValues::SRC_SGPR_MASK;
477void AMDGPUMCCodeEmitter::getSDWAVopcDstEncoding(
480 using namespace AMDGPU::SDWA;
487 if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) {
488 RegEnc |=
MRI.getEncodingValue(Reg);
489 RegEnc &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
490 RegEnc |= SDWA9EncValues::VOPC_DST_VCC_MASK;
495void AMDGPUMCCodeEmitter::getAVOperandEncoding(
498 unsigned Reg =
MI.getOperand(OpNo).getReg();
504 if (
MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) ||
505 MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) ||
506 MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) ||
507 MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) ||
508 MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) ||
509 MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) ||
510 MRI.getRegClass(AMDGPU::AReg_224RegClassID).contains(Reg) ||
511 MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) ||
512 MRI.getRegClass(AMDGPU::AReg_288RegClassID).contains(Reg) ||
513 MRI.getRegClass(AMDGPU::AReg_320RegClassID).contains(Reg) ||
514 MRI.getRegClass(AMDGPU::AReg_352RegClassID).contains(Reg) ||
515 MRI.getRegClass(AMDGPU::AReg_384RegClassID).contains(Reg) ||
516 MRI.getRegClass(AMDGPU::AReg_512RegClassID).contains(Reg) ||
517 MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg))
526 auto *SE = cast<MCSymbolRefExpr>(Expr);
532 auto *BE = cast<MCBinaryExpr>(Expr);
538 return needsPCRel(cast<MCUnaryExpr>(Expr)->getSubExpr());
546void AMDGPUMCCodeEmitter::getMachineOpValue(
const MCInst &
MI,
554 unsigned OpNo = &MO -
MI.begin();
555 getMachineOpValueCommon(
MI, MO, OpNo,
Op, Fixups, STI);
558void AMDGPUMCCodeEmitter::getMachineOpValueT16(
564void AMDGPUMCCodeEmitter::getMachineOpValueT16Lo128(
573 assert((!IsVGPR || isUInt<7>(RegIdx)) &&
"VGPR0-VGPR127 expected!");
574 Op = (IsVGPR ? 0x100 : 0) | (IsHi ? 0x80 : 0) | RegIdx;
577 getMachineOpValueCommon(
MI, MO, OpNo,
Op, Fixups, STI);
580void AMDGPUMCCodeEmitter::getMachineOpValueCommon(
610 if (
auto Enc = getLitEncoding(MO,
Desc.operands()[OpNo], STI)) {
614 }
else if (MO.
isImm()) {
622#include "AMDGPUGenMCCodeEmitter.inc"
unsigned const MachineRegisterInfo * MRI
static uint32_t getLit16IntEncoding(uint16_t Val, const MCSubtargetInfo &STI)
static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI)
static bool isVCMPX64(const MCInstrDesc &Desc)
static uint32_t getLit16Encoding(uint16_t Val, const MCSubtargetInfo &STI)
static uint32_t getIntInlineImmEncoding(IntTy Imm)
static bool needsPCRel(const MCExpr *Expr)
static uint32_t getLit32Encoding(uint32_t Val, const MCSubtargetInfo &STI)
Provides AMDGPU specific target descriptions.
This file implements a class to represent arbitrary precision integral constant values and operations...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Class for arbitrary precision integers.
uint64_t extractBitsAsZExtValue(unsigned numBits, unsigned bitPosition) const
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value.
static APInt getZero(unsigned numBits)
Get the '0' value for the specified bit-width.
This class represents an Operation in the Expression.
MCCodeEmitter - Generic instruction encoding interface.
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
Base class for the full range of assembler expressions which are needed for parsing.
@ Unary
Unary expressions.
@ Constant
Constant expressions.
@ SymbolRef
References to labels and assigned expressions.
@ Target
Target specific expression.
@ Binary
Binary expressions.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
Interface to description of machine instruction set.
This holds information about one operand of a machine instruction, indicating the register class for ...
uint8_t OperandType
Information about the type of the operand.
Instances of this class represent operands of the MCInst class.
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
@ fixup_si_sopp_br
16-bit PC relative fixup for SOPP branch instructions.
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this an AMDGPU specific source operand? These include registers, inline constants,...
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
bool isGFX10Plus(const MCSubtargetInfo &STI)
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
@ OPERAND_REG_INLINE_C_V2INT32
@ OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
@ OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
@ OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
bool isVI(const MCSubtargetInfo &STI)
@ C
The default llvm calling convention, compatible with C.
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_PCRel_4
A four-byte pc relative fixup.
@ FK_Data_4
A four-byte fixup.
MCCodeEmitter * createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Description of the encoding of one expression Op.