LLVM  14.0.0git
SIPostRABundler.cpp
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1 //===-- SIPostRABundler.cpp -----------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This pass creates bundles of memory instructions to protect adjacent loads
11 /// and stores from being rescheduled apart from each other post-RA.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPU.h"
16 #include "GCNSubtarget.h"
17 #include "llvm/ADT/SmallSet.h"
19 
20 using namespace llvm;
21 
22 #define DEBUG_TYPE "si-post-ra-bundler"
23 
24 namespace {
25 
26 class SIPostRABundler : public MachineFunctionPass {
27 public:
28  static char ID;
29 
30 public:
31  SIPostRABundler() : MachineFunctionPass(ID) {
33  }
34 
35  bool runOnMachineFunction(MachineFunction &MF) override;
36 
37  StringRef getPassName() const override {
38  return "SI post-RA bundler";
39  }
40 
41  void getAnalysisUsage(AnalysisUsage &AU) const override {
42  AU.setPreservesAll();
44  }
45 
46 private:
47  const SIRegisterInfo *TRI;
48 
50 
51  void collectUsedRegUnits(const MachineInstr &MI,
52  BitVector &UsedRegUnits) const;
53 
54  bool isBundleCandidate(const MachineInstr &MI) const;
55  bool isDependentLoad(const MachineInstr &MI) const;
56  bool canBundle(const MachineInstr &MI, const MachineInstr &NextMI) const;
57 };
58 
59 constexpr uint64_t MemFlags = SIInstrFlags::MTBUF | SIInstrFlags::MUBUF |
62 
63 } // End anonymous namespace.
64 
65 INITIALIZE_PASS(SIPostRABundler, DEBUG_TYPE, "SI post-RA bundler", false, false)
66 
67 char SIPostRABundler::ID = 0;
68 
69 char &llvm::SIPostRABundlerID = SIPostRABundler::ID;
70 
72  return new SIPostRABundler();
73 }
74 
75 bool SIPostRABundler::isDependentLoad(const MachineInstr &MI) const {
76  if (!MI.mayLoad())
77  return false;
78 
79  for (const MachineOperand &Op : MI.explicit_operands()) {
80  if (!Op.isReg())
81  continue;
82  Register Reg = Op.getReg();
83  for (Register Def : Defs)
84  if (TRI->regsOverlap(Reg, Def))
85  return true;
86  }
87 
88  return false;
89 }
90 
91 void SIPostRABundler::collectUsedRegUnits(const MachineInstr &MI,
92  BitVector &UsedRegUnits) const {
93  if (MI.isDebugInstr())
94  return;
95 
96  for (const MachineOperand &Op : MI.operands()) {
97  if (!Op.isReg() || !Op.readsReg())
98  continue;
99 
100  Register Reg = Op.getReg();
101  assert(!Op.getSubReg() &&
102  "subregister indexes should not be present after RA");
103 
104  for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
105  UsedRegUnits.set(*Units);
106  }
107 }
108 
109 bool SIPostRABundler::isBundleCandidate(const MachineInstr &MI) const {
110  const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags;
111  return IMemFlags != 0 && MI.mayLoadOrStore() && !MI.isBundled();
112 }
113 
114 bool SIPostRABundler::canBundle(const MachineInstr &MI,
115  const MachineInstr &NextMI) const {
116  const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags;
117 
118  return (IMemFlags != 0 && MI.mayLoadOrStore() && !NextMI.isBundled() &&
119  NextMI.mayLoad() == MI.mayLoad() && NextMI.mayStore() == MI.mayStore() &&
120  ((NextMI.getDesc().TSFlags & MemFlags) == IMemFlags) &&
121  !isDependentLoad(NextMI));
122 }
123 
124 bool SIPostRABundler::runOnMachineFunction(MachineFunction &MF) {
125  if (skipFunction(MF.getFunction()))
126  return false;
127 
128  TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
129  BitVector BundleUsedRegUnits(TRI->getNumRegUnits());
130  BitVector KillUsedRegUnits(TRI->getNumRegUnits());
131 
132  bool Changed = false;
133  for (MachineBasicBlock &MBB : MF) {
137 
138  for (auto I = B; I != E; I = Next) {
139  Next = std::next(I);
140  if (!isBundleCandidate(*I))
141  continue;
142 
143  assert(Defs.empty());
144 
145  if (I->getNumExplicitDefs() != 0)
146  Defs.insert(I->defs().begin()->getReg());
147 
148  MachineBasicBlock::instr_iterator BundleStart = I;
150  unsigned ClauseLength = 1;
151  for (I = Next; I != E; I = Next) {
152  Next = std::next(I);
153 
154  assert(BundleEnd != I);
155  if (canBundle(*BundleEnd, *I)) {
156  BundleEnd = I;
157  if (I->getNumExplicitDefs() != 0)
158  Defs.insert(I->defs().begin()->getReg());
159  ++ClauseLength;
160  } else if (!I->isMetaInstruction()) {
161  // Allow meta instructions in between bundle candidates, but do not
162  // start or end a bundle on one.
163  //
164  // TODO: It may be better to move meta instructions like dbg_value
165  // after the bundle. We're relying on the memory legalizer to unbundle
166  // these.
167  break;
168  }
169  }
170 
171  Next = std::next(BundleEnd);
172  if (ClauseLength > 1) {
173  Changed = true;
174 
175  // Before register allocation, kills are inserted after potential soft
176  // clauses to hint register allocation. Look for kills that look like
177  // this, and erase them.
178  if (Next != E && Next->isKill()) {
179 
180  // TODO: Should maybe back-propagate kill flags to the bundle.
181  for (const MachineInstr &BundleMI : make_range(BundleStart, Next))
182  collectUsedRegUnits(BundleMI, BundleUsedRegUnits);
183 
184  BundleUsedRegUnits.flip();
185 
186  while (Next != E && Next->isKill()) {
187  MachineInstr &Kill = *Next;
188  collectUsedRegUnits(Kill, KillUsedRegUnits);
189 
190  KillUsedRegUnits &= BundleUsedRegUnits;
191 
192  // Erase the kill if it's a subset of the used registers.
193  //
194  // TODO: Should we just remove all kills? Is there any real reason to
195  // keep them after RA?
196  if (KillUsedRegUnits.none()) {
197  ++Next;
198  Kill.eraseFromParent();
199  } else
200  break;
201 
202  KillUsedRegUnits.reset();
203  }
204 
205  BundleUsedRegUnits.reset();
206  }
207 
208  finalizeBundle(MBB, BundleStart, Next);
209  }
210 
211  Defs.clear();
212  }
213  }
214 
215  return Changed;
216 }
llvm::createSIPostRABundlerPass
FunctionPass * createSIPostRABundlerPass()
Definition: SIPostRABundler.cpp:71
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
llvm::SIInstrFlags::FLAT
@ FLAT
Definition: SIDefines.h:58
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1005
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::SIInstrFlags::DS
@ DS
Definition: SIDefines.h:59
llvm::MachineInstr::isBundled
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:391
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:486
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::MCRegisterInfo::getNumRegUnits
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
Definition: MCRegisterInfo.h:505
llvm::SIPostRABundlerID
char & SIPostRABundlerID
Definition: SIPostRABundler.cpp:69
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
llvm::finalizeBundle
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
Definition: MachineInstrBundle.cpp:123
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:203
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
GCNSubtarget.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register regA, Register regB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:418
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::BitVector
Definition: BitVector.h:74
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:634
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::SIInstrFlags::MUBUF
@ MUBUF
Definition: SIDefines.h:53
I
#define I(x, y, z)
Definition: MD5.cpp:59
MachineFunctionPass.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::initializeSIPostRABundlerPass
void initializeSIPostRABundlerPass(PassRegistry &)
llvm::MachineBasicBlock::instr_begin
instr_iterator instr_begin()
Definition: MachineBasicBlock.h:252
llvm::MachineBasicBlock::instr_end
instr_iterator instr_end()
Definition: MachineBasicBlock.h:254
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::SIInstrFlags::SMRD
@ SMRD
Definition: SIDefines.h:55
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
AMDGPU.h
DEBUG_TYPE
#define DEBUG_TYPE
Definition: SIPostRABundler.cpp:22
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SIInstrFlags::MIMG
@ MIMG
Definition: SIDefines.h:56
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:600
llvm::AnalysisUsage::setPreservesAll
void setPreservesAll()
Set by analyses that do not transform their input at all.
Definition: PassAnalysisSupport.h:130
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
llvm::MachineInstr::mayStore
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:1018
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:677
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::SIInstrFlags::MTBUF
@ MTBUF
Definition: SIDefines.h:54
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
SmallSet.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38