LLVM  12.0.0git
AMDGPURegBankCombiner.cpp
Go to the documentation of this file.
1 //=== lib/CodeGen/GlobalISel/AMDGPURegBankCombiner.cpp ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass does combining of machine instructions at the generic MI level,
10 // after register banks are known.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AMDGPUTargetMachine.h"
15 #include "AMDGPULegalizerInfo.h"
24 #include "llvm/Support/Debug.h"
26 
27 #define DEBUG_TYPE "amdgpu-regbank-combiner"
28 
29 using namespace llvm;
30 using namespace MIPatternMatch;
31 
32 
33 #define AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_DEPS
34 #include "AMDGPUGenRegBankGICombiner.inc"
35 #undef AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_DEPS
36 
37 namespace {
38 #define AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_H
39 #include "AMDGPUGenRegBankGICombiner.inc"
40 #undef AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_H
41 
42 class AMDGPURegBankCombinerInfo : public CombinerInfo {
43  GISelKnownBits *KB;
45 
46 public:
47  AMDGPUGenRegBankCombinerHelperRuleConfig GeneratedRuleCfg;
48 
49  AMDGPURegBankCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
50  const AMDGPULegalizerInfo *LI,
52  : CombinerInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true,
53  /*LegalizerInfo*/ LI, EnableOpt, OptSize, MinSize),
54  KB(KB), MDT(MDT) {
55  if (!GeneratedRuleCfg.parseCommandLineOption())
56  report_fatal_error("Invalid rule identifier");
57  }
58 
59  bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
60  MachineIRBuilder &B) const override;
61 };
62 
65  MachineIRBuilder &B) const {
66  CombinerHelper Helper(Observer, B, KB, MDT);
67  AMDGPUGenRegBankCombinerHelper Generated(GeneratedRuleCfg);
68 
69  if (Generated.tryCombineAll(Observer, MI, B, Helper))
70  return true;
71 
72  return false;
73 }
74 
75 #define AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_CPP
76 #include "AMDGPUGenRegBankGICombiner.inc"
77 #undef AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_CPP
78 
79 // Pass boilerplate
80 // ================
81 
82 class AMDGPURegBankCombiner : public MachineFunctionPass {
83 public:
84  static char ID;
85 
86  AMDGPURegBankCombiner(bool IsOptNone = false);
87 
88  StringRef getPassName() const override {
89  return "AMDGPURegBankCombiner";
90  }
91 
92  bool runOnMachineFunction(MachineFunction &MF) override;
93 
94  void getAnalysisUsage(AnalysisUsage &AU) const override;
95 private:
96  bool IsOptNone;
97 };
98 } // end anonymous namespace
99 
100 void AMDGPURegBankCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
102  AU.setPreservesCFG();
106  if (!IsOptNone) {
109  }
111 }
112 
113 AMDGPURegBankCombiner::AMDGPURegBankCombiner(bool IsOptNone)
114  : MachineFunctionPass(ID), IsOptNone(IsOptNone) {
116 }
117 
118 bool AMDGPURegBankCombiner::runOnMachineFunction(MachineFunction &MF) {
119  if (MF.getProperties().hasProperty(
121  return false;
122  auto *TPC = &getAnalysis<TargetPassConfig>();
123  const Function &F = MF.getFunction();
124  bool EnableOpt =
125  MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
126 
127  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
128  const AMDGPULegalizerInfo *LI
129  = static_cast<const AMDGPULegalizerInfo *>(ST.getLegalizerInfo());
130 
131  GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
132  MachineDominatorTree *MDT =
133  IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>();
134  AMDGPURegBankCombinerInfo PCInfo(EnableOpt, F.hasOptSize(),
135  F.hasMinSize(), LI, KB, MDT);
136  Combiner C(PCInfo, TPC);
137  return C.combineMachineInstrs(MF, /*CSEInfo*/ nullptr);
138 }
139 
141 INITIALIZE_PASS_BEGIN(AMDGPURegBankCombiner, DEBUG_TYPE,
142  "Combine AMDGPU machine instrs after regbankselect",
143  false, false)
146 INITIALIZE_PASS_END(AMDGPURegBankCombiner, DEBUG_TYPE,
147  "Combine AMDGPU machine instrs after regbankselect", false,
148  false)
149 
150 namespace llvm {
152  return new AMDGPURegBankCombiner(IsOptNone);
153 }
154 } // end namespace llvm
uint64_t CallInst * C
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
coro Split coroutine into a set of functions driving its state machine
Definition: CoroSplit.cpp:1806
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:509
const MachineFunctionProperties & getProperties() const
Get the function properties.
F(f)
Function & getFunction()
Return the LLVM function that this machine code represents.
AnalysisUsage & addRequired()
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Target-Independent Code Generator Pass Configuration Options.
Combine AMDGPU machine instrs after regbankselect
To use KnownBitsInfo analysis in a pass, KnownBitsInfo &Info = getAnalysis<GISelKnownBitsInfoAnalysis...
Abstract class that contains various methods for clients to notify about changes. ...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Helper class to build MachineInstr.
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
The AMDGPU TargetMachine interface definition for hw codgen targets.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:253
This class provides the information for the target register banks.
This file declares the targeting of the Machinelegalizer class for AMDGPU.
#define DEBUG_TYPE
vector combine
void initializeAMDGPURegBankCombinerPass(PassRegistry &)
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
Definition: MachineInstr.h:62
FunctionPass * createAMDGPURegBankCombiner(bool IsOptNone)
INITIALIZE_PASS_BEGIN(AMDGPURegBankCombiner, DEBUG_TYPE, "Combine AMDGPU machine instrs after regbankselect", false, false) INITIALIZE_PASS_END(AMDGPURegBankCombiner
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool hasProperty(Property P) const
const LegalizerInfo * getLegalizerInfo() const override
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)