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CombinerHelper.h
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1 //===-- llvm/CodeGen/GlobalISel/CombinerHelper.h --------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===--------------------------------------------------------------------===//
8 /// \file
9 /// This contains common combine transformations that may be used in a combine
10 /// pass,or by the target elsewhere.
11 /// Targets can pick individual opcode transformations from the helper or use
12 /// tryCombine which invokes all transformations. All of the transformations
13 /// return true if the MachineInstruction changed and false otherwise.
14 ///
15 //===--------------------------------------------------------------------===//
16 
17 #ifndef LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
18 #define LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
19 
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/CodeGen/Register.h"
24 #include <functional>
25 
26 namespace llvm {
27 
28 class GISelChangeObserver;
29 class APFloat;
30 class APInt;
31 class GPtrAdd;
32 class GStore;
33 class GZExtLoad;
34 class MachineIRBuilder;
35 class MachineInstrBuilder;
36 class MachineRegisterInfo;
37 class MachineInstr;
38 class MachineOperand;
39 class GISelKnownBits;
40 class MachineDominatorTree;
41 class LegalizerInfo;
42 struct LegalityQuery;
43 class RegisterBank;
44 class RegisterBankInfo;
45 class TargetLowering;
46 class TargetRegisterInfo;
47 
49  LLT Ty; // The result type of the extend.
50  unsigned ExtendOpcode; // G_ANYEXT/G_SEXT/G_ZEXT
52 };
53 
58  bool IsPre;
59 };
60 
61 struct PtrAddChain {
62  int64_t Imm;
65 };
66 
69  int64_t Imm;
70 };
71 
77 };
78 
80 
83  GStore *LowestIdxStore = nullptr;
85  bool NeedBSwap = false;
86  bool NeedRotate = false;
87 };
88 
89 using OperandBuildSteps =
92  unsigned Opcode = 0; /// The opcode for the produced instruction.
93  OperandBuildSteps OperandFns; /// Operands to be added to the instruction.
94  InstructionBuildSteps() = default;
97 };
98 
100  /// Describes instructions to be built during a combine.
102  InstructionStepsMatchInfo() = default;
104  std::initializer_list<InstructionBuildSteps> InstrsToBuild)
106 };
107 
109 protected:
118 
119 public:
121  GISelKnownBits *KB = nullptr,
122  MachineDominatorTree *MDT = nullptr,
123  const LegalizerInfo *LI = nullptr);
124 
126  return KB;
127  }
128 
129  const TargetLowering &getTargetLowering() const;
130 
131  /// \returns true if the combiner is running pre-legalization.
132  bool isPreLegalize() const;
133 
134  /// \returns true if \p Query is legal on the target.
135  bool isLegal(const LegalityQuery &Query) const;
136 
137  /// \return true if the combine is running prior to legalization, or if \p
138  /// Query is legal on the target.
139  bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const;
140 
141  /// \return true if the combine is running prior to legalization, or if \p Ty
142  /// is a legal integer constant type on the target.
143  bool isConstantLegalOrBeforeLegalizer(const LLT Ty) const;
144 
145  /// MachineRegisterInfo::replaceRegWith() and inform the observer of the changes
146  void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const;
147 
148  /// Replace a single register operand with a new register and inform the
149  /// observer of the changes.
151  Register ToReg) const;
152 
153  /// Replace the opcode in instruction with a new opcode and inform the
154  /// observer of the changes.
155  void replaceOpcodeWith(MachineInstr &FromMI, unsigned ToOpcode) const;
156 
157  /// Get the register bank of \p Reg.
158  /// If Reg has not been assigned a register, a register class,
159  /// or a register bank, then this returns nullptr.
160  ///
161  /// \pre Reg.isValid()
162  const RegisterBank *getRegBank(Register Reg) const;
163 
164  /// Set the register bank of \p Reg.
165  /// Does nothing if the RegBank is null.
166  /// This is the counterpart to getRegBank.
167  void setRegBank(Register Reg, const RegisterBank *RegBank);
168 
169  /// If \p MI is COPY, try to combine it.
170  /// Returns true if MI changed.
174 
175  /// Returns true if \p DefMI precedes \p UseMI or they are the same
176  /// instruction. Both must be in the same basic block.
177  bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI);
178 
179  /// Returns true if \p DefMI dominates \p UseMI. By definition an
180  /// instruction dominates itself.
181  ///
182  /// If we haven't been provided with a MachineDominatorTree during
183  /// construction, this function returns a conservative result that tracks just
184  /// a single basic block.
185  bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI);
186 
187  /// If \p MI is extend that consumes the result of a load, try to combine it.
188  /// Returns true if MI changed.
192 
193  /// Match (and (load x), mask) -> zextload x
195 
196  /// Combine \p MI into a pre-indexed or post-indexed load/store operation if
197  /// legal and the surrounding code makes it useful.
201 
204 
205  /// Match sext_inreg(load p), imm -> sextload p
206  bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
207  void applySextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
208 
209  /// Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM
210  /// when their source operands are identical.
213 
214  /// If a brcond's true block is not the fallthrough, make it so by inverting
215  /// the condition and swapping operands.
218 
219  /// If \p MI is G_CONCAT_VECTORS, try to combine it.
220  /// Returns true if MI changed.
221  /// Right now, we support:
222  /// - concat_vector(undef, undef) => undef
223  /// - concat_vector(build_vector(A, B), build_vector(C, D)) =>
224  /// build_vector(A, B, C, D)
225  ///
226  /// \pre MI.getOpcode() == G_CONCAT_VECTORS.
228  /// Check if the G_CONCAT_VECTORS \p MI is undef or if it
229  /// can be flattened into a build_vector.
230  /// In the first case \p IsUndef will be true.
231  /// In the second case \p Ops will contain the operands needed
232  /// to produce the flattened build_vector.
233  ///
234  /// \pre MI.getOpcode() == G_CONCAT_VECTORS.
235  bool matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef,
237  /// Replace \p MI with a flattened build_vector with \p Ops or an
238  /// implicit_def if IsUndef is true.
239  void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef,
240  const ArrayRef<Register> Ops);
241 
242  /// Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
243  /// Returns true if MI changed.
244  ///
245  /// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
247  /// Check if the G_SHUFFLE_VECTOR \p MI can be replaced by a
248  /// concat_vectors.
249  /// \p Ops will contain the operands needed to produce the flattened
250  /// concat_vectors.
251  ///
252  /// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
255  /// Replace \p MI with a concat_vectors with \p Ops.
257  const ArrayRef<Register> Ops);
258 
259  /// Optimize memcpy intrinsics et al, e.g. constant len calls.
260  /// /p MaxLen if non-zero specifies the max length of a mem libcall to inline.
261  ///
262  /// For example (pre-indexed):
263  ///
264  /// $addr = G_PTR_ADD $base, $offset
265  /// [...]
266  /// $val = G_LOAD $addr
267  /// [...]
268  /// $whatever = COPY $addr
269  ///
270  /// -->
271  ///
272  /// $val, $addr = G_INDEXED_LOAD $base, $offset, 1 (IsPre)
273  /// [...]
274  /// $whatever = COPY $addr
275  ///
276  /// or (post-indexed):
277  ///
278  /// G_STORE $val, $base
279  /// [...]
280  /// $addr = G_PTR_ADD $base, $offset
281  /// [...]
282  /// $whatever = COPY $addr
283  ///
284  /// -->
285  ///
286  /// $addr = G_INDEXED_STORE $val, $base, $offset
287  /// [...]
288  /// $whatever = COPY $addr
289  bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
290 
293 
294  /// Fold (shift (shift base, x), y) -> (shift base (x+y))
297 
298  /// If we have a shift-by-constant of a bitwise logic op that itself has a
299  /// shift-by-constant operand with identical opcode, we may be able to convert
300  /// that into 2 independent shifts followed by the logic op.
302  ShiftOfShiftedLogic &MatchInfo);
304  ShiftOfShiftedLogic &MatchInfo);
305 
306  /// Transform a multiply by a power-of-2 value to a left shift.
307  bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
308  void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
309 
310  // Transform a G_SHL with an extended source into a narrower shift if
311  // possible.
314  const RegisterImmPair &MatchData);
315 
316  /// Fold away a merge of an unmerge of the corresponding values.
318 
319  /// Reduce a shift by a constant to an unmerge and a shift on a half sized
320  /// type. This will not produce a shift smaller than \p TargetShiftSize.
321  bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize,
322  unsigned &ShiftVal);
323  void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal);
324  bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount);
325 
326  /// Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
327  bool
330  void
333 
334  /// Transform G_UNMERGE Constant -> Constant1, Constant2, ...
336  SmallVectorImpl<APInt> &Csts);
338  SmallVectorImpl<APInt> &Csts);
339 
340  /// Transform G_UNMERGE G_IMPLICIT_DEF -> G_IMPLICIT_DEF, G_IMPLICIT_DEF, ...
341  bool
343  std::function<void(MachineIRBuilder &)> &MatchInfo);
344 
345  /// Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
348 
349  /// Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0
352 
353  /// Transform fp_instr(cst) to constant result of the fp operation.
355  Optional<APFloat> &Cst);
357  Optional<APFloat> &Cst);
358 
359  /// Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
362 
363  /// Transform PtrToInt(IntToPtr(x)) to x.
366 
367  /// Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y)
368  /// Transform G_ADD y, (G_PTRTOINT x) -> G_PTRTOINT (G_PTR_ADD x, y)
370  std::pair<Register, bool> &PtrRegAndCommute);
372  std::pair<Register, bool> &PtrRegAndCommute);
373 
374  // Transform G_PTR_ADD (G_PTRTOINT C1), C2 -> C1 + C2
377 
378  /// Transform anyext(trunc(x)) to x.
381 
382  /// Transform zext(trunc(x)) to x.
384 
385  /// Transform [asz]ext([asz]ext(x)) to [asz]ext x.
387  std::tuple<Register, unsigned> &MatchInfo);
389  std::tuple<Register, unsigned> &MatchInfo);
390 
391  /// Transform fneg(fneg(x)) to x.
393 
394  /// Match fabs(fabs(x)) to fabs(x).
397 
398  /// Transform fabs(fneg(x)) to fabs(x).
399  bool matchCombineFAbsOfFNeg(MachineInstr &MI, BuildFnTy &MatchInfo);
400 
401  /// Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
403  std::pair<Register, unsigned> &MatchInfo);
405  std::pair<Register, unsigned> &MatchInfo);
406 
407  /// Transform trunc (shl x, K) to shl (trunc x),
408  /// K => K < VT.getScalarSizeInBits().
410  std::pair<Register, Register> &MatchInfo);
412  std::pair<Register, Register> &MatchInfo);
413 
414  /// Transform G_MUL(x, -1) to G_SUB(0, x)
416 
417  /// Return true if any explicit use operand on \p MI is defined by a
418  /// G_IMPLICIT_DEF.
420 
421  /// Return true if all register explicit use operands on \p MI are defined by
422  /// a G_IMPLICIT_DEF.
424 
425  /// Return true if a G_SHUFFLE_VECTOR instruction \p MI has an undef mask.
427 
428  /// Return true if a G_STORE instruction \p MI is storing an undef value.
430 
431  /// Return true if a G_SELECT instruction \p MI has an undef comparison.
433 
434  /// Return true if a G_SELECT instruction \p MI has a constant comparison. If
435  /// true, \p OpIdx will store the operand index of the known selected value.
436  bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx);
437 
438  /// Replace an instruction with a G_FCONSTANT with value \p C.
439  bool replaceInstWithFConstant(MachineInstr &MI, double C);
440 
441  /// Replace an instruction with a G_CONSTANT with value \p C.
442  bool replaceInstWithConstant(MachineInstr &MI, int64_t C);
443 
444  /// Replace an instruction with a G_CONSTANT with value \p C.
446 
447  /// Replace an instruction with a G_IMPLICIT_DEF.
449 
450  /// Delete \p MI and replace all of its uses with its \p OpIdx-th operand.
451  bool replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx);
452 
453  /// Delete \p MI and replace all of its uses with \p Replacement.
455 
456  /// Return true if \p MOP1 and \p MOP2 are register operands are defined by
457  /// equivalent instructions.
458  bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2);
459 
460  /// Return true if \p MOP is defined by a G_CONSTANT with a value equal to
461  /// \p C.
462  bool matchConstantOp(const MachineOperand &MOP, int64_t C);
463 
464  /// Optimize (cond ? x : x) -> x
466 
467  /// Optimize (x op x) -> x
469 
470  /// Check if operand \p OpIdx is zero.
471  bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx);
472 
473  /// Check if operand \p OpIdx is undef.
474  bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx);
475 
476  /// Check if operand \p OpIdx is known to be a power of 2.
477  bool matchOperandIsKnownToBeAPowerOfTwo(MachineInstr &MI, unsigned OpIdx);
478 
479  /// Erase \p MI
480  bool eraseInst(MachineInstr &MI);
481 
482  /// Return true if MI is a G_ADD which can be simplified to a G_SUB.
484  std::tuple<Register, Register> &MatchInfo);
486  std::tuple<Register, Register> &MatchInfo);
487 
488  /// Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
489  bool
491  InstructionStepsMatchInfo &MatchInfo);
492 
493  /// Replace \p MI with a series of instructions described in \p MatchInfo.
495  InstructionStepsMatchInfo &MatchInfo);
496 
497  /// Match ashr (shl x, C), C -> sext_inreg (C)
499  std::tuple<Register, int64_t> &MatchInfo);
501  std::tuple<Register, int64_t> &MatchInfo);
502 
503  /// Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0
505  BuildFnTy &MatchInfo);
506 
507  /// \return true if \p MI is a G_AND instruction whose operands are x and y
508  /// where x & y == x or x & y == y. (E.g., one of operands is all-ones value.)
509  ///
510  /// \param [in] MI - The G_AND instruction.
511  /// \param [out] Replacement - A register the G_AND should be replaced with on
512  /// success.
513  bool matchRedundantAnd(MachineInstr &MI, Register &Replacement);
514 
515  /// \return true if \p MI is a G_OR instruction whose operands are x and y
516  /// where x | y == x or x | y == y. (E.g., one of operands is all-zeros
517  /// value.)
518  ///
519  /// \param [in] MI - The G_OR instruction.
520  /// \param [out] Replacement - A register the G_OR should be replaced with on
521  /// success.
522  bool matchRedundantOr(MachineInstr &MI, Register &Replacement);
523 
524  /// \return true if \p MI is a G_SEXT_INREG that can be erased.
526 
527  /// Combine inverting a result of a compare into the opposite cond code.
530 
531  /// Fold (xor (and x, y), y) -> (and (not x), y)
532  ///{
534  std::pair<Register, Register> &MatchInfo);
536  std::pair<Register, Register> &MatchInfo);
537  ///}
538 
539  /// Combine G_PTR_ADD with nullptr to G_INTTOPTR
542 
543  /// Combine G_UREM x, (known power of 2) to an add and bitmasking.
545 
546  /// Push a binary operator through a select on constants.
547  ///
548  /// binop (select cond, K0, K1), K2 ->
549  /// select cond, (binop K0, K2), (binop K1, K2)
550  bool matchFoldBinOpIntoSelect(MachineInstr &MI, unsigned &SelectOpNo);
551  bool applyFoldBinOpIntoSelect(MachineInstr &MI, const unsigned &SelectOpNo);
552 
554  SmallVectorImpl<Register> &MatchInfo);
555 
557  SmallVectorImpl<Register> &MatchInfo);
558 
559  /// Match expression trees of the form
560  ///
561  /// \code
562  /// sN *a = ...
563  /// sM val = a[0] | (a[1] << N) | (a[2] << 2N) | (a[3] << 3N) ...
564  /// \endcode
565  ///
566  /// And check if the tree can be replaced with a M-bit load + possibly a
567  /// bswap.
568  bool matchLoadOrCombine(MachineInstr &MI, BuildFnTy &MatchInfo);
569 
572 
575 
578 
580  MachineInstr &MI,
581  SmallVectorImpl<std::pair<Register, MachineInstr *>> &MatchInfo);
583  MachineInstr &MI,
584  SmallVectorImpl<std::pair<Register, MachineInstr *>> &MatchInfo);
585 
586  /// Use a function which takes in a MachineIRBuilder to perform a combine.
587  /// By default, it erases the instruction \p MI from the function.
588  void applyBuildFn(MachineInstr &MI, BuildFnTy &MatchInfo);
589  /// Use a function which takes in a MachineIRBuilder to perform a combine.
590  /// This variant does not erase \p MI after calling the build function.
591  void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo);
592 
598 
599  /// \returns true if a G_ICMP instruction \p MI can be replaced with a true
600  /// or false constant based off of KnownBits information.
601  bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo);
602 
603  /// \returns true if a G_ICMP \p MI can be replaced with its LHS based off of
604  /// KnownBits information.
605  bool
607  BuildFnTy &MatchInfo);
608 
609  /// \returns true if (and (or x, c1), c2) can be replaced with (and x, c2)
610  bool matchAndOrDisjointMask(MachineInstr &MI, BuildFnTy &MatchInfo);
611 
613  BuildFnTy &MatchInfo);
614  /// Match: and (lshr x, cst), mask -> ubfx x, cst, width
616 
617  /// Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width
619 
620  /// Match: shr (and x, n), k -> ubfx x, pos, width
622 
623  // Helpers for reassociation:
625  BuildFnTy &MatchInfo);
627  MachineInstr *RHS,
628  BuildFnTy &MatchInfo);
630  MachineInstr *RHS, BuildFnTy &MatchInfo);
631  /// Reassociate pointer calculations with G_ADD involved, to allow better
632  /// addressing mode usage.
633  bool matchReassocPtrAdd(MachineInstr &MI, BuildFnTy &MatchInfo);
634 
635  /// Do constant folding when opportunities are exposed after MIR building.
636  bool matchConstantFold(MachineInstr &MI, APInt &MatchInfo);
637 
638  /// \returns true if it is possible to narrow the width of a scalar binop
639  /// feeding a G_AND instruction \p MI.
641 
642  /// Given an G_UDIV \p MI expressing a divide by constant, return an
643  /// expression that implements it by multiplying by a magic number.
644  /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
646  /// Combine G_UDIV by constant into a multiply by magic constant.
649 
650  // G_UMULH x, (1 << c)) -> x >> (bitwidth - c)
653 
654  /// Try to transform \p MI by using all of the above
655  /// combine functions. Returns true if changed.
656  bool tryCombine(MachineInstr &MI);
657 
658  /// Emit loads and stores that perform the given memcpy.
659  /// Assumes \p MI is a G_MEMCPY_INLINE
660  /// TODO: implement dynamically sized inline memcpy,
661  /// and rename: s/bool tryEmit/void emit/
663 
664  /// Match:
665  /// (G_UMULO x, 2) -> (G_UADDO x, x)
666  /// (G_SMULO x, 2) -> (G_SADDO x, x)
667  bool matchMulOBy2(MachineInstr &MI, BuildFnTy &MatchInfo);
668 
669  /// Match:
670  /// (G_*MULO x, 0) -> 0 + no carry out
671  bool matchMulOBy0(MachineInstr &MI, BuildFnTy &MatchInfo);
672 
673  /// Match:
674  /// (G_*ADDO x, 0) -> x + no carry out
675  bool matchAddOBy0(MachineInstr &MI, BuildFnTy &MatchInfo);
676 
677  /// Transform (fadd x, fneg(y)) -> (fsub x, y)
678  /// (fadd fneg(x), y) -> (fsub y, x)
679  /// (fsub x, fneg(y)) -> (fadd x, y)
680  /// (fmul fneg(x), fneg(y)) -> (fmul x, y)
681  /// (fdiv fneg(x), fneg(y)) -> (fdiv x, y)
682  /// (fmad fneg(x), fneg(y), z) -> (fmad x, y, z)
683  /// (fma fneg(x), fneg(y), z) -> (fma x, y, z)
685 
686  bool canCombineFMadOrFMA(MachineInstr &MI, bool &AllowFusionGlobally,
687  bool &HasFMAD, bool &Aggressive,
688  bool CanReassociate = false);
689 
690  /// Transform (fadd (fmul x, y), z) -> (fma x, y, z)
691  /// (fadd (fmul x, y), z) -> (fmad x, y, z)
693 
694  /// Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z)
695  /// (fadd (fpext (fmul x, y)), z) -> (fmad (fpext x), (fpext y), z)
697  BuildFnTy &MatchInfo);
698 
699  /// Transform (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y, (fma u, v, z))
700  /// (fadd (fmad x, y, (fmul u, v)), z) -> (fmad x, y, (fmad u, v, z))
702  BuildFnTy &MatchInfo);
703 
704  // Transform (fadd (fma x, y, (fpext (fmul u, v))), z)
705  // -> (fma x, y, (fma (fpext u), (fpext v), z))
706  // (fadd (fmad x, y, (fpext (fmul u, v))), z)
707  // -> (fmad x, y, (fmad (fpext u), (fpext v), z))
709  BuildFnTy &MatchInfo);
710 
711  /// Transform (fsub (fmul x, y), z) -> (fma x, y, -z)
712  /// (fsub (fmul x, y), z) -> (fmad x, y, -z)
714 
715  /// Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
716  /// (fsub (fneg (fmul, x, y)), z) -> (fmad (fneg x), y, (fneg z))
718  BuildFnTy &MatchInfo);
719 
720  /// Transform (fsub (fpext (fmul x, y)), z)
721  /// -> (fma (fpext x), (fpext y), (fneg z))
722  /// (fsub (fpext (fmul x, y)), z)
723  /// -> (fmad (fpext x), (fpext y), (fneg z))
725  BuildFnTy &MatchInfo);
726 
727  /// Transform (fsub (fpext (fneg (fmul x, y))), z)
728  /// -> (fneg (fma (fpext x), (fpext y), z))
729  /// (fsub (fpext (fneg (fmul x, y))), z)
730  /// -> (fneg (fmad (fpext x), (fpext y), z))
732  BuildFnTy &MatchInfo);
733 
734  /// Fold boolean selects to logical operations.
735  bool matchSelectToLogical(MachineInstr &MI, BuildFnTy &MatchInfo);
736 
737  bool matchCombineFMinMaxNaN(MachineInstr &MI, unsigned &Info);
738 
739  /// Transform G_ADD(x, G_SUB(y, x)) to y.
740  /// Transform G_ADD(G_SUB(y, x), x) to y.
742 
743 private:
744  /// Given a non-indexed load or store instruction \p MI, find an offset that
745  /// can be usefully and legally folded into it as a post-indexing operation.
746  ///
747  /// \returns true if a candidate is found.
748  bool findPostIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
749  Register &Offset);
750 
751  /// Given a non-indexed load or store instruction \p MI, find an offset that
752  /// can be usefully and legally folded into it as a pre-indexing operation.
753  ///
754  /// \returns true if a candidate is found.
755  bool findPreIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
756  Register &Offset);
757 
758  /// Helper function for matchLoadOrCombine. Searches for Registers
759  /// which may have been produced by a load instruction + some arithmetic.
760  ///
761  /// \param [in] Root - The search root.
762  ///
763  /// \returns The Registers found during the search.
765  findCandidatesForLoadOrCombine(const MachineInstr *Root) const;
766 
767  /// Helper function for matchLoadOrCombine.
768  ///
769  /// Checks if every register in \p RegsToVisit is defined by a load
770  /// instruction + some arithmetic.
771  ///
772  /// \param [out] MemOffset2Idx - Maps the byte positions each load ends up
773  /// at to the index of the load.
774  /// \param [in] MemSizeInBits - The number of bits each load should produce.
775  ///
776  /// \returns On success, a 3-tuple containing lowest-index load found, the
777  /// lowest index, and the last load in the sequence.
779  findLoadOffsetsForLoadOrCombine(
780  SmallDenseMap<int64_t, int64_t, 8> &MemOffset2Idx,
781  const SmallVector<Register, 8> &RegsToVisit,
782  const unsigned MemSizeInBits);
783 
784  /// Examines the G_PTR_ADD instruction \p PtrAdd and determines if performing
785  /// a re-association of its operands would break an existing legal addressing
786  /// mode that the address computation currently represents.
787  bool reassociationCanBreakAddressingModePattern(MachineInstr &PtrAdd);
788 };
789 } // namespace llvm
790 
791 #endif
llvm::CombinerHelper::matchCombineUnmergeWithDeadLanesToTrunc
bool matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI)
Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
Definition: CombinerHelper.cpp:1781
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@ APFloat
Definition: LLToken.h:437
llvm::CombinerHelper::matchFoldBinOpIntoSelect
bool matchFoldBinOpIntoSelect(MachineInstr &MI, unsigned &SelectOpNo)
Push a binary operator through a select on constants.
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Register Addr
Definition: CombinerHelper.h:55
llvm::CombinerHelper::matchConstantFold
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Do constant folding when opportunities are exposed after MIR building.
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void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal)
Definition: CombinerHelper.cpp:1898
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unsigned Opcode
Definition: CombinerHelper.h:92
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IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::CombinerHelper::applyExtractVecEltBuildVec
void applyExtractVecEltBuildVec(MachineInstr &MI, Register &Reg)
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Definition: CombinerHelper.h:67
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Definition: AArch64ExpandPseudoInsts.cpp:103
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Definition: CombinerHelper.h:84
llvm::CombinerHelper::matchCombineUnmergeConstant
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Transform G_UNMERGE Constant -> Constant1, Constant2, ...
Definition: CombinerHelper.cpp:1726
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Definition: CombinerHelper.h:111
llvm::CombinerHelper::applyOptBrCondByInvertingCond
void applyOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond)
Definition: CombinerHelper.cpp:1198
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bool matchHoistLogicOpWithSameOpcodeHands(MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo)
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Definition: GISelKnownBits.h:29
llvm::ShiftOfShiftedLogic::Shift2
MachineInstr * Shift2
Definition: CombinerHelper.h:74
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MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
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void applyCombineI2PToP2I(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:1991
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bool eraseInst(MachineInstr &MI)
Erase MI.
Definition: CombinerHelper.cpp:2322
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Register Base
Definition: CombinerHelper.h:56
llvm::CombinerHelper::getKnownBits
GISelKnownBits * getKnownBits() const
Definition: CombinerHelper.h:125
llvm::CombinerHelper::matchCombineP2IToI2P
bool matchCombineP2IToI2P(MachineInstr &MI, Register &Reg)
Transform PtrToInt(IntToPtr(x)) to x.
Definition: CombinerHelper.cpp:1999
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This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
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const TargetLowering & getTargetLowering() const
Definition: CombinerHelper.cpp:58
llvm::InstructionBuildSteps::InstructionBuildSteps
InstructionBuildSteps(unsigned Opcode, const OperandBuildSteps &OperandFns)
Definition: CombinerHelper.h:95
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bool matchCombineFSubFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fmul x, y), z) -> (fma x, y, -z) (fsub (fmul x, y), z) -> (fmad x,...
Definition: CombinerHelper.cpp:5343
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bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen=0)
Optimize memcpy intrinsics et al, e.g.
Definition: CombinerHelper.cpp:1238
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bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI)
Returns true if DefMI dominates UseMI.
Definition: CombinerHelper.cpp:759
llvm::MergeTruncStoresInfo
Definition: CombinerHelper.h:81
llvm::CombinerHelper::matchCombineFAddFMAFMulToFMadOrFMA
bool matchCombineFAddFMAFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y, (fma u, v, z)) (fadd (fmad x,...
Definition: CombinerHelper.cpp:5152
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Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::SmallDenseMap
Definition: DenseMap.h:882
llvm::CombinerHelper::matchConstantSelectCmp
bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx)
Return true if a G_SELECT instruction MI has a constant comparison.
Definition: CombinerHelper.cpp:2312
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void applyFunnelShiftToRotate(MachineInstr &MI)
Definition: CombinerHelper.cpp:4078
llvm::CombinerHelper::matchCombineFSubFpExtFNegFMulToFMadOrFMA
bool matchCombineFSubFpExtFNegFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fpext (fneg (fmul x, y))), z) -> (fneg (fma (fpext x), (fpext y),...
Definition: CombinerHelper.cpp:5493
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Use a function which takes in a MachineIRBuilder to perform a combine.
Definition: CombinerHelper.cpp:3999
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bool tryCombineShuffleVector(MachineInstr &MI)
Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
Definition: CombinerHelper.cpp:294
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::CombinerHelper::replaceOpcodeWith
void replaceOpcodeWith(MachineInstr &FromMI, unsigned ToOpcode) const
Replace the opcode in instruction with a new opcode and inform the observer of the changes.
Definition: CombinerHelper.cpp:178
llvm::CombinerHelper::matchCombineDivRem
bool matchCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI)
Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM when their source operands are iden...
Definition: CombinerHelper.cpp:1070
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bool tryCombineIndexedLoadStore(MachineInstr &MI)
Combine MI into a pre-indexed or post-indexed load/store operation if legal and the surrounding code ...
Definition: CombinerHelper.cpp:998
DenseMap.h
llvm::MergeTruncStoresInfo::NeedRotate
bool NeedRotate
Definition: CombinerHelper.h:86
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bool matchNarrowBinopFeedingAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4616
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Definition: CombinerHelper.h:99
llvm::MergeTruncStoresInfo::FoundStores
SmallVector< GStore * > FoundStores
Definition: CombinerHelper.h:82
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void applyCombineExtOfExt(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Definition: CombinerHelper.cpp:2132
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Definition: APInt.h:33
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bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount)
Definition: CombinerHelper.cpp:1971
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bool matchSextTruncSextLoad(MachineInstr &MI)
Definition: CombinerHelper.cpp:771
Aggressive
static cl::opt< bool > Aggressive("aggressive-ext-opt", cl::Hidden, cl::desc("Aggressive extension optimization"))
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
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bool matchPtrAddZero(MachineInstr &MI)
}
Definition: CombinerHelper.cpp:3040
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bool tryCombineExtendingLoads(MachineInstr &MI)
If MI is extend that consumes the result of a load, try to combine it.
Definition: CombinerHelper.cpp:479
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int64_t Imm
Definition: CombinerHelper.h:62
llvm::CombinerHelper::matchPtrAddImmedChain
bool matchPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo)
Definition: CombinerHelper.cpp:1308
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bool matchRotateOutOfRange(MachineInstr &MI)
Definition: CombinerHelper.cpp:4090
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bool matchNotCmp(MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate)
Combine inverting a result of a compare into the opposite cond code.
Definition: CombinerHelper.cpp:2886
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void applyCombineTruncOfExt(MachineInstr &MI, std::pair< Register, unsigned > &MatchInfo)
Definition: CombinerHelper.cpp:2219
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bool isConstantLegalOrBeforeLegalizer(const LLT Ty) const
Definition: CombinerHelper.cpp:144
llvm::CombinerHelper::applyNotCmp
void applyNotCmp(MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate)
Definition: CombinerHelper.cpp:2963
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Definition: CombinerHelper.cpp:203
llvm::CombinerHelper::matchCombineAddP2IToPtrAdd
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Definition: CombinerHelper.cpp:2013
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Definition: CombinerHelper.h:61
llvm::CombinerHelper::matchAshrShlToSextInreg
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Match ashr (shl x, C), C -> sext_inreg (C)
Definition: CombinerHelper.cpp:2713
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void applyTruncStoreMerge(MachineInstr &MI, MergeTruncStoresInfo &MatchInfo)
Definition: CombinerHelper.cpp:3763
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Definition: CombinerHelper.h:91
llvm::PtrAddChain::Base
Register Base
Definition: CombinerHelper.h:63
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
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int64_t Imm
Definition: CombinerHelper.h:69
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void applyPtrAddZero(MachineInstr &MI)
Definition: CombinerHelper.cpp:3059
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Definition: CombinerHelper.h:79
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OperandBuildSteps OperandFns
The opcode for the produced instruction.
Definition: CombinerHelper.h:93
llvm::CombinerHelper::setRegBank
void setRegBank(Register Reg, const RegisterBank *RegBank)
Set the register bank of Reg.
Definition: CombinerHelper.cpp:191
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Reassociate pointer calculations with G_ADD involved, to allow better addressing mode usage.
Definition: CombinerHelper.cpp:4573
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This class implements the register bank concept.
Definition: RegisterBank.h:28
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Transform G_UNMERGE G_IMPLICIT_DEF -> G_IMPLICIT_DEF, G_IMPLICIT_DEF, ...
Definition: CombinerHelper.cpp:1767
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Definition: CombinerHelper.h:114
llvm::CombinerHelper::buildUDivUsingMul
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Given an G_UDIV MI expressing a divide by constant, return an expression that implements it by multip...
Definition: CombinerHelper.cpp:4761
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Check if the G_CONCAT_VECTORS MI is undef or if it can be flattened into a build_vector.
Definition: CombinerHelper.cpp:227
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bool matchRedundantSExtInReg(MachineInstr &MI)
Definition: CombinerHelper.cpp:2871
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bool matchCombineZextTrunc(MachineInstr &MI, Register &Reg)
Transform zext(trunc(x)) to x.
Definition: CombinerHelper.cpp:2097
llvm::ShiftOfShiftedLogic
Definition: CombinerHelper.h:72
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
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This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3412
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Definition: CombinerHelper.cpp:4544
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Definition: CombinerHelper.h:103
llvm::CombinerHelper::applySimplifyURemByPow2
void applySimplifyURemByPow2(MachineInstr &MI)
Combine G_UREM x, (known power of 2) to an add and bitmasking.
Definition: CombinerHelper.cpp:3067
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bool matchLoadOrCombine(MachineInstr &MI, BuildFnTy &MatchInfo)
Match expression trees of the form.
Definition: CombinerHelper.cpp:3409
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bool matchCombineFAddFpExtFMulToFMadOrFMAAggressive(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:5217
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Return true if any explicit use operand on MI is defined by a G_IMPLICIT_DEF.
Definition: CombinerHelper.cpp:2280
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::CombinerHelper::applyCombineUnmergeZExtToZExt
void applyCombineUnmergeZExtToZExt(MachineInstr &MI)
Definition: CombinerHelper.cpp:1839
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LLT Ty
Definition: CombinerHelper.h:49
llvm::CombinerHelper::applyExtendThroughPhis
void applyExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI)
Definition: CombinerHelper.cpp:3845
llvm::CombinerHelper::matchCombineI2PToP2I
bool matchCombineI2PToP2I(MachineInstr &MI, Register &Reg)
Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
Definition: CombinerHelper.cpp:1982
llvm::CombinerHelper::isPreLegalize
bool isPreLegalize() const
Definition: CombinerHelper.cpp:132
llvm::CombinerHelper::matchCombineFNegOfFNeg
bool matchCombineFNegOfFNeg(MachineInstr &MI, Register &Reg)
Transform fneg(fneg(x)) to x.
Definition: CombinerHelper.cpp:2175
llvm::CombinerHelper::TRI
const TargetRegisterInfo * TRI
Definition: CombinerHelper.h:117
llvm::CombinerHelper::matchAddOBy0
bool matchAddOBy0(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: (G_*ADDO x, 0) -> x + no carry out.
Definition: CombinerHelper.cpp:4743
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::CombinerHelper::applyCombineUnmergeConstant
void applyCombineUnmergeConstant(MachineInstr &MI, SmallVectorImpl< APInt > &Csts)
Definition: CombinerHelper.cpp:1751
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bool matchCombineFAddFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd (fmul x, y), z) -> (fma x, y, z) (fadd (fmul x, y), z) -> (fmad x,...
Definition: CombinerHelper.cpp:5045
llvm::CombinerHelper
Definition: CombinerHelper.h:108
llvm::CombinerHelper::applyCombineConcatVectors
void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef, const ArrayRef< Register > Ops)
Replace MI with a flattened build_vector with Ops or an implicit_def if IsUndef is true.
Definition: CombinerHelper.cpp:272
llvm::CombinerHelper::matchCombineShuffleVector
bool matchCombineShuffleVector(MachineInstr &MI, SmallVectorImpl< Register > &Ops)
Check if the G_SHUFFLE_VECTOR MI can be replaced by a concat_vectors.
Definition: CombinerHelper.cpp:303
llvm::CombinerHelper::isLegal
bool isLegal(const LegalityQuery &Query) const
Definition: CombinerHelper.cpp:134
llvm::MergeTruncStoresInfo::NeedBSwap
bool NeedBSwap
Definition: CombinerHelper.h:85
llvm::CombinerHelper::tryCombineCopy
bool tryCombineCopy(MachineInstr &MI)
If MI is COPY, try to combine it.
Definition: CombinerHelper.cpp:196
llvm::CombinerHelper::Observer
GISelChangeObserver & Observer
Definition: CombinerHelper.h:112
llvm::CombinerHelper::matchCombineUnmergeZExtToZExt
bool matchCombineUnmergeZExtToZExt(MachineInstr &MI)
Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0.
Definition: CombinerHelper.cpp:1813
llvm::CombinerHelper::matchUndefShuffleVectorMask
bool matchUndefShuffleVectorMask(MachineInstr &MI)
Return true if a G_SHUFFLE_VECTOR instruction MI has an undef mask.
Definition: CombinerHelper.cpp:2294
llvm::CombinerHelper::matchICmpToTrueFalseKnownBits
bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo)
Definition: CombinerHelper.cpp:4120
llvm::CombinerHelper::applyCombineFAbsOfFAbs
void applyCombineFAbsOfFAbs(MachineInstr &MI, Register &Src)
LowLevelTypeImpl.h
llvm::CombinerHelper::matchCombineMergeUnmerge
bool matchCombineMergeUnmerge(MachineInstr &MI, Register &MatchInfo)
Fold away a merge of an unmerge of the corresponding values.
Definition: CombinerHelper.cpp:1652
llvm::CombinerHelper::KB
GISelKnownBits * KB
Definition: CombinerHelper.h:113
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::CombinerHelper::matchAddSubSameReg
bool matchAddSubSameReg(MachineInstr &MI, Register &Src)
Transform G_ADD(x, G_SUB(y, x)) to y.
Definition: CombinerHelper.cpp:5636
llvm::InstructionStepsMatchInfo::InstructionStepsMatchInfo
InstructionStepsMatchInfo()=default
llvm::IndexedLoadStoreMatchInfo::Offset
Register Offset
Definition: CombinerHelper.h:57
llvm::CombinerHelper::applyPtrAddImmedChain
void applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo)
Definition: CombinerHelper.cpp:1370
llvm::GStore
Represents a G_STORE.
Definition: GenericMachineInstrs.h:130
llvm::CombinerHelper::matchOverlappingAnd
bool matchOverlappingAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0.
Definition: CombinerHelper.cpp:2744
llvm::CombinerHelper::applyBuildInstructionSteps
void applyBuildInstructionSteps(MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo)
Replace MI with a series of instructions described in MatchInfo.
Definition: CombinerHelper.cpp:2698
llvm::CombinerHelper::matchRedundantAnd
bool matchRedundantAnd(MachineInstr &MI, Register &Replacement)
Definition: CombinerHelper.cpp:2770
llvm::GPtrAdd
Represents a G_PTR_ADD.
Definition: GenericMachineInstrs.h:200
llvm::CombinerHelper::applySimplifyAddToSub
void applySimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo)
Definition: CombinerHelper.cpp:2598
llvm::CombinerHelper::matchTruncStoreMerge
bool matchTruncStoreMerge(MachineInstr &MI, MergeTruncStoresInfo &MatchInfo)
Match a pattern where a wide type scalar value is stored by several narrow stores.
Definition: CombinerHelper.cpp:3590
llvm::CombinerHelper::matchBitfieldExtractFromShr
bool matchBitfieldExtractFromShr(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width.
Definition: CombinerHelper.cpp:4316
llvm::CombinerHelper::tryCombineConcatVectors
bool tryCombineConcatVectors(MachineInstr &MI)
If MI is G_CONCAT_VECTORS, try to combine it.
Definition: CombinerHelper.cpp:217
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::CombinerHelper::matchUndefStore
bool matchUndefStore(MachineInstr &MI)
Return true if a G_STORE instruction MI is storing an undef value.
Definition: CombinerHelper.cpp:2300
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:219
llvm::CombinerHelper::matchReassocConstantInnerLHS
bool matchReassocConstantInnerLHS(GPtrAdd &MI, MachineInstr *LHS, MachineInstr *RHS, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4515
llvm::CombinerHelper::matchBitfieldExtractFromSExtInReg
bool matchBitfieldExtractFromSExtInReg(MachineInstr &MI, BuildFnTy &MatchInfo)
Form a G_SBFX from a G_SEXT_INREG fed by a right shift.
Definition: CombinerHelper.cpp:4251
llvm::CombinerHelper::matchUMulHToLShr
bool matchUMulHToLShr(MachineInstr &MI)
Definition: CombinerHelper.cpp:4917
llvm::CombinerHelper::applyBuildFnNoErase
void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo)
Use a function which takes in a MachineIRBuilder to perform a combine.
Definition: CombinerHelper.cpp:4006
llvm::CombinerHelper::matchBitfieldExtractFromShrAnd
bool matchBitfieldExtractFromShrAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: shr (and x, n), k -> ubfx x, pos, width.
Definition: CombinerHelper.cpp:4365
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::CombinerHelper::matchUndefSelectCmp
bool matchUndefSelectCmp(MachineInstr &MI)
Return true if a G_SELECT instruction MI has an undef comparison.
Definition: CombinerHelper.cpp:2306
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::CombinerHelper::matchSelectToLogical
bool matchSelectToLogical(MachineInstr &MI, BuildFnTy &MatchInfo)
Fold boolean selects to logical operations.
Definition: CombinerHelper.cpp:5552
llvm::CombinerHelper::matchCombineConstPtrAddToI2P
bool matchCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst)
Definition: CombinerHelper.cpp:2057
llvm::CombinerHelper::applyCombineTruncOfShl
void applyCombineTruncOfShl(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Definition: CombinerHelper.cpp:2264
llvm::CombinerHelper::applyRotateOutOfRange
void applyRotateOutOfRange(MachineInstr &MI)
Definition: CombinerHelper.cpp:4105
llvm::ShiftOfShiftedLogic::LogicNonShiftReg
Register LogicNonShiftReg
Definition: CombinerHelper.h:75
llvm::CombinerHelper::Builder
MachineIRBuilder & Builder
Definition: CombinerHelper.h:110
llvm::MergeTruncStoresInfo::LowestIdxStore
GStore * LowestIdxStore
Definition: CombinerHelper.h:83
llvm::CombinerHelper::matchICmpToLHSKnownBits
bool matchICmpToLHSKnownBits(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4173
llvm::CombinerHelper::matchCombineIndexedLoadStore
bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo)
Definition: CombinerHelper.cpp:1007
llvm::CombinerHelper::matchCombineConstantFoldFpUnary
bool matchCombineConstantFoldFpUnary(MachineInstr &MI, Optional< APFloat > &Cst)
Transform fp_instr(cst) to constant result of the fp operation.
Definition: CombinerHelper.cpp:1288
llvm::CombinerHelper::matchCombineShlOfExtend
bool matchCombineShlOfExtend(MachineInstr &MI, RegisterImmPair &MatchData)
Definition: CombinerHelper.cpp:1601
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bool matchConstantOp(const MachineOperand &MOP, int64_t C)
Return true if MOP is defined by a G_CONSTANT with a value equal to C.
Definition: CombinerHelper.cpp:2424
llvm::CombinerHelper::matchEqualDefs
bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2)
Return true if MOP1 and MOP2 are register operands are defined by equivalent instructions.
Definition: CombinerHelper.cpp:2327
llvm::CombinerHelper::replaceSingleDefInstWithOperand
bool replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx)
Delete MI and replace all of its uses with its OpIdx-th operand.
Definition: CombinerHelper.cpp:2433
llvm::CombinerHelper::matchCombineTruncOfExt
bool matchCombineTruncOfExt(MachineInstr &MI, std::pair< Register, unsigned > &MatchInfo)
Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
Definition: CombinerHelper.cpp:2205
llvm::CombinerHelper::matchCombineMulToShl
bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal)
Transform a multiply by a power-of-2 value to a left shift.
Definition: CombinerHelper.cpp:1576
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unsigned ExtendOpcode
Definition: CombinerHelper.h:50
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::CombinerHelper::applyCombineMulByNegativeOne
void applyCombineMulByNegativeOne(MachineInstr &MI)
Transform G_MUL(x, -1) to G_SUB(0, x)
Definition: CombinerHelper.cpp:2163
llvm::CombinerHelper::isLegalOrBeforeLegalizer
bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const
Definition: CombinerHelper.cpp:139
llvm::CombinerHelper::replaceInstWithUndef
bool replaceInstWithUndef(MachineInstr &MI)
Replace an instruction with a G_IMPLICIT_DEF.
Definition: CombinerHelper.cpp:2510
llvm::CombinerHelper::matchCombineInsertVecElts
bool matchCombineInsertVecElts(MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo)
Definition: CombinerHelper.cpp:2538
llvm::CombinerHelper::applySextTruncSextLoad
void applySextTruncSextLoad(MachineInstr &MI)
Definition: CombinerHelper.cpp:797
llvm::CombinerHelper::applyUMulHToLShr
void applyUMulHToLShr(MachineInstr &MI)
Definition: CombinerHelper.cpp:4933
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Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::CombinerHelper::matchAndOrDisjointMask
bool matchAndOrDisjointMask(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4216
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bool matchReassocConstantInnerRHS(GPtrAdd &MI, MachineInstr *RHS, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4491
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bool IsPre
Definition: CombinerHelper.h:58
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The LegalityQuery object bundles together all the information that's needed to decide whether a given...
Definition: LegalizerInfo.h:108
llvm::CombinerHelper::isPredecessor
bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI)
Returns true if DefMI precedes UseMI or they are the same instruction.
Definition: CombinerHelper.cpp:743
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bool matchXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Fold (xor (and x, y), y) -> (and (not x), y) {.
Definition: CombinerHelper.cpp:2995
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SmallVector< InstructionBuildSteps, 2 > InstrsToBuild
Describes instructions to be built during a combine.
Definition: CombinerHelper.h:101
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::CombinerHelper::matchCombineExtOfExt
bool matchCombineExtOfExt(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Transform [asz]ext([asz]ext(x)) to [asz]ext x.
Definition: CombinerHelper.cpp:2111
llvm::CombinerHelper::replaceRegOpWith
void replaceRegOpWith(MachineRegisterInfo &MRI, MachineOperand &FromRegOp, Register ToReg) const
Replace a single register operand with a new register and inform the observer of the changes.
Definition: CombinerHelper.cpp:167
llvm::CombinerHelper::matchBinOpSameVal
bool matchBinOpSameVal(MachineInstr &MI)
Optimize (x op x) -> x.
Definition: CombinerHelper.cpp:2462
llvm::CombinerHelper::matchBitfieldExtractFromAnd
bool matchBitfieldExtractFromAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: and (lshr x, cst), mask -> ubfx x, cst, width.
Definition: CombinerHelper.cpp:4280
llvm::CombinerHelper::matchOrShiftToFunnelShift
bool matchOrShiftToFunnelShift(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4012
llvm::CombinerHelper::applyCombineConstantFoldFpUnary
void applyCombineConstantFoldFpUnary(MachineInstr &MI, Optional< APFloat > &Cst)
Definition: CombinerHelper.cpp:1297
llvm::CombinerHelper::applyCombineExtendingLoads
void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo)
Definition: CombinerHelper.cpp:563
llvm::CombinerHelper::applyAshShlToSextInreg
void applyAshShlToSextInreg(MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo)
Definition: CombinerHelper.cpp:2731
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Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::CombinerHelper::applyCombineInsertVecElts
void applyCombineInsertVecElts(MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo)
Definition: CombinerHelper.cpp:2579
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bool matchSelectSameVal(MachineInstr &MI)
Optimize (cond ? x : x) -> x.
Definition: CombinerHelper.cpp:2454
llvm::CombinerHelper::matchOperandIsUndef
bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is undef.
Definition: CombinerHelper.cpp:2474
llvm::CombinerHelper::applyShiftImmedChain
void applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo)
Definition: CombinerHelper.cpp:1428
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::CombinerHelper::tryEmitMemcpyInline
bool tryEmitMemcpyInline(MachineInstr &MI)
Emit loads and stores that perform the given memcpy.
Definition: CombinerHelper.cpp:1230
llvm::CombinerHelper::matchCombineLoadWithAndMask
bool matchCombineLoadWithAndMask(MachineInstr &MI, BuildFnTy &MatchInfo)
Match (and (load x), mask) -> zextload x.
Definition: CombinerHelper.cpp:673
llvm::CombinerHelper::matchShiftOfShiftedLogic
bool matchShiftOfShiftedLogic(MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo)
If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with...
Definition: CombinerHelper.cpp:1461
llvm::CombinerHelper::matchCombineFAbsOfFAbs
bool matchCombineFAbsOfFAbs(MachineInstr &MI, Register &Src)
Match fabs(fabs(x)) to fabs(x).
Definition: CombinerHelper.cpp:2181
llvm::CombinerHelper::matchCombineAnyExtTrunc
bool matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg)
Transform anyext(trunc(x)) to x.
Definition: CombinerHelper.cpp:2088
llvm::CombinerHelper::matchMulOBy0
bool matchMulOBy0(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: (G_*MULO x, 0) -> 0 + no carry out.
Definition: CombinerHelper.cpp:4725
llvm::CombinerHelper::CombinerHelper
CombinerHelper(GISelChangeObserver &Observer, MachineIRBuilder &B, GISelKnownBits *KB=nullptr, MachineDominatorTree *MDT=nullptr, const LegalizerInfo *LI=nullptr)
Definition: CombinerHelper.cpp:48
llvm::CombinerHelper::matchOperandIsKnownToBeAPowerOfTwo
bool matchOperandIsKnownToBeAPowerOfTwo(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is known to be a power of 2.
Definition: CombinerHelper.cpp:2480
llvm::CombinerHelper::matchCombineFMinMaxNaN
bool matchCombineFMinMaxNaN(MachineInstr &MI, unsigned &Info)
Definition: CombinerHelper.cpp:5608
llvm::CombinerHelper::applyCombineUnmergeMergeToPlainValues
void applyCombineUnmergeMergeToPlainValues(MachineInstr &MI, SmallVectorImpl< Register > &Operands)
Definition: CombinerHelper.cpp:1703
llvm::CombinerHelper::matchSextInRegOfLoad
bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Match sext_inreg(load p), imm -> sextload p.
Definition: CombinerHelper.cpp:804
llvm::CombinerHelper::matchFunnelShiftToRotate
bool matchFunnelShiftToRotate(MachineInstr &MI)
Match an FSHL or FSHR that can be combined to a ROTR or ROTL rotate.
Definition: CombinerHelper.cpp:4066
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const RegisterBank * Bank
Definition: CombinerHelper.h:64
llvm::CombinerHelper::matchSimplifyAddToSub
bool matchSimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo)
Return true if MI is a G_ADD which can be simplified to a G_SUB.
Definition: CombinerHelper.cpp:2518
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const RegisterBankInfo * RBI
Definition: CombinerHelper.h:116
llvm::CombinerHelper::LI
const LegalizerInfo * LI
Definition: CombinerHelper.h:115
llvm::CombinerHelper::applyUDivByConst
void applyUDivByConst(MachineInstr &MI)
Definition: CombinerHelper.cpp:4912
llvm::CombinerHelper::applyFoldBinOpIntoSelect
bool applyFoldBinOpIntoSelect(MachineInstr &MI, const unsigned &SelectOpNo)
SelectOperand is the operand in binary operator MI that is the select to fold.
Definition: CombinerHelper.cpp:3135
llvm::CombinerHelper::matchShiftImmedChain
bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo)
Fold (shift (shift base, x), y) -> (shift base (x+y))
Definition: CombinerHelper.cpp:1383
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void applyXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Definition: CombinerHelper.cpp:3026
llvm::CombinerHelper::applyCombineAddP2IToPtrAdd
void applyCombineAddP2IToPtrAdd(MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute)
Definition: CombinerHelper.cpp:2038
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Definition: CombinerHelper.h:51
llvm::CombinerHelper::applyCombineConstPtrAddToI2P
void applyCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst)
Definition: CombinerHelper.cpp:2078
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Register Reg
Definition: CombinerHelper.h:68
SmallVector.h
llvm::IndexedLoadStoreMatchInfo
Definition: CombinerHelper.h:54
llvm::CombinerHelper::matchExtendThroughPhis
bool matchExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI)
Definition: CombinerHelper.cpp:3790
llvm::CombinerHelper::matchCombineShiftToUnmerge
bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize, unsigned &ShiftVal)
Reduce a shift by a constant to an unmerge and a shift on a half sized type.
Definition: CombinerHelper.cpp:1873
llvm::CombinerHelper::getRegBank
const RegisterBank * getRegBank(Register Reg) const
Get the register bank of Reg.
Definition: CombinerHelper.cpp:187
llvm::CombinerHelper::applyCombineCopy
void applyCombineCopy(MachineInstr &MI)
Definition: CombinerHelper.cpp:210
llvm::CombinerHelper::tryCombine
bool tryCombine(MachineInstr &MI)
Try to transform MI by using all of the above combine functions.
Definition: CombinerHelper.cpp:5652
llvm::InstructionBuildSteps::InstructionBuildSteps
InstructionBuildSteps()=default
Operands to be added to the instruction.
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:104
llvm::CombinerHelper::applyCombineDivRem
void applyCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI)
Definition: CombinerHelper.cpp:1132
llvm::CombinerHelper::replaceInstWithConstant
bool replaceInstWithConstant(MachineInstr &MI, int64_t C)
Replace an instruction with a G_CONSTANT with value C.
Definition: CombinerHelper.cpp:2494
llvm::CombinerHelper::matchCombineUnmergeMergeToPlainValues
bool matchCombineUnmergeMergeToPlainValues(MachineInstr &MI, SmallVectorImpl< Register > &Operands)
Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
Definition: CombinerHelper.cpp:1679
llvm::CombinerHelper::applyCombineP2IToI2P
void applyCombineP2IToI2P(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:2005
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uint64_t ValSum
Definition: CombinerHelper.h:76
llvm::CombinerHelper::applyExtractAllEltsFromBuildVector
void applyExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * >> &MatchInfo)
Definition: CombinerHelper.cpp:3987
llvm::CombinerHelper::applyShiftOfShiftedLogic
void applyShiftOfShiftedLogic(MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo)
Definition: CombinerHelper.cpp:1542
llvm::CombinerHelper::matchOperandIsZero
bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is zero.
Definition: CombinerHelper.cpp:2468
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Definition: CombinerHelper.h:48
llvm::CombinerHelper::matchCombineExtendingLoads
bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo)
Definition: CombinerHelper.cpp:488
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMA
bool matchCombineFAddFpExtFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z) (fadd (fpext (fmul x,...
Definition: CombinerHelper.cpp:5093
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Definition: LegalizerInfo.h:1180
llvm::CombinerHelper::matchMulOBy2
bool matchMulOBy2(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: (G_UMULO x, 2) -> (G_UADDO x, x) (G_SMULO x, 2) -> (G_SADDO x, x)
Definition: CombinerHelper.cpp:4707
llvm::CombinerHelper::applySextInRegOfLoad
void applySextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Definition: CombinerHelper.cpp:845
Register.h
llvm::CombinerHelper::matchAllExplicitUsesAreUndef
bool matchAllExplicitUsesAreUndef(MachineInstr &MI)
Return true if all register explicit use operands on MI are defined by a G_IMPLICIT_DEF.
Definition: CombinerHelper.cpp:2287
llvm::CombinerHelper::replaceSingleDefInstWithReg
bool replaceSingleDefInstWithReg(MachineInstr &MI, Register Replacement)
Delete MI and replace all of its uses with Replacement.
Definition: CombinerHelper.cpp:2444
llvm::CombinerHelper::matchExtractAllEltsFromBuildVector
bool matchExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * >> &MatchInfo)
Definition: CombinerHelper.cpp:3945
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MachineInstr * Logic
Definition: CombinerHelper.h:73
llvm::CombinerHelper::applyCombineIndexedLoadStore
void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo)
Definition: CombinerHelper.cpp:1028
llvm::CombinerHelper::matchRedundantOr
bool matchRedundantOr(MachineInstr &MI, Register &Replacement)
Definition: CombinerHelper.cpp:2825
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:51
llvm::CombinerHelper::applyCombineAnyExtTrunc
void applyCombineAnyExtTrunc(MachineInstr &MI, Register &Reg)
llvm::CombinerHelper::matchCombineTruncOfShl
bool matchCombineTruncOfShl(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Transform trunc (shl x, K) to shl (trunc x), K => K < VT.getScalarSizeInBits().
Definition: CombinerHelper.cpp:2240
llvm::CombinerHelper::applyCombineMulToShl
void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal)
Definition: CombinerHelper.cpp:1588
llvm::CombinerHelper::matchOptBrCondByInvertingCond
bool matchOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond)
If a brcond's true block is not the fallthrough, make it so by inverting the condition and swapping o...
Definition: CombinerHelper.cpp:1164
llvm::CombinerHelper::applyCombineShlOfExtend
void applyCombineShlOfExtend(MachineInstr &MI, const RegisterImmPair &MatchData)
Definition: CombinerHelper.cpp:1638
llvm::CombinerHelper::matchRedundantNegOperands
bool matchRedundantNegOperands(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd x, fneg(y)) -> (fsub x, y) (fadd fneg(x), y) -> (fsub y, x) (fsub x,...
Definition: CombinerHelper.cpp:4950
llvm::CombinerHelper::applyCombineUnmergeWithDeadLanesToTrunc
void applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI)
Definition: CombinerHelper.cpp:1792
llvm::CombinerHelper::matchExtractVecEltBuildVec
bool matchExtractVecEltBuildVec(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:3890
llvm::CombinerHelper::canCombineFMadOrFMA
bool canCombineFMadOrFMA(MachineInstr &MI, bool &AllowFusionGlobally, bool &HasFMAD, bool &Aggressive, bool CanReassociate=false)
Definition: CombinerHelper.cpp:5012
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@ Base
Definition: Discriminator.h:58
llvm::CombinerHelper::matchCombineFSubFpExtFMulToFMadOrFMA
bool matchCombineFSubFpExtFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), (fneg z)) (fsub (fpext (fmul x,...
Definition: CombinerHelper.cpp:5442
llvm::CombinerHelper::matchUDivByConst
bool matchUDivByConst(MachineInstr &MI)
Combine G_UDIV by constant into a multiply by magic constant.
Definition: CombinerHelper.cpp:4869
llvm::CombinerHelper::replaceRegWith
void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const
MachineRegisterInfo::replaceRegWith() and inform the observer of the changes.
Definition: CombinerHelper.cpp:155
llvm::CombinerHelper::matchCombineFSubFNegFMulToFMadOrFMA
bool matchCombineFSubFNegFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) (fsub (fneg (fmul,...
Definition: CombinerHelper.cpp:5395
llvm::CombinerHelper::replaceInstWithFConstant
bool replaceInstWithFConstant(MachineInstr &MI, double C)
Replace an instruction with a G_FCONSTANT with value C.
Definition: CombinerHelper.cpp:2486
llvm::CombinerHelper::matchCombineFAbsOfFNeg
bool matchCombineFAbsOfFNeg(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform fabs(fneg(x)) to fabs(x).
Definition: CombinerHelper.cpp:2188
llvm::CombinerHelper::applyCombineShuffleVector
void applyCombineShuffleVector(MachineInstr &MI, const ArrayRef< Register > Ops)
Replace MI with a concat_vectors with Ops.
Definition: CombinerHelper.cpp:379
llvm::LLT
Definition: LowLevelTypeImpl.h:39