LLVM 20.0.0git
CombinerHelper.h
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1//===-- llvm/CodeGen/GlobalISel/CombinerHelper.h --------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===--------------------------------------------------------------------===//
8/// \file
9/// This contains common combine transformations that may be used in a combine
10/// pass,or by the target elsewhere.
11/// Targets can pick individual opcode transformations from the helper or use
12/// tryCombine which invokes all transformations. All of the transformations
13/// return true if the MachineInstruction changed and false otherwise.
14///
15//===--------------------------------------------------------------------===//
16
17#ifndef LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
18#define LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
19
20#include "llvm/ADT/DenseMap.h"
26#include "llvm/IR/InstrTypes.h"
27#include <functional>
28
29namespace llvm {
30
31class GISelChangeObserver;
32class APInt;
33class ConstantFP;
34class GPtrAdd;
35class GZExtLoad;
36class MachineIRBuilder;
37class MachineInstrBuilder;
38class MachineRegisterInfo;
39class MachineInstr;
40class MachineOperand;
41class GISelKnownBits;
42class MachineDominatorTree;
43class LegalizerInfo;
44struct LegalityQuery;
45class RegisterBank;
46class RegisterBankInfo;
47class TargetLowering;
48class TargetRegisterInfo;
49
51 LLT Ty; // The result type of the extend.
52 unsigned ExtendOpcode; // G_ANYEXT/G_SEXT/G_ZEXT
54};
55
60 bool RematOffset = false; // True if Offset is a constant that needs to be
61 // rematerialized before the new load/store.
62 bool IsPre = false;
63};
64
66 int64_t Imm;
69};
70
73 int64_t Imm;
74};
75
81};
82
83using BuildFnTy = std::function<void(MachineIRBuilder &)>;
84
86 SmallVector<std::function<void(MachineInstrBuilder &)>, 4>;
88 unsigned Opcode = 0; /// The opcode for the produced instruction.
89 OperandBuildSteps OperandFns; /// Operands to be added to the instruction.
93};
94
96 /// Describes instructions to be built during a combine.
100 std::initializer_list<InstructionBuildSteps> InstrsToBuild)
102};
103
105protected:
115
116public:
118 bool IsPreLegalize,
119 GISelKnownBits *KB = nullptr,
120 MachineDominatorTree *MDT = nullptr,
121 const LegalizerInfo *LI = nullptr);
122
124 return KB;
125 }
126
128 return Builder;
129 }
130
131 const TargetLowering &getTargetLowering() const;
132
133 const MachineFunction &getMachineFunction() const;
134
135 const DataLayout &getDataLayout() const;
136
137 LLVMContext &getContext() const;
138
139 /// \returns true if the combiner is running pre-legalization.
140 bool isPreLegalize() const;
141
142 /// \returns true if \p Query is legal on the target.
143 bool isLegal(const LegalityQuery &Query) const;
144
145 /// \return true if the combine is running prior to legalization, or if \p
146 /// Query is legal on the target.
147 bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const;
148
149 /// \return true if the combine is running prior to legalization, or if \p Ty
150 /// is a legal integer constant type on the target.
151 bool isConstantLegalOrBeforeLegalizer(const LLT Ty) const;
152
153 /// MachineRegisterInfo::replaceRegWith() and inform the observer of the changes
154 void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const;
155
156 /// Replace a single register operand with a new register and inform the
157 /// observer of the changes.
159 Register ToReg) const;
160
161 /// Replace the opcode in instruction with a new opcode and inform the
162 /// observer of the changes.
163 void replaceOpcodeWith(MachineInstr &FromMI, unsigned ToOpcode) const;
164
165 /// Get the register bank of \p Reg.
166 /// If Reg has not been assigned a register, a register class,
167 /// or a register bank, then this returns nullptr.
168 ///
169 /// \pre Reg.isValid()
170 const RegisterBank *getRegBank(Register Reg) const;
171
172 /// Set the register bank of \p Reg.
173 /// Does nothing if the RegBank is null.
174 /// This is the counterpart to getRegBank.
175 void setRegBank(Register Reg, const RegisterBank *RegBank) const;
176
177 /// If \p MI is COPY, try to combine it.
178 /// Returns true if MI changed.
179 bool tryCombineCopy(MachineInstr &MI) const;
180 bool matchCombineCopy(MachineInstr &MI) const;
181 void applyCombineCopy(MachineInstr &MI) const;
182
183 /// Returns true if \p DefMI precedes \p UseMI or they are the same
184 /// instruction. Both must be in the same basic block.
185 bool isPredecessor(const MachineInstr &DefMI,
186 const MachineInstr &UseMI) const;
187
188 /// Returns true if \p DefMI dominates \p UseMI. By definition an
189 /// instruction dominates itself.
190 ///
191 /// If we haven't been provided with a MachineDominatorTree during
192 /// construction, this function returns a conservative result that tracks just
193 /// a single basic block.
194 bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI) const;
195
196 /// If \p MI is extend that consumes the result of a load, try to combine it.
197 /// Returns true if MI changed.
200 PreferredTuple &MatchInfo) const;
202 PreferredTuple &MatchInfo) const;
203
204 /// Match (and (load x), mask) -> zextload x
206 BuildFnTy &MatchInfo) const;
207
208 /// Combine a G_EXTRACT_VECTOR_ELT of a load into a narrowed
209 /// load.
211 BuildFnTy &MatchInfo) const;
212
214 IndexedLoadStoreMatchInfo &MatchInfo) const;
216 IndexedLoadStoreMatchInfo &MatchInfo) const;
217
220
221 /// Match sext_inreg(load p), imm -> sextload p
223 std::tuple<Register, unsigned> &MatchInfo) const;
225 std::tuple<Register, unsigned> &MatchInfo) const;
226
227 /// Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM
228 /// when their source operands are identical.
229 bool matchCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI) const;
230 void applyCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI) const;
231
232 /// If a brcond's true block is not the fallthrough, make it so by inverting
233 /// the condition and swapping operands.
235 MachineInstr *&BrCond) const;
237 MachineInstr *&BrCond) const;
238
239 /// If \p MI is G_CONCAT_VECTORS, try to combine it.
240 /// Returns true if MI changed.
241 /// Right now, we support:
242 /// - concat_vector(undef, undef) => undef
243 /// - concat_vector(build_vector(A, B), build_vector(C, D)) =>
244 /// build_vector(A, B, C, D)
245 /// ==========================================================
246 /// Check if the G_CONCAT_VECTORS \p MI is undef or if it
247 /// can be flattened into a build_vector.
248 /// In the first case \p Ops will be empty
249 /// In the second case \p Ops will contain the operands
250 /// needed to produce the flattened build_vector.
251 ///
252 /// \pre MI.getOpcode() == G_CONCAT_VECTORS.
254 SmallVector<Register> &Ops) const;
255 /// Replace \p MI with a flattened build_vector with \p Ops
256 /// or an implicit_def if \p Ops is empty.
258 SmallVector<Register> &Ops) const;
259
261 SmallVector<Register> &Ops) const;
262 /// Replace \p MI with a flattened build_vector with \p Ops
263 /// or an implicit_def if \p Ops is empty.
265 SmallVector<Register> &Ops) const;
266
267 /// Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
268 /// Returns true if MI changed.
269 ///
270 /// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
272 /// Check if the G_SHUFFLE_VECTOR \p MI can be replaced by a
273 /// concat_vectors.
274 /// \p Ops will contain the operands needed to produce the flattened
275 /// concat_vectors.
276 ///
277 /// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
279 SmallVectorImpl<Register> &Ops) const;
280 /// Replace \p MI with a concat_vectors with \p Ops.
282 const ArrayRef<Register> Ops) const;
285
286 /// Optimize memcpy intrinsics et al, e.g. constant len calls.
287 /// /p MaxLen if non-zero specifies the max length of a mem libcall to inline.
288 ///
289 /// For example (pre-indexed):
290 ///
291 /// $addr = G_PTR_ADD $base, $offset
292 /// [...]
293 /// $val = G_LOAD $addr
294 /// [...]
295 /// $whatever = COPY $addr
296 ///
297 /// -->
298 ///
299 /// $val, $addr = G_INDEXED_LOAD $base, $offset, 1 (IsPre)
300 /// [...]
301 /// $whatever = COPY $addr
302 ///
303 /// or (post-indexed):
304 ///
305 /// G_STORE $val, $base
306 /// [...]
307 /// $addr = G_PTR_ADD $base, $offset
308 /// [...]
309 /// $whatever = COPY $addr
310 ///
311 /// -->
312 ///
313 /// $addr = G_INDEXED_STORE $val, $base, $offset
314 /// [...]
315 /// $whatever = COPY $addr
316 bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0) const;
317
318 bool matchPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo) const;
319 void applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo) const;
320
321 /// Fold (shift (shift base, x), y) -> (shift base (x+y))
322 bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo) const;
323 void applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo) const;
324
325 /// If we have a shift-by-constant of a bitwise logic op that itself has a
326 /// shift-by-constant operand with identical opcode, we may be able to convert
327 /// that into 2 independent shifts followed by the logic op.
329 ShiftOfShiftedLogic &MatchInfo) const;
331 ShiftOfShiftedLogic &MatchInfo) const;
332
333 bool matchCommuteShift(MachineInstr &MI, BuildFnTy &MatchInfo) const;
334
335 /// Transform a multiply by a power-of-2 value to a left shift.
336 bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal) const;
337 void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal) const;
338
339 // Transform a G_SUB with constant on the RHS to G_ADD.
340 bool matchCombineSubToAdd(MachineInstr &MI, BuildFnTy &MatchInfo) const;
341
342 // Transform a G_SHL with an extended source into a narrower shift if
343 // possible.
345 RegisterImmPair &MatchData) const;
347 const RegisterImmPair &MatchData) const;
348
349 /// Fold away a merge of an unmerge of the corresponding values.
350 bool matchCombineMergeUnmerge(MachineInstr &MI, Register &MatchInfo) const;
351
352 /// Reduce a shift by a constant to an unmerge and a shift on a half sized
353 /// type. This will not produce a shift smaller than \p TargetShiftSize.
354 bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize,
355 unsigned &ShiftVal) const;
357 const unsigned &ShiftVal) const;
359 unsigned TargetShiftAmount) const;
360
361 /// Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
366
367 /// Transform G_UNMERGE Constant -> Constant1, Constant2, ...
369 SmallVectorImpl<APInt> &Csts) const;
371 SmallVectorImpl<APInt> &Csts) const;
372
373 /// Transform G_UNMERGE G_IMPLICIT_DEF -> G_IMPLICIT_DEF, G_IMPLICIT_DEF, ...
376 std::function<void(MachineIRBuilder &)> &MatchInfo) const;
377
378 /// Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
381
382 /// Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0
385
386 /// Transform fp_instr(cst) to constant result of the fp operation.
388 const ConstantFP *Cst) const;
389
390 /// Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
393
394 /// Transform PtrToInt(IntToPtr(x)) to x.
396
397 /// Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y)
398 /// Transform G_ADD y, (G_PTRTOINT x) -> G_PTRTOINT (G_PTR_ADD x, y)
399 bool
401 std::pair<Register, bool> &PtrRegAndCommute) const;
402 void
404 std::pair<Register, bool> &PtrRegAndCommute) const;
405
406 // Transform G_PTR_ADD (G_PTRTOINT C1), C2 -> C1 + C2
409
410 /// Transform anyext(trunc(x)) to x.
412
413 /// Transform zext(trunc(x)) to x.
415
416 /// Transform trunc (shl x, K) to shl (trunc x), K
417 /// if K < VT.getScalarSizeInBits().
418 ///
419 /// Transforms trunc ([al]shr x, K) to (trunc ([al]shr (MidVT (trunc x)), K))
420 /// if K <= (MidVT.getScalarSizeInBits() - VT.getScalarSizeInBits())
421 /// MidVT is obtained by finding a legal type between the trunc's src and dst
422 /// types.
423 bool
425 std::pair<MachineInstr *, LLT> &MatchInfo) const;
426 void
428 std::pair<MachineInstr *, LLT> &MatchInfo) const;
429
430 /// Return true if any explicit use operand on \p MI is defined by a
431 /// G_IMPLICIT_DEF.
433
434 /// Return true if all register explicit use operands on \p MI are defined by
435 /// a G_IMPLICIT_DEF.
437
438 /// Return true if a G_SHUFFLE_VECTOR instruction \p MI has an undef mask.
440
441 /// Return true if a G_STORE instruction \p MI is storing an undef value.
442 bool matchUndefStore(MachineInstr &MI) const;
443
444 /// Return true if a G_SELECT instruction \p MI has an undef comparison.
446
447 /// Return true if a G_{EXTRACT,INSERT}_VECTOR_ELT has an out of range index.
449
450 /// Return true if a G_SELECT instruction \p MI has a constant comparison. If
451 /// true, \p OpIdx will store the operand index of the known selected value.
452 bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx) const;
453
454 /// Replace an instruction with a G_FCONSTANT with value \p C.
455 void replaceInstWithFConstant(MachineInstr &MI, double C) const;
456
457 /// Replace an instruction with an G_FCONSTANT with value \p CFP.
459
460 /// Replace an instruction with a G_CONSTANT with value \p C.
461 void replaceInstWithConstant(MachineInstr &MI, int64_t C) const;
462
463 /// Replace an instruction with a G_CONSTANT with value \p C.
465
466 /// Replace an instruction with a G_IMPLICIT_DEF.
468
469 /// Delete \p MI and replace all of its uses with its \p OpIdx-th operand.
470 void replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx) const;
471
472 /// Delete \p MI and replace all of its uses with \p Replacement.
474 Register Replacement) const;
475
476 /// @brief Replaces the shift amount in \p MI with ShiftAmt % BW
477 /// @param MI
479
480 /// Return true if \p MOP1 and \p MOP2 are register operands are defined by
481 /// equivalent instructions.
482 bool matchEqualDefs(const MachineOperand &MOP1,
483 const MachineOperand &MOP2) const;
484
485 /// Return true if \p MOP is defined by a G_CONSTANT or splat with a value equal to
486 /// \p C.
487 bool matchConstantOp(const MachineOperand &MOP, int64_t C) const;
488
489 /// Return true if \p MOP is defined by a G_FCONSTANT or splat with a value exactly
490 /// equal to \p C.
491 bool matchConstantFPOp(const MachineOperand &MOP, double C) const;
492
493 /// @brief Checks if constant at \p ConstIdx is larger than \p MI 's bitwidth
494 /// @param ConstIdx Index of the constant
495 bool matchConstantLargerBitWidth(MachineInstr &MI, unsigned ConstIdx) const;
496
497 /// Optimize (cond ? x : x) -> x
499
500 /// Optimize (x op x) -> x
501 bool matchBinOpSameVal(MachineInstr &MI) const;
502
503 /// Check if operand \p OpIdx is zero.
504 bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx) const;
505
506 /// Check if operand \p OpIdx is undef.
507 bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx) const;
508
509 /// Check if operand \p OpIdx is known to be a power of 2.
511 unsigned OpIdx) const;
512
513 /// Erase \p MI
514 void eraseInst(MachineInstr &MI) const;
515
516 /// Return true if MI is a G_ADD which can be simplified to a G_SUB.
518 std::tuple<Register, Register> &MatchInfo) const;
520 std::tuple<Register, Register> &MatchInfo) const;
521
522 /// Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
524 MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo) const;
525
526 /// Replace \p MI with a series of instructions described in \p MatchInfo.
528 InstructionStepsMatchInfo &MatchInfo) const;
529
530 /// Match ashr (shl x, C), C -> sext_inreg (C)
532 std::tuple<Register, int64_t> &MatchInfo) const;
534 std::tuple<Register, int64_t> &MatchInfo) const;
535
536 /// Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0
537 bool matchOverlappingAnd(MachineInstr &MI, BuildFnTy &MatchInfo) const;
538
539 /// \return true if \p MI is a G_AND instruction whose operands are x and y
540 /// where x & y == x or x & y == y. (E.g., one of operands is all-ones value.)
541 ///
542 /// \param [in] MI - The G_AND instruction.
543 /// \param [out] Replacement - A register the G_AND should be replaced with on
544 /// success.
545 bool matchRedundantAnd(MachineInstr &MI, Register &Replacement) const;
546
547 /// \return true if \p MI is a G_OR instruction whose operands are x and y
548 /// where x | y == x or x | y == y. (E.g., one of operands is all-zeros
549 /// value.)
550 ///
551 /// \param [in] MI - The G_OR instruction.
552 /// \param [out] Replacement - A register the G_OR should be replaced with on
553 /// success.
554 bool matchRedundantOr(MachineInstr &MI, Register &Replacement) const;
555
556 /// \return true if \p MI is a G_SEXT_INREG that can be erased.
558
559 /// Combine inverting a result of a compare into the opposite cond code.
561 SmallVectorImpl<Register> &RegsToNegate) const;
563 SmallVectorImpl<Register> &RegsToNegate) const;
564
565 /// Fold (xor (and x, y), y) -> (and (not x), y)
566 ///{
568 std::pair<Register, Register> &MatchInfo) const;
570 std::pair<Register, Register> &MatchInfo) const;
571 ///}
572
573 /// Combine G_PTR_ADD with nullptr to G_INTTOPTR
574 bool matchPtrAddZero(MachineInstr &MI) const;
575 void applyPtrAddZero(MachineInstr &MI) const;
576
577 /// Combine G_UREM x, (known power of 2) to an add and bitmasking.
579
580 /// Push a binary operator through a select on constants.
581 ///
582 /// binop (select cond, K0, K1), K2 ->
583 /// select cond, (binop K0, K2), (binop K1, K2)
584 bool matchFoldBinOpIntoSelect(MachineInstr &MI, unsigned &SelectOpNo) const;
586 const unsigned &SelectOpNo) const;
587
589 SmallVectorImpl<Register> &MatchInfo) const;
590
592 SmallVectorImpl<Register> &MatchInfo) const;
593
594 /// Match expression trees of the form
595 ///
596 /// \code
597 /// sN *a = ...
598 /// sM val = a[0] | (a[1] << N) | (a[2] << 2N) | (a[3] << 3N) ...
599 /// \endcode
600 ///
601 /// And check if the tree can be replaced with a M-bit load + possibly a
602 /// bswap.
603 bool matchLoadOrCombine(MachineInstr &MI, BuildFnTy &MatchInfo) const;
604
607
610
613 SmallVectorImpl<std::pair<Register, MachineInstr *>> &MatchInfo) const;
616 SmallVectorImpl<std::pair<Register, MachineInstr *>> &MatchInfo) const;
617
618 /// Use a function which takes in a MachineIRBuilder to perform a combine.
619 /// By default, it erases the instruction \p MI from the function.
620 void applyBuildFn(MachineInstr &MI, BuildFnTy &MatchInfo) const;
621 /// Use a function which takes in a MachineIRBuilder to perform a combine.
622 /// This variant does not erase \p MI after calling the build function.
623 void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo) const;
624
625 bool matchOrShiftToFunnelShift(MachineInstr &MI, BuildFnTy &MatchInfo) const;
630
631 bool matchUseVectorTruncate(MachineInstr &MI, Register &MatchInfo) const;
632 void applyUseVectorTruncate(MachineInstr &MI, Register &MatchInfo) const;
633
634 /// \returns true if a G_ICMP instruction \p MI can be replaced with a true
635 /// or false constant based off of KnownBits information.
637 int64_t &MatchInfo) const;
638
639 /// \returns true if a G_ICMP \p MI can be replaced with its LHS based off of
640 /// KnownBits information.
641 bool matchICmpToLHSKnownBits(MachineInstr &MI, BuildFnTy &MatchInfo) const;
642
643 /// \returns true if (and (or x, c1), c2) can be replaced with (and x, c2)
644 bool matchAndOrDisjointMask(MachineInstr &MI, BuildFnTy &MatchInfo) const;
645
647 BuildFnTy &MatchInfo) const;
648 /// Match: and (lshr x, cst), mask -> ubfx x, cst, width
650 BuildFnTy &MatchInfo) const;
651
652 /// Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width
654 BuildFnTy &MatchInfo) const;
655
656 /// Match: shr (and x, n), k -> ubfx x, pos, width
658 BuildFnTy &MatchInfo) const;
659
660 // Helpers for reassociation:
662 BuildFnTy &MatchInfo) const;
665 BuildFnTy &MatchInfo) const;
668 BuildFnTy &MatchInfo) const;
669 /// Reassociate pointer calculations with G_ADD involved, to allow better
670 /// addressing mode usage.
671 bool matchReassocPtrAdd(MachineInstr &MI, BuildFnTy &MatchInfo) const;
672
673 /// Try to reassociate to reassociate operands of a commutative binop.
674 bool tryReassocBinOp(unsigned Opc, Register DstReg, Register Op0,
675 Register Op1, BuildFnTy &MatchInfo) const;
676 /// Reassociate commutative binary operations like G_ADD.
677 bool matchReassocCommBinOp(MachineInstr &MI, BuildFnTy &MatchInfo) const;
678
679 /// Do constant folding when opportunities are exposed after MIR building.
680 bool matchConstantFoldCastOp(MachineInstr &MI, APInt &MatchInfo) const;
681
682 /// Do constant folding when opportunities are exposed after MIR building.
683 bool matchConstantFoldBinOp(MachineInstr &MI, APInt &MatchInfo) const;
684
685 /// Do constant FP folding when opportunities are exposed after MIR building.
686 bool matchConstantFoldFPBinOp(MachineInstr &MI, ConstantFP *&MatchInfo) const;
687
688 /// Constant fold G_FMA/G_FMAD.
689 bool matchConstantFoldFMA(MachineInstr &MI, ConstantFP *&MatchInfo) const;
690
691 /// \returns true if it is possible to narrow the width of a scalar binop
692 /// feeding a G_AND instruction \p MI.
693 bool matchNarrowBinopFeedingAnd(MachineInstr &MI, BuildFnTy &MatchInfo) const;
694
695 /// Given an G_UDIV \p MI expressing a divide by constant, return an
696 /// expression that implements it by multiplying by a magic number.
697 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
699 /// Combine G_UDIV by constant into a multiply by magic constant.
700 bool matchUDivByConst(MachineInstr &MI) const;
701 void applyUDivByConst(MachineInstr &MI) const;
702
703 /// Given an G_SDIV \p MI expressing a signed divide by constant, return an
704 /// expression that implements it by multiplying by a magic number.
705 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
707 bool matchSDivByConst(MachineInstr &MI) const;
708 void applySDivByConst(MachineInstr &MI) const;
709
710 /// Given an G_SDIV \p MI expressing a signed divided by a pow2 constant,
711 /// return expressions that implements it by shifting.
712 bool matchDivByPow2(MachineInstr &MI, bool IsSigned) const;
713 void applySDivByPow2(MachineInstr &MI) const;
714 /// Given an G_UDIV \p MI expressing an unsigned divided by a pow2 constant,
715 /// return expressions that implements it by shifting.
716 void applyUDivByPow2(MachineInstr &MI) const;
717
718 // G_UMULH x, (1 << c)) -> x >> (bitwidth - c)
719 bool matchUMulHToLShr(MachineInstr &MI) const;
720 void applyUMulHToLShr(MachineInstr &MI) const;
721
722 /// Try to transform \p MI by using all of the above
723 /// combine functions. Returns true if changed.
725
726 /// Emit loads and stores that perform the given memcpy.
727 /// Assumes \p MI is a G_MEMCPY_INLINE
728 /// TODO: implement dynamically sized inline memcpy,
729 /// and rename: s/bool tryEmit/void emit/
731
732 /// Match:
733 /// (G_UMULO x, 2) -> (G_UADDO x, x)
734 /// (G_SMULO x, 2) -> (G_SADDO x, x)
735 bool matchMulOBy2(MachineInstr &MI, BuildFnTy &MatchInfo) const;
736
737 /// Match:
738 /// (G_*MULO x, 0) -> 0 + no carry out
739 bool matchMulOBy0(MachineInstr &MI, BuildFnTy &MatchInfo) const;
740
741 /// Match:
742 /// (G_*ADDE x, y, 0) -> (G_*ADDO x, y)
743 /// (G_*SUBE x, y, 0) -> (G_*SUBO x, y)
744 bool matchAddEToAddO(MachineInstr &MI, BuildFnTy &MatchInfo) const;
745
746 /// Transform (fadd x, fneg(y)) -> (fsub x, y)
747 /// (fadd fneg(x), y) -> (fsub y, x)
748 /// (fsub x, fneg(y)) -> (fadd x, y)
749 /// (fmul fneg(x), fneg(y)) -> (fmul x, y)
750 /// (fdiv fneg(x), fneg(y)) -> (fdiv x, y)
751 /// (fmad fneg(x), fneg(y), z) -> (fmad x, y, z)
752 /// (fma fneg(x), fneg(y), z) -> (fma x, y, z)
753 bool matchRedundantNegOperands(MachineInstr &MI, BuildFnTy &MatchInfo) const;
754
755 bool matchFsubToFneg(MachineInstr &MI, Register &MatchInfo) const;
756 void applyFsubToFneg(MachineInstr &MI, Register &MatchInfo) const;
757
758 bool canCombineFMadOrFMA(MachineInstr &MI, bool &AllowFusionGlobally,
759 bool &HasFMAD, bool &Aggressive,
760 bool CanReassociate = false) const;
761
762 /// Transform (fadd (fmul x, y), z) -> (fma x, y, z)
763 /// (fadd (fmul x, y), z) -> (fmad x, y, z)
765 BuildFnTy &MatchInfo) const;
766
767 /// Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z)
768 /// (fadd (fpext (fmul x, y)), z) -> (fmad (fpext x), (fpext y), z)
770 BuildFnTy &MatchInfo) const;
771
772 /// Transform (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y, (fma u, v, z))
773 /// (fadd (fmad x, y, (fmul u, v)), z) -> (fmad x, y, (fmad u, v, z))
775 BuildFnTy &MatchInfo) const;
776
777 // Transform (fadd (fma x, y, (fpext (fmul u, v))), z)
778 // -> (fma x, y, (fma (fpext u), (fpext v), z))
779 // (fadd (fmad x, y, (fpext (fmul u, v))), z)
780 // -> (fmad x, y, (fmad (fpext u), (fpext v), z))
781 bool
783 BuildFnTy &MatchInfo) const;
784
785 /// Transform (fsub (fmul x, y), z) -> (fma x, y, -z)
786 /// (fsub (fmul x, y), z) -> (fmad x, y, -z)
788 BuildFnTy &MatchInfo) const;
789
790 /// Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
791 /// (fsub (fneg (fmul, x, y)), z) -> (fmad (fneg x), y, (fneg z))
793 BuildFnTy &MatchInfo) const;
794
795 /// Transform (fsub (fpext (fmul x, y)), z)
796 /// -> (fma (fpext x), (fpext y), (fneg z))
797 /// (fsub (fpext (fmul x, y)), z)
798 /// -> (fmad (fpext x), (fpext y), (fneg z))
800 BuildFnTy &MatchInfo) const;
801
802 /// Transform (fsub (fpext (fneg (fmul x, y))), z)
803 /// -> (fneg (fma (fpext x), (fpext y), z))
804 /// (fsub (fpext (fneg (fmul x, y))), z)
805 /// -> (fneg (fmad (fpext x), (fpext y), z))
807 BuildFnTy &MatchInfo) const;
808
809 bool matchCombineFMinMaxNaN(MachineInstr &MI, unsigned &Info) const;
810
811 /// Transform G_ADD(x, G_SUB(y, x)) to y.
812 /// Transform G_ADD(G_SUB(y, x), x) to y.
813 bool matchAddSubSameReg(MachineInstr &MI, Register &Src) const;
814
816 Register &MatchInfo) const;
817 bool matchTruncBuildVectorFold(MachineInstr &MI, Register &MatchInfo) const;
819 Register &MatchInfo) const;
820
821 /// Transform:
822 /// (x + y) - y -> x
823 /// (x + y) - x -> y
824 /// x - (y + x) -> 0 - y
825 /// x - (x + z) -> 0 - z
826 bool matchSubAddSameReg(MachineInstr &MI, BuildFnTy &MatchInfo) const;
827
828 /// \returns true if it is possible to simplify a select instruction \p MI
829 /// to a min/max instruction of some sort.
831 BuildFnTy &MatchInfo) const;
832
833 /// Transform:
834 /// (X + Y) == X -> Y == 0
835 /// (X - Y) == X -> Y == 0
836 /// (X ^ Y) == X -> Y == 0
837 /// (X + Y) != X -> Y != 0
838 /// (X - Y) != X -> Y != 0
839 /// (X ^ Y) != X -> Y != 0
841 BuildFnTy &MatchInfo) const;
842
843 /// Match shifts greater or equal to the bitwidth of the operation.
844 bool matchShiftsTooBig(MachineInstr &MI) const;
845
846 /// Match constant LHS ops that should be commuted.
848
849 /// Combine sext of trunc.
850 bool matchSextOfTrunc(const MachineOperand &MO, BuildFnTy &MatchInfo) const;
851
852 /// Combine zext of trunc.
853 bool matchZextOfTrunc(const MachineOperand &MO, BuildFnTy &MatchInfo) const;
854
855 /// Combine zext nneg to sext.
856 bool matchNonNegZext(const MachineOperand &MO, BuildFnTy &MatchInfo) const;
857
858 /// Match constant LHS FP ops that should be commuted.
860
861 // Given a binop \p MI, commute operands 1 and 2.
863
864 /// Combine select to integer min/max.
865 bool matchSelectIMinMax(const MachineOperand &MO, BuildFnTy &MatchInfo) const;
866
867 /// Combine selects.
868 bool matchSelect(MachineInstr &MI, BuildFnTy &MatchInfo) const;
869
870 /// Combine ands.
871 bool matchAnd(MachineInstr &MI, BuildFnTy &MatchInfo) const;
872
873 /// Combine ors.
874 bool matchOr(MachineInstr &MI, BuildFnTy &MatchInfo) const;
875
876 /// trunc (binop X, C) --> binop (trunc X, trunc C).
877 bool matchNarrowBinop(const MachineInstr &TruncMI,
878 const MachineInstr &BinopMI,
879 BuildFnTy &MatchInfo) const;
880
881 bool matchCastOfInteger(const MachineInstr &CastMI, APInt &MatchInfo) const;
882
883 /// Combine addos.
884 bool matchAddOverflow(MachineInstr &MI, BuildFnTy &MatchInfo) const;
885
886 /// Combine extract vector element.
887 bool matchExtractVectorElement(MachineInstr &MI, BuildFnTy &MatchInfo) const;
888
889 /// Combine extract vector element with a build vector on the vector register.
891 const MachineInstr &MI2,
892 BuildFnTy &MatchInfo) const;
893
894 /// Combine extract vector element with a build vector trunc on the vector
895 /// register.
896 bool
898 BuildFnTy &MatchInfo) const;
899
900 /// Combine extract vector element with a shuffle vector on the vector
901 /// register.
903 const MachineInstr &MI2,
904 BuildFnTy &MatchInfo) const;
905
906 /// Combine extract vector element with a insert vector element on the vector
907 /// register and different indices.
908 bool
910 BuildFnTy &MatchInfo) const;
911
912 /// Remove references to rhs if it is undef
913 bool matchShuffleUndefRHS(MachineInstr &MI, BuildFnTy &MatchInfo) const;
914
915 /// Turn shuffle a, b, mask -> shuffle undef, b, mask iff mask does not
916 /// reference a.
917 bool matchShuffleDisjointMask(MachineInstr &MI, BuildFnTy &MatchInfo) const;
918
919 /// Use a function which takes in a MachineIRBuilder to perform a combine.
920 /// By default, it erases the instruction def'd on \p MO from the function.
921 void applyBuildFnMO(const MachineOperand &MO, BuildFnTy &MatchInfo) const;
922
923 /// Match FPOWI if it's safe to extend it into a series of multiplications.
924 bool matchFPowIExpansion(MachineInstr &MI, int64_t Exponent) const;
925
926 /// Expands FPOWI into a series of multiplications and a division if the
927 /// exponent is negative.
928 void applyExpandFPowI(MachineInstr &MI, int64_t Exponent) const;
929
930 /// Combine insert vector element OOB.
932 BuildFnTy &MatchInfo) const;
933
935 BuildFnTy &MatchInfo) const;
936
937 bool matchAddOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo) const;
938
939 bool matchMulOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo) const;
940
941 bool matchSubOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo) const;
942
943 bool matchShlOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo) const;
944
945 /// Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
946 bool matchTruncateOfExt(const MachineInstr &Root, const MachineInstr &ExtMI,
947 BuildFnTy &MatchInfo) const;
948
949 bool matchCastOfSelect(const MachineInstr &Cast, const MachineInstr &SelectMI,
950 BuildFnTy &MatchInfo) const;
952 BuildFnTy &MatchInfo) const;
953
955 BuildFnTy &MatchInfo) const;
956
958 BuildFnTy &MatchInfo) const;
959
961 BuildFnTy &MatchInfo) const;
962
963 // fold ((A-C1)+C2) -> (A+(C2-C1))
965 BuildFnTy &MatchInfo) const;
966
967 bool matchExtOfExt(const MachineInstr &FirstMI, const MachineInstr &SecondMI,
968 BuildFnTy &MatchInfo) const;
969
970 bool matchCastOfBuildVector(const MachineInstr &CastMI,
971 const MachineInstr &BVMI,
972 BuildFnTy &MatchInfo) const;
973
975 BuildFnTy &MatchInfo) const;
977 BuildFnTy &MatchInfo) const;
978
979 // unmerge_values(anyext(build vector)) -> build vector(anyext)
981 BuildFnTy &MatchInfo) const;
982
983 // merge_values(_, undef) -> anyext
984 bool matchMergeXAndUndef(const MachineInstr &MI, BuildFnTy &MatchInfo) const;
985
986 // merge_values(_, zero) -> zext
987 bool matchMergeXAndZero(const MachineInstr &MI, BuildFnTy &MatchInfo) const;
988
989 // overflow sub
990 bool matchSuboCarryOut(const MachineInstr &MI, BuildFnTy &MatchInfo) const;
991
992private:
993 /// Checks for legality of an indexed variant of \p LdSt.
994 bool isIndexedLoadStoreLegal(GLoadStore &LdSt) const;
995 /// Given a non-indexed load or store instruction \p MI, find an offset that
996 /// can be usefully and legally folded into it as a post-indexing operation.
997 ///
998 /// \returns true if a candidate is found.
999 bool findPostIndexCandidate(GLoadStore &MI, Register &Addr, Register &Base,
1000 Register &Offset, bool &RematOffset) const;
1001
1002 /// Given a non-indexed load or store instruction \p MI, find an offset that
1003 /// can be usefully and legally folded into it as a pre-indexing operation.
1004 ///
1005 /// \returns true if a candidate is found.
1006 bool findPreIndexCandidate(GLoadStore &MI, Register &Addr, Register &Base,
1007 Register &Offset) const;
1008
1009 /// Helper function for matchLoadOrCombine. Searches for Registers
1010 /// which may have been produced by a load instruction + some arithmetic.
1011 ///
1012 /// \param [in] Root - The search root.
1013 ///
1014 /// \returns The Registers found during the search.
1015 std::optional<SmallVector<Register, 8>>
1016 findCandidatesForLoadOrCombine(const MachineInstr *Root) const;
1017
1018 /// Helper function for matchLoadOrCombine.
1019 ///
1020 /// Checks if every register in \p RegsToVisit is defined by a load
1021 /// instruction + some arithmetic.
1022 ///
1023 /// \param [out] MemOffset2Idx - Maps the byte positions each load ends up
1024 /// at to the index of the load.
1025 /// \param [in] MemSizeInBits - The number of bits each load should produce.
1026 ///
1027 /// \returns On success, a 3-tuple containing lowest-index load found, the
1028 /// lowest index, and the last load in the sequence.
1029 std::optional<std::tuple<GZExtLoad *, int64_t, GZExtLoad *>>
1030 findLoadOffsetsForLoadOrCombine(
1032 const SmallVector<Register, 8> &RegsToVisit,
1033 const unsigned MemSizeInBits) const;
1034
1035 /// Examines the G_PTR_ADD instruction \p PtrAdd and determines if performing
1036 /// a re-association of its operands would break an existing legal addressing
1037 /// mode that the address computation currently represents.
1038 bool reassociationCanBreakAddressingModePattern(MachineInstr &PtrAdd) const;
1039
1040 /// Behavior when a floating point min/max is given one NaN and one
1041 /// non-NaN as input.
1042 enum class SelectPatternNaNBehaviour {
1043 NOT_APPLICABLE = 0, /// NaN behavior not applicable.
1044 RETURNS_NAN, /// Given one NaN input, returns the NaN.
1045 RETURNS_OTHER, /// Given one NaN input, returns the non-NaN.
1046 RETURNS_ANY /// Given one NaN input, can return either (or both operands are
1047 /// known non-NaN.)
1048 };
1049
1050 /// \returns which of \p LHS and \p RHS would be the result of a non-equality
1051 /// floating point comparison where one of \p LHS and \p RHS may be NaN.
1052 ///
1053 /// If both \p LHS and \p RHS may be NaN, returns
1054 /// SelectPatternNaNBehaviour::NOT_APPLICABLE.
1055 SelectPatternNaNBehaviour
1056 computeRetValAgainstNaN(Register LHS, Register RHS,
1057 bool IsOrderedComparison) const;
1058
1059 /// Determines the floating point min/max opcode which should be used for
1060 /// a G_SELECT fed by a G_FCMP with predicate \p Pred.
1061 ///
1062 /// \returns 0 if this G_SELECT should not be combined to a floating point
1063 /// min or max. If it should be combined, returns one of
1064 ///
1065 /// * G_FMAXNUM
1066 /// * G_FMAXIMUM
1067 /// * G_FMINNUM
1068 /// * G_FMINIMUM
1069 ///
1070 /// Helper function for matchFPSelectToMinMax.
1071 unsigned getFPMinMaxOpcForSelect(CmpInst::Predicate Pred, LLT DstTy,
1072 SelectPatternNaNBehaviour VsNaNRetVal) const;
1073
1074 /// Handle floating point cases for matchSimplifySelectToMinMax.
1075 ///
1076 /// E.g.
1077 ///
1078 /// select (fcmp uge x, 1.0) x, 1.0 -> fmax x, 1.0
1079 /// select (fcmp uge x, 1.0) 1.0, x -> fminnm x, 1.0
1080 bool matchFPSelectToMinMax(Register Dst, Register Cond, Register TrueVal,
1081 Register FalseVal, BuildFnTy &MatchInfo) const;
1082
1083 /// Try to fold selects to logical operations.
1084 bool tryFoldBoolSelectToLogic(GSelect *Select, BuildFnTy &MatchInfo) const;
1085
1086 bool tryFoldSelectOfConstants(GSelect *Select, BuildFnTy &MatchInfo) const;
1087
1088 bool isOneOrOneSplat(Register Src, bool AllowUndefs) const;
1089 bool isZeroOrZeroSplat(Register Src, bool AllowUndefs) const;
1090 bool isConstantSplatVector(Register Src, int64_t SplatValue,
1091 bool AllowUndefs) const;
1092 bool isConstantOrConstantVectorI(Register Src) const;
1093
1094 std::optional<APInt> getConstantOrConstantSplatVector(Register Src) const;
1095
1096 /// Fold (icmp Pred1 V1, C1) && (icmp Pred2 V2, C2)
1097 /// or (icmp Pred1 V1, C1) || (icmp Pred2 V2, C2)
1098 /// into a single comparison using range-based reasoning.
1099 bool tryFoldAndOrOrICmpsUsingRanges(GLogicalBinOp *Logic,
1100 BuildFnTy &MatchInfo) const;
1101
1102 // Simplify (cmp cc0 x, y) (&& or ||) (cmp cc1 x, y) -> cmp cc2 x, y.
1103 bool tryFoldLogicOfFCmps(GLogicalBinOp *Logic, BuildFnTy &MatchInfo) const;
1104
1105 bool isCastFree(unsigned Opcode, LLT ToTy, LLT FromTy) const;
1106
1107 bool constantFoldICmp(const GICmp &ICmp, const GIConstant &LHSCst,
1108 const GIConstant &RHSCst, BuildFnTy &MatchInfo) const;
1109 bool constantFoldFCmp(const GFCmp &FCmp, const GFConstant &LHSCst,
1110 const GFConstant &RHSCst, BuildFnTy &MatchInfo) const;
1111};
1112} // namespace llvm
1113
1114#endif
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
AMDGPU Register Bank Select
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
This file defines the DenseMap class.
uint64_t Addr
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
IRTranslator LLVM IR MI
Implement a low-level type suitable for MachineInstr level instruction selection.
mir Rename Register Operands
unsigned Reg
const SmallVectorImpl< MachineOperand > & Cond
This file defines the SmallVector class.
Value * RHS
Value * LHS
Class for arbitrary precision integers.
Definition: APInt.h:78
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:673
void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo) const
bool matchCommuteShift(MachineInstr &MI, BuildFnTy &MatchInfo) const
bool matchFoldC2MinusAPlusC1(const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool matchLoadOrCombine(MachineInstr &MI, BuildFnTy &MatchInfo) const
Match expression trees of the form.
bool tryCombine(MachineInstr &MI) const
Try to transform MI by using all of the above combine functions.
const RegisterBank * getRegBank(Register Reg) const
Get the register bank of Reg.
void applyPtrAddZero(MachineInstr &MI) const
bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2) const
Return true if MOP1 and MOP2 are register operands are defined by equivalent instructions.
bool matchConstantFoldBinOp(MachineInstr &MI, APInt &MatchInfo) const
Do constant folding when opportunities are exposed after MIR building.
void applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI) const
bool matchUnmergeValuesAnyExtBuildVector(const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool matchSelectSameVal(MachineInstr &MI) const
Optimize (cond ? x : x) -> x.
bool matchAddEToAddO(MachineInstr &MI, BuildFnTy &MatchInfo) const
Match: (G_*ADDE x, y, 0) -> (G_*ADDO x, y) (G_*SUBE x, y, 0) -> (G_*SUBO x, y)
bool matchShuffleToExtract(MachineInstr &MI) const
bool matchReassocConstantInnerRHS(GPtrAdd &MI, MachineInstr *RHS, BuildFnTy &MatchInfo) const
bool matchBitfieldExtractFromShr(MachineInstr &MI, BuildFnTy &MatchInfo) const
Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width.
bool matchFoldAMinusC1PlusC2(const MachineInstr &MI, BuildFnTy &MatchInfo) const
void applySimplifyURemByPow2(MachineInstr &MI) const
Combine G_UREM x, (known power of 2) to an add and bitmasking.
bool matchCombineUnmergeZExtToZExt(MachineInstr &MI) const
Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0.
bool matchPtrAddZero(MachineInstr &MI) const
}
void applyCombineConcatVectors(MachineInstr &MI, SmallVector< Register > &Ops) const
Replace MI with a flattened build_vector with Ops or an implicit_def if Ops is empty.
void applyXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo) const
bool canCombineFMadOrFMA(MachineInstr &MI, bool &AllowFusionGlobally, bool &HasFMAD, bool &Aggressive, bool CanReassociate=false) const
bool matchFoldAPlusC1MinusC2(const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool matchExtractVecEltBuildVec(MachineInstr &MI, Register &Reg) const
void applyCombineUnmergeConstant(MachineInstr &MI, SmallVectorImpl< APInt > &Csts) const
bool matchSDivByConst(MachineInstr &MI) const
bool matchCombineFAddFpExtFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo) const
Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z) (fadd (fpext (fmul x,...
bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo) const
void applyCombineShuffleConcat(MachineInstr &MI, SmallVector< Register > &Ops) const
Replace MI with a flattened build_vector with Ops or an implicit_def if Ops is empty.
void replaceSingleDefInstWithReg(MachineInstr &MI, Register Replacement) const
Delete MI and replace all of its uses with Replacement.
bool matchZextOfTrunc(const MachineOperand &MO, BuildFnTy &MatchInfo) const
Combine zext of trunc.
bool matchCombineExtractedVectorLoad(MachineInstr &MI, BuildFnTy &MatchInfo) const
Combine a G_EXTRACT_VECTOR_ELT of a load into a narrowed load.
void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const
MachineRegisterInfo::replaceRegWith() and inform the observer of the changes.
void replaceRegOpWith(MachineRegisterInfo &MRI, MachineOperand &FromRegOp, Register ToReg) const
Replace a single register operand with a new register and inform the observer of the changes.
bool matchReassocCommBinOp(MachineInstr &MI, BuildFnTy &MatchInfo) const
Reassociate commutative binary operations like G_ADD.
bool matchExtractVectorElementWithBuildVectorTrunc(const MachineOperand &MO, BuildFnTy &MatchInfo) const
Combine extract vector element with a build vector trunc on the vector register.
void applyBuildFnMO(const MachineOperand &MO, BuildFnTy &MatchInfo) const
Use a function which takes in a MachineIRBuilder to perform a combine.
bool matchCommuteConstantToRHS(MachineInstr &MI) const
Match constant LHS ops that should be commuted.
const DataLayout & getDataLayout() const
bool matchBinOpSameVal(MachineInstr &MI) const
Optimize (x op x) -> x.
bool matchCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI) const
Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM when their source operands are iden...
bool matchNonNegZext(const MachineOperand &MO, BuildFnTy &MatchInfo) const
Combine zext nneg to sext.
void applyUMulHToLShr(MachineInstr &MI) const
void applyNotCmp(MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate) const
bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo) const
Fold (shift (shift base, x), y) -> (shift base (x+y))
void applyCombineI2PToP2I(MachineInstr &MI, Register &Reg) const
bool matchTruncLshrBuildVectorFold(MachineInstr &MI, Register &MatchInfo) const
bool matchAllExplicitUsesAreUndef(MachineInstr &MI) const
Return true if all register explicit use operands on MI are defined by a G_IMPLICIT_DEF.
bool matchOrShiftToFunnelShift(MachineInstr &MI, BuildFnTy &MatchInfo) const
bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI) const
Returns true if DefMI precedes UseMI or they are the same instruction.
bool matchPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo) const
const TargetLowering & getTargetLowering() const
bool matchExtractVectorElementWithDifferentIndices(const MachineOperand &MO, BuildFnTy &MatchInfo) const
Combine extract vector element with a insert vector element on the vector register and different indi...
bool matchShuffleUndefRHS(MachineInstr &MI, BuildFnTy &MatchInfo) const
Remove references to rhs if it is undef.
void applyBuildInstructionSteps(MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo) const
Replace MI with a series of instructions described in MatchInfo.
void applySDivByPow2(MachineInstr &MI) const
void applySimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo) const
void applyUDivByPow2(MachineInstr &MI) const
Given an G_UDIV MI expressing an unsigned divided by a pow2 constant, return expressions that impleme...
bool matchOr(MachineInstr &MI, BuildFnTy &MatchInfo) const
Combine ors.
bool matchInsertVectorElementOOB(MachineInstr &MI, BuildFnTy &MatchInfo) const
Combine insert vector element OOB.
void applySDivByConst(MachineInstr &MI) const
bool matchSimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo) const
Return true if MI is a G_ADD which can be simplified to a G_SUB.
void replaceInstWithConstant(MachineInstr &MI, int64_t C) const
Replace an instruction with a G_CONSTANT with value C.
bool tryEmitMemcpyInline(MachineInstr &MI) const
Emit loads and stores that perform the given memcpy.
bool matchCombineFSubFpExtFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo) const
Transform (fsub (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), (fneg z)) (fsub (fpext (fmul x,...
void applyFsubToFneg(MachineInstr &MI, Register &MatchInfo) const
bool matchConstantLargerBitWidth(MachineInstr &MI, unsigned ConstIdx) const
Checks if constant at ConstIdx is larger than MI 's bitwidth.
GISelKnownBits * getKnownBits() const
void applyCombineCopy(MachineInstr &MI) const
bool matchExtractVectorElement(MachineInstr &MI, BuildFnTy &MatchInfo) const
Combine extract vector element.
bool matchSextOfTrunc(const MachineOperand &MO, BuildFnTy &MatchInfo) const
Combine sext of trunc.
bool matchAddSubSameReg(MachineInstr &MI, Register &Src) const
Transform G_ADD(x, G_SUB(y, x)) to y.
bool matchCombineShlOfExtend(MachineInstr &MI, RegisterImmPair &MatchData) const
bool matchMergeXAndZero(const MachineInstr &MI, BuildFnTy &MatchInfo) const
void applyCombineAddP2IToPtrAdd(MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute) const
bool matchUDivByConst(MachineInstr &MI) const
Combine G_UDIV by constant into a multiply by magic constant.
bool matchCombineFSubFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo) const
Transform (fsub (fmul x, y), z) -> (fma x, y, -z) (fsub (fmul x, y), z) -> (fmad x,...
bool matchCombineFAddFMAFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo) const
Transform (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y, (fma u, v, z)) (fadd (fmad x,...
bool matchSextTruncSextLoad(MachineInstr &MI) const
bool matchMulOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo) const
bool matchCombineMergeUnmerge(MachineInstr &MI, Register &MatchInfo) const
Fold away a merge of an unmerge of the corresponding values.
bool matchCombineInsertVecElts(MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo) const
bool matchDivByPow2(MachineInstr &MI, bool IsSigned) const
Given an G_SDIV MI expressing a signed divided by a pow2 constant, return expressions that implements...
bool matchAddOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo) const
bool matchNarrowBinopFeedingAnd(MachineInstr &MI, BuildFnTy &MatchInfo) const
bool matchShlOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo) const
bool matchRedundantNegOperands(MachineInstr &MI, BuildFnTy &MatchInfo) const
Transform (fadd x, fneg(y)) -> (fsub x, y) (fadd fneg(x), y) -> (fsub y, x) (fsub x,...
bool matchCombineLoadWithAndMask(MachineInstr &MI, BuildFnTy &MatchInfo) const
Match (and (load x), mask) -> zextload x.
bool matchCombineFAddFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo) const
Transform (fadd (fmul x, y), z) -> (fma x, y, z) (fadd (fmul x, y), z) -> (fmad x,...
bool matchCombineCopy(MachineInstr &MI) const
bool matchExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI) const
void applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo) const
bool matchXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo) const
Fold (xor (and x, y), y) -> (and (not x), y) {.
bool matchCombineShuffleVector(MachineInstr &MI, SmallVectorImpl< Register > &Ops) const
Check if the G_SHUFFLE_VECTOR MI can be replaced by a concat_vectors.
void applyCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst) const
bool matchTruncateOfExt(const MachineInstr &Root, const MachineInstr &ExtMI, BuildFnTy &MatchInfo) const
Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
bool matchCombineAddP2IToPtrAdd(MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute) const
Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y) Transform G_ADD y,...
bool matchShiftsTooBig(MachineInstr &MI) const
Match shifts greater or equal to the bitwidth of the operation.
void replaceInstWithFConstant(MachineInstr &MI, double C) const
Replace an instruction with a G_FCONSTANT with value C.
bool matchMergeXAndUndef(const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool matchFunnelShiftToRotate(MachineInstr &MI) const
Match an FSHL or FSHR that can be combined to a ROTR or ROTL rotate.
bool matchRedundantSExtInReg(MachineInstr &MI) const
void replaceOpcodeWith(MachineInstr &FromMI, unsigned ToOpcode) const
Replace the opcode in instruction with a new opcode and inform the observer of the changes.
void applyFunnelShiftConstantModulo(MachineInstr &MI) const
Replaces the shift amount in MI with ShiftAmt % BW.
bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx) const
Check if operand OpIdx is zero.
bool matchFoldC1Minus2MinusC2(const MachineInstr &MI, BuildFnTy &MatchInfo) const
void applyCombineShlOfExtend(MachineInstr &MI, const RegisterImmPair &MatchData) const
void applyUseVectorTruncate(MachineInstr &MI, Register &MatchInfo) const
bool matchShuffleDisjointMask(MachineInstr &MI, BuildFnTy &MatchInfo) const
Turn shuffle a, b, mask -> shuffle undef, b, mask iff mask does not reference a.
bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal) const
Transform a multiply by a power-of-2 value to a left shift.
bool matchCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst) const
bool matchCombineUnmergeUndef(MachineInstr &MI, std::function< void(MachineIRBuilder &)> &MatchInfo) const
Transform G_UNMERGE G_IMPLICIT_DEF -> G_IMPLICIT_DEF, G_IMPLICIT_DEF, ...
void applyFoldBinOpIntoSelect(MachineInstr &MI, const unsigned &SelectOpNo) const
SelectOperand is the operand in binary operator MI that is the select to fold.
bool matchFoldAMinusC1MinusC2(const MachineInstr &MI, BuildFnTy &MatchInfo) const
void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo) const
bool matchMulOBy2(MachineInstr &MI, BuildFnTy &MatchInfo) const
Match: (G_UMULO x, 2) -> (G_UADDO x, x) (G_SMULO x, 2) -> (G_SADDO x, x)
GISelKnownBits * KB
bool matchCombineShuffleConcat(MachineInstr &MI, SmallVector< Register > &Ops) const
void applySextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo) const
bool tryCombineCopy(MachineInstr &MI) const
If MI is COPY, try to combine it.
bool matchICmpToLHSKnownBits(MachineInstr &MI, BuildFnTy &MatchInfo) const
bool matchExtOfExt(const MachineInstr &FirstMI, const MachineInstr &SecondMI, BuildFnTy &MatchInfo) const
bool matchReassocPtrAdd(MachineInstr &MI, BuildFnTy &MatchInfo) const
Reassociate pointer calculations with G_ADD involved, to allow better addressing mode usage.
bool matchCanonicalizeFCmp(const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool isPreLegalize() const
void applyCombineShuffleVector(MachineInstr &MI, const ArrayRef< Register > Ops) const
Replace MI with a concat_vectors with Ops.
bool matchUndefShuffleVectorMask(MachineInstr &MI) const
Return true if a G_SHUFFLE_VECTOR instruction MI has an undef mask.
bool matchAnyExplicitUseIsUndef(MachineInstr &MI) const
Return true if any explicit use operand on MI is defined by a G_IMPLICIT_DEF.
bool matchCombineI2PToP2I(MachineInstr &MI, Register &Reg) const
Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
bool matchCombineSubToAdd(MachineInstr &MI, BuildFnTy &MatchInfo) const
bool matchShiftOfShiftedLogic(MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo) const
If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with...
bool matchOperandIsKnownToBeAPowerOfTwo(MachineInstr &MI, unsigned OpIdx) const
Check if operand OpIdx is known to be a power of 2.
bool matchCombineConcatVectors(MachineInstr &MI, SmallVector< Register > &Ops) const
If MI is G_CONCAT_VECTORS, try to combine it.
bool matchInsertExtractVecEltOutOfBounds(MachineInstr &MI) const
Return true if a G_{EXTRACT,INSERT}_VECTOR_ELT has an out of range index.
bool matchExtractVectorElementWithShuffleVector(const MachineInstr &MI, const MachineInstr &MI2, BuildFnTy &MatchInfo) const
Combine extract vector element with a shuffle vector on the vector register.
bool matchExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * > > &MatchInfo) const
LLVMContext & getContext() const
void applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo) const
bool isConstantLegalOrBeforeLegalizer(const LLT Ty) const
bool matchNotCmp(MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate) const
Combine inverting a result of a compare into the opposite cond code.
bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo) const
Match sext_inreg(load p), imm -> sextload p.
bool matchSelectIMinMax(const MachineOperand &MO, BuildFnTy &MatchInfo) const
Combine select to integer min/max.
void applyCombineConstantFoldFpUnary(MachineInstr &MI, const ConstantFP *Cst) const
Transform fp_instr(cst) to constant result of the fp operation.
bool isLegal(const LegalityQuery &Query) const
bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo) const
bool tryReassocBinOp(unsigned Opc, Register DstReg, Register Op0, Register Op1, BuildFnTy &MatchInfo) const
Try to reassociate to reassociate operands of a commutative binop.
void eraseInst(MachineInstr &MI) const
Erase MI.
bool matchConstantFoldFPBinOp(MachineInstr &MI, ConstantFP *&MatchInfo) const
Do constant FP folding when opportunities are exposed after MIR building.
void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo) const
Use a function which takes in a MachineIRBuilder to perform a combine.
bool matchUseVectorTruncate(MachineInstr &MI, Register &MatchInfo) const
bool matchUndefStore(MachineInstr &MI) const
Return true if a G_STORE instruction MI is storing an undef value.
MachineRegisterInfo & MRI
void applyCombineP2IToI2P(MachineInstr &MI, Register &Reg) const
Transform PtrToInt(IntToPtr(x)) to x.
void applyExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI) const
bool matchConstantFPOp(const MachineOperand &MOP, double C) const
Return true if MOP is defined by a G_FCONSTANT or splat with a value exactly equal to C.
void applyExtractVecEltBuildVec(MachineInstr &MI, Register &Reg) const
bool matchFoldBinOpIntoSelect(MachineInstr &MI, unsigned &SelectOpNo) const
Push a binary operator through a select on constants.
bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount) const
bool tryCombineExtendingLoads(MachineInstr &MI) const
If MI is extend that consumes the result of a load, try to combine it.
bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const
bool matchBuildVectorIdentityFold(MachineInstr &MI, Register &MatchInfo) const
bool matchBitfieldExtractFromShrAnd(MachineInstr &MI, BuildFnTy &MatchInfo) const
Match: shr (and x, n), k -> ubfx x, pos, width.
bool matchConstantFoldCastOp(MachineInstr &MI, APInt &MatchInfo) const
Do constant folding when opportunities are exposed after MIR building.
bool tryCombineShuffleVector(MachineInstr &MI) const
Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
void applyRotateOutOfRange(MachineInstr &MI) const
bool matchReassocFoldConstantsInSubTree(GPtrAdd &MI, MachineInstr *LHS, MachineInstr *RHS, BuildFnTy &MatchInfo) const
bool matchHoistLogicOpWithSameOpcodeHands(MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo) const
Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
bool matchBitfieldExtractFromAnd(MachineInstr &MI, BuildFnTy &MatchInfo) const
Match: and (lshr x, cst), mask -> ubfx x, cst, width.
bool matchBitfieldExtractFromSExtInReg(MachineInstr &MI, BuildFnTy &MatchInfo) const
Form a G_SBFX from a G_SEXT_INREG fed by a right shift.
bool matchNarrowBinop(const MachineInstr &TruncMI, const MachineInstr &BinopMI, BuildFnTy &MatchInfo) const
trunc (binop X, C) --> binop (trunc X, trunc C).
bool matchUndefSelectCmp(MachineInstr &MI) const
Return true if a G_SELECT instruction MI has an undef comparison.
bool matchAndOrDisjointMask(MachineInstr &MI, BuildFnTy &MatchInfo) const
void replaceInstWithUndef(MachineInstr &MI) const
Replace an instruction with a G_IMPLICIT_DEF.
bool matchRedundantBinOpInEquality(MachineInstr &MI, BuildFnTy &MatchInfo) const
Transform: (X + Y) == X -> Y == 0 (X - Y) == X -> Y == 0 (X ^ Y) == X -> Y == 0 (X + Y) !...
bool matchOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond) const
If a brcond's true block is not the fallthrough, make it so by inverting the condition and swapping o...
bool matchAddOverflow(MachineInstr &MI, BuildFnTy &MatchInfo) const
Combine addos.
void applyAshShlToSextInreg(MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo) const
bool matchSelect(MachineInstr &MI, BuildFnTy &MatchInfo) const
Combine selects.
bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo) const
bool matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI) const
Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
bool matchFsubToFneg(MachineInstr &MI, Register &MatchInfo) const
bool matchRotateOutOfRange(MachineInstr &MI) const
void applyExpandFPowI(MachineInstr &MI, int64_t Exponent) const
Expands FPOWI into a series of multiplications and a division if the exponent is negative.
void setRegBank(Register Reg, const RegisterBank *RegBank) const
Set the register bank of Reg.
bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx) const
Return true if a G_SELECT instruction MI has a constant comparison.
bool matchCommuteFPConstantToRHS(MachineInstr &MI) const
Match constant LHS FP ops that should be commuted.
void applyCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI) const
bool matchCombineFMinMaxNaN(MachineInstr &MI, unsigned &Info) const
bool matchRedundantOr(MachineInstr &MI, Register &Replacement) const
bool matchCombineFSubFpExtFNegFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo) const
Transform (fsub (fpext (fneg (fmul x, y))), z) -> (fneg (fma (fpext x), (fpext y),...
bool matchTruncBuildVectorFold(MachineInstr &MI, Register &MatchInfo) const
bool matchSubOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo) const
void applyCombineTruncOfShift(MachineInstr &MI, std::pair< MachineInstr *, LLT > &MatchInfo) const
bool matchConstantOp(const MachineOperand &MOP, int64_t C) const
Return true if MOP is defined by a G_CONSTANT or splat with a value equal to C.
const LegalizerInfo * LI
void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal) const
bool matchUMulHToLShr(MachineInstr &MI) const
MachineDominatorTree * MDT
MachineIRBuilder & getBuilder() const
void applyFunnelShiftToRotate(MachineInstr &MI) const
bool matchSimplifySelectToMinMax(MachineInstr &MI, BuildFnTy &MatchInfo) const
const RegisterBankInfo * RBI
bool matchMulOBy0(MachineInstr &MI, BuildFnTy &MatchInfo) const
Match: (G_*MULO x, 0) -> 0 + no carry out.
bool matchCombineUnmergeConstant(MachineInstr &MI, SmallVectorImpl< APInt > &Csts) const
Transform G_UNMERGE Constant -> Constant1, Constant2, ...
void applyUDivByConst(MachineInstr &MI) const
void applyShiftOfShiftedLogic(MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo) const
const TargetRegisterInfo * TRI
bool matchRedundantAnd(MachineInstr &MI, Register &Replacement) const
bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI) const
Returns true if DefMI dominates UseMI.
GISelChangeObserver & Observer
void applyBuildFn(MachineInstr &MI, BuildFnTy &MatchInfo) const
Use a function which takes in a MachineIRBuilder to perform a combine.
bool matchCombineTruncOfShift(MachineInstr &MI, std::pair< MachineInstr *, LLT > &MatchInfo) const
Transform trunc (shl x, K) to shl (trunc x), K if K < VT.getScalarSizeInBits().
bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize, unsigned &ShiftVal) const
Reduce a shift by a constant to an unmerge and a shift on a half sized type.
bool matchAnd(MachineInstr &MI, BuildFnTy &MatchInfo) const
Combine ands.
bool matchSuboCarryOut(const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool matchConstantFoldFMA(MachineInstr &MI, ConstantFP *&MatchInfo) const
Constant fold G_FMA/G_FMAD.
bool matchCombineFSubFNegFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo) const
Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) (fsub (fneg (fmul,...
bool matchCombineZextTrunc(MachineInstr &MI, Register &Reg) const
Transform zext(trunc(x)) to x.
bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx) const
Check if operand OpIdx is undef.
bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen=0) const
Optimize memcpy intrinsics et al, e.g.
bool matchFreezeOfSingleMaybePoisonOperand(MachineInstr &MI, BuildFnTy &MatchInfo) const
void applyShuffleToExtract(MachineInstr &MI) const
bool matchCanonicalizeICmp(const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool matchCastOfBuildVector(const MachineInstr &CastMI, const MachineInstr &BVMI, BuildFnTy &MatchInfo) const
bool matchSubAddSameReg(MachineInstr &MI, BuildFnTy &MatchInfo) const
Transform: (x + y) - y -> x (x + y) - x -> y x - (y + x) -> 0 - y x - (x + z) -> 0 - z.
bool matchReassocConstantInnerLHS(GPtrAdd &MI, MachineInstr *LHS, MachineInstr *RHS, BuildFnTy &MatchInfo) const
bool matchCastOfInteger(const MachineInstr &CastMI, APInt &MatchInfo) const
bool matchOverlappingAnd(MachineInstr &MI, BuildFnTy &MatchInfo) const
Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0.
bool matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg) const
Transform anyext(trunc(x)) to x.
void applyExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * > > &MatchInfo) const
MachineIRBuilder & Builder
void applyCommuteBinOpOperands(MachineInstr &MI) const
void replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx) const
Delete MI and replace all of its uses with its OpIdx-th operand.
void applySextTruncSextLoad(MachineInstr &MI) const
MachineInstr * buildUDivUsingMul(MachineInstr &MI) const
Given an G_UDIV MI expressing a divide by constant, return an expression that implements it by multip...
const MachineFunction & getMachineFunction() const
MachineInstr * buildSDivUsingMul(MachineInstr &MI) const
Given an G_SDIV MI expressing a signed divide by constant, return an expression that implements it by...
bool matchCombineFAddFpExtFMulToFMadOrFMAAggressive(MachineInstr &MI, BuildFnTy &MatchInfo) const
bool matchExtractVectorElementWithBuildVector(const MachineInstr &MI, const MachineInstr &MI2, BuildFnTy &MatchInfo) const
Combine extract vector element with a build vector on the vector register.
void applyOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond) const
void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal) const
bool matchCastOfSelect(const MachineInstr &Cast, const MachineInstr &SelectMI, BuildFnTy &MatchInfo) const
bool matchFPowIExpansion(MachineInstr &MI, int64_t Exponent) const
Match FPOWI if it's safe to extend it into a series of multiplications.
void applyCombineInsertVecElts(MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo) const
bool matchCombineUnmergeMergeToPlainValues(MachineInstr &MI, SmallVectorImpl< Register > &Operands) const
Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
void applyCombineUnmergeMergeToPlainValues(MachineInstr &MI, SmallVectorImpl< Register > &Operands) const
bool matchAshrShlToSextInreg(MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo) const
Match ashr (shl x, C), C -> sext_inreg (C)
void applyCombineUnmergeZExtToZExt(MachineInstr &MI) const
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:271
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:63
Represent a G_FCMP.
An floating-point-like constant.
Definition: Utils.h:645
Represent a G_ICMP.
An integer-like constant.
Definition: Utils.h:606
Abstract class that contains various methods for clients to notify about changes.
Represents any type of generic load or store.
Represents a logical binary operation.
Represents a G_PTR_ADD.
Represents a G_SELECT.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Helper class to build MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Holds all the information related to register banks.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:573
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ ConstantFP
Definition: ISDOpcodes.h:77
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
std::function< void(MachineIRBuilder &)> BuildFnTy
InstructionBuildSteps(unsigned Opcode, const OperandBuildSteps &OperandFns)
InstructionBuildSteps()=default
Operands to be added to the instruction.
OperandBuildSteps OperandFns
The opcode for the produced instruction.
InstructionStepsMatchInfo(std::initializer_list< InstructionBuildSteps > InstrsToBuild)
SmallVector< InstructionBuildSteps, 2 > InstrsToBuild
Describes instructions to be built during a combine.
The LegalityQuery object bundles together all the information that's needed to decide whether a given...
MachineInstr * MI
const RegisterBank * Bank