LLVM  14.0.0git
CombinerHelper.h
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1 //===-- llvm/CodeGen/GlobalISel/CombinerHelper.h --------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===--------------------------------------------------------------------===//
8 /// \file
9 /// This contains common combine transformations that may be used in a combine
10 /// pass,or by the target elsewhere.
11 /// Targets can pick individual opcode transformations from the helper or use
12 /// tryCombine which invokes all transformations. All of the transformations
13 /// return true if the MachineInstruction changed and false otherwise.
14 ///
15 //===--------------------------------------------------------------------===//
16 
17 #ifndef LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
18 #define LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
19 
20 #include "llvm/ADT/APFloat.h"
21 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/CodeGen/Register.h"
25 #include "llvm/Support/Alignment.h"
26 
27 namespace llvm {
28 
29 class GISelChangeObserver;
30 class MachineIRBuilder;
31 class MachineInstrBuilder;
32 class MachineRegisterInfo;
33 class MachineInstr;
34 class MachineOperand;
35 class GISelKnownBits;
36 class MachineDominatorTree;
37 class LegalizerInfo;
38 struct LegalityQuery;
39 class RegisterBank;
40 class RegisterBankInfo;
41 class TargetLowering;
42 class TargetRegisterInfo;
43 
45  LLT Ty; // The result type of the extend.
46  unsigned ExtendOpcode; // G_ANYEXT/G_SEXT/G_ZEXT
48 };
49 
54  bool IsPre;
55 };
56 
57 struct PtrAddChain {
58  int64_t Imm;
61 };
62 
65  int64_t Imm;
66 };
67 
73 };
74 
76 
79  GStore *LowestIdxStore = nullptr;
81  bool NeedBSwap = false;
82  bool NeedRotate = false;
83 };
84 
85 using OperandBuildSteps =
88  unsigned Opcode = 0; /// The opcode for the produced instruction.
89  OperandBuildSteps OperandFns; /// Operands to be added to the instruction.
90  InstructionBuildSteps() = default;
93 };
94 
96  /// Describes instructions to be built during a combine.
98  InstructionStepsMatchInfo() = default;
100  std::initializer_list<InstructionBuildSteps> InstrsToBuild)
102 };
103 
105 protected:
114 
115 public:
117  GISelKnownBits *KB = nullptr,
118  MachineDominatorTree *MDT = nullptr,
119  const LegalizerInfo *LI = nullptr);
120 
122  return KB;
123  }
124 
125  const TargetLowering &getTargetLowering() const;
126 
127  /// \return true if the combine is running prior to legalization, or if \p
128  /// Query is legal on the target.
129  bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const;
130 
131  /// MachineRegisterInfo::replaceRegWith() and inform the observer of the changes
132  void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const;
133 
134  /// Replace a single register operand with a new register and inform the
135  /// observer of the changes.
137  Register ToReg) const;
138 
139  /// Get the register bank of \p Reg.
140  /// If Reg has not been assigned a register, a register class,
141  /// or a register bank, then this returns nullptr.
142  ///
143  /// \pre Reg.isValid()
144  const RegisterBank *getRegBank(Register Reg) const;
145 
146  /// Set the register bank of \p Reg.
147  /// Does nothing if the RegBank is null.
148  /// This is the counterpart to getRegBank.
149  void setRegBank(Register Reg, const RegisterBank *RegBank);
150 
151  /// If \p MI is COPY, try to combine it.
152  /// Returns true if MI changed.
156 
157  /// Returns true if \p DefMI precedes \p UseMI or they are the same
158  /// instruction. Both must be in the same basic block.
159  bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI);
160 
161  /// Returns true if \p DefMI dominates \p UseMI. By definition an
162  /// instruction dominates itself.
163  ///
164  /// If we haven't been provided with a MachineDominatorTree during
165  /// construction, this function returns a conservative result that tracks just
166  /// a single basic block.
167  bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI);
168 
169  /// If \p MI is extend that consumes the result of a load, try to combine it.
170  /// Returns true if MI changed.
174 
175  /// Match (and (load x), mask) -> zextload x
177 
178  /// Combine \p MI into a pre-indexed or post-indexed load/store operation if
179  /// legal and the surrounding code makes it useful.
183 
186 
187  /// Match sext_inreg(load p), imm -> sextload p
188  bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
189  void applySextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
190 
191  /// Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM
192  /// when their source operands are identical.
195 
196  /// If a brcond's true block is not the fallthrough, make it so by inverting
197  /// the condition and swapping operands.
200 
201  /// If \p MI is G_CONCAT_VECTORS, try to combine it.
202  /// Returns true if MI changed.
203  /// Right now, we support:
204  /// - concat_vector(undef, undef) => undef
205  /// - concat_vector(build_vector(A, B), build_vector(C, D)) =>
206  /// build_vector(A, B, C, D)
207  ///
208  /// \pre MI.getOpcode() == G_CONCAT_VECTORS.
210  /// Check if the G_CONCAT_VECTORS \p MI is undef or if it
211  /// can be flattened into a build_vector.
212  /// In the first case \p IsUndef will be true.
213  /// In the second case \p Ops will contain the operands needed
214  /// to produce the flattened build_vector.
215  ///
216  /// \pre MI.getOpcode() == G_CONCAT_VECTORS.
217  bool matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef,
219  /// Replace \p MI with a flattened build_vector with \p Ops or an
220  /// implicit_def if IsUndef is true.
221  void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef,
222  const ArrayRef<Register> Ops);
223 
224  /// Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
225  /// Returns true if MI changed.
226  ///
227  /// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
229  /// Check if the G_SHUFFLE_VECTOR \p MI can be replaced by a
230  /// concat_vectors.
231  /// \p Ops will contain the operands needed to produce the flattened
232  /// concat_vectors.
233  ///
234  /// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
237  /// Replace \p MI with a concat_vectors with \p Ops.
239  const ArrayRef<Register> Ops);
240 
241  /// Optimize memcpy intrinsics et al, e.g. constant len calls.
242  /// /p MaxLen if non-zero specifies the max length of a mem libcall to inline.
243  ///
244  /// For example (pre-indexed):
245  ///
246  /// $addr = G_PTR_ADD $base, $offset
247  /// [...]
248  /// $val = G_LOAD $addr
249  /// [...]
250  /// $whatever = COPY $addr
251  ///
252  /// -->
253  ///
254  /// $val, $addr = G_INDEXED_LOAD $base, $offset, 1 (IsPre)
255  /// [...]
256  /// $whatever = COPY $addr
257  ///
258  /// or (post-indexed):
259  ///
260  /// G_STORE $val, $base
261  /// [...]
262  /// $addr = G_PTR_ADD $base, $offset
263  /// [...]
264  /// $whatever = COPY $addr
265  ///
266  /// -->
267  ///
268  /// $addr = G_INDEXED_STORE $val, $base, $offset
269  /// [...]
270  /// $whatever = COPY $addr
271  bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
272 
275 
276  /// Fold (shift (shift base, x), y) -> (shift base (x+y))
279 
280  /// If we have a shift-by-constant of a bitwise logic op that itself has a
281  /// shift-by-constant operand with identical opcode, we may be able to convert
282  /// that into 2 independent shifts followed by the logic op.
284  ShiftOfShiftedLogic &MatchInfo);
286  ShiftOfShiftedLogic &MatchInfo);
287 
288  /// Transform a multiply by a power-of-2 value to a left shift.
289  bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
290  void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
291 
292  // Transform a G_SHL with an extended source into a narrower shift if
293  // possible.
296  const RegisterImmPair &MatchData);
297 
298  /// Fold away a merge of an unmerge of the corresponding values.
300 
301  /// Reduce a shift by a constant to an unmerge and a shift on a half sized
302  /// type. This will not produce a shift smaller than \p TargetShiftSize.
303  bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize,
304  unsigned &ShiftVal);
305  void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal);
306  bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount);
307 
308  /// Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
309  bool
312  void
315 
316  /// Transform G_UNMERGE Constant -> Constant1, Constant2, ...
318  SmallVectorImpl<APInt> &Csts);
320  SmallVectorImpl<APInt> &Csts);
321 
322  /// Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
325 
326  /// Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0
329 
330  /// Transform fp_instr(cst) to constant result of the fp operation.
332  Optional<APFloat> &Cst);
334  Optional<APFloat> &Cst);
335 
336  /// Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
339 
340  /// Transform PtrToInt(IntToPtr(x)) to x.
343 
344  /// Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y)
345  /// Transform G_ADD y, (G_PTRTOINT x) -> G_PTRTOINT (G_PTR_ADD x, y)
347  std::pair<Register, bool> &PtrRegAndCommute);
349  std::pair<Register, bool> &PtrRegAndCommute);
350 
351  // Transform G_PTR_ADD (G_PTRTOINT C1), C2 -> C1 + C2
352  bool matchCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst);
353  void applyCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst);
354 
355  /// Transform anyext(trunc(x)) to x.
358 
359  /// Transform zext(trunc(x)) to x.
361 
362  /// Transform [asz]ext([asz]ext(x)) to [asz]ext x.
364  std::tuple<Register, unsigned> &MatchInfo);
366  std::tuple<Register, unsigned> &MatchInfo);
367 
368  /// Transform fneg(fneg(x)) to x.
370 
371  /// Match fabs(fabs(x)) to fabs(x).
374 
375  /// Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
377  std::pair<Register, unsigned> &MatchInfo);
379  std::pair<Register, unsigned> &MatchInfo);
380 
381  /// Transform trunc (shl x, K) to shl (trunc x),
382  /// K => K < VT.getScalarSizeInBits().
384  std::pair<Register, Register> &MatchInfo);
386  std::pair<Register, Register> &MatchInfo);
387 
388  /// Transform G_MUL(x, -1) to G_SUB(0, x)
390 
391  /// Return true if any explicit use operand on \p MI is defined by a
392  /// G_IMPLICIT_DEF.
394 
395  /// Return true if all register explicit use operands on \p MI are defined by
396  /// a G_IMPLICIT_DEF.
398 
399  /// Return true if a G_SHUFFLE_VECTOR instruction \p MI has an undef mask.
401 
402  /// Return true if a G_STORE instruction \p MI is storing an undef value.
404 
405  /// Return true if a G_SELECT instruction \p MI has an undef comparison.
407 
408  /// Return true if a G_SELECT instruction \p MI has a constant comparison. If
409  /// true, \p OpIdx will store the operand index of the known selected value.
410  bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx);
411 
412  /// Replace an instruction with a G_FCONSTANT with value \p C.
413  bool replaceInstWithFConstant(MachineInstr &MI, double C);
414 
415  /// Replace an instruction with a G_CONSTANT with value \p C.
416  bool replaceInstWithConstant(MachineInstr &MI, int64_t C);
417 
418  /// Replace an instruction with a G_CONSTANT with value \p C.
420 
421  /// Replace an instruction with a G_IMPLICIT_DEF.
423 
424  /// Delete \p MI and replace all of its uses with its \p OpIdx-th operand.
425  bool replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx);
426 
427  /// Delete \p MI and replace all of its uses with \p Replacement.
429 
430  /// Return true if \p MOP1 and \p MOP2 are register operands are defined by
431  /// equivalent instructions.
432  bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2);
433 
434  /// Return true if \p MOP is defined by a G_CONSTANT with a value equal to
435  /// \p C.
436  bool matchConstantOp(const MachineOperand &MOP, int64_t C);
437 
438  /// Optimize (cond ? x : x) -> x
440 
441  /// Optimize (x op x) -> x
443 
444  /// Check if operand \p OpIdx is zero.
445  bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx);
446 
447  /// Check if operand \p OpIdx is undef.
448  bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx);
449 
450  /// Check if operand \p OpIdx is known to be a power of 2.
451  bool matchOperandIsKnownToBeAPowerOfTwo(MachineInstr &MI, unsigned OpIdx);
452 
453  /// Erase \p MI
454  bool eraseInst(MachineInstr &MI);
455 
456  /// Return true if MI is a G_ADD which can be simplified to a G_SUB.
458  std::tuple<Register, Register> &MatchInfo);
460  std::tuple<Register, Register> &MatchInfo);
461 
462  /// Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
463  bool
465  InstructionStepsMatchInfo &MatchInfo);
466 
467  /// Replace \p MI with a series of instructions described in \p MatchInfo.
469  InstructionStepsMatchInfo &MatchInfo);
470 
471  /// Match ashr (shl x, C), C -> sext_inreg (C)
473  std::tuple<Register, int64_t> &MatchInfo);
475  std::tuple<Register, int64_t> &MatchInfo);
476 
477  /// Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0
479  BuildFnTy &MatchInfo);
480 
481  /// \return true if \p MI is a G_AND instruction whose operands are x and y
482  /// where x & y == x or x & y == y. (E.g., one of operands is all-ones value.)
483  ///
484  /// \param [in] MI - The G_AND instruction.
485  /// \param [out] Replacement - A register the G_AND should be replaced with on
486  /// success.
487  bool matchRedundantAnd(MachineInstr &MI, Register &Replacement);
488 
489  /// \return true if \p MI is a G_OR instruction whose operands are x and y
490  /// where x | y == x or x | y == y. (E.g., one of operands is all-zeros
491  /// value.)
492  ///
493  /// \param [in] MI - The G_OR instruction.
494  /// \param [out] Replacement - A register the G_OR should be replaced with on
495  /// success.
496  bool matchRedundantOr(MachineInstr &MI, Register &Replacement);
497 
498  /// \return true if \p MI is a G_SEXT_INREG that can be erased.
500 
501  /// Combine inverting a result of a compare into the opposite cond code.
504 
505  /// Fold (xor (and x, y), y) -> (and (not x), y)
506  ///{
508  std::pair<Register, Register> &MatchInfo);
510  std::pair<Register, Register> &MatchInfo);
511  ///}
512 
513  /// Combine G_PTR_ADD with nullptr to G_INTTOPTR
516 
517  /// Combine G_UREM x, (known power of 2) to an add and bitmasking.
519 
521  SmallVectorImpl<Register> &MatchInfo);
522 
524  SmallVectorImpl<Register> &MatchInfo);
525 
526  /// Match expression trees of the form
527  ///
528  /// \code
529  /// sN *a = ...
530  /// sM val = a[0] | (a[1] << N) | (a[2] << 2N) | (a[3] << 3N) ...
531  /// \endcode
532  ///
533  /// And check if the tree can be replaced with a M-bit load + possibly a
534  /// bswap.
535  bool matchLoadOrCombine(MachineInstr &MI, BuildFnTy &MatchInfo);
536 
539 
542 
545 
547  MachineInstr &MI,
548  SmallVectorImpl<std::pair<Register, MachineInstr *>> &MatchInfo);
550  MachineInstr &MI,
551  SmallVectorImpl<std::pair<Register, MachineInstr *>> &MatchInfo);
552 
553  /// Use a function which takes in a MachineIRBuilder to perform a combine.
554  /// By default, it erases the instruction \p MI from the function.
555  void applyBuildFn(MachineInstr &MI, BuildFnTy &MatchInfo);
556  /// Use a function which takes in a MachineIRBuilder to perform a combine.
557  /// This variant does not erase \p MI after calling the build function.
558  void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo);
559 
564 
565  /// \returns true if a G_ICMP instruction \p MI can be replaced with a true
566  /// or false constant based off of KnownBits information.
567  bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo);
568 
569  /// \returns true if a G_ICMP \p MI can be replaced with its LHS based off of
570  /// KnownBits information.
571  bool
573  BuildFnTy &MatchInfo);
574 
576  BuildFnTy &MatchInfo);
577  /// Match: and (lshr x, cst), mask -> ubfx x, cst, width
579 
580  /// Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width
582 
583  // Helpers for reassociation:
585  BuildFnTy &MatchInfo);
587  MachineInstr *RHS,
588  BuildFnTy &MatchInfo);
590  MachineInstr *RHS, BuildFnTy &MatchInfo);
591  /// Reassociate pointer calculations with G_ADD involved, to allow better
592  /// addressing mode usage.
593  bool matchReassocPtrAdd(MachineInstr &MI, BuildFnTy &MatchInfo);
594 
595  /// Do constant folding when opportunities are exposed after MIR building.
596  bool matchConstantFold(MachineInstr &MI, APInt &MatchInfo);
597 
598  /// \returns true if it is possible to narrow the width of a scalar binop
599  /// feeding a G_AND instruction \p MI.
601 
602  /// Try to transform \p MI by using all of the above
603  /// combine functions. Returns true if changed.
604  bool tryCombine(MachineInstr &MI);
605 
606  /// Emit loads and stores that perform the given memcpy.
607  /// Assumes \p MI is a G_MEMCPY_INLINE
608  /// TODO: implement dynamically sized inline memcpy,
609  /// and rename: s/bool tryEmit/void emit/
611 
612 private:
613  /// Given a non-indexed load or store instruction \p MI, find an offset that
614  /// can be usefully and legally folded into it as a post-indexing operation.
615  ///
616  /// \returns true if a candidate is found.
617  bool findPostIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
618  Register &Offset);
619 
620  /// Given a non-indexed load or store instruction \p MI, find an offset that
621  /// can be usefully and legally folded into it as a pre-indexing operation.
622  ///
623  /// \returns true if a candidate is found.
624  bool findPreIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
625  Register &Offset);
626 
627  /// Helper function for matchLoadOrCombine. Searches for Registers
628  /// which may have been produced by a load instruction + some arithmetic.
629  ///
630  /// \param [in] Root - The search root.
631  ///
632  /// \returns The Registers found during the search.
634  findCandidatesForLoadOrCombine(const MachineInstr *Root) const;
635 
636  /// Helper function for matchLoadOrCombine.
637  ///
638  /// Checks if every register in \p RegsToVisit is defined by a load
639  /// instruction + some arithmetic.
640  ///
641  /// \param [out] MemOffset2Idx - Maps the byte positions each load ends up
642  /// at to the index of the load.
643  /// \param [in] MemSizeInBits - The number of bits each load should produce.
644  ///
645  /// \returns On success, a 3-tuple containing lowest-index load found, the
646  /// lowest index, and the last load in the sequence.
648  findLoadOffsetsForLoadOrCombine(
649  SmallDenseMap<int64_t, int64_t, 8> &MemOffset2Idx,
650  const SmallVector<Register, 8> &RegsToVisit,
651  const unsigned MemSizeInBits);
652 
653  /// Examines the G_PTR_ADD instruction \p PtrAdd and determines if performing
654  /// a re-association of its operands would break an existing legal addressing
655  /// mode that the address computation currently represents.
656  bool reassociationCanBreakAddressingModePattern(MachineInstr &PtrAdd);
657 };
658 } // namespace llvm
659 
660 #endif
llvm::CombinerHelper::matchCombineConstPtrAddToI2P
bool matchCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst)
Definition: CombinerHelper.cpp:2006
llvm::CombinerHelper::matchCombineUnmergeWithDeadLanesToTrunc
bool matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI)
Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
Definition: CombinerHelper.cpp:1730
llvm::IndexedLoadStoreMatchInfo::Addr
Register Addr
Definition: CombinerHelper.h:51
llvm::CombinerHelper::matchConstantFold
bool matchConstantFold(MachineInstr &MI, APInt &MatchInfo)
Do constant folding when opportunities are exposed after MIR building.
Definition: CombinerHelper.cpp:4278
llvm::CombinerHelper::applyCombineShiftToUnmerge
void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal)
Definition: CombinerHelper.cpp:1847
LowLevelType.h
llvm::InstructionBuildSteps::Opcode
unsigned Opcode
Definition: CombinerHelper.h:88
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::CombinerHelper::applyExtractVecEltBuildVec
void applyExtractVecEltBuildVec(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:3744
llvm::RegisterImmPair
Definition: CombinerHelper.h:63
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::MergeTruncStoresInfo::WideSrcVal
Register WideSrcVal
Definition: CombinerHelper.h:80
llvm::CombinerHelper::matchCombineUnmergeConstant
bool matchCombineUnmergeConstant(MachineInstr &MI, SmallVectorImpl< APInt > &Csts)
Transform G_UNMERGE Constant -> Constant1, Constant2, ...
Definition: CombinerHelper.cpp:1689
llvm::CombinerHelper::MRI
MachineRegisterInfo & MRI
Definition: CombinerHelper.h:107
llvm::CombinerHelper::applyOptBrCondByInvertingCond
void applyOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond)
Definition: CombinerHelper.cpp:1161
llvm::CombinerHelper::matchHoistLogicOpWithSameOpcodeHands
bool matchHoistLogicOpWithSameOpcodeHands(MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo)
Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
Definition: CombinerHelper.cpp:2522
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::ShiftOfShiftedLogic::Shift2
MachineInstr * Shift2
Definition: CombinerHelper.h:70
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::CombinerHelper::applyCombineI2PToP2I
void applyCombineI2PToP2I(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:1940
llvm::CombinerHelper::eraseInst
bool eraseInst(MachineInstr &MI)
Erase MI.
Definition: CombinerHelper.cpp:2251
llvm::IndexedLoadStoreMatchInfo::Base
Register Base
Definition: CombinerHelper.h:52
llvm::CombinerHelper::getKnownBits
GISelKnownBits * getKnownBits() const
Definition: CombinerHelper.h:121
llvm::CombinerHelper::matchCombineP2IToI2P
bool matchCombineP2IToI2P(MachineInstr &MI, Register &Reg)
Transform PtrToInt(IntToPtr(x)) to x.
Definition: CombinerHelper.cpp:1948
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::CombinerHelper::getTargetLowering
const TargetLowering & getTargetLowering() const
Definition: CombinerHelper.cpp:58
llvm::InstructionBuildSteps::InstructionBuildSteps
InstructionBuildSteps(unsigned Opcode, const OperandBuildSteps &OperandFns)
Definition: CombinerHelper.h:91
llvm::CombinerHelper::tryCombineMemCpyFamily
bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen=0)
Optimize memcpy intrinsics et al, e.g.
Definition: CombinerHelper.cpp:1201
llvm::CombinerHelper::dominates
bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI)
Returns true if DefMI dominates UseMI.
Definition: CombinerHelper.cpp:722
llvm::MergeTruncStoresInfo
Definition: CombinerHelper.h:77
llvm::SmallDenseMap
Definition: DenseMap.h:880
llvm::CombinerHelper::matchConstantSelectCmp
bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx)
Return true if a G_SELECT instruction MI has a constant comparison.
Definition: CombinerHelper.cpp:2241
llvm::CombinerHelper::applyFunnelShiftToRotate
void applyFunnelShiftToRotate(MachineInstr &MI)
Definition: CombinerHelper.cpp:3843
llvm::CombinerHelper::applyBuildFn
void applyBuildFn(MachineInstr &MI, BuildFnTy &MatchInfo)
Use a function which takes in a MachineIRBuilder to perform a combine.
Definition: CombinerHelper.cpp:3817
llvm::CombinerHelper::tryCombineShuffleVector
bool tryCombineShuffleVector(MachineInstr &MI)
Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
Definition: CombinerHelper.cpp:257
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::CombinerHelper::matchCombineDivRem
bool matchCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI)
Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM when their source operands are iden...
Definition: CombinerHelper.cpp:1033
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bool tryCombineIndexedLoadStore(MachineInstr &MI)
Combine MI into a pre-indexed or post-indexed load/store operation if legal and the surrounding code ...
Definition: CombinerHelper.cpp:961
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llvm::MergeTruncStoresInfo::NeedRotate
bool NeedRotate
Definition: CombinerHelper.h:82
llvm::CombinerHelper::matchNarrowBinopFeedingAnd
bool matchNarrowBinopFeedingAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4288
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Definition: CombinerHelper.h:95
llvm::MergeTruncStoresInfo::FoundStores
SmallVector< GStore * > FoundStores
Definition: CombinerHelper.h:78
llvm::CombinerHelper::applyCombineExtOfExt
void applyCombineExtOfExt(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Definition: CombinerHelper.cpp:2078
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Definition: APInt.h:33
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
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bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount)
Definition: CombinerHelper.cpp:1920
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bool matchSextTruncSextLoad(MachineInstr &MI)
Definition: CombinerHelper.cpp:734
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bool matchPtrAddZero(MachineInstr &MI)
}
Definition: CombinerHelper.cpp:2955
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bool tryCombineExtendingLoads(MachineInstr &MI)
If MI is extend that consumes the result of a load, try to combine it.
Definition: CombinerHelper.cpp:442
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int64_t Imm
Definition: CombinerHelper.h:58
llvm::CombinerHelper::matchPtrAddImmedChain
bool matchPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo)
Definition: CombinerHelper.cpp:1271
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bool matchRotateOutOfRange(MachineInstr &MI)
Definition: CombinerHelper.cpp:3855
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bool matchNotCmp(MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate)
Combine inverting a result of a compare into the opposite cond code.
Definition: CombinerHelper.cpp:2801
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void applyCombineTruncOfExt(MachineInstr &MI, std::pair< Register, unsigned > &MatchInfo)
Definition: CombinerHelper.cpp:2148
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void applyNotCmp(MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate)
Definition: CombinerHelper.cpp:2878
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bool matchCombineCopy(MachineInstr &MI)
Definition: CombinerHelper.cpp:166
llvm::CombinerHelper::matchCombineAddP2IToPtrAdd
bool matchCombineAddP2IToPtrAdd(MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute)
Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y) Transform G_ADD y,...
Definition: CombinerHelper.cpp:1962
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Definition: CombinerHelper.h:57
llvm::CombinerHelper::matchAshrShlToSextInreg
bool matchAshrShlToSextInreg(MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo)
Match ashr (shl x, C), C -> sext_inreg (C)
Definition: CombinerHelper.cpp:2628
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void applyTruncStoreMerge(MachineInstr &MI, MergeTruncStoresInfo &MatchInfo)
Definition: CombinerHelper.cpp:3579
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Definition: CombinerHelper.h:87
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Register Base
Definition: CombinerHelper.h:59
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int64_t Imm
Definition: CombinerHelper.h:65
llvm::CombinerHelper::applyPtrAddZero
void applyPtrAddZero(MachineInstr &MI)
Definition: CombinerHelper.cpp:2974
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std::function< void(MachineIRBuilder &)> BuildFnTy
Definition: CombinerHelper.h:75
llvm::InstructionBuildSteps::OperandFns
OperandBuildSteps OperandFns
The opcode for the produced instruction.
Definition: CombinerHelper.h:89
llvm::CombinerHelper::setRegBank
void setRegBank(Register Reg, const RegisterBank *RegBank)
Set the register bank of Reg.
Definition: CombinerHelper.cpp:154
llvm::CombinerHelper::matchReassocPtrAdd
bool matchReassocPtrAdd(MachineInstr &MI, BuildFnTy &MatchInfo)
Reassociate pointer calculations with G_ADD involved, to allow better addressing mode usage.
Definition: CombinerHelper.cpp:4245
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This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::CombinerHelper::MDT
MachineDominatorTree * MDT
Definition: CombinerHelper.h:110
llvm::CombinerHelper::matchCombineConcatVectors
bool matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef, SmallVectorImpl< Register > &Ops)
Check if the G_CONCAT_VECTORS MI is undef or if it can be flattened into a build_vector.
Definition: CombinerHelper.cpp:190
llvm::CombinerHelper::matchRedundantSExtInReg
bool matchRedundantSExtInReg(MachineInstr &MI)
Definition: CombinerHelper.cpp:2786
llvm::CombinerHelper::matchCombineZextTrunc
bool matchCombineZextTrunc(MachineInstr &MI, Register &Reg)
Transform zext(trunc(x)) to x.
Definition: CombinerHelper.cpp:2043
llvm::ShiftOfShiftedLogic
Definition: CombinerHelper.h:68
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3189
llvm::CombinerHelper::matchReassocFoldConstantsInSubTree
bool matchReassocFoldConstantsInSubTree(GPtrAdd &MI, MachineInstr *LHS, MachineInstr *RHS, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4216
llvm::InstructionStepsMatchInfo::InstructionStepsMatchInfo
InstructionStepsMatchInfo(std::initializer_list< InstructionBuildSteps > InstrsToBuild)
Definition: CombinerHelper.h:99
llvm::CombinerHelper::applySimplifyURemByPow2
void applySimplifyURemByPow2(MachineInstr &MI)
Combine G_UREM x, (known power of 2) to an add and bitmasking.
Definition: CombinerHelper.cpp:2982
llvm::CombinerHelper::matchLoadOrCombine
bool matchLoadOrCombine(MachineInstr &MI, BuildFnTy &MatchInfo)
Match expression trees of the form.
Definition: CombinerHelper.cpp:3228
llvm::CombinerHelper::matchAnyExplicitUseIsUndef
bool matchAnyExplicitUseIsUndef(MachineInstr &MI)
Return true if any explicit use operand on MI is defined by a G_IMPLICIT_DEF.
Definition: CombinerHelper.cpp:2209
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::CombinerHelper::applyCombineUnmergeZExtToZExt
void applyCombineUnmergeZExtToZExt(MachineInstr &MI)
Definition: CombinerHelper.cpp:1788
llvm::PreferredTuple::Ty
LLT Ty
Definition: CombinerHelper.h:45
llvm::CombinerHelper::applyExtendThroughPhis
void applyExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI)
Definition: CombinerHelper.cpp:3661
llvm::CombinerHelper::matchCombineI2PToP2I
bool matchCombineI2PToP2I(MachineInstr &MI, Register &Reg)
Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
Definition: CombinerHelper.cpp:1931
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
llvm::CombinerHelper::matchCombineFNegOfFNeg
bool matchCombineFNegOfFNeg(MachineInstr &MI, Register &Reg)
Transform fneg(fneg(x)) to x.
Definition: CombinerHelper.cpp:2121
llvm::CombinerHelper::TRI
const TargetRegisterInfo * TRI
Definition: CombinerHelper.h:113
llvm::CombinerHelper::applyCombineUnmergeConstant
void applyCombineUnmergeConstant(MachineInstr &MI, SmallVectorImpl< APInt > &Csts)
Definition: CombinerHelper.cpp:1714
llvm::CombinerHelper
Definition: CombinerHelper.h:104
llvm::CombinerHelper::applyCombineConcatVectors
void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef, const ArrayRef< Register > Ops)
Replace MI with a flattened build_vector with Ops or an implicit_def if IsUndef is true.
Definition: CombinerHelper.cpp:235
llvm::CombinerHelper::matchCombineShuffleVector
bool matchCombineShuffleVector(MachineInstr &MI, SmallVectorImpl< Register > &Ops)
Check if the G_SHUFFLE_VECTOR MI can be replaced by a concat_vectors.
Definition: CombinerHelper.cpp:266
llvm::MergeTruncStoresInfo::NeedBSwap
bool NeedBSwap
Definition: CombinerHelper.h:81
llvm::CombinerHelper::tryCombineCopy
bool tryCombineCopy(MachineInstr &MI)
If MI is COPY, try to combine it.
Definition: CombinerHelper.cpp:159
llvm::CombinerHelper::Observer
GISelChangeObserver & Observer
Definition: CombinerHelper.h:108
llvm::CombinerHelper::matchCombineUnmergeZExtToZExt
bool matchCombineUnmergeZExtToZExt(MachineInstr &MI)
Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0.
Definition: CombinerHelper.cpp:1762
llvm::CombinerHelper::matchUndefShuffleVectorMask
bool matchUndefShuffleVectorMask(MachineInstr &MI)
Return true if a G_SHUFFLE_VECTOR instruction MI has an undef mask.
Definition: CombinerHelper.cpp:2223
llvm::CombinerHelper::matchICmpToTrueFalseKnownBits
bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo)
Definition: CombinerHelper.cpp:3885
llvm::CombinerHelper::applyCombineFAbsOfFAbs
void applyCombineFAbsOfFAbs(MachineInstr &MI, Register &Src)
llvm::CombinerHelper::matchCombineMergeUnmerge
bool matchCombineMergeUnmerge(MachineInstr &MI, Register &MatchInfo)
Fold away a merge of an unmerge of the corresponding values.
Definition: CombinerHelper.cpp:1615
llvm::CombinerHelper::KB
GISelKnownBits * KB
Definition: CombinerHelper.h:109
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::InstructionStepsMatchInfo::InstructionStepsMatchInfo
InstructionStepsMatchInfo()=default
llvm::IndexedLoadStoreMatchInfo::Offset
Register Offset
Definition: CombinerHelper.h:53
llvm::CombinerHelper::applyPtrAddImmedChain
void applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo)
Definition: CombinerHelper.cpp:1333
llvm::GStore
Represents a G_STORE.
Definition: GenericMachineInstrs.h:129
llvm::CombinerHelper::matchOverlappingAnd
bool matchOverlappingAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0.
Definition: CombinerHelper.cpp:2659
llvm::CombinerHelper::applyBuildInstructionSteps
void applyBuildInstructionSteps(MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo)
Replace MI with a series of instructions described in MatchInfo.
Definition: CombinerHelper.cpp:2613
llvm::CombinerHelper::matchRedundantAnd
bool matchRedundantAnd(MachineInstr &MI, Register &Replacement)
Definition: CombinerHelper.cpp:2685
llvm::GPtrAdd
Represents a G_PTR_ADD.
Definition: GenericMachineInstrs.h:199
llvm::CombinerHelper::applySimplifyAddToSub
void applySimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo)
Definition: CombinerHelper.cpp:2513
llvm::CombinerHelper::matchTruncStoreMerge
bool matchTruncStoreMerge(MachineInstr &MI, MergeTruncStoresInfo &MatchInfo)
Match a pattern where a wide type scalar value is stored by several narrow stores.
Definition: CombinerHelper.cpp:3409
llvm::CombinerHelper::matchBitfieldExtractFromShr
bool matchBitfieldExtractFromShr(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width.
Definition: CombinerHelper.cpp:4046
llvm::CombinerHelper::tryCombineConcatVectors
bool tryCombineConcatVectors(MachineInstr &MI)
If MI is G_CONCAT_VECTORS, try to combine it.
Definition: CombinerHelper.cpp:180
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::CombinerHelper::matchUndefStore
bool matchUndefStore(MachineInstr &MI)
Return true if a G_STORE instruction MI is storing an undef value.
Definition: CombinerHelper.cpp:2229
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:212
llvm::CombinerHelper::matchReassocConstantInnerLHS
bool matchReassocConstantInnerLHS(GPtrAdd &MI, MachineInstr *LHS, MachineInstr *RHS, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4187
llvm::CombinerHelper::matchBitfieldExtractFromSExtInReg
bool matchBitfieldExtractFromSExtInReg(MachineInstr &MI, BuildFnTy &MatchInfo)
Form a G_SBFX from a G_SEXT_INREG fed by a right shift.
Definition: CombinerHelper.cpp:3981
llvm::CombinerHelper::applyBuildFnNoErase
void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo)
Use a function which takes in a MachineIRBuilder to perform a combine.
Definition: CombinerHelper.cpp:3824
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::CombinerHelper::matchUndefSelectCmp
bool matchUndefSelectCmp(MachineInstr &MI)
Return true if a G_SELECT instruction MI has an undef comparison.
Definition: CombinerHelper.cpp:2235
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::CombinerHelper::applyCombineTruncOfShl
void applyCombineTruncOfShl(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Definition: CombinerHelper.cpp:2193
llvm::CombinerHelper::applyRotateOutOfRange
void applyRotateOutOfRange(MachineInstr &MI)
Definition: CombinerHelper.cpp:3870
llvm::CombinerHelper::applyCombineConstPtrAddToI2P
void applyCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst)
Definition: CombinerHelper.cpp:2024
llvm::ShiftOfShiftedLogic::LogicNonShiftReg
Register LogicNonShiftReg
Definition: CombinerHelper.h:71
llvm::CombinerHelper::Builder
MachineIRBuilder & Builder
Definition: CombinerHelper.h:106
llvm::MergeTruncStoresInfo::LowestIdxStore
GStore * LowestIdxStore
Definition: CombinerHelper.h:79
llvm::CombinerHelper::matchICmpToLHSKnownBits
bool matchICmpToLHSKnownBits(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:3938
llvm::CombinerHelper::matchCombineIndexedLoadStore
bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo)
Definition: CombinerHelper.cpp:970
llvm::CombinerHelper::matchCombineConstantFoldFpUnary
bool matchCombineConstantFoldFpUnary(MachineInstr &MI, Optional< APFloat > &Cst)
Transform fp_instr(cst) to constant result of the fp operation.
Definition: CombinerHelper.cpp:1251
llvm::CombinerHelper::matchCombineShlOfExtend
bool matchCombineShlOfExtend(MachineInstr &MI, RegisterImmPair &MatchData)
Definition: CombinerHelper.cpp:1564
llvm::CombinerHelper::matchConstantOp
bool matchConstantOp(const MachineOperand &MOP, int64_t C)
Return true if MOP is defined by a G_CONSTANT with a value equal to C.
Definition: CombinerHelper.cpp:2340
llvm::CombinerHelper::matchEqualDefs
bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2)
Return true if MOP1 and MOP2 are register operands are defined by equivalent instructions.
Definition: CombinerHelper.cpp:2256
llvm::CombinerHelper::replaceSingleDefInstWithOperand
bool replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx)
Delete MI and replace all of its uses with its OpIdx-th operand.
Definition: CombinerHelper.cpp:2348
llvm::CombinerHelper::matchCombineTruncOfExt
bool matchCombineTruncOfExt(MachineInstr &MI, std::pair< Register, unsigned > &MatchInfo)
Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
Definition: CombinerHelper.cpp:2134
llvm::CombinerHelper::matchCombineMulToShl
bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal)
Transform a multiply by a power-of-2 value to a left shift.
Definition: CombinerHelper.cpp:1539
llvm::PreferredTuple::ExtendOpcode
unsigned ExtendOpcode
Definition: CombinerHelper.h:46
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::CombinerHelper::applyCombineMulByNegativeOne
void applyCombineMulByNegativeOne(MachineInstr &MI)
Transform G_MUL(x, -1) to G_SUB(0, x)
Definition: CombinerHelper.cpp:2109
llvm::CombinerHelper::isLegalOrBeforeLegalizer
bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const
Definition: CombinerHelper.cpp:122
llvm::CombinerHelper::replaceInstWithUndef
bool replaceInstWithUndef(MachineInstr &MI)
Replace an instruction with a G_IMPLICIT_DEF.
Definition: CombinerHelper.cpp:2425
llvm::CombinerHelper::matchCombineInsertVecElts
bool matchCombineInsertVecElts(MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo)
Definition: CombinerHelper.cpp:2453
llvm::CombinerHelper::applySextTruncSextLoad
void applySextTruncSextLoad(MachineInstr &MI)
Definition: CombinerHelper.cpp:760
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::CombinerHelper::matchReassocConstantInnerRHS
bool matchReassocConstantInnerRHS(GPtrAdd &MI, MachineInstr *RHS, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4163
llvm::IndexedLoadStoreMatchInfo::IsPre
bool IsPre
Definition: CombinerHelper.h:54
llvm::LegalityQuery
The LegalityQuery object bundles together all the information that's needed to decide whether a given...
Definition: LegalizerInfo.h:108
llvm::CombinerHelper::isPredecessor
bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI)
Returns true if DefMI precedes UseMI or they are the same instruction.
Definition: CombinerHelper.cpp:706
llvm::CombinerHelper::matchXorOfAndWithSameReg
bool matchXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Fold (xor (and x, y), y) -> (and (not x), y) {.
Definition: CombinerHelper.cpp:2910
llvm::InstructionStepsMatchInfo::InstrsToBuild
SmallVector< InstructionBuildSteps, 2 > InstrsToBuild
Describes instructions to be built during a combine.
Definition: CombinerHelper.h:97
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::CombinerHelper::matchCombineExtOfExt
bool matchCombineExtOfExt(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Transform [asz]ext([asz]ext(x)) to [asz]ext x.
Definition: CombinerHelper.cpp:2057
llvm::CombinerHelper::replaceRegOpWith
void replaceRegOpWith(MachineRegisterInfo &MRI, MachineOperand &FromRegOp, Register ToReg) const
Replace a single register operand with a new register and inform the observer of the changes.
Definition: CombinerHelper.cpp:139
llvm::CombinerHelper::matchBinOpSameVal
bool matchBinOpSameVal(MachineInstr &MI)
Optimize (x op x) -> x.
Definition: CombinerHelper.cpp:2377
llvm::CombinerHelper::matchBitfieldExtractFromAnd
bool matchBitfieldExtractFromAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: and (lshr x, cst), mask -> ubfx x, cst, width.
Definition: CombinerHelper.cpp:4010
llvm::CombinerHelper::applyCombineConstantFoldFpUnary
void applyCombineConstantFoldFpUnary(MachineInstr &MI, Optional< APFloat > &Cst)
Definition: CombinerHelper.cpp:1260
llvm::CombinerHelper::applyCombineExtendingLoads
void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo)
Definition: CombinerHelper.cpp:526
llvm::CombinerHelper::applyAshShlToSextInreg
void applyAshShlToSextInreg(MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo)
Definition: CombinerHelper.cpp:2646
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::CombinerHelper::applyCombineInsertVecElts
void applyCombineInsertVecElts(MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo)
Definition: CombinerHelper.cpp:2494
llvm::CombinerHelper::matchSelectSameVal
bool matchSelectSameVal(MachineInstr &MI)
Optimize (cond ? x : x) -> x.
Definition: CombinerHelper.cpp:2369
llvm::CombinerHelper::matchOperandIsUndef
bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is undef.
Definition: CombinerHelper.cpp:2389
llvm::CombinerHelper::applyShiftImmedChain
void applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo)
Definition: CombinerHelper.cpp:1391
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::CombinerHelper::tryEmitMemcpyInline
bool tryEmitMemcpyInline(MachineInstr &MI)
Emit loads and stores that perform the given memcpy.
Definition: CombinerHelper.cpp:1193
llvm::CombinerHelper::matchCombineLoadWithAndMask
bool matchCombineLoadWithAndMask(MachineInstr &MI, BuildFnTy &MatchInfo)
Match (and (load x), mask) -> zextload x.
Definition: CombinerHelper.cpp:636
llvm::CombinerHelper::matchShiftOfShiftedLogic
bool matchShiftOfShiftedLogic(MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo)
If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with...
Definition: CombinerHelper.cpp:1424
llvm::CombinerHelper::matchCombineFAbsOfFAbs
bool matchCombineFAbsOfFAbs(MachineInstr &MI, Register &Src)
Match fabs(fabs(x)) to fabs(x).
Definition: CombinerHelper.cpp:2127
llvm::CombinerHelper::matchCombineAnyExtTrunc
bool matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg)
Transform anyext(trunc(x)) to x.
Definition: CombinerHelper.cpp:2034
Alignment.h
llvm::CombinerHelper::CombinerHelper
CombinerHelper(GISelChangeObserver &Observer, MachineIRBuilder &B, GISelKnownBits *KB=nullptr, MachineDominatorTree *MDT=nullptr, const LegalizerInfo *LI=nullptr)
Definition: CombinerHelper.cpp:48
llvm::CombinerHelper::matchOperandIsKnownToBeAPowerOfTwo
bool matchOperandIsKnownToBeAPowerOfTwo(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is known to be a power of 2.
Definition: CombinerHelper.cpp:2395
llvm::CombinerHelper::applyCombineUnmergeMergeToPlainValues
void applyCombineUnmergeMergeToPlainValues(MachineInstr &MI, SmallVectorImpl< Register > &Operands)
Definition: CombinerHelper.cpp:1666
llvm::CombinerHelper::matchSextInRegOfLoad
bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Match sext_inreg(load p), imm -> sextload p.
Definition: CombinerHelper.cpp:767
llvm::CombinerHelper::matchFunnelShiftToRotate
bool matchFunnelShiftToRotate(MachineInstr &MI)
Match an FSHL or FSHR that can be combined to a ROTR or ROTL rotate.
Definition: CombinerHelper.cpp:3831
llvm::PtrAddChain::Bank
const RegisterBank * Bank
Definition: CombinerHelper.h:60
llvm::CombinerHelper::matchSimplifyAddToSub
bool matchSimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo)
Return true if MI is a G_ADD which can be simplified to a G_SUB.
Definition: CombinerHelper.cpp:2433
llvm::CombinerHelper::RBI
const RegisterBankInfo * RBI
Definition: CombinerHelper.h:112
llvm::CombinerHelper::LI
const LegalizerInfo * LI
Definition: CombinerHelper.h:111
llvm::CombinerHelper::matchShiftImmedChain
bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo)
Fold (shift (shift base, x), y) -> (shift base (x+y))
Definition: CombinerHelper.cpp:1346
llvm::CombinerHelper::applyXorOfAndWithSameReg
void applyXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Definition: CombinerHelper.cpp:2941
llvm::CombinerHelper::applyCombineAddP2IToPtrAdd
void applyCombineAddP2IToPtrAdd(MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute)
Definition: CombinerHelper.cpp:1987
llvm::PreferredTuple::MI
MachineInstr * MI
Definition: CombinerHelper.h:47
llvm::RegisterImmPair::Reg
Register Reg
Definition: CombinerHelper.h:64
llvm::IndexedLoadStoreMatchInfo
Definition: CombinerHelper.h:50
llvm::CombinerHelper::matchExtendThroughPhis
bool matchExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI)
Definition: CombinerHelper.cpp:3606
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bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize, unsigned &ShiftVal)
Reduce a shift by a constant to an unmerge and a shift on a half sized type.
Definition: CombinerHelper.cpp:1822
llvm::CombinerHelper::getRegBank
const RegisterBank * getRegBank(Register Reg) const
Get the register bank of Reg.
Definition: CombinerHelper.cpp:150
llvm::CombinerHelper::applyCombineCopy
void applyCombineCopy(MachineInstr &MI)
Definition: CombinerHelper.cpp:173
llvm::CombinerHelper::tryCombine
bool tryCombine(MachineInstr &MI)
Try to transform MI by using all of the above combine functions.
Definition: CombinerHelper.cpp:4379
llvm::InstructionBuildSteps::InstructionBuildSteps
InstructionBuildSteps()=default
Operands to be added to the instruction.
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::CombinerHelper::applyCombineDivRem
void applyCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI)
Definition: CombinerHelper.cpp:1095
llvm::CombinerHelper::replaceInstWithConstant
bool replaceInstWithConstant(MachineInstr &MI, int64_t C)
Replace an instruction with a G_CONSTANT with value C.
Definition: CombinerHelper.cpp:2409
llvm::CombinerHelper::matchCombineUnmergeMergeToPlainValues
bool matchCombineUnmergeMergeToPlainValues(MachineInstr &MI, SmallVectorImpl< Register > &Operands)
Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
Definition: CombinerHelper.cpp:1642
llvm::CombinerHelper::applyCombineP2IToI2P
void applyCombineP2IToI2P(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:1954
llvm::ShiftOfShiftedLogic::ValSum
uint64_t ValSum
Definition: CombinerHelper.h:72
llvm::CombinerHelper::applyExtractAllEltsFromBuildVector
void applyExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * >> &MatchInfo)
Definition: CombinerHelper.cpp:3805
llvm::CombinerHelper::applyShiftOfShiftedLogic
void applyShiftOfShiftedLogic(MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo)
Definition: CombinerHelper.cpp:1505
llvm::CombinerHelper::matchOperandIsZero
bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is zero.
Definition: CombinerHelper.cpp:2383
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Definition: CombinerHelper.h:44
llvm::CombinerHelper::matchCombineExtendingLoads
bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo)
Definition: CombinerHelper.cpp:451
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This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1110
llvm::CombinerHelper::applySextInRegOfLoad
void applySextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Definition: CombinerHelper.cpp:808
Register.h
llvm::CombinerHelper::matchAllExplicitUsesAreUndef
bool matchAllExplicitUsesAreUndef(MachineInstr &MI)
Return true if all register explicit use operands on MI are defined by a G_IMPLICIT_DEF.
Definition: CombinerHelper.cpp:2216
llvm::CombinerHelper::replaceSingleDefInstWithReg
bool replaceSingleDefInstWithReg(MachineInstr &MI, Register Replacement)
Delete MI and replace all of its uses with Replacement.
Definition: CombinerHelper.cpp:2359
llvm::CombinerHelper::matchExtractAllEltsFromBuildVector
bool matchExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * >> &MatchInfo)
Definition: CombinerHelper.cpp:3762
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MachineInstr * Logic
Definition: CombinerHelper.h:69
llvm::CombinerHelper::applyCombineIndexedLoadStore
void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo)
Definition: CombinerHelper.cpp:991
llvm::CombinerHelper::matchRedundantOr
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Definition: CombinerHelper.cpp:2740
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:45
llvm::CombinerHelper::applyCombineAnyExtTrunc
void applyCombineAnyExtTrunc(MachineInstr &MI, Register &Reg)
llvm::CombinerHelper::matchCombineTruncOfShl
bool matchCombineTruncOfShl(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Transform trunc (shl x, K) to shl (trunc x), K => K < VT.getScalarSizeInBits().
Definition: CombinerHelper.cpp:2169
llvm::CombinerHelper::applyCombineMulToShl
void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal)
Definition: CombinerHelper.cpp:1551
llvm::CombinerHelper::matchOptBrCondByInvertingCond
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If a brcond's true block is not the fallthrough, make it so by inverting the condition and swapping o...
Definition: CombinerHelper.cpp:1127
llvm::CombinerHelper::applyCombineShlOfExtend
void applyCombineShlOfExtend(MachineInstr &MI, const RegisterImmPair &MatchData)
Definition: CombinerHelper.cpp:1601
llvm::CombinerHelper::applyCombineUnmergeWithDeadLanesToTrunc
void applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI)
Definition: CombinerHelper.cpp:1741
llvm::CombinerHelper::matchExtractVecEltBuildVec
bool matchExtractVecEltBuildVec(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:3707
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::CombinerHelper::replaceRegWith
void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const
MachineRegisterInfo::replaceRegWith() and inform the observer of the changes.
Definition: CombinerHelper.cpp:127
llvm::CombinerHelper::replaceInstWithFConstant
bool replaceInstWithFConstant(MachineInstr &MI, double C)
Replace an instruction with a G_FCONSTANT with value C.
Definition: CombinerHelper.cpp:2401
llvm::CombinerHelper::applyCombineShuffleVector
void applyCombineShuffleVector(MachineInstr &MI, const ArrayRef< Register > Ops)
Replace MI with a concat_vectors with Ops.
Definition: CombinerHelper.cpp:342
llvm::LLT
Definition: LowLevelTypeImpl.h:40