LLVM  14.0.0git
CombinerHelper.h
Go to the documentation of this file.
1 //===-- llvm/CodeGen/GlobalISel/CombinerHelper.h --------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===--------------------------------------------------------------------===//
8 /// \file
9 /// This contains common combine transformations that may be used in a combine
10 /// pass,or by the target elsewhere.
11 /// Targets can pick individual opcode transformations from the helper or use
12 /// tryCombine which invokes all transformations. All of the transformations
13 /// return true if the MachineInstruction changed and false otherwise.
14 ///
15 //===--------------------------------------------------------------------===//
16 
17 #ifndef LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
18 #define LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
19 
20 #include "llvm/ADT/APFloat.h"
21 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/CodeGen/Register.h"
25 #include "llvm/Support/Alignment.h"
26 
27 namespace llvm {
28 
29 class GISelChangeObserver;
30 class MachineIRBuilder;
31 class MachineInstrBuilder;
32 class MachineRegisterInfo;
33 class MachineInstr;
34 class MachineOperand;
35 class GISelKnownBits;
36 class MachineDominatorTree;
37 class LegalizerInfo;
38 struct LegalityQuery;
39 class RegisterBank;
40 class RegisterBankInfo;
41 class TargetLowering;
42 class TargetRegisterInfo;
43 
45  LLT Ty; // The result type of the extend.
46  unsigned ExtendOpcode; // G_ANYEXT/G_SEXT/G_ZEXT
48 };
49 
54  bool IsPre;
55 };
56 
57 struct PtrAddChain {
58  int64_t Imm;
61 };
62 
65  int64_t Imm;
66 };
67 
73 };
74 
76 
79  GStore *LowestIdxStore = nullptr;
81  bool NeedBSwap = false;
82  bool NeedRotate = false;
83 };
84 
85 using OperandBuildSteps =
88  unsigned Opcode = 0; /// The opcode for the produced instruction.
89  OperandBuildSteps OperandFns; /// Operands to be added to the instruction.
90  InstructionBuildSteps() = default;
93 };
94 
96  /// Describes instructions to be built during a combine.
98  InstructionStepsMatchInfo() = default;
100  std::initializer_list<InstructionBuildSteps> InstrsToBuild)
102 };
103 
105 protected:
114 
115 public:
117  GISelKnownBits *KB = nullptr,
118  MachineDominatorTree *MDT = nullptr,
119  const LegalizerInfo *LI = nullptr);
120 
122  return KB;
123  }
124 
125  const TargetLowering &getTargetLowering() const;
126 
127  /// \return true if the combine is running prior to legalization, or if \p
128  /// Query is legal on the target.
129  bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const;
130 
131  /// MachineRegisterInfo::replaceRegWith() and inform the observer of the changes
132  void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const;
133 
134  /// Replace a single register operand with a new register and inform the
135  /// observer of the changes.
137  Register ToReg) const;
138 
139  /// Replace the opcode in instruction with a new opcode and inform the
140  /// observer of the changes.
141  void replaceOpcodeWith(MachineInstr &FromMI, unsigned ToOpcode) const;
142 
143  /// Get the register bank of \p Reg.
144  /// If Reg has not been assigned a register, a register class,
145  /// or a register bank, then this returns nullptr.
146  ///
147  /// \pre Reg.isValid()
148  const RegisterBank *getRegBank(Register Reg) const;
149 
150  /// Set the register bank of \p Reg.
151  /// Does nothing if the RegBank is null.
152  /// This is the counterpart to getRegBank.
153  void setRegBank(Register Reg, const RegisterBank *RegBank);
154 
155  /// If \p MI is COPY, try to combine it.
156  /// Returns true if MI changed.
160 
161  /// Returns true if \p DefMI precedes \p UseMI or they are the same
162  /// instruction. Both must be in the same basic block.
163  bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI);
164 
165  /// Returns true if \p DefMI dominates \p UseMI. By definition an
166  /// instruction dominates itself.
167  ///
168  /// If we haven't been provided with a MachineDominatorTree during
169  /// construction, this function returns a conservative result that tracks just
170  /// a single basic block.
171  bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI);
172 
173  /// If \p MI is extend that consumes the result of a load, try to combine it.
174  /// Returns true if MI changed.
178 
179  /// Match (and (load x), mask) -> zextload x
181 
182  /// Combine \p MI into a pre-indexed or post-indexed load/store operation if
183  /// legal and the surrounding code makes it useful.
187 
190 
191  /// Match sext_inreg(load p), imm -> sextload p
192  bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
193  void applySextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
194 
195  /// Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM
196  /// when their source operands are identical.
199 
200  /// If a brcond's true block is not the fallthrough, make it so by inverting
201  /// the condition and swapping operands.
204 
205  /// If \p MI is G_CONCAT_VECTORS, try to combine it.
206  /// Returns true if MI changed.
207  /// Right now, we support:
208  /// - concat_vector(undef, undef) => undef
209  /// - concat_vector(build_vector(A, B), build_vector(C, D)) =>
210  /// build_vector(A, B, C, D)
211  ///
212  /// \pre MI.getOpcode() == G_CONCAT_VECTORS.
214  /// Check if the G_CONCAT_VECTORS \p MI is undef or if it
215  /// can be flattened into a build_vector.
216  /// In the first case \p IsUndef will be true.
217  /// In the second case \p Ops will contain the operands needed
218  /// to produce the flattened build_vector.
219  ///
220  /// \pre MI.getOpcode() == G_CONCAT_VECTORS.
221  bool matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef,
223  /// Replace \p MI with a flattened build_vector with \p Ops or an
224  /// implicit_def if IsUndef is true.
225  void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef,
226  const ArrayRef<Register> Ops);
227 
228  /// Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
229  /// Returns true if MI changed.
230  ///
231  /// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
233  /// Check if the G_SHUFFLE_VECTOR \p MI can be replaced by a
234  /// concat_vectors.
235  /// \p Ops will contain the operands needed to produce the flattened
236  /// concat_vectors.
237  ///
238  /// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
241  /// Replace \p MI with a concat_vectors with \p Ops.
243  const ArrayRef<Register> Ops);
244 
245  /// Optimize memcpy intrinsics et al, e.g. constant len calls.
246  /// /p MaxLen if non-zero specifies the max length of a mem libcall to inline.
247  ///
248  /// For example (pre-indexed):
249  ///
250  /// $addr = G_PTR_ADD $base, $offset
251  /// [...]
252  /// $val = G_LOAD $addr
253  /// [...]
254  /// $whatever = COPY $addr
255  ///
256  /// -->
257  ///
258  /// $val, $addr = G_INDEXED_LOAD $base, $offset, 1 (IsPre)
259  /// [...]
260  /// $whatever = COPY $addr
261  ///
262  /// or (post-indexed):
263  ///
264  /// G_STORE $val, $base
265  /// [...]
266  /// $addr = G_PTR_ADD $base, $offset
267  /// [...]
268  /// $whatever = COPY $addr
269  ///
270  /// -->
271  ///
272  /// $addr = G_INDEXED_STORE $val, $base, $offset
273  /// [...]
274  /// $whatever = COPY $addr
275  bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
276 
279 
280  /// Fold (shift (shift base, x), y) -> (shift base (x+y))
283 
284  /// If we have a shift-by-constant of a bitwise logic op that itself has a
285  /// shift-by-constant operand with identical opcode, we may be able to convert
286  /// that into 2 independent shifts followed by the logic op.
288  ShiftOfShiftedLogic &MatchInfo);
290  ShiftOfShiftedLogic &MatchInfo);
291 
292  /// Transform a multiply by a power-of-2 value to a left shift.
293  bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
294  void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
295 
296  // Transform a G_SHL with an extended source into a narrower shift if
297  // possible.
300  const RegisterImmPair &MatchData);
301 
302  /// Fold away a merge of an unmerge of the corresponding values.
304 
305  /// Reduce a shift by a constant to an unmerge and a shift on a half sized
306  /// type. This will not produce a shift smaller than \p TargetShiftSize.
307  bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize,
308  unsigned &ShiftVal);
309  void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal);
310  bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount);
311 
312  /// Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
313  bool
316  void
319 
320  /// Transform G_UNMERGE Constant -> Constant1, Constant2, ...
322  SmallVectorImpl<APInt> &Csts);
324  SmallVectorImpl<APInt> &Csts);
325 
326  /// Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
329 
330  /// Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0
333 
334  /// Transform fp_instr(cst) to constant result of the fp operation.
336  Optional<APFloat> &Cst);
338  Optional<APFloat> &Cst);
339 
340  /// Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
343 
344  /// Transform PtrToInt(IntToPtr(x)) to x.
347 
348  /// Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y)
349  /// Transform G_ADD y, (G_PTRTOINT x) -> G_PTRTOINT (G_PTR_ADD x, y)
351  std::pair<Register, bool> &PtrRegAndCommute);
353  std::pair<Register, bool> &PtrRegAndCommute);
354 
355  // Transform G_PTR_ADD (G_PTRTOINT C1), C2 -> C1 + C2
356  bool matchCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst);
357  void applyCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst);
358 
359  /// Transform anyext(trunc(x)) to x.
362 
363  /// Transform zext(trunc(x)) to x.
365 
366  /// Transform [asz]ext([asz]ext(x)) to [asz]ext x.
368  std::tuple<Register, unsigned> &MatchInfo);
370  std::tuple<Register, unsigned> &MatchInfo);
371 
372  /// Transform fneg(fneg(x)) to x.
374 
375  /// Match fabs(fabs(x)) to fabs(x).
378 
379  /// Transform fabs(fneg(x)) to fabs(x).
380  bool matchCombineFAbsOfFNeg(MachineInstr &MI, BuildFnTy &MatchInfo);
381 
382  /// Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
384  std::pair<Register, unsigned> &MatchInfo);
386  std::pair<Register, unsigned> &MatchInfo);
387 
388  /// Transform trunc (shl x, K) to shl (trunc x),
389  /// K => K < VT.getScalarSizeInBits().
391  std::pair<Register, Register> &MatchInfo);
393  std::pair<Register, Register> &MatchInfo);
394 
395  /// Transform G_MUL(x, -1) to G_SUB(0, x)
397 
398  /// Return true if any explicit use operand on \p MI is defined by a
399  /// G_IMPLICIT_DEF.
401 
402  /// Return true if all register explicit use operands on \p MI are defined by
403  /// a G_IMPLICIT_DEF.
405 
406  /// Return true if a G_SHUFFLE_VECTOR instruction \p MI has an undef mask.
408 
409  /// Return true if a G_STORE instruction \p MI is storing an undef value.
411 
412  /// Return true if a G_SELECT instruction \p MI has an undef comparison.
414 
415  /// Return true if a G_SELECT instruction \p MI has a constant comparison. If
416  /// true, \p OpIdx will store the operand index of the known selected value.
417  bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx);
418 
419  /// Replace an instruction with a G_FCONSTANT with value \p C.
420  bool replaceInstWithFConstant(MachineInstr &MI, double C);
421 
422  /// Replace an instruction with a G_CONSTANT with value \p C.
423  bool replaceInstWithConstant(MachineInstr &MI, int64_t C);
424 
425  /// Replace an instruction with a G_CONSTANT with value \p C.
427 
428  /// Replace an instruction with a G_IMPLICIT_DEF.
430 
431  /// Delete \p MI and replace all of its uses with its \p OpIdx-th operand.
432  bool replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx);
433 
434  /// Delete \p MI and replace all of its uses with \p Replacement.
436 
437  /// Return true if \p MOP1 and \p MOP2 are register operands are defined by
438  /// equivalent instructions.
439  bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2);
440 
441  /// Return true if \p MOP is defined by a G_CONSTANT with a value equal to
442  /// \p C.
443  bool matchConstantOp(const MachineOperand &MOP, int64_t C);
444 
445  /// Optimize (cond ? x : x) -> x
447 
448  /// Optimize (x op x) -> x
450 
451  /// Check if operand \p OpIdx is zero.
452  bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx);
453 
454  /// Check if operand \p OpIdx is undef.
455  bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx);
456 
457  /// Check if operand \p OpIdx is known to be a power of 2.
458  bool matchOperandIsKnownToBeAPowerOfTwo(MachineInstr &MI, unsigned OpIdx);
459 
460  /// Erase \p MI
461  bool eraseInst(MachineInstr &MI);
462 
463  /// Return true if MI is a G_ADD which can be simplified to a G_SUB.
465  std::tuple<Register, Register> &MatchInfo);
467  std::tuple<Register, Register> &MatchInfo);
468 
469  /// Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
470  bool
472  InstructionStepsMatchInfo &MatchInfo);
473 
474  /// Replace \p MI with a series of instructions described in \p MatchInfo.
476  InstructionStepsMatchInfo &MatchInfo);
477 
478  /// Match ashr (shl x, C), C -> sext_inreg (C)
480  std::tuple<Register, int64_t> &MatchInfo);
482  std::tuple<Register, int64_t> &MatchInfo);
483 
484  /// Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0
486  BuildFnTy &MatchInfo);
487 
488  /// \return true if \p MI is a G_AND instruction whose operands are x and y
489  /// where x & y == x or x & y == y. (E.g., one of operands is all-ones value.)
490  ///
491  /// \param [in] MI - The G_AND instruction.
492  /// \param [out] Replacement - A register the G_AND should be replaced with on
493  /// success.
494  bool matchRedundantAnd(MachineInstr &MI, Register &Replacement);
495 
496  /// \return true if \p MI is a G_OR instruction whose operands are x and y
497  /// where x | y == x or x | y == y. (E.g., one of operands is all-zeros
498  /// value.)
499  ///
500  /// \param [in] MI - The G_OR instruction.
501  /// \param [out] Replacement - A register the G_OR should be replaced with on
502  /// success.
503  bool matchRedundantOr(MachineInstr &MI, Register &Replacement);
504 
505  /// \return true if \p MI is a G_SEXT_INREG that can be erased.
507 
508  /// Combine inverting a result of a compare into the opposite cond code.
511 
512  /// Fold (xor (and x, y), y) -> (and (not x), y)
513  ///{
515  std::pair<Register, Register> &MatchInfo);
517  std::pair<Register, Register> &MatchInfo);
518  ///}
519 
520  /// Combine G_PTR_ADD with nullptr to G_INTTOPTR
523 
524  /// Combine G_UREM x, (known power of 2) to an add and bitmasking.
526 
528  SmallVectorImpl<Register> &MatchInfo);
529 
531  SmallVectorImpl<Register> &MatchInfo);
532 
533  /// Match expression trees of the form
534  ///
535  /// \code
536  /// sN *a = ...
537  /// sM val = a[0] | (a[1] << N) | (a[2] << 2N) | (a[3] << 3N) ...
538  /// \endcode
539  ///
540  /// And check if the tree can be replaced with a M-bit load + possibly a
541  /// bswap.
542  bool matchLoadOrCombine(MachineInstr &MI, BuildFnTy &MatchInfo);
543 
546 
549 
552 
554  MachineInstr &MI,
555  SmallVectorImpl<std::pair<Register, MachineInstr *>> &MatchInfo);
557  MachineInstr &MI,
558  SmallVectorImpl<std::pair<Register, MachineInstr *>> &MatchInfo);
559 
560  /// Use a function which takes in a MachineIRBuilder to perform a combine.
561  /// By default, it erases the instruction \p MI from the function.
562  void applyBuildFn(MachineInstr &MI, BuildFnTy &MatchInfo);
563  /// Use a function which takes in a MachineIRBuilder to perform a combine.
564  /// This variant does not erase \p MI after calling the build function.
565  void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo);
566 
572 
573  /// \returns true if a G_ICMP instruction \p MI can be replaced with a true
574  /// or false constant based off of KnownBits information.
575  bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo);
576 
577  /// \returns true if a G_ICMP \p MI can be replaced with its LHS based off of
578  /// KnownBits information.
579  bool
581  BuildFnTy &MatchInfo);
582 
583  /// \returns true if (and (or x, c1), c2) can be replaced with (and x, c2)
584  bool matchAndOrDisjointMask(MachineInstr &MI, BuildFnTy &MatchInfo);
585 
587  BuildFnTy &MatchInfo);
588  /// Match: and (lshr x, cst), mask -> ubfx x, cst, width
590 
591  /// Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width
593 
594  /// Match: shr (and x, n), k -> ubfx x, pos, width
596 
597  // Helpers for reassociation:
599  BuildFnTy &MatchInfo);
601  MachineInstr *RHS,
602  BuildFnTy &MatchInfo);
604  MachineInstr *RHS, BuildFnTy &MatchInfo);
605  /// Reassociate pointer calculations with G_ADD involved, to allow better
606  /// addressing mode usage.
607  bool matchReassocPtrAdd(MachineInstr &MI, BuildFnTy &MatchInfo);
608 
609  /// Do constant folding when opportunities are exposed after MIR building.
610  bool matchConstantFold(MachineInstr &MI, APInt &MatchInfo);
611 
612  /// \returns true if it is possible to narrow the width of a scalar binop
613  /// feeding a G_AND instruction \p MI.
615 
616  /// Given an G_UDIV \p MI expressing a divide by constant, return an
617  /// expression that implements it by multiplying by a magic number.
618  /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
620  /// Combine G_UDIV by constant into a multiply by magic constant.
623 
624  // G_UMULH x, (1 << c)) -> x >> (bitwidth - c)
627 
628  /// Try to transform \p MI by using all of the above
629  /// combine functions. Returns true if changed.
630  bool tryCombine(MachineInstr &MI);
631 
632  /// Emit loads and stores that perform the given memcpy.
633  /// Assumes \p MI is a G_MEMCPY_INLINE
634  /// TODO: implement dynamically sized inline memcpy,
635  /// and rename: s/bool tryEmit/void emit/
637 
638  /// Match:
639  /// (G_UMULO x, 2) -> (G_UADDO x, x)
640  /// (G_SMULO x, 2) -> (G_SADDO x, x)
641  bool matchMulOBy2(MachineInstr &MI, BuildFnTy &MatchInfo);
642 
643  /// Transform (fadd x, fneg(y)) -> (fsub x, y)
644  /// (fadd fneg(x), y) -> (fsub y, x)
645  /// (fsub x, fneg(y)) -> (fadd x, y)
646  /// (fmul fneg(x), fneg(y)) -> (fmul x, y)
647  /// (fdiv fneg(x), fneg(y)) -> (fdiv x, y)
648  /// (fmad fneg(x), fneg(y), z) -> (fmad x, y, z)
649  /// (fma fneg(x), fneg(y), z) -> (fma x, y, z)
651 
652  bool canCombineFMadOrFMA(MachineInstr &MI, bool &AllowFusionGlobally,
653  bool &HasFMAD, bool &Aggressive,
654  bool CanReassociate = false);
655 
656  /// Transform (fadd (fmul x, y), z) -> (fma x, y, z)
657  /// (fadd (fmul x, y), z) -> (fmad x, y, z)
659 
660  /// Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z)
661  /// (fadd (fpext (fmul x, y)), z) -> (fmad (fpext x), (fpext y), z)
663  BuildFnTy &MatchInfo);
664 
665  /// Transform (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y, (fma u, v, z))
666  /// (fadd (fmad x, y, (fmul u, v)), z) -> (fmad x, y, (fmad u, v, z))
668  BuildFnTy &MatchInfo);
669 
670  // Transform (fadd (fma x, y, (fpext (fmul u, v))), z)
671  // -> (fma x, y, (fma (fpext u), (fpext v), z))
672  // (fadd (fmad x, y, (fpext (fmul u, v))), z)
673  // -> (fmad x, y, (fmad (fpext u), (fpext v), z))
675  BuildFnTy &MatchInfo);
676 
677  /// Transform (fsub (fmul x, y), z) -> (fma x, y, -z)
678  /// (fsub (fmul x, y), z) -> (fmad x, y, -z)
680 
681  /// Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
682  /// (fsub (fneg (fmul, x, y)), z) -> (fmad (fneg x), y, (fneg z))
684  BuildFnTy &MatchInfo);
685 
686  /// Transform (fsub (fpext (fmul x, y)), z)
687  /// -> (fma (fpext x), (fpext y), (fneg z))
688  /// (fsub (fpext (fmul x, y)), z)
689  /// -> (fmad (fpext x), (fpext y), (fneg z))
691  BuildFnTy &MatchInfo);
692 
693  /// Transform (fsub (fpext (fneg (fmul x, y))), z)
694  /// -> (fneg (fma (fpext x), (fpext y), z))
695  /// (fsub (fpext (fneg (fmul x, y))), z)
696  /// -> (fneg (fmad (fpext x), (fpext y), z))
698  BuildFnTy &MatchInfo);
699 
700 private:
701  /// Given a non-indexed load or store instruction \p MI, find an offset that
702  /// can be usefully and legally folded into it as a post-indexing operation.
703  ///
704  /// \returns true if a candidate is found.
705  bool findPostIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
706  Register &Offset);
707 
708  /// Given a non-indexed load or store instruction \p MI, find an offset that
709  /// can be usefully and legally folded into it as a pre-indexing operation.
710  ///
711  /// \returns true if a candidate is found.
712  bool findPreIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
713  Register &Offset);
714 
715  /// Helper function for matchLoadOrCombine. Searches for Registers
716  /// which may have been produced by a load instruction + some arithmetic.
717  ///
718  /// \param [in] Root - The search root.
719  ///
720  /// \returns The Registers found during the search.
722  findCandidatesForLoadOrCombine(const MachineInstr *Root) const;
723 
724  /// Helper function for matchLoadOrCombine.
725  ///
726  /// Checks if every register in \p RegsToVisit is defined by a load
727  /// instruction + some arithmetic.
728  ///
729  /// \param [out] MemOffset2Idx - Maps the byte positions each load ends up
730  /// at to the index of the load.
731  /// \param [in] MemSizeInBits - The number of bits each load should produce.
732  ///
733  /// \returns On success, a 3-tuple containing lowest-index load found, the
734  /// lowest index, and the last load in the sequence.
736  findLoadOffsetsForLoadOrCombine(
737  SmallDenseMap<int64_t, int64_t, 8> &MemOffset2Idx,
738  const SmallVector<Register, 8> &RegsToVisit,
739  const unsigned MemSizeInBits);
740 
741  /// Examines the G_PTR_ADD instruction \p PtrAdd and determines if performing
742  /// a re-association of its operands would break an existing legal addressing
743  /// mode that the address computation currently represents.
744  bool reassociationCanBreakAddressingModePattern(MachineInstr &PtrAdd);
745 };
746 } // namespace llvm
747 
748 #endif
llvm::CombinerHelper::matchCombineConstPtrAddToI2P
bool matchCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst)
Definition: CombinerHelper.cpp:2027
llvm::CombinerHelper::matchCombineUnmergeWithDeadLanesToTrunc
bool matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI)
Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
Definition: CombinerHelper.cpp:1751
llvm::IndexedLoadStoreMatchInfo::Addr
Register Addr
Definition: CombinerHelper.h:51
llvm::CombinerHelper::matchConstantFold
bool matchConstantFold(MachineInstr &MI, APInt &MatchInfo)
Do constant folding when opportunities are exposed after MIR building.
Definition: CombinerHelper.cpp:4443
llvm::CombinerHelper::applyCombineShiftToUnmerge
void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal)
Definition: CombinerHelper.cpp:1868
LowLevelType.h
llvm::InstructionBuildSteps::Opcode
unsigned Opcode
Definition: CombinerHelper.h:88
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1563
llvm::CombinerHelper::applyExtractVecEltBuildVec
void applyExtractVecEltBuildVec(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:3785
llvm::RegisterImmPair
Definition: CombinerHelper.h:63
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::MergeTruncStoresInfo::WideSrcVal
Register WideSrcVal
Definition: CombinerHelper.h:80
llvm::CombinerHelper::matchCombineUnmergeConstant
bool matchCombineUnmergeConstant(MachineInstr &MI, SmallVectorImpl< APInt > &Csts)
Transform G_UNMERGE Constant -> Constant1, Constant2, ...
Definition: CombinerHelper.cpp:1710
llvm::CombinerHelper::MRI
MachineRegisterInfo & MRI
Definition: CombinerHelper.h:107
llvm::CombinerHelper::applyOptBrCondByInvertingCond
void applyOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond)
Definition: CombinerHelper.cpp:1182
llvm::CombinerHelper::matchHoistLogicOpWithSameOpcodeHands
bool matchHoistLogicOpWithSameOpcodeHands(MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo)
Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
Definition: CombinerHelper.cpp:2561
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::ShiftOfShiftedLogic::Shift2
MachineInstr * Shift2
Definition: CombinerHelper.h:70
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::CombinerHelper::applyCombineI2PToP2I
void applyCombineI2PToP2I(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:1961
llvm::CombinerHelper::eraseInst
bool eraseInst(MachineInstr &MI)
Erase MI.
Definition: CombinerHelper.cpp:2289
llvm::IndexedLoadStoreMatchInfo::Base
Register Base
Definition: CombinerHelper.h:52
llvm::CombinerHelper::getKnownBits
GISelKnownBits * getKnownBits() const
Definition: CombinerHelper.h:121
llvm::CombinerHelper::matchCombineP2IToI2P
bool matchCombineP2IToI2P(MachineInstr &MI, Register &Reg)
Transform PtrToInt(IntToPtr(x)) to x.
Definition: CombinerHelper.cpp:1969
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1177
llvm::CombinerHelper::getTargetLowering
const TargetLowering & getTargetLowering() const
Definition: CombinerHelper.cpp:60
llvm::InstructionBuildSteps::InstructionBuildSteps
InstructionBuildSteps(unsigned Opcode, const OperandBuildSteps &OperandFns)
Definition: CombinerHelper.h:91
llvm::CombinerHelper::matchCombineFSubFMulToFMadOrFMA
bool matchCombineFSubFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fmul x, y), z) -> (fma x, y, -z) (fsub (fmul x, y), z) -> (fmad x,...
Definition: CombinerHelper.cpp:5144
llvm::CombinerHelper::tryCombineMemCpyFamily
bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen=0)
Optimize memcpy intrinsics et al, e.g.
Definition: CombinerHelper.cpp:1222
llvm::CombinerHelper::dominates
bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI)
Returns true if DefMI dominates UseMI.
Definition: CombinerHelper.cpp:743
llvm::MergeTruncStoresInfo
Definition: CombinerHelper.h:77
llvm::CombinerHelper::matchCombineFAddFMAFMulToFMadOrFMA
bool matchCombineFAddFMAFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y, (fma u, v, z)) (fadd (fmad x,...
Definition: CombinerHelper.cpp:4953
llvm::SmallDenseMap
Definition: DenseMap.h:880
llvm::CombinerHelper::matchConstantSelectCmp
bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx)
Return true if a G_SELECT instruction MI has a constant comparison.
Definition: CombinerHelper.cpp:2279
llvm::CombinerHelper::applyFunnelShiftToRotate
void applyFunnelShiftToRotate(MachineInstr &MI)
Definition: CombinerHelper.cpp:3928
llvm::CombinerHelper::matchCombineFSubFpExtFNegFMulToFMadOrFMA
bool matchCombineFSubFpExtFNegFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fpext (fneg (fmul x, y))), z) -> (fneg (fma (fpext x), (fpext y),...
Definition: CombinerHelper.cpp:5294
llvm::CombinerHelper::applyBuildFn
void applyBuildFn(MachineInstr &MI, BuildFnTy &MatchInfo)
Use a function which takes in a MachineIRBuilder to perform a combine.
Definition: CombinerHelper.cpp:3857
llvm::CombinerHelper::tryCombineShuffleVector
bool tryCombineShuffleVector(MachineInstr &MI)
Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
Definition: CombinerHelper.cpp:278
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::CombinerHelper::replaceOpcodeWith
void replaceOpcodeWith(MachineInstr &FromMI, unsigned ToOpcode) const
Replace the opcode in instruction with a new opcode and inform the observer of the changes.
Definition: CombinerHelper.cpp:162
llvm::CombinerHelper::matchCombineDivRem
bool matchCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI)
Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM when their source operands are iden...
Definition: CombinerHelper.cpp:1054
llvm::CombinerHelper::tryCombineIndexedLoadStore
bool tryCombineIndexedLoadStore(MachineInstr &MI)
Combine MI into a pre-indexed or post-indexed load/store operation if legal and the surrounding code ...
Definition: CombinerHelper.cpp:982
DenseMap.h
llvm::MergeTruncStoresInfo::NeedRotate
bool NeedRotate
Definition: CombinerHelper.h:82
llvm::CombinerHelper::matchNarrowBinopFeedingAnd
bool matchNarrowBinopFeedingAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4453
llvm::InstructionStepsMatchInfo
Definition: CombinerHelper.h:95
llvm::MergeTruncStoresInfo::FoundStores
SmallVector< GStore * > FoundStores
Definition: CombinerHelper.h:78
llvm::CombinerHelper::applyCombineExtOfExt
void applyCombineExtOfExt(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Definition: CombinerHelper.cpp:2099
GenericMachineInstrs.h
llvm::Optional
Definition: APInt.h:33
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:80
llvm::CombinerHelper::tryCombineShiftToUnmerge
bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount)
Definition: CombinerHelper.cpp:1941
llvm::CombinerHelper::matchSextTruncSextLoad
bool matchSextTruncSextLoad(MachineInstr &MI)
Definition: CombinerHelper.cpp:755
Aggressive
static cl::opt< bool > Aggressive("aggressive-ext-opt", cl::Hidden, cl::desc("Aggressive extension optimization"))
RHS
Value * RHS
Definition: X86PartialReduction.cpp:74
llvm::CombinerHelper::matchPtrAddZero
bool matchPtrAddZero(MachineInstr &MI)
}
Definition: CombinerHelper.cpp:2994
llvm::CombinerHelper::tryCombineExtendingLoads
bool tryCombineExtendingLoads(MachineInstr &MI)
If MI is extend that consumes the result of a load, try to combine it.
Definition: CombinerHelper.cpp:463
llvm::PtrAddChain::Imm
int64_t Imm
Definition: CombinerHelper.h:58
llvm::CombinerHelper::matchPtrAddImmedChain
bool matchPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo)
Definition: CombinerHelper.cpp:1292
llvm::CombinerHelper::matchRotateOutOfRange
bool matchRotateOutOfRange(MachineInstr &MI)
Definition: CombinerHelper.cpp:3940
llvm::CombinerHelper::matchNotCmp
bool matchNotCmp(MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate)
Combine inverting a result of a compare into the opposite cond code.
Definition: CombinerHelper.cpp:2840
llvm::CombinerHelper::applyCombineTruncOfExt
void applyCombineTruncOfExt(MachineInstr &MI, std::pair< Register, unsigned > &MatchInfo)
Definition: CombinerHelper.cpp:2186
llvm::CombinerHelper::applyNotCmp
void applyNotCmp(MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate)
Definition: CombinerHelper.cpp:2917
llvm::CombinerHelper::matchCombineCopy
bool matchCombineCopy(MachineInstr &MI)
Definition: CombinerHelper.cpp:187
llvm::CombinerHelper::matchCombineAddP2IToPtrAdd
bool matchCombineAddP2IToPtrAdd(MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute)
Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y) Transform G_ADD y,...
Definition: CombinerHelper.cpp:1983
llvm::PtrAddChain
Definition: CombinerHelper.h:57
llvm::CombinerHelper::matchAshrShlToSextInreg
bool matchAshrShlToSextInreg(MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo)
Match ashr (shl x, C), C -> sext_inreg (C)
Definition: CombinerHelper.cpp:2667
llvm::CombinerHelper::applyTruncStoreMerge
void applyTruncStoreMerge(MachineInstr &MI, MergeTruncStoresInfo &MatchInfo)
Definition: CombinerHelper.cpp:3621
llvm::InstructionBuildSteps
Definition: CombinerHelper.h:87
llvm::PtrAddChain::Base
Register Base
Definition: CombinerHelper.h:59
LHS
Value * LHS
Definition: X86PartialReduction.cpp:73
llvm::RegisterImmPair::Imm
int64_t Imm
Definition: CombinerHelper.h:65
llvm::CombinerHelper::applyPtrAddZero
void applyPtrAddZero(MachineInstr &MI)
Definition: CombinerHelper.cpp:3013
llvm::BuildFnTy
std::function< void(MachineIRBuilder &)> BuildFnTy
Definition: CombinerHelper.h:75
llvm::InstructionBuildSteps::OperandFns
OperandBuildSteps OperandFns
The opcode for the produced instruction.
Definition: CombinerHelper.h:89
llvm::CombinerHelper::setRegBank
void setRegBank(Register Reg, const RegisterBank *RegBank)
Set the register bank of Reg.
Definition: CombinerHelper.cpp:175
llvm::CombinerHelper::matchReassocPtrAdd
bool matchReassocPtrAdd(MachineInstr &MI, BuildFnTy &MatchInfo)
Reassociate pointer calculations with G_ADD involved, to allow better addressing mode usage.
Definition: CombinerHelper.cpp:4410
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::CombinerHelper::MDT
MachineDominatorTree * MDT
Definition: CombinerHelper.h:110
llvm::CombinerHelper::buildUDivUsingMul
MachineInstr * buildUDivUsingMul(MachineInstr &MI)
Given an G_UDIV MI expressing a divide by constant, return an expression that implements it by multip...
Definition: CombinerHelper.cpp:4562
llvm::CombinerHelper::matchCombineConcatVectors
bool matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef, SmallVectorImpl< Register > &Ops)
Check if the G_CONCAT_VECTORS MI is undef or if it can be flattened into a build_vector.
Definition: CombinerHelper.cpp:211
llvm::CombinerHelper::matchRedundantSExtInReg
bool matchRedundantSExtInReg(MachineInstr &MI)
Definition: CombinerHelper.cpp:2825
llvm::CombinerHelper::matchCombineZextTrunc
bool matchCombineZextTrunc(MachineInstr &MI, Register &Reg)
Transform zext(trunc(x)) to x.
Definition: CombinerHelper.cpp:2064
llvm::ShiftOfShiftedLogic
Definition: CombinerHelper.h:68
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3277
llvm::CombinerHelper::matchReassocFoldConstantsInSubTree
bool matchReassocFoldConstantsInSubTree(GPtrAdd &MI, MachineInstr *LHS, MachineInstr *RHS, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4381
llvm::InstructionStepsMatchInfo::InstructionStepsMatchInfo
InstructionStepsMatchInfo(std::initializer_list< InstructionBuildSteps > InstrsToBuild)
Definition: CombinerHelper.h:99
llvm::CombinerHelper::applySimplifyURemByPow2
void applySimplifyURemByPow2(MachineInstr &MI)
Combine G_UREM x, (known power of 2) to an add and bitmasking.
Definition: CombinerHelper.cpp:3021
llvm::CombinerHelper::matchLoadOrCombine
bool matchLoadOrCombine(MachineInstr &MI, BuildFnTy &MatchInfo)
Match expression trees of the form.
Definition: CombinerHelper.cpp:3267
llvm::CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMAAggressive
bool matchCombineFAddFpExtFMulToFMadOrFMAAggressive(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:5018
llvm::CombinerHelper::matchAnyExplicitUseIsUndef
bool matchAnyExplicitUseIsUndef(MachineInstr &MI)
Return true if any explicit use operand on MI is defined by a G_IMPLICIT_DEF.
Definition: CombinerHelper.cpp:2247
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::CombinerHelper::applyCombineUnmergeZExtToZExt
void applyCombineUnmergeZExtToZExt(MachineInstr &MI)
Definition: CombinerHelper.cpp:1809
llvm::PreferredTuple::Ty
LLT Ty
Definition: CombinerHelper.h:45
llvm::CombinerHelper::applyExtendThroughPhis
void applyExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI)
Definition: CombinerHelper.cpp:3703
llvm::CombinerHelper::matchCombineI2PToP2I
bool matchCombineI2PToP2I(MachineInstr &MI, Register &Reg)
Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
Definition: CombinerHelper.cpp:1952
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
llvm::CombinerHelper::matchCombineFNegOfFNeg
bool matchCombineFNegOfFNeg(MachineInstr &MI, Register &Reg)
Transform fneg(fneg(x)) to x.
Definition: CombinerHelper.cpp:2142
llvm::CombinerHelper::TRI
const TargetRegisterInfo * TRI
Definition: CombinerHelper.h:113
llvm::CombinerHelper::applyCombineUnmergeConstant
void applyCombineUnmergeConstant(MachineInstr &MI, SmallVectorImpl< APInt > &Csts)
Definition: CombinerHelper.cpp:1735
llvm::CombinerHelper::matchCombineFAddFMulToFMadOrFMA
bool matchCombineFAddFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd (fmul x, y), z) -> (fma x, y, z) (fadd (fmul x, y), z) -> (fmad x,...
Definition: CombinerHelper.cpp:4846
llvm::CombinerHelper
Definition: CombinerHelper.h:104
llvm::CombinerHelper::applyCombineConcatVectors
void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef, const ArrayRef< Register > Ops)
Replace MI with a flattened build_vector with Ops or an implicit_def if IsUndef is true.
Definition: CombinerHelper.cpp:256
llvm::CombinerHelper::matchCombineShuffleVector
bool matchCombineShuffleVector(MachineInstr &MI, SmallVectorImpl< Register > &Ops)
Check if the G_SHUFFLE_VECTOR MI can be replaced by a concat_vectors.
Definition: CombinerHelper.cpp:287
llvm::MergeTruncStoresInfo::NeedBSwap
bool NeedBSwap
Definition: CombinerHelper.h:81
llvm::CombinerHelper::tryCombineCopy
bool tryCombineCopy(MachineInstr &MI)
If MI is COPY, try to combine it.
Definition: CombinerHelper.cpp:180
llvm::CombinerHelper::Observer
GISelChangeObserver & Observer
Definition: CombinerHelper.h:108
llvm::CombinerHelper::matchCombineUnmergeZExtToZExt
bool matchCombineUnmergeZExtToZExt(MachineInstr &MI)
Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0.
Definition: CombinerHelper.cpp:1783
llvm::CombinerHelper::matchUndefShuffleVectorMask
bool matchUndefShuffleVectorMask(MachineInstr &MI)
Return true if a G_SHUFFLE_VECTOR instruction MI has an undef mask.
Definition: CombinerHelper.cpp:2261
llvm::CombinerHelper::matchICmpToTrueFalseKnownBits
bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo)
Definition: CombinerHelper.cpp:3970
llvm::CombinerHelper::applyCombineFAbsOfFAbs
void applyCombineFAbsOfFAbs(MachineInstr &MI, Register &Src)
llvm::CombinerHelper::matchCombineMergeUnmerge
bool matchCombineMergeUnmerge(MachineInstr &MI, Register &MatchInfo)
Fold away a merge of an unmerge of the corresponding values.
Definition: CombinerHelper.cpp:1636
llvm::CombinerHelper::KB
GISelKnownBits * KB
Definition: CombinerHelper.h:109
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::InstructionStepsMatchInfo::InstructionStepsMatchInfo
InstructionStepsMatchInfo()=default
llvm::IndexedLoadStoreMatchInfo::Offset
Register Offset
Definition: CombinerHelper.h:53
llvm::CombinerHelper::applyPtrAddImmedChain
void applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo)
Definition: CombinerHelper.cpp:1354
llvm::GStore
Represents a G_STORE.
Definition: GenericMachineInstrs.h:129
llvm::CombinerHelper::matchOverlappingAnd
bool matchOverlappingAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0.
Definition: CombinerHelper.cpp:2698
llvm::CombinerHelper::applyBuildInstructionSteps
void applyBuildInstructionSteps(MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo)
Replace MI with a series of instructions described in MatchInfo.
Definition: CombinerHelper.cpp:2652
llvm::CombinerHelper::matchRedundantAnd
bool matchRedundantAnd(MachineInstr &MI, Register &Replacement)
Definition: CombinerHelper.cpp:2724
llvm::GPtrAdd
Represents a G_PTR_ADD.
Definition: GenericMachineInstrs.h:199
llvm::CombinerHelper::applySimplifyAddToSub
void applySimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo)
Definition: CombinerHelper.cpp:2552
llvm::CombinerHelper::matchTruncStoreMerge
bool matchTruncStoreMerge(MachineInstr &MI, MergeTruncStoresInfo &MatchInfo)
Match a pattern where a wide type scalar value is stored by several narrow stores.
Definition: CombinerHelper.cpp:3448
llvm::CombinerHelper::matchBitfieldExtractFromShr
bool matchBitfieldExtractFromShr(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width.
Definition: CombinerHelper.cpp:4161
llvm::CombinerHelper::tryCombineConcatVectors
bool tryCombineConcatVectors(MachineInstr &MI)
If MI is G_CONCAT_VECTORS, try to combine it.
Definition: CombinerHelper.cpp:201
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::CombinerHelper::matchUndefStore
bool matchUndefStore(MachineInstr &MI)
Return true if a G_STORE instruction MI is storing an undef value.
Definition: CombinerHelper.cpp:2267
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:212
llvm::CombinerHelper::matchReassocConstantInnerLHS
bool matchReassocConstantInnerLHS(GPtrAdd &MI, MachineInstr *LHS, MachineInstr *RHS, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4352
llvm::CombinerHelper::matchBitfieldExtractFromSExtInReg
bool matchBitfieldExtractFromSExtInReg(MachineInstr &MI, BuildFnTy &MatchInfo)
Form a G_SBFX from a G_SEXT_INREG fed by a right shift.
Definition: CombinerHelper.cpp:4096
llvm::CombinerHelper::matchUMulHToLShr
bool matchUMulHToLShr(MachineInstr &MI)
Definition: CombinerHelper.cpp:4718
llvm::CombinerHelper::applyBuildFnNoErase
void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo)
Use a function which takes in a MachineIRBuilder to perform a combine.
Definition: CombinerHelper.cpp:3864
llvm::CombinerHelper::matchBitfieldExtractFromShrAnd
bool matchBitfieldExtractFromShrAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: shr (and x, n), k -> ubfx x, pos, width.
Definition: CombinerHelper.cpp:4210
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::CombinerHelper::matchUndefSelectCmp
bool matchUndefSelectCmp(MachineInstr &MI)
Return true if a G_SELECT instruction MI has an undef comparison.
Definition: CombinerHelper.cpp:2273
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
llvm::CombinerHelper::applyCombineTruncOfShl
void applyCombineTruncOfShl(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Definition: CombinerHelper.cpp:2231
llvm::CombinerHelper::applyRotateOutOfRange
void applyRotateOutOfRange(MachineInstr &MI)
Definition: CombinerHelper.cpp:3955
llvm::CombinerHelper::applyCombineConstPtrAddToI2P
void applyCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst)
Definition: CombinerHelper.cpp:2045
llvm::ShiftOfShiftedLogic::LogicNonShiftReg
Register LogicNonShiftReg
Definition: CombinerHelper.h:71
llvm::CombinerHelper::Builder
MachineIRBuilder & Builder
Definition: CombinerHelper.h:106
llvm::MergeTruncStoresInfo::LowestIdxStore
GStore * LowestIdxStore
Definition: CombinerHelper.h:79
llvm::CombinerHelper::matchICmpToLHSKnownBits
bool matchICmpToLHSKnownBits(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4023
llvm::CombinerHelper::matchCombineIndexedLoadStore
bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo)
Definition: CombinerHelper.cpp:991
llvm::CombinerHelper::matchCombineConstantFoldFpUnary
bool matchCombineConstantFoldFpUnary(MachineInstr &MI, Optional< APFloat > &Cst)
Transform fp_instr(cst) to constant result of the fp operation.
Definition: CombinerHelper.cpp:1272
llvm::CombinerHelper::matchCombineShlOfExtend
bool matchCombineShlOfExtend(MachineInstr &MI, RegisterImmPair &MatchData)
Definition: CombinerHelper.cpp:1585
llvm::CombinerHelper::matchConstantOp
bool matchConstantOp(const MachineOperand &MOP, int64_t C)
Return true if MOP is defined by a G_CONSTANT with a value equal to C.
Definition: CombinerHelper.cpp:2378
llvm::CombinerHelper::matchEqualDefs
bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2)
Return true if MOP1 and MOP2 are register operands are defined by equivalent instructions.
Definition: CombinerHelper.cpp:2294
llvm::CombinerHelper::replaceSingleDefInstWithOperand
bool replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx)
Delete MI and replace all of its uses with its OpIdx-th operand.
Definition: CombinerHelper.cpp:2387
llvm::CombinerHelper::matchCombineTruncOfExt
bool matchCombineTruncOfExt(MachineInstr &MI, std::pair< Register, unsigned > &MatchInfo)
Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
Definition: CombinerHelper.cpp:2172
llvm::CombinerHelper::matchCombineMulToShl
bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal)
Transform a multiply by a power-of-2 value to a left shift.
Definition: CombinerHelper.cpp:1560
llvm::PreferredTuple::ExtendOpcode
unsigned ExtendOpcode
Definition: CombinerHelper.h:46
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::CombinerHelper::applyCombineMulByNegativeOne
void applyCombineMulByNegativeOne(MachineInstr &MI)
Transform G_MUL(x, -1) to G_SUB(0, x)
Definition: CombinerHelper.cpp:2130
llvm::CombinerHelper::isLegalOrBeforeLegalizer
bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const
Definition: CombinerHelper.cpp:134
llvm::CombinerHelper::replaceInstWithUndef
bool replaceInstWithUndef(MachineInstr &MI)
Replace an instruction with a G_IMPLICIT_DEF.
Definition: CombinerHelper.cpp:2464
llvm::CombinerHelper::matchCombineInsertVecElts
bool matchCombineInsertVecElts(MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo)
Definition: CombinerHelper.cpp:2492
llvm::CombinerHelper::applySextTruncSextLoad
void applySextTruncSextLoad(MachineInstr &MI)
Definition: CombinerHelper.cpp:781
llvm::CombinerHelper::applyUMulHToLShr
void applyUMulHToLShr(MachineInstr &MI)
Definition: CombinerHelper.cpp:4734
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::CombinerHelper::matchAndOrDisjointMask
bool matchAndOrDisjointMask(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4066
llvm::CombinerHelper::matchReassocConstantInnerRHS
bool matchReassocConstantInnerRHS(GPtrAdd &MI, MachineInstr *RHS, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4328
llvm::IndexedLoadStoreMatchInfo::IsPre
bool IsPre
Definition: CombinerHelper.h:54
llvm::LegalityQuery
The LegalityQuery object bundles together all the information that's needed to decide whether a given...
Definition: LegalizerInfo.h:108
llvm::CombinerHelper::isPredecessor
bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI)
Returns true if DefMI precedes UseMI or they are the same instruction.
Definition: CombinerHelper.cpp:727
llvm::CombinerHelper::matchXorOfAndWithSameReg
bool matchXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Fold (xor (and x, y), y) -> (and (not x), y) {.
Definition: CombinerHelper.cpp:2949
llvm::InstructionStepsMatchInfo::InstrsToBuild
SmallVector< InstructionBuildSteps, 2 > InstrsToBuild
Describes instructions to be built during a combine.
Definition: CombinerHelper.h:97
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::CombinerHelper::matchCombineExtOfExt
bool matchCombineExtOfExt(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Transform [asz]ext([asz]ext(x)) to [asz]ext x.
Definition: CombinerHelper.cpp:2078
llvm::CombinerHelper::replaceRegOpWith
void replaceRegOpWith(MachineRegisterInfo &MRI, MachineOperand &FromRegOp, Register ToReg) const
Replace a single register operand with a new register and inform the observer of the changes.
Definition: CombinerHelper.cpp:151
llvm::CombinerHelper::matchBinOpSameVal
bool matchBinOpSameVal(MachineInstr &MI)
Optimize (x op x) -> x.
Definition: CombinerHelper.cpp:2416
llvm::CombinerHelper::matchBitfieldExtractFromAnd
bool matchBitfieldExtractFromAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: and (lshr x, cst), mask -> ubfx x, cst, width.
Definition: CombinerHelper.cpp:4125
llvm::CombinerHelper::matchOrShiftToFunnelShift
bool matchOrShiftToFunnelShift(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:3870
llvm::CombinerHelper::applyCombineConstantFoldFpUnary
void applyCombineConstantFoldFpUnary(MachineInstr &MI, Optional< APFloat > &Cst)
Definition: CombinerHelper.cpp:1281
llvm::CombinerHelper::applyCombineExtendingLoads
void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo)
Definition: CombinerHelper.cpp:547
llvm::CombinerHelper::applyAshShlToSextInreg
void applyAshShlToSextInreg(MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo)
Definition: CombinerHelper.cpp:2685
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::CombinerHelper::applyCombineInsertVecElts
void applyCombineInsertVecElts(MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo)
Definition: CombinerHelper.cpp:2533
llvm::CombinerHelper::matchSelectSameVal
bool matchSelectSameVal(MachineInstr &MI)
Optimize (cond ? x : x) -> x.
Definition: CombinerHelper.cpp:2408
llvm::CombinerHelper::matchOperandIsUndef
bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is undef.
Definition: CombinerHelper.cpp:2428
llvm::CombinerHelper::applyShiftImmedChain
void applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo)
Definition: CombinerHelper.cpp:1412
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::CombinerHelper::tryEmitMemcpyInline
bool tryEmitMemcpyInline(MachineInstr &MI)
Emit loads and stores that perform the given memcpy.
Definition: CombinerHelper.cpp:1214
llvm::CombinerHelper::matchCombineLoadWithAndMask
bool matchCombineLoadWithAndMask(MachineInstr &MI, BuildFnTy &MatchInfo)
Match (and (load x), mask) -> zextload x.
Definition: CombinerHelper.cpp:657
llvm::CombinerHelper::matchShiftOfShiftedLogic
bool matchShiftOfShiftedLogic(MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo)
If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with...
Definition: CombinerHelper.cpp:1445
llvm::CombinerHelper::matchCombineFAbsOfFAbs
bool matchCombineFAbsOfFAbs(MachineInstr &MI, Register &Src)
Match fabs(fabs(x)) to fabs(x).
Definition: CombinerHelper.cpp:2148
llvm::CombinerHelper::matchCombineAnyExtTrunc
bool matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg)
Transform anyext(trunc(x)) to x.
Definition: CombinerHelper.cpp:2055
Alignment.h
llvm::CombinerHelper::CombinerHelper
CombinerHelper(GISelChangeObserver &Observer, MachineIRBuilder &B, GISelKnownBits *KB=nullptr, MachineDominatorTree *MDT=nullptr, const LegalizerInfo *LI=nullptr)
Definition: CombinerHelper.cpp:50
llvm::CombinerHelper::matchOperandIsKnownToBeAPowerOfTwo
bool matchOperandIsKnownToBeAPowerOfTwo(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is known to be a power of 2.
Definition: CombinerHelper.cpp:2434
llvm::CombinerHelper::applyCombineUnmergeMergeToPlainValues
void applyCombineUnmergeMergeToPlainValues(MachineInstr &MI, SmallVectorImpl< Register > &Operands)
Definition: CombinerHelper.cpp:1687
llvm::CombinerHelper::matchSextInRegOfLoad
bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Match sext_inreg(load p), imm -> sextload p.
Definition: CombinerHelper.cpp:788
llvm::CombinerHelper::matchFunnelShiftToRotate
bool matchFunnelShiftToRotate(MachineInstr &MI)
Match an FSHL or FSHR that can be combined to a ROTR or ROTL rotate.
Definition: CombinerHelper.cpp:3916
llvm::PtrAddChain::Bank
const RegisterBank * Bank
Definition: CombinerHelper.h:60
llvm::CombinerHelper::matchSimplifyAddToSub
bool matchSimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo)
Return true if MI is a G_ADD which can be simplified to a G_SUB.
Definition: CombinerHelper.cpp:2472
llvm::CombinerHelper::RBI
const RegisterBankInfo * RBI
Definition: CombinerHelper.h:112
llvm::CombinerHelper::LI
const LegalizerInfo * LI
Definition: CombinerHelper.h:111
llvm::CombinerHelper::applyUDivByConst
void applyUDivByConst(MachineInstr &MI)
Definition: CombinerHelper.cpp:4713
llvm::CombinerHelper::matchShiftImmedChain
bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo)
Fold (shift (shift base, x), y) -> (shift base (x+y))
Definition: CombinerHelper.cpp:1367
llvm::CombinerHelper::applyXorOfAndWithSameReg
void applyXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Definition: CombinerHelper.cpp:2980
llvm::CombinerHelper::applyCombineAddP2IToPtrAdd
void applyCombineAddP2IToPtrAdd(MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute)
Definition: CombinerHelper.cpp:2008
llvm::PreferredTuple::MI
MachineInstr * MI
Definition: CombinerHelper.h:47
llvm::RegisterImmPair::Reg
Register Reg
Definition: CombinerHelper.h:64
llvm::IndexedLoadStoreMatchInfo
Definition: CombinerHelper.h:50
llvm::CombinerHelper::matchExtendThroughPhis
bool matchExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI)
Definition: CombinerHelper.cpp:3648
llvm::CombinerHelper::matchCombineShiftToUnmerge
bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize, unsigned &ShiftVal)
Reduce a shift by a constant to an unmerge and a shift on a half sized type.
Definition: CombinerHelper.cpp:1843
llvm::CombinerHelper::getRegBank
const RegisterBank * getRegBank(Register Reg) const
Get the register bank of Reg.
Definition: CombinerHelper.cpp:171
llvm::CombinerHelper::applyCombineCopy
void applyCombineCopy(MachineInstr &MI)
Definition: CombinerHelper.cpp:194
llvm::CombinerHelper::tryCombine
bool tryCombine(MachineInstr &MI)
Try to transform MI by using all of the above combine functions.
Definition: CombinerHelper.cpp:5353
llvm::InstructionBuildSteps::InstructionBuildSteps
InstructionBuildSteps()=default
Operands to be added to the instruction.
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::CombinerHelper::applyCombineDivRem
void applyCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI)
Definition: CombinerHelper.cpp:1116
llvm::CombinerHelper::replaceInstWithConstant
bool replaceInstWithConstant(MachineInstr &MI, int64_t C)
Replace an instruction with a G_CONSTANT with value C.
Definition: CombinerHelper.cpp:2448
llvm::CombinerHelper::matchCombineUnmergeMergeToPlainValues
bool matchCombineUnmergeMergeToPlainValues(MachineInstr &MI, SmallVectorImpl< Register > &Operands)
Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
Definition: CombinerHelper.cpp:1663
llvm::CombinerHelper::applyCombineP2IToI2P
void applyCombineP2IToI2P(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:1975
llvm::ShiftOfShiftedLogic::ValSum
uint64_t ValSum
Definition: CombinerHelper.h:72
llvm::CombinerHelper::applyExtractAllEltsFromBuildVector
void applyExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * >> &MatchInfo)
Definition: CombinerHelper.cpp:3845
llvm::CombinerHelper::applyShiftOfShiftedLogic
void applyShiftOfShiftedLogic(MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo)
Definition: CombinerHelper.cpp:1526
llvm::CombinerHelper::matchOperandIsZero
bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is zero.
Definition: CombinerHelper.cpp:2422
llvm::PreferredTuple
Definition: CombinerHelper.h:44
llvm::CombinerHelper::matchCombineExtendingLoads
bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo)
Definition: CombinerHelper.cpp:472
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMA
bool matchCombineFAddFpExtFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z) (fadd (fpext (fmul x,...
Definition: CombinerHelper.cpp:4894
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1143
llvm::CombinerHelper::matchMulOBy2
bool matchMulOBy2(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: (G_UMULO x, 2) -> (G_UADDO x, x) (G_SMULO x, 2) -> (G_SADDO x, x)
Definition: CombinerHelper.cpp:4544
llvm::CombinerHelper::applySextInRegOfLoad
void applySextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Definition: CombinerHelper.cpp:829
Register.h
llvm::CombinerHelper::matchAllExplicitUsesAreUndef
bool matchAllExplicitUsesAreUndef(MachineInstr &MI)
Return true if all register explicit use operands on MI are defined by a G_IMPLICIT_DEF.
Definition: CombinerHelper.cpp:2254
llvm::CombinerHelper::replaceSingleDefInstWithReg
bool replaceSingleDefInstWithReg(MachineInstr &MI, Register Replacement)
Delete MI and replace all of its uses with Replacement.
Definition: CombinerHelper.cpp:2398
llvm::CombinerHelper::matchExtractAllEltsFromBuildVector
bool matchExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * >> &MatchInfo)
Definition: CombinerHelper.cpp:3803
llvm::ShiftOfShiftedLogic::Logic
MachineInstr * Logic
Definition: CombinerHelper.h:69
llvm::CombinerHelper::applyCombineIndexedLoadStore
void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo)
Definition: CombinerHelper.cpp:1012
llvm::CombinerHelper::matchRedundantOr
bool matchRedundantOr(MachineInstr &MI, Register &Replacement)
Definition: CombinerHelper.cpp:2779
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:46
llvm::CombinerHelper::applyCombineAnyExtTrunc
void applyCombineAnyExtTrunc(MachineInstr &MI, Register &Reg)
llvm::CombinerHelper::matchCombineTruncOfShl
bool matchCombineTruncOfShl(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Transform trunc (shl x, K) to shl (trunc x), K => K < VT.getScalarSizeInBits().
Definition: CombinerHelper.cpp:2207
llvm::CombinerHelper::applyCombineMulToShl
void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal)
Definition: CombinerHelper.cpp:1572
llvm::CombinerHelper::matchOptBrCondByInvertingCond
bool matchOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond)
If a brcond's true block is not the fallthrough, make it so by inverting the condition and swapping o...
Definition: CombinerHelper.cpp:1148
llvm::CombinerHelper::applyCombineShlOfExtend
void applyCombineShlOfExtend(MachineInstr &MI, const RegisterImmPair &MatchData)
Definition: CombinerHelper.cpp:1622
llvm::CombinerHelper::matchRedundantNegOperands
bool matchRedundantNegOperands(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd x, fneg(y)) -> (fsub x, y) (fadd fneg(x), y) -> (fsub y, x) (fsub x,...
Definition: CombinerHelper.cpp:4751
llvm::CombinerHelper::applyCombineUnmergeWithDeadLanesToTrunc
void applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI)
Definition: CombinerHelper.cpp:1762
llvm::CombinerHelper::matchExtractVecEltBuildVec
bool matchExtractVecEltBuildVec(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:3748
llvm::CombinerHelper::canCombineFMadOrFMA
bool canCombineFMadOrFMA(MachineInstr &MI, bool &AllowFusionGlobally, bool &HasFMAD, bool &Aggressive, bool CanReassociate=false)
Definition: CombinerHelper.cpp:4813
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::CombinerHelper::matchCombineFSubFpExtFMulToFMadOrFMA
bool matchCombineFSubFpExtFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), (fneg z)) (fsub (fpext (fmul x,...
Definition: CombinerHelper.cpp:5243
llvm::CombinerHelper::matchUDivByConst
bool matchUDivByConst(MachineInstr &MI)
Combine G_UDIV by constant into a multiply by magic constant.
Definition: CombinerHelper.cpp:4670
llvm::CombinerHelper::replaceRegWith
void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const
MachineRegisterInfo::replaceRegWith() and inform the observer of the changes.
Definition: CombinerHelper.cpp:139
llvm::CombinerHelper::matchCombineFSubFNegFMulToFMadOrFMA
bool matchCombineFSubFNegFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) (fsub (fneg (fmul,...
Definition: CombinerHelper.cpp:5196
llvm::CombinerHelper::replaceInstWithFConstant
bool replaceInstWithFConstant(MachineInstr &MI, double C)
Replace an instruction with a G_FCONSTANT with value C.
Definition: CombinerHelper.cpp:2440
llvm::CombinerHelper::matchCombineFAbsOfFNeg
bool matchCombineFAbsOfFNeg(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform fabs(fneg(x)) to fabs(x).
Definition: CombinerHelper.cpp:2155
llvm::CombinerHelper::applyCombineShuffleVector
void applyCombineShuffleVector(MachineInstr &MI, const ArrayRef< Register > Ops)
Replace MI with a concat_vectors with Ops.
Definition: CombinerHelper.cpp:363
llvm::LLT
Definition: LowLevelTypeImpl.h:39