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17 #ifndef LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
18 #define LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
28 class GISelChangeObserver;
34 class MachineIRBuilder;
35 class MachineInstrBuilder;
36 class MachineRegisterInfo;
40 class MachineDominatorTree;
44 class RegisterBankInfo;
46 class TargetRegisterInfo;
370 std::pair<Register, bool> &PtrRegAndCommute);
372 std::pair<Register, bool> &PtrRegAndCommute);
387 std::tuple<Register, unsigned> &MatchInfo);
389 std::tuple<Register, unsigned> &MatchInfo);
403 std::pair<Register, unsigned> &MatchInfo);
405 std::pair<Register, unsigned> &MatchInfo);
410 std::pair<Register, Register> &MatchInfo);
412 std::pair<Register, Register> &MatchInfo);
484 std::tuple<Register, Register> &MatchInfo);
486 std::tuple<Register, Register> &MatchInfo);
499 std::tuple<Register, int64_t> &MatchInfo);
501 std::tuple<Register, int64_t> &MatchInfo);
534 std::pair<Register, Register> &MatchInfo);
536 std::pair<Register, Register> &MatchInfo);
688 bool CanReassociate =
false);
765 findCandidatesForLoadOrCombine(
const MachineInstr *Root)
const;
779 findLoadOffsetsForLoadOrCombine(
782 const unsigned MemSizeInBits);
787 bool reassociationCanBreakAddressingModePattern(
MachineInstr &PtrAdd);
bool matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI)
Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
bool matchFoldBinOpIntoSelect(MachineInstr &MI, unsigned &SelectOpNo)
Push a binary operator through a select on constants.
bool matchConstantFold(MachineInstr &MI, APInt &MatchInfo)
Do constant folding when opportunities are exposed after MIR building.
void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal)
This is an optimization pass for GlobalISel generic memory operations.
void applyExtractVecEltBuildVec(MachineInstr &MI, Register &Reg)
MachineInstrBuilder & UseMI
bool matchCombineUnmergeConstant(MachineInstr &MI, SmallVectorImpl< APInt > &Csts)
Transform G_UNMERGE Constant -> Constant1, Constant2, ...
MachineRegisterInfo & MRI
void applyOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond)
bool matchHoistLogicOpWithSameOpcodeHands(MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo)
Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void applyCombineI2PToP2I(MachineInstr &MI, Register &Reg)
bool eraseInst(MachineInstr &MI)
Erase MI.
GISelKnownBits * getKnownBits() const
bool matchCombineP2IToI2P(MachineInstr &MI, Register &Reg)
Transform PtrToInt(IntToPtr(x)) to x.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
const TargetLowering & getTargetLowering() const
InstructionBuildSteps(unsigned Opcode, const OperandBuildSteps &OperandFns)
bool matchCombineFSubFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fmul x, y), z) -> (fma x, y, -z) (fsub (fmul x, y), z) -> (fmad x,...
bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen=0)
Optimize memcpy intrinsics et al, e.g.
bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI)
Returns true if DefMI dominates UseMI.
bool matchCombineFAddFMAFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y, (fma u, v, z)) (fadd (fmad x,...
Reg
All possible values of the reg field in the ModR/M byte.
bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx)
Return true if a G_SELECT instruction MI has a constant comparison.
void applyFunnelShiftToRotate(MachineInstr &MI)
bool matchCombineFSubFpExtFNegFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fpext (fneg (fmul x, y))), z) -> (fneg (fma (fpext x), (fpext y),...
void applyBuildFn(MachineInstr &MI, BuildFnTy &MatchInfo)
Use a function which takes in a MachineIRBuilder to perform a combine.
bool tryCombineShuffleVector(MachineInstr &MI)
Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void replaceOpcodeWith(MachineInstr &FromMI, unsigned ToOpcode) const
Replace the opcode in instruction with a new opcode and inform the observer of the changes.
bool matchCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI)
Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM when their source operands are iden...
bool tryCombineIndexedLoadStore(MachineInstr &MI)
Combine MI into a pre-indexed or post-indexed load/store operation if legal and the surrounding code ...
bool matchNarrowBinopFeedingAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
SmallVector< GStore * > FoundStores
void applyCombineExtOfExt(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount)
bool matchSextTruncSextLoad(MachineInstr &MI)
static cl::opt< bool > Aggressive("aggressive-ext-opt", cl::Hidden, cl::desc("Aggressive extension optimization"))
bool matchPtrAddZero(MachineInstr &MI)
}
bool tryCombineExtendingLoads(MachineInstr &MI)
If MI is extend that consumes the result of a load, try to combine it.
bool matchPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo)
bool matchRotateOutOfRange(MachineInstr &MI)
bool matchNotCmp(MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate)
Combine inverting a result of a compare into the opposite cond code.
void applyCombineTruncOfExt(MachineInstr &MI, std::pair< Register, unsigned > &MatchInfo)
bool isConstantLegalOrBeforeLegalizer(const LLT Ty) const
void applyNotCmp(MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate)
bool matchCombineCopy(MachineInstr &MI)
bool matchCombineAddP2IToPtrAdd(MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute)
Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y) Transform G_ADD y,...
bool matchAshrShlToSextInreg(MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo)
Match ashr (shl x, C), C -> sext_inreg (C)
void applyTruncStoreMerge(MachineInstr &MI, MergeTruncStoresInfo &MatchInfo)
void applyPtrAddZero(MachineInstr &MI)
std::function< void(MachineIRBuilder &)> BuildFnTy
OperandBuildSteps OperandFns
The opcode for the produced instruction.
void setRegBank(Register Reg, const RegisterBank *RegBank)
Set the register bank of Reg.
bool matchReassocPtrAdd(MachineInstr &MI, BuildFnTy &MatchInfo)
Reassociate pointer calculations with G_ADD involved, to allow better addressing mode usage.
This class implements the register bank concept.
bool matchCombineUnmergeUndef(MachineInstr &MI, std::function< void(MachineIRBuilder &)> &MatchInfo)
Transform G_UNMERGE G_IMPLICIT_DEF -> G_IMPLICIT_DEF, G_IMPLICIT_DEF, ...
MachineDominatorTree * MDT
MachineInstr * buildUDivUsingMul(MachineInstr &MI)
Given an G_UDIV MI expressing a divide by constant, return an expression that implements it by multip...
bool matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef, SmallVectorImpl< Register > &Ops)
Check if the G_CONCAT_VECTORS MI is undef or if it can be flattened into a build_vector.
bool matchRedundantSExtInReg(MachineInstr &MI)
bool matchCombineZextTrunc(MachineInstr &MI, Register &Reg)
Transform zext(trunc(x)) to x.
(vector float) vec_cmpeq(*A, *B) C
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool matchReassocFoldConstantsInSubTree(GPtrAdd &MI, MachineInstr *LHS, MachineInstr *RHS, BuildFnTy &MatchInfo)
InstructionStepsMatchInfo(std::initializer_list< InstructionBuildSteps > InstrsToBuild)
void applySimplifyURemByPow2(MachineInstr &MI)
Combine G_UREM x, (known power of 2) to an add and bitmasking.
bool matchLoadOrCombine(MachineInstr &MI, BuildFnTy &MatchInfo)
Match expression trees of the form.
bool matchCombineFAddFpExtFMulToFMadOrFMAAggressive(MachineInstr &MI, BuildFnTy &MatchInfo)
bool matchAnyExplicitUseIsUndef(MachineInstr &MI)
Return true if any explicit use operand on MI is defined by a G_IMPLICIT_DEF.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineOperand class - Representation of each machine instruction operand.
void applyCombineUnmergeZExtToZExt(MachineInstr &MI)
void applyExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI)
bool matchCombineI2PToP2I(MachineInstr &MI, Register &Reg)
Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
bool isPreLegalize() const
bool matchCombineFNegOfFNeg(MachineInstr &MI, Register &Reg)
Transform fneg(fneg(x)) to x.
const TargetRegisterInfo * TRI
bool matchAddOBy0(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: (G_*ADDO x, 0) -> x + no carry out.
Analysis containing CSE Info
void applyCombineUnmergeConstant(MachineInstr &MI, SmallVectorImpl< APInt > &Csts)
bool matchCombineFAddFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd (fmul x, y), z) -> (fma x, y, z) (fadd (fmul x, y), z) -> (fmad x,...
void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef, const ArrayRef< Register > Ops)
Replace MI with a flattened build_vector with Ops or an implicit_def if IsUndef is true.
bool matchCombineShuffleVector(MachineInstr &MI, SmallVectorImpl< Register > &Ops)
Check if the G_SHUFFLE_VECTOR MI can be replaced by a concat_vectors.
bool isLegal(const LegalityQuery &Query) const
bool tryCombineCopy(MachineInstr &MI)
If MI is COPY, try to combine it.
GISelChangeObserver & Observer
bool matchCombineUnmergeZExtToZExt(MachineInstr &MI)
Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0.
bool matchUndefShuffleVectorMask(MachineInstr &MI)
Return true if a G_SHUFFLE_VECTOR instruction MI has an undef mask.
bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo)
void applyCombineFAbsOfFAbs(MachineInstr &MI, Register &Src)
bool matchCombineMergeUnmerge(MachineInstr &MI, Register &MatchInfo)
Fold away a merge of an unmerge of the corresponding values.
mir Rename Register Operands
bool matchAddSubSameReg(MachineInstr &MI, Register &Src)
Transform G_ADD(x, G_SUB(y, x)) to y.
InstructionStepsMatchInfo()=default
void applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo)
bool matchOverlappingAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0.
void applyBuildInstructionSteps(MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo)
Replace MI with a series of instructions described in MatchInfo.
bool matchRedundantAnd(MachineInstr &MI, Register &Replacement)
void applySimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo)
bool matchTruncStoreMerge(MachineInstr &MI, MergeTruncStoresInfo &MatchInfo)
Match a pattern where a wide type scalar value is stored by several narrow stores.
bool matchBitfieldExtractFromShr(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width.
bool tryCombineConcatVectors(MachineInstr &MI)
If MI is G_CONCAT_VECTORS, try to combine it.
Holds all the information related to register banks.
bool matchUndefStore(MachineInstr &MI)
Return true if a G_STORE instruction MI is storing an undef value.
Helper class to build MachineInstr.
bool matchReassocConstantInnerLHS(GPtrAdd &MI, MachineInstr *LHS, MachineInstr *RHS, BuildFnTy &MatchInfo)
bool matchBitfieldExtractFromSExtInReg(MachineInstr &MI, BuildFnTy &MatchInfo)
Form a G_SBFX from a G_SEXT_INREG fed by a right shift.
bool matchUMulHToLShr(MachineInstr &MI)
void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo)
Use a function which takes in a MachineIRBuilder to perform a combine.
bool matchBitfieldExtractFromShrAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: shr (and x, n), k -> ubfx x, pos, width.
Representation of each machine instruction.
bool matchUndefSelectCmp(MachineInstr &MI)
Return true if a G_SELECT instruction MI has an undef comparison.
bool matchSelectToLogical(MachineInstr &MI, BuildFnTy &MatchInfo)
Fold boolean selects to logical operations.
bool matchCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst)
void applyCombineTruncOfShl(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
void applyRotateOutOfRange(MachineInstr &MI)
Register LogicNonShiftReg
MachineIRBuilder & Builder
bool matchICmpToLHSKnownBits(MachineInstr &MI, BuildFnTy &MatchInfo)
bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo)
bool matchCombineConstantFoldFpUnary(MachineInstr &MI, Optional< APFloat > &Cst)
Transform fp_instr(cst) to constant result of the fp operation.
bool matchCombineShlOfExtend(MachineInstr &MI, RegisterImmPair &MatchData)
bool matchConstantOp(const MachineOperand &MOP, int64_t C)
Return true if MOP is defined by a G_CONSTANT with a value equal to C.
bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2)
Return true if MOP1 and MOP2 are register operands are defined by equivalent instructions.
bool replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx)
Delete MI and replace all of its uses with its OpIdx-th operand.
bool matchCombineTruncOfExt(MachineInstr &MI, std::pair< Register, unsigned > &MatchInfo)
Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal)
Transform a multiply by a power-of-2 value to a left shift.
print Print MemDeps of function
void applyCombineMulByNegativeOne(MachineInstr &MI)
Transform G_MUL(x, -1) to G_SUB(0, x)
bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const
bool replaceInstWithUndef(MachineInstr &MI)
Replace an instruction with a G_IMPLICIT_DEF.
bool matchCombineInsertVecElts(MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo)
void applySextTruncSextLoad(MachineInstr &MI)
void applyUMulHToLShr(MachineInstr &MI)
Class for arbitrary precision integers.
bool matchAndOrDisjointMask(MachineInstr &MI, BuildFnTy &MatchInfo)
bool matchReassocConstantInnerRHS(GPtrAdd &MI, MachineInstr *RHS, BuildFnTy &MatchInfo)
The LegalityQuery object bundles together all the information that's needed to decide whether a given...
bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI)
Returns true if DefMI precedes UseMI or they are the same instruction.
bool matchXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Fold (xor (and x, y), y) -> (and (not x), y) {.
SmallVector< InstructionBuildSteps, 2 > InstrsToBuild
Describes instructions to be built during a combine.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool matchCombineExtOfExt(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Transform [asz]ext([asz]ext(x)) to [asz]ext x.
void replaceRegOpWith(MachineRegisterInfo &MRI, MachineOperand &FromRegOp, Register ToReg) const
Replace a single register operand with a new register and inform the observer of the changes.
bool matchBinOpSameVal(MachineInstr &MI)
Optimize (x op x) -> x.
bool matchBitfieldExtractFromAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: and (lshr x, cst), mask -> ubfx x, cst, width.
bool matchOrShiftToFunnelShift(MachineInstr &MI, BuildFnTy &MatchInfo)
void applyCombineConstantFoldFpUnary(MachineInstr &MI, Optional< APFloat > &Cst)
void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo)
void applyAshShlToSextInreg(MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo)
Abstract class that contains various methods for clients to notify about changes.
void applyCombineInsertVecElts(MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo)
bool matchSelectSameVal(MachineInstr &MI)
Optimize (cond ? x : x) -> x.
bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is undef.
void applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo)
Wrapper class representing virtual and physical registers.
bool tryEmitMemcpyInline(MachineInstr &MI)
Emit loads and stores that perform the given memcpy.
bool matchCombineLoadWithAndMask(MachineInstr &MI, BuildFnTy &MatchInfo)
Match (and (load x), mask) -> zextload x.
bool matchShiftOfShiftedLogic(MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo)
If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with...
bool matchCombineFAbsOfFAbs(MachineInstr &MI, Register &Src)
Match fabs(fabs(x)) to fabs(x).
bool matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg)
Transform anyext(trunc(x)) to x.
bool matchMulOBy0(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: (G_*MULO x, 0) -> 0 + no carry out.
CombinerHelper(GISelChangeObserver &Observer, MachineIRBuilder &B, GISelKnownBits *KB=nullptr, MachineDominatorTree *MDT=nullptr, const LegalizerInfo *LI=nullptr)
bool matchOperandIsKnownToBeAPowerOfTwo(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is known to be a power of 2.
bool matchCombineFMinMaxNaN(MachineInstr &MI, unsigned &Info)
void applyCombineUnmergeMergeToPlainValues(MachineInstr &MI, SmallVectorImpl< Register > &Operands)
bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Match sext_inreg(load p), imm -> sextload p.
bool matchFunnelShiftToRotate(MachineInstr &MI)
Match an FSHL or FSHR that can be combined to a ROTR or ROTL rotate.
const RegisterBank * Bank
bool matchSimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo)
Return true if MI is a G_ADD which can be simplified to a G_SUB.
const RegisterBankInfo * RBI
void applyUDivByConst(MachineInstr &MI)
bool applyFoldBinOpIntoSelect(MachineInstr &MI, const unsigned &SelectOpNo)
SelectOperand is the operand in binary operator MI that is the select to fold.
bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo)
Fold (shift (shift base, x), y) -> (shift base (x+y))
void applyXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
void applyCombineAddP2IToPtrAdd(MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute)
void applyCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst)
bool matchExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI)
bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize, unsigned &ShiftVal)
Reduce a shift by a constant to an unmerge and a shift on a half sized type.
const RegisterBank * getRegBank(Register Reg) const
Get the register bank of Reg.
void applyCombineCopy(MachineInstr &MI)
bool tryCombine(MachineInstr &MI)
Try to transform MI by using all of the above combine functions.
InstructionBuildSteps()=default
Operands to be added to the instruction.
MachineInstrBuilder MachineInstrBuilder & DefMI
void applyCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI)
bool replaceInstWithConstant(MachineInstr &MI, int64_t C)
Replace an instruction with a G_CONSTANT with value C.
bool matchCombineUnmergeMergeToPlainValues(MachineInstr &MI, SmallVectorImpl< Register > &Operands)
Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
void applyCombineP2IToI2P(MachineInstr &MI, Register &Reg)
void applyExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * >> &MatchInfo)
void applyShiftOfShiftedLogic(MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo)
bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is zero.
bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool matchCombineFAddFpExtFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z) (fadd (fpext (fmul x,...
bool matchMulOBy2(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: (G_UMULO x, 2) -> (G_UADDO x, x) (G_SMULO x, 2) -> (G_SADDO x, x)
void applySextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
bool matchAllExplicitUsesAreUndef(MachineInstr &MI)
Return true if all register explicit use operands on MI are defined by a G_IMPLICIT_DEF.
bool replaceSingleDefInstWithReg(MachineInstr &MI, Register Replacement)
Delete MI and replace all of its uses with Replacement.
bool matchExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * >> &MatchInfo)
void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo)
bool matchRedundantOr(MachineInstr &MI, Register &Replacement)
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
void applyCombineAnyExtTrunc(MachineInstr &MI, Register &Reg)
bool matchCombineTruncOfShl(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Transform trunc (shl x, K) to shl (trunc x), K => K < VT.getScalarSizeInBits().
void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal)
bool matchOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond)
If a brcond's true block is not the fallthrough, make it so by inverting the condition and swapping o...
void applyCombineShlOfExtend(MachineInstr &MI, const RegisterImmPair &MatchData)
bool matchRedundantNegOperands(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd x, fneg(y)) -> (fsub x, y) (fadd fneg(x), y) -> (fsub y, x) (fsub x,...
void applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI)
bool matchExtractVecEltBuildVec(MachineInstr &MI, Register &Reg)
bool canCombineFMadOrFMA(MachineInstr &MI, bool &AllowFusionGlobally, bool &HasFMAD, bool &Aggressive, bool CanReassociate=false)
bool matchCombineFSubFpExtFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), (fneg z)) (fsub (fpext (fmul x,...
bool matchUDivByConst(MachineInstr &MI)
Combine G_UDIV by constant into a multiply by magic constant.
void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const
MachineRegisterInfo::replaceRegWith() and inform the observer of the changes.
bool matchCombineFSubFNegFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) (fsub (fneg (fmul,...
bool replaceInstWithFConstant(MachineInstr &MI, double C)
Replace an instruction with a G_FCONSTANT with value C.
bool matchCombineFAbsOfFNeg(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform fabs(fneg(x)) to fabs(x).
void applyCombineShuffleVector(MachineInstr &MI, const ArrayRef< Register > Ops)
Replace MI with a concat_vectors with Ops.