LLVM  16.0.0git
CombinerHelper.h
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1 //===-- llvm/CodeGen/GlobalISel/CombinerHelper.h --------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===--------------------------------------------------------------------===//
8 /// \file
9 /// This contains common combine transformations that may be used in a combine
10 /// pass,or by the target elsewhere.
11 /// Targets can pick individual opcode transformations from the helper or use
12 /// tryCombine which invokes all transformations. All of the transformations
13 /// return true if the MachineInstruction changed and false otherwise.
14 ///
15 //===--------------------------------------------------------------------===//
16 
17 #ifndef LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
18 #define LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
19 
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/CodeGen/Register.h"
24 #include "llvm/IR/InstrTypes.h"
25 #include <functional>
26 
27 namespace llvm {
28 
29 class GISelChangeObserver;
30 class APFloat;
31 class APInt;
32 class GPtrAdd;
33 class GStore;
34 class GZExtLoad;
35 class MachineIRBuilder;
36 class MachineInstrBuilder;
37 class MachineRegisterInfo;
38 class MachineInstr;
39 class MachineOperand;
40 class GISelKnownBits;
41 class MachineDominatorTree;
42 class LegalizerInfo;
43 struct LegalityQuery;
44 class RegisterBank;
45 class RegisterBankInfo;
46 class TargetLowering;
47 class TargetRegisterInfo;
48 
50  LLT Ty; // The result type of the extend.
51  unsigned ExtendOpcode; // G_ANYEXT/G_SEXT/G_ZEXT
53 };
54 
59  bool IsPre;
60 };
61 
62 struct PtrAddChain {
63  int64_t Imm;
66 };
67 
70  int64_t Imm;
71 };
72 
78 };
79 
81 
84  GStore *LowestIdxStore = nullptr;
86  bool NeedBSwap = false;
87  bool NeedRotate = false;
88 };
89 
90 using OperandBuildSteps =
93  unsigned Opcode = 0; /// The opcode for the produced instruction.
94  OperandBuildSteps OperandFns; /// Operands to be added to the instruction.
95  InstructionBuildSteps() = default;
98 };
99 
101  /// Describes instructions to be built during a combine.
103  InstructionStepsMatchInfo() = default;
105  std::initializer_list<InstructionBuildSteps> InstrsToBuild)
107 };
108 
110 protected:
120 
121 public:
123  bool IsPreLegalize,
124  GISelKnownBits *KB = nullptr,
125  MachineDominatorTree *MDT = nullptr,
126  const LegalizerInfo *LI = nullptr);
127 
129  return KB;
130  }
131 
133  return Builder;
134  }
135 
136  const TargetLowering &getTargetLowering() const;
137 
138  /// \returns true if the combiner is running pre-legalization.
139  bool isPreLegalize() const;
140 
141  /// \returns true if \p Query is legal on the target.
142  bool isLegal(const LegalityQuery &Query) const;
143 
144  /// \return true if the combine is running prior to legalization, or if \p
145  /// Query is legal on the target.
146  bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const;
147 
148  /// \return true if the combine is running prior to legalization, or if \p Ty
149  /// is a legal integer constant type on the target.
150  bool isConstantLegalOrBeforeLegalizer(const LLT Ty) const;
151 
152  /// MachineRegisterInfo::replaceRegWith() and inform the observer of the changes
153  void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const;
154 
155  /// Replace a single register operand with a new register and inform the
156  /// observer of the changes.
158  Register ToReg) const;
159 
160  /// Replace the opcode in instruction with a new opcode and inform the
161  /// observer of the changes.
162  void replaceOpcodeWith(MachineInstr &FromMI, unsigned ToOpcode) const;
163 
164  /// Get the register bank of \p Reg.
165  /// If Reg has not been assigned a register, a register class,
166  /// or a register bank, then this returns nullptr.
167  ///
168  /// \pre Reg.isValid()
169  const RegisterBank *getRegBank(Register Reg) const;
170 
171  /// Set the register bank of \p Reg.
172  /// Does nothing if the RegBank is null.
173  /// This is the counterpart to getRegBank.
174  void setRegBank(Register Reg, const RegisterBank *RegBank);
175 
176  /// If \p MI is COPY, try to combine it.
177  /// Returns true if MI changed.
181 
182  /// Returns true if \p DefMI precedes \p UseMI or they are the same
183  /// instruction. Both must be in the same basic block.
184  bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI);
185 
186  /// Returns true if \p DefMI dominates \p UseMI. By definition an
187  /// instruction dominates itself.
188  ///
189  /// If we haven't been provided with a MachineDominatorTree during
190  /// construction, this function returns a conservative result that tracks just
191  /// a single basic block.
192  bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI);
193 
194  /// If \p MI is extend that consumes the result of a load, try to combine it.
195  /// Returns true if MI changed.
199 
200  /// Match (and (load x), mask) -> zextload x
202 
203  /// Combine \p MI into a pre-indexed or post-indexed load/store operation if
204  /// legal and the surrounding code makes it useful.
208 
211 
212  /// Match sext_inreg(load p), imm -> sextload p
213  bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
214  void applySextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
215 
216  /// Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM
217  /// when their source operands are identical.
220 
221  /// If a brcond's true block is not the fallthrough, make it so by inverting
222  /// the condition and swapping operands.
225 
226  /// If \p MI is G_CONCAT_VECTORS, try to combine it.
227  /// Returns true if MI changed.
228  /// Right now, we support:
229  /// - concat_vector(undef, undef) => undef
230  /// - concat_vector(build_vector(A, B), build_vector(C, D)) =>
231  /// build_vector(A, B, C, D)
232  ///
233  /// \pre MI.getOpcode() == G_CONCAT_VECTORS.
235  /// Check if the G_CONCAT_VECTORS \p MI is undef or if it
236  /// can be flattened into a build_vector.
237  /// In the first case \p IsUndef will be true.
238  /// In the second case \p Ops will contain the operands needed
239  /// to produce the flattened build_vector.
240  ///
241  /// \pre MI.getOpcode() == G_CONCAT_VECTORS.
242  bool matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef,
244  /// Replace \p MI with a flattened build_vector with \p Ops or an
245  /// implicit_def if IsUndef is true.
246  void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef,
247  const ArrayRef<Register> Ops);
248 
249  /// Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
250  /// Returns true if MI changed.
251  ///
252  /// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
254  /// Check if the G_SHUFFLE_VECTOR \p MI can be replaced by a
255  /// concat_vectors.
256  /// \p Ops will contain the operands needed to produce the flattened
257  /// concat_vectors.
258  ///
259  /// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
262  /// Replace \p MI with a concat_vectors with \p Ops.
264  const ArrayRef<Register> Ops);
265 
266  /// Optimize memcpy intrinsics et al, e.g. constant len calls.
267  /// /p MaxLen if non-zero specifies the max length of a mem libcall to inline.
268  ///
269  /// For example (pre-indexed):
270  ///
271  /// $addr = G_PTR_ADD $base, $offset
272  /// [...]
273  /// $val = G_LOAD $addr
274  /// [...]
275  /// $whatever = COPY $addr
276  ///
277  /// -->
278  ///
279  /// $val, $addr = G_INDEXED_LOAD $base, $offset, 1 (IsPre)
280  /// [...]
281  /// $whatever = COPY $addr
282  ///
283  /// or (post-indexed):
284  ///
285  /// G_STORE $val, $base
286  /// [...]
287  /// $addr = G_PTR_ADD $base, $offset
288  /// [...]
289  /// $whatever = COPY $addr
290  ///
291  /// -->
292  ///
293  /// $addr = G_INDEXED_STORE $val, $base, $offset
294  /// [...]
295  /// $whatever = COPY $addr
296  bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
297 
300 
301  /// Fold (shift (shift base, x), y) -> (shift base (x+y))
304 
305  /// If we have a shift-by-constant of a bitwise logic op that itself has a
306  /// shift-by-constant operand with identical opcode, we may be able to convert
307  /// that into 2 independent shifts followed by the logic op.
309  ShiftOfShiftedLogic &MatchInfo);
311  ShiftOfShiftedLogic &MatchInfo);
312 
313  /// Transform a multiply by a power-of-2 value to a left shift.
314  bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
315  void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
316 
317  // Transform a G_SHL with an extended source into a narrower shift if
318  // possible.
321  const RegisterImmPair &MatchData);
322 
323  /// Fold away a merge of an unmerge of the corresponding values.
325 
326  /// Reduce a shift by a constant to an unmerge and a shift on a half sized
327  /// type. This will not produce a shift smaller than \p TargetShiftSize.
328  bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize,
329  unsigned &ShiftVal);
330  void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal);
331  bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount);
332 
333  /// Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
334  bool
337  void
340 
341  /// Transform G_UNMERGE Constant -> Constant1, Constant2, ...
343  SmallVectorImpl<APInt> &Csts);
345  SmallVectorImpl<APInt> &Csts);
346 
347  /// Transform G_UNMERGE G_IMPLICIT_DEF -> G_IMPLICIT_DEF, G_IMPLICIT_DEF, ...
348  bool
350  std::function<void(MachineIRBuilder &)> &MatchInfo);
351 
352  /// Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
355 
356  /// Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0
359 
360  /// Transform fp_instr(cst) to constant result of the fp operation.
362  Optional<APFloat> &Cst);
364  Optional<APFloat> &Cst);
365 
366  /// Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
369 
370  /// Transform PtrToInt(IntToPtr(x)) to x.
372 
373  /// Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y)
374  /// Transform G_ADD y, (G_PTRTOINT x) -> G_PTRTOINT (G_PTR_ADD x, y)
376  std::pair<Register, bool> &PtrRegAndCommute);
378  std::pair<Register, bool> &PtrRegAndCommute);
379 
380  // Transform G_PTR_ADD (G_PTRTOINT C1), C2 -> C1 + C2
383 
384  /// Transform anyext(trunc(x)) to x.
387 
388  /// Transform zext(trunc(x)) to x.
390 
391  /// Transform [asz]ext([asz]ext(x)) to [asz]ext x.
393  std::tuple<Register, unsigned> &MatchInfo);
395  std::tuple<Register, unsigned> &MatchInfo);
396 
397  /// Transform fabs(fabs(x)) to fabs(x).
399 
400  /// Transform fabs(fneg(x)) to fabs(x).
401  bool matchCombineFAbsOfFNeg(MachineInstr &MI, BuildFnTy &MatchInfo);
402 
403  /// Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
405  std::pair<Register, unsigned> &MatchInfo);
407  std::pair<Register, unsigned> &MatchInfo);
408 
409  /// Transform trunc (shl x, K) to shl (trunc x),
410  /// K => K < VT.getScalarSizeInBits().
412  std::pair<Register, Register> &MatchInfo);
414  std::pair<Register, Register> &MatchInfo);
415 
416  /// Transform G_MUL(x, -1) to G_SUB(0, x)
418 
419  /// Return true if any explicit use operand on \p MI is defined by a
420  /// G_IMPLICIT_DEF.
422 
423  /// Return true if all register explicit use operands on \p MI are defined by
424  /// a G_IMPLICIT_DEF.
426 
427  /// Return true if a G_SHUFFLE_VECTOR instruction \p MI has an undef mask.
429 
430  /// Return true if a G_STORE instruction \p MI is storing an undef value.
432 
433  /// Return true if a G_SELECT instruction \p MI has an undef comparison.
435 
436  /// Return true if a G_{EXTRACT,INSERT}_VECTOR_ELT has an out of range index.
438 
439  /// Return true if a G_SELECT instruction \p MI has a constant comparison. If
440  /// true, \p OpIdx will store the operand index of the known selected value.
441  bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx);
442 
443  /// Replace an instruction with a G_FCONSTANT with value \p C.
444  bool replaceInstWithFConstant(MachineInstr &MI, double C);
445 
446  /// Replace an instruction with a G_CONSTANT with value \p C.
447  bool replaceInstWithConstant(MachineInstr &MI, int64_t C);
448 
449  /// Replace an instruction with a G_CONSTANT with value \p C.
451 
452  /// Replace an instruction with a G_IMPLICIT_DEF.
454 
455  /// Delete \p MI and replace all of its uses with its \p OpIdx-th operand.
456  bool replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx);
457 
458  /// Delete \p MI and replace all of its uses with \p Replacement.
460 
461  /// Return true if \p MOP1 and \p MOP2 are register operands are defined by
462  /// equivalent instructions.
463  bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2);
464 
465  /// Return true if \p MOP is defined by a G_CONSTANT with a value equal to
466  /// \p C.
467  bool matchConstantOp(const MachineOperand &MOP, int64_t C);
468 
469  /// Optimize (cond ? x : x) -> x
471 
472  /// Optimize (x op x) -> x
474 
475  /// Check if operand \p OpIdx is zero.
476  bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx);
477 
478  /// Check if operand \p OpIdx is undef.
479  bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx);
480 
481  /// Check if operand \p OpIdx is known to be a power of 2.
482  bool matchOperandIsKnownToBeAPowerOfTwo(MachineInstr &MI, unsigned OpIdx);
483 
484  /// Erase \p MI
485  bool eraseInst(MachineInstr &MI);
486 
487  /// Return true if MI is a G_ADD which can be simplified to a G_SUB.
489  std::tuple<Register, Register> &MatchInfo);
491  std::tuple<Register, Register> &MatchInfo);
492 
493  /// Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
494  bool
496  InstructionStepsMatchInfo &MatchInfo);
497 
498  /// Replace \p MI with a series of instructions described in \p MatchInfo.
500  InstructionStepsMatchInfo &MatchInfo);
501 
502  /// Match ashr (shl x, C), C -> sext_inreg (C)
504  std::tuple<Register, int64_t> &MatchInfo);
506  std::tuple<Register, int64_t> &MatchInfo);
507 
508  /// Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0
510  BuildFnTy &MatchInfo);
511 
512  /// \return true if \p MI is a G_AND instruction whose operands are x and y
513  /// where x & y == x or x & y == y. (E.g., one of operands is all-ones value.)
514  ///
515  /// \param [in] MI - The G_AND instruction.
516  /// \param [out] Replacement - A register the G_AND should be replaced with on
517  /// success.
518  bool matchRedundantAnd(MachineInstr &MI, Register &Replacement);
519 
520  /// \return true if \p MI is a G_OR instruction whose operands are x and y
521  /// where x | y == x or x | y == y. (E.g., one of operands is all-zeros
522  /// value.)
523  ///
524  /// \param [in] MI - The G_OR instruction.
525  /// \param [out] Replacement - A register the G_OR should be replaced with on
526  /// success.
527  bool matchRedundantOr(MachineInstr &MI, Register &Replacement);
528 
529  /// \return true if \p MI is a G_SEXT_INREG that can be erased.
531 
532  /// Combine inverting a result of a compare into the opposite cond code.
535 
536  /// Fold (xor (and x, y), y) -> (and (not x), y)
537  ///{
539  std::pair<Register, Register> &MatchInfo);
541  std::pair<Register, Register> &MatchInfo);
542  ///}
543 
544  /// Combine G_PTR_ADD with nullptr to G_INTTOPTR
547 
548  /// Combine G_UREM x, (known power of 2) to an add and bitmasking.
550 
551  /// Push a binary operator through a select on constants.
552  ///
553  /// binop (select cond, K0, K1), K2 ->
554  /// select cond, (binop K0, K2), (binop K1, K2)
555  bool matchFoldBinOpIntoSelect(MachineInstr &MI, unsigned &SelectOpNo);
556  bool applyFoldBinOpIntoSelect(MachineInstr &MI, const unsigned &SelectOpNo);
557 
559  SmallVectorImpl<Register> &MatchInfo);
560 
562  SmallVectorImpl<Register> &MatchInfo);
563 
564  /// Match expression trees of the form
565  ///
566  /// \code
567  /// sN *a = ...
568  /// sM val = a[0] | (a[1] << N) | (a[2] << 2N) | (a[3] << 3N) ...
569  /// \endcode
570  ///
571  /// And check if the tree can be replaced with a M-bit load + possibly a
572  /// bswap.
573  bool matchLoadOrCombine(MachineInstr &MI, BuildFnTy &MatchInfo);
574 
577 
580 
583 
585  MachineInstr &MI,
586  SmallVectorImpl<std::pair<Register, MachineInstr *>> &MatchInfo);
588  MachineInstr &MI,
589  SmallVectorImpl<std::pair<Register, MachineInstr *>> &MatchInfo);
590 
591  /// Use a function which takes in a MachineIRBuilder to perform a combine.
592  /// By default, it erases the instruction \p MI from the function.
593  void applyBuildFn(MachineInstr &MI, BuildFnTy &MatchInfo);
594  /// Use a function which takes in a MachineIRBuilder to perform a combine.
595  /// This variant does not erase \p MI after calling the build function.
596  void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo);
597 
603 
604  /// \returns true if a G_ICMP instruction \p MI can be replaced with a true
605  /// or false constant based off of KnownBits information.
606  bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo);
607 
608  /// \returns true if a G_ICMP \p MI can be replaced with its LHS based off of
609  /// KnownBits information.
610  bool
612  BuildFnTy &MatchInfo);
613 
614  /// \returns true if (and (or x, c1), c2) can be replaced with (and x, c2)
615  bool matchAndOrDisjointMask(MachineInstr &MI, BuildFnTy &MatchInfo);
616 
618  BuildFnTy &MatchInfo);
619  /// Match: and (lshr x, cst), mask -> ubfx x, cst, width
621 
622  /// Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width
624 
625  /// Match: shr (and x, n), k -> ubfx x, pos, width
627 
628  // Helpers for reassociation:
630  BuildFnTy &MatchInfo);
632  MachineInstr *RHS,
633  BuildFnTy &MatchInfo);
635  MachineInstr *RHS, BuildFnTy &MatchInfo);
636  /// Reassociate pointer calculations with G_ADD involved, to allow better
637  /// addressing mode usage.
638  bool matchReassocPtrAdd(MachineInstr &MI, BuildFnTy &MatchInfo);
639 
640  /// Do constant folding when opportunities are exposed after MIR building.
641  bool matchConstantFold(MachineInstr &MI, APInt &MatchInfo);
642 
643  /// \returns true if it is possible to narrow the width of a scalar binop
644  /// feeding a G_AND instruction \p MI.
646 
647  /// Given an G_UDIV \p MI expressing a divide by constant, return an
648  /// expression that implements it by multiplying by a magic number.
649  /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
651  /// Combine G_UDIV by constant into a multiply by magic constant.
654 
655  /// Given an G_SDIV \p MI expressing a signed divide by constant, return an
656  /// expression that implements it by multiplying by a magic number.
657  /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
661 
662  // G_UMULH x, (1 << c)) -> x >> (bitwidth - c)
665 
666  /// Try to transform \p MI by using all of the above
667  /// combine functions. Returns true if changed.
668  bool tryCombine(MachineInstr &MI);
669 
670  /// Emit loads and stores that perform the given memcpy.
671  /// Assumes \p MI is a G_MEMCPY_INLINE
672  /// TODO: implement dynamically sized inline memcpy,
673  /// and rename: s/bool tryEmit/void emit/
675 
676  /// Match:
677  /// (G_UMULO x, 2) -> (G_UADDO x, x)
678  /// (G_SMULO x, 2) -> (G_SADDO x, x)
679  bool matchMulOBy2(MachineInstr &MI, BuildFnTy &MatchInfo);
680 
681  /// Match:
682  /// (G_*MULO x, 0) -> 0 + no carry out
683  bool matchMulOBy0(MachineInstr &MI, BuildFnTy &MatchInfo);
684 
685  /// Match:
686  /// (G_*ADDO x, 0) -> x + no carry out
687  bool matchAddOBy0(MachineInstr &MI, BuildFnTy &MatchInfo);
688 
689  /// Match:
690  /// (G_*ADDE x, y, 0) -> (G_*ADDO x, y)
691  /// (G_*SUBE x, y, 0) -> (G_*SUBO x, y)
692  bool matchAddEToAddO(MachineInstr &MI, BuildFnTy &MatchInfo);
693 
694  /// Transform (fadd x, fneg(y)) -> (fsub x, y)
695  /// (fadd fneg(x), y) -> (fsub y, x)
696  /// (fsub x, fneg(y)) -> (fadd x, y)
697  /// (fmul fneg(x), fneg(y)) -> (fmul x, y)
698  /// (fdiv fneg(x), fneg(y)) -> (fdiv x, y)
699  /// (fmad fneg(x), fneg(y), z) -> (fmad x, y, z)
700  /// (fma fneg(x), fneg(y), z) -> (fma x, y, z)
702 
703  bool matchFsubToFneg(MachineInstr &MI, Register &MatchInfo);
704  void applyFsubToFneg(MachineInstr &MI, Register &MatchInfo);
705 
706  bool canCombineFMadOrFMA(MachineInstr &MI, bool &AllowFusionGlobally,
707  bool &HasFMAD, bool &Aggressive,
708  bool CanReassociate = false);
709 
710  /// Transform (fadd (fmul x, y), z) -> (fma x, y, z)
711  /// (fadd (fmul x, y), z) -> (fmad x, y, z)
713 
714  /// Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z)
715  /// (fadd (fpext (fmul x, y)), z) -> (fmad (fpext x), (fpext y), z)
717  BuildFnTy &MatchInfo);
718 
719  /// Transform (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y, (fma u, v, z))
720  /// (fadd (fmad x, y, (fmul u, v)), z) -> (fmad x, y, (fmad u, v, z))
722  BuildFnTy &MatchInfo);
723 
724  // Transform (fadd (fma x, y, (fpext (fmul u, v))), z)
725  // -> (fma x, y, (fma (fpext u), (fpext v), z))
726  // (fadd (fmad x, y, (fpext (fmul u, v))), z)
727  // -> (fmad x, y, (fmad (fpext u), (fpext v), z))
729  BuildFnTy &MatchInfo);
730 
731  /// Transform (fsub (fmul x, y), z) -> (fma x, y, -z)
732  /// (fsub (fmul x, y), z) -> (fmad x, y, -z)
734 
735  /// Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
736  /// (fsub (fneg (fmul, x, y)), z) -> (fmad (fneg x), y, (fneg z))
738  BuildFnTy &MatchInfo);
739 
740  /// Transform (fsub (fpext (fmul x, y)), z)
741  /// -> (fma (fpext x), (fpext y), (fneg z))
742  /// (fsub (fpext (fmul x, y)), z)
743  /// -> (fmad (fpext x), (fpext y), (fneg z))
745  BuildFnTy &MatchInfo);
746 
747  /// Transform (fsub (fpext (fneg (fmul x, y))), z)
748  /// -> (fneg (fma (fpext x), (fpext y), z))
749  /// (fsub (fpext (fneg (fmul x, y))), z)
750  /// -> (fneg (fmad (fpext x), (fpext y), z))
752  BuildFnTy &MatchInfo);
753 
754  /// Fold boolean selects to logical operations.
755  bool matchSelectToLogical(MachineInstr &MI, BuildFnTy &MatchInfo);
756 
757  bool matchCombineFMinMaxNaN(MachineInstr &MI, unsigned &Info);
758 
759  /// Transform G_ADD(x, G_SUB(y, x)) to y.
760  /// Transform G_ADD(G_SUB(y, x), x) to y.
762 
766 
767  /// Transform:
768  /// (x + y) - y -> x
769  /// (x + y) - x -> y
770  /// x - (y + x) -> 0 - y
771  /// x - (x + z) -> 0 - z
772  bool matchSubAddSameReg(MachineInstr &MI, BuildFnTy &MatchInfo);
773 
774  /// \returns true if it is possible to simplify a select instruction \p MI
775  /// to a min/max instruction of some sort.
777 
778  /// Transform:
779  /// (X + Y) == X -> Y == 0
780  /// (X - Y) == X -> Y == 0
781  /// (X ^ Y) == X -> Y == 0
782  /// (X + Y) != X -> Y != 0
783  /// (X - Y) != X -> Y != 0
784  /// (X ^ Y) != X -> Y != 0
786 
787 private:
788  /// Given a non-indexed load or store instruction \p MI, find an offset that
789  /// can be usefully and legally folded into it as a post-indexing operation.
790  ///
791  /// \returns true if a candidate is found.
792  bool findPostIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
793  Register &Offset);
794 
795  /// Given a non-indexed load or store instruction \p MI, find an offset that
796  /// can be usefully and legally folded into it as a pre-indexing operation.
797  ///
798  /// \returns true if a candidate is found.
799  bool findPreIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
800  Register &Offset);
801 
802  /// Helper function for matchLoadOrCombine. Searches for Registers
803  /// which may have been produced by a load instruction + some arithmetic.
804  ///
805  /// \param [in] Root - The search root.
806  ///
807  /// \returns The Registers found during the search.
809  findCandidatesForLoadOrCombine(const MachineInstr *Root) const;
810 
811  /// Helper function for matchLoadOrCombine.
812  ///
813  /// Checks if every register in \p RegsToVisit is defined by a load
814  /// instruction + some arithmetic.
815  ///
816  /// \param [out] MemOffset2Idx - Maps the byte positions each load ends up
817  /// at to the index of the load.
818  /// \param [in] MemSizeInBits - The number of bits each load should produce.
819  ///
820  /// \returns On success, a 3-tuple containing lowest-index load found, the
821  /// lowest index, and the last load in the sequence.
823  findLoadOffsetsForLoadOrCombine(
824  SmallDenseMap<int64_t, int64_t, 8> &MemOffset2Idx,
825  const SmallVector<Register, 8> &RegsToVisit,
826  const unsigned MemSizeInBits);
827 
828  /// Examines the G_PTR_ADD instruction \p PtrAdd and determines if performing
829  /// a re-association of its operands would break an existing legal addressing
830  /// mode that the address computation currently represents.
831  bool reassociationCanBreakAddressingModePattern(MachineInstr &PtrAdd);
832 
833  /// Behavior when a floating point min/max is given one NaN and one
834  /// non-NaN as input.
835  enum class SelectPatternNaNBehaviour {
836  NOT_APPLICABLE = 0, /// NaN behavior not applicable.
837  RETURNS_NAN, /// Given one NaN input, returns the NaN.
838  RETURNS_OTHER, /// Given one NaN input, returns the non-NaN.
839  RETURNS_ANY /// Given one NaN input, can return either (or both operands are
840  /// known non-NaN.)
841  };
842 
843  /// \returns which of \p LHS and \p RHS would be the result of a non-equality
844  /// floating point comparison where one of \p LHS and \p RHS may be NaN.
845  ///
846  /// If both \p LHS and \p RHS may be NaN, returns
847  /// SelectPatternNaNBehaviour::NOT_APPLICABLE.
848  SelectPatternNaNBehaviour
849  computeRetValAgainstNaN(Register LHS, Register RHS,
850  bool IsOrderedComparison) const;
851 
852  /// Determines the floating point min/max opcode which should be used for
853  /// a G_SELECT fed by a G_FCMP with predicate \p Pred.
854  ///
855  /// \returns 0 if this G_SELECT should not be combined to a floating point
856  /// min or max. If it should be combined, returns one of
857  ///
858  /// * G_FMAXNUM
859  /// * G_FMAXIMUM
860  /// * G_FMINNUM
861  /// * G_FMINIMUM
862  ///
863  /// Helper function for matchFPSelectToMinMax.
864  unsigned getFPMinMaxOpcForSelect(CmpInst::Predicate Pred, LLT DstTy,
865  SelectPatternNaNBehaviour VsNaNRetVal) const;
866 
867  /// Handle floating point cases for matchSimplifySelectToMinMax.
868  ///
869  /// E.g.
870  ///
871  /// select (fcmp uge x, 1.0) x, 1.0 -> fmax x, 1.0
872  /// select (fcmp uge x, 1.0) 1.0, x -> fminnm x, 1.0
873  bool matchFPSelectToMinMax(Register Dst, Register Cond, Register TrueVal,
874  Register FalseVal, BuildFnTy &MatchInfo);
875 };
876 } // namespace llvm
877 
878 #endif
llvm::CombinerHelper::matchCombineUnmergeWithDeadLanesToTrunc
bool matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI)
Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
Definition: CombinerHelper.cpp:1829
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:459
llvm::CombinerHelper::matchFoldBinOpIntoSelect
bool matchFoldBinOpIntoSelect(MachineInstr &MI, unsigned &SelectOpNo)
Push a binary operator through a select on constants.
Definition: CombinerHelper.cpp:3111
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Register Addr
Definition: CombinerHelper.h:56
llvm::CombinerHelper::matchConstantFold
bool matchConstantFold(MachineInstr &MI, APInt &MatchInfo)
Do constant folding when opportunities are exposed after MIR building.
Definition: CombinerHelper.cpp:4636
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void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal)
Definition: CombinerHelper.cpp:1946
llvm::InstructionBuildSteps::Opcode
unsigned Opcode
Definition: CombinerHelper.h:93
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::CombinerHelper::applyExtractVecEltBuildVec
void applyExtractVecEltBuildVec(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:3955
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bool IsPreLegalize
Definition: CombinerHelper.h:116
llvm::RegisterImmPair
Definition: CombinerHelper.h:68
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bool matchTruncLshrBuildVectorFold(MachineInstr &MI, Register &MatchInfo)
Definition: CombinerHelper.cpp:5948
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Definition: AArch64ExpandPseudoInsts.cpp:107
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bool matchFsubToFneg(MachineInstr &MI, Register &MatchInfo)
Definition: CombinerHelper.cpp:5203
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Register WideSrcVal
Definition: CombinerHelper.h:85
llvm::CombinerHelper::matchCombineUnmergeConstant
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Transform G_UNMERGE Constant -> Constant1, Constant2, ...
Definition: CombinerHelper.cpp:1774
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Definition: CombinerHelper.h:112
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Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:720
llvm::CombinerHelper::applyOptBrCondByInvertingCond
void applyOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond)
Definition: CombinerHelper.cpp:1240
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Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
Definition: CombinerHelper.cpp:2649
llvm::CombinerHelper::CombinerHelper
CombinerHelper(GISelChangeObserver &Observer, MachineIRBuilder &B, bool IsPreLegalize, GISelKnownBits *KB=nullptr, MachineDominatorTree *MDT=nullptr, const LegalizerInfo *LI=nullptr)
Definition: CombinerHelper.cpp:51
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::ShiftOfShiftedLogic::Shift2
MachineInstr * Shift2
Definition: CombinerHelper.h:75
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::CombinerHelper::applyCombineI2PToP2I
void applyCombineI2PToP2I(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:2039
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bool eraseInst(MachineInstr &MI)
Erase MI.
Definition: CombinerHelper.cpp:2364
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Register Base
Definition: CombinerHelper.h:57
llvm::CombinerHelper::getKnownBits
GISelKnownBits * getKnownBits() const
Definition: CombinerHelper.h:128
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::CombinerHelper::getTargetLowering
const TargetLowering & getTargetLowering() const
Definition: CombinerHelper.cpp:62
llvm::InstructionBuildSteps::InstructionBuildSteps
InstructionBuildSteps(unsigned Opcode, const OperandBuildSteps &OperandFns)
Definition: CombinerHelper.h:96
llvm::CombinerHelper::matchCombineFSubFMulToFMadOrFMA
bool matchCombineFSubFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fmul x, y), z) -> (fma x, y, -z) (fsub (fmul x, y), z) -> (fmad x,...
Definition: CombinerHelper.cpp:5582
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bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen=0)
Optimize memcpy intrinsics et al, e.g.
Definition: CombinerHelper.cpp:1280
llvm::CombinerHelper::dominates
bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI)
Returns true if DefMI dominates UseMI.
Definition: CombinerHelper.cpp:789
llvm::MergeTruncStoresInfo
Definition: CombinerHelper.h:82
llvm::CombinerHelper::matchCombineFAddFMAFMulToFMadOrFMA
bool matchCombineFAddFMAFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y, (fma u, v, z)) (fadd (fmad x,...
Definition: CombinerHelper.cpp:5391
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Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::SmallDenseMap
Definition: DenseMap.h:880
llvm::CombinerHelper::matchConstantSelectCmp
bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx)
Return true if a G_SELECT instruction MI has a constant comparison.
Definition: CombinerHelper.cpp:2354
llvm::CombinerHelper::applyFunnelShiftToRotate
void applyFunnelShiftToRotate(MachineInstr &MI)
Definition: CombinerHelper.cpp:4106
llvm::CombinerHelper::matchCombineFSubFpExtFNegFMulToFMadOrFMA
bool matchCombineFSubFpExtFNegFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fpext (fneg (fmul x, y))), z) -> (fneg (fma (fpext x), (fpext y),...
Definition: CombinerHelper.cpp:5732
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void applyBuildFn(MachineInstr &MI, BuildFnTy &MatchInfo)
Use a function which takes in a MachineIRBuilder to perform a combine.
Definition: CombinerHelper.cpp:4027
llvm::CombinerHelper::tryCombineShuffleVector
bool tryCombineShuffleVector(MachineInstr &MI)
Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
Definition: CombinerHelper.cpp:298
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::CombinerHelper::matchTruncBuildVectorFold
bool matchTruncBuildVectorFold(MachineInstr &MI, Register &MatchInfo)
Definition: CombinerHelper.cpp:5937
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void replaceOpcodeWith(MachineInstr &FromMI, unsigned ToOpcode) const
Replace the opcode in instruction with a new opcode and inform the observer of the changes.
Definition: CombinerHelper.cpp:182
llvm::CombinerHelper::matchCombineDivRem
bool matchCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI)
Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM when their source operands are iden...
Definition: CombinerHelper.cpp:1111
llvm::CombinerHelper::tryCombineIndexedLoadStore
bool tryCombineIndexedLoadStore(MachineInstr &MI)
Combine MI into a pre-indexed or post-indexed load/store operation if legal and the surrounding code ...
Definition: CombinerHelper.cpp:1039
DenseMap.h
llvm::MergeTruncStoresInfo::NeedRotate
bool NeedRotate
Definition: CombinerHelper.h:87
llvm::CombinerHelper::matchSimplifySelectToMinMax
bool matchSimplifySelectToMinMax(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:6079
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bool matchNarrowBinopFeedingAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4646
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Definition: CombinerHelper.h:100
llvm::MergeTruncStoresInfo::FoundStores
SmallVector< GStore * > FoundStores
Definition: CombinerHelper.h:83
llvm::CombinerHelper::applyCombineExtOfExt
void applyCombineExtOfExt(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Definition: CombinerHelper.cpp:2174
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Definition: APInt.h:33
llvm::CombinerHelper::tryCombineShiftToUnmerge
bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount)
Definition: CombinerHelper.cpp:2019
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@ FalseVal
Definition: TGLexer.h:62
llvm::CombinerHelper::matchSextTruncSextLoad
bool matchSextTruncSextLoad(MachineInstr &MI)
Definition: CombinerHelper.cpp:801
Aggressive
static cl::opt< bool > Aggressive("aggressive-ext-opt", cl::Hidden, cl::desc("Aggressive extension optimization"))
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
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bool matchPtrAddZero(MachineInstr &MI)
}
Definition: CombinerHelper.cpp:3070
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bool tryCombineExtendingLoads(MachineInstr &MI)
If MI is extend that consumes the result of a load, try to combine it.
Definition: CombinerHelper.cpp:483
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int64_t Imm
Definition: CombinerHelper.h:63
llvm::CombinerHelper::matchPtrAddImmedChain
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Definition: CombinerHelper.cpp:1350
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Definition: CombinerHelper.cpp:4118
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Combine inverting a result of a compare into the opposite cond code.
Definition: CombinerHelper.cpp:2916
llvm::CombinerHelper::applyCombineTruncOfExt
void applyCombineTruncOfExt(MachineInstr &MI, std::pair< Register, unsigned > &MatchInfo)
Definition: CombinerHelper.cpp:2248
llvm::CombinerHelper::isConstantLegalOrBeforeLegalizer
bool isConstantLegalOrBeforeLegalizer(const LLT Ty) const
Definition: CombinerHelper.cpp:148
llvm::CombinerHelper::applyNotCmp
void applyNotCmp(MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate)
Definition: CombinerHelper.cpp:2993
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Definition: CombinerHelper.cpp:207
llvm::CombinerHelper::matchCombineAddP2IToPtrAdd
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Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y) Transform G_ADD y,...
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Definition: CombinerHelper.h:62
llvm::CombinerHelper::matchAshrShlToSextInreg
bool matchAshrShlToSextInreg(MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo)
Match ashr (shl x, C), C -> sext_inreg (C)
Definition: CombinerHelper.cpp:2755
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void applyTruncStoreMerge(MachineInstr &MI, MergeTruncStoresInfo &MatchInfo)
Definition: CombinerHelper.cpp:3794
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Definition: CombinerHelper.h:92
llvm::PtrAddChain::Base
Register Base
Definition: CombinerHelper.h:64
llvm::CombinerHelper::getBuilder
MachineIRBuilder & getBuilder() const
Definition: CombinerHelper.h:132
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::RegisterImmPair::Imm
int64_t Imm
Definition: CombinerHelper.h:70
llvm::CombinerHelper::applyPtrAddZero
void applyPtrAddZero(MachineInstr &MI)
Definition: CombinerHelper.cpp:3089
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std::function< void(MachineIRBuilder &)> BuildFnTy
Definition: CombinerHelper.h:80
llvm::InstructionBuildSteps::OperandFns
OperandBuildSteps OperandFns
The opcode for the produced instruction.
Definition: CombinerHelper.h:94
llvm::CombinerHelper::setRegBank
void setRegBank(Register Reg, const RegisterBank *RegBank)
Set the register bank of Reg.
Definition: CombinerHelper.cpp:195
llvm::CombinerHelper::matchReassocPtrAdd
bool matchReassocPtrAdd(MachineInstr &MI, BuildFnTy &MatchInfo)
Reassociate pointer calculations with G_ADD involved, to allow better addressing mode usage.
Definition: CombinerHelper.cpp:4603
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This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::CombinerHelper::matchCombineUnmergeUndef
bool matchCombineUnmergeUndef(MachineInstr &MI, std::function< void(MachineIRBuilder &)> &MatchInfo)
Transform G_UNMERGE G_IMPLICIT_DEF -> G_IMPLICIT_DEF, G_IMPLICIT_DEF, ...
Definition: CombinerHelper.cpp:1815
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MachineDominatorTree * MDT
Definition: CombinerHelper.h:115
llvm::CombinerHelper::buildUDivUsingMul
MachineInstr * buildUDivUsingMul(MachineInstr &MI)
Given an G_UDIV MI expressing a divide by constant, return an expression that implements it by multip...
Definition: CombinerHelper.cpp:4868
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bool matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef, SmallVectorImpl< Register > &Ops)
Check if the G_CONCAT_VECTORS MI is undef or if it can be flattened into a build_vector.
Definition: CombinerHelper.cpp:231
llvm::CombinerHelper::matchRedundantSExtInReg
bool matchRedundantSExtInReg(MachineInstr &MI)
Definition: CombinerHelper.cpp:2901
llvm::CombinerHelper::matchCombineZextTrunc
bool matchCombineZextTrunc(MachineInstr &MI, Register &Reg)
Transform zext(trunc(x)) to x.
Definition: CombinerHelper.cpp:2139
llvm::ShiftOfShiftedLogic
Definition: CombinerHelper.h:73
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
InstrTypes.h
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3490
llvm::CombinerHelper::matchReassocFoldConstantsInSubTree
bool matchReassocFoldConstantsInSubTree(GPtrAdd &MI, MachineInstr *LHS, MachineInstr *RHS, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4574
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InstructionStepsMatchInfo(std::initializer_list< InstructionBuildSteps > InstrsToBuild)
Definition: CombinerHelper.h:104
llvm::CombinerHelper::applySimplifyURemByPow2
void applySimplifyURemByPow2(MachineInstr &MI)
Combine G_UREM x, (known power of 2) to an add and bitmasking.
Definition: CombinerHelper.cpp:3097
llvm::CombinerHelper::buildSDivUsingMul
MachineInstr * buildSDivUsingMul(MachineInstr &MI)
Given an G_SDIV MI expressing a signed divide by constant, return an expression that implements it by...
Definition: CombinerHelper.cpp:5056
llvm::CombinerHelper::matchLoadOrCombine
bool matchLoadOrCombine(MachineInstr &MI, BuildFnTy &MatchInfo)
Match expression trees of the form.
Definition: CombinerHelper.cpp:3439
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bool matchCombineFAddFpExtFMulToFMadOrFMAAggressive(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:5456
llvm::CombinerHelper::matchAnyExplicitUseIsUndef
bool matchAnyExplicitUseIsUndef(MachineInstr &MI)
Return true if any explicit use operand on MI is defined by a G_IMPLICIT_DEF.
Definition: CombinerHelper.cpp:2309
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::CombinerHelper::applyCombineUnmergeZExtToZExt
void applyCombineUnmergeZExtToZExt(MachineInstr &MI)
Definition: CombinerHelper.cpp:1887
llvm::PreferredTuple::Ty
LLT Ty
Definition: CombinerHelper.h:50
llvm::CombinerHelper::applyExtendThroughPhis
void applyExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI)
Definition: CombinerHelper.cpp:3876
llvm::CombinerHelper::matchCombineI2PToP2I
bool matchCombineI2PToP2I(MachineInstr &MI, Register &Reg)
Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
Definition: CombinerHelper.cpp:2030
llvm::CombinerHelper::isPreLegalize
bool isPreLegalize() const
Definition: CombinerHelper.cpp:136
llvm::CombinerHelper::TRI
const TargetRegisterInfo * TRI
Definition: CombinerHelper.h:119
llvm::CombinerHelper::matchAddOBy0
bool matchAddOBy0(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: (G_*ADDO x, 0) -> x + no carry out.
Definition: CombinerHelper.cpp:4773
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::CombinerHelper::applyCombineUnmergeConstant
void applyCombineUnmergeConstant(MachineInstr &MI, SmallVectorImpl< APInt > &Csts)
Definition: CombinerHelper.cpp:1799
llvm::CombinerHelper::matchCombineFAddFMulToFMadOrFMA
bool matchCombineFAddFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd (fmul x, y), z) -> (fma x, y, z) (fadd (fmul x, y), z) -> (fmad x,...
Definition: CombinerHelper.cpp:5284
llvm::CombinerHelper
Definition: CombinerHelper.h:109
llvm::CombinerHelper::applyCombineConcatVectors
void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef, const ArrayRef< Register > Ops)
Replace MI with a flattened build_vector with Ops or an implicit_def if IsUndef is true.
Definition: CombinerHelper.cpp:276
llvm::CombinerHelper::matchCombineShuffleVector
bool matchCombineShuffleVector(MachineInstr &MI, SmallVectorImpl< Register > &Ops)
Check if the G_SHUFFLE_VECTOR MI can be replaced by a concat_vectors.
Definition: CombinerHelper.cpp:307
llvm::CombinerHelper::isLegal
bool isLegal(const LegalityQuery &Query) const
Definition: CombinerHelper.cpp:138
llvm::MergeTruncStoresInfo::NeedBSwap
bool NeedBSwap
Definition: CombinerHelper.h:86
llvm::CombinerHelper::tryCombineCopy
bool tryCombineCopy(MachineInstr &MI)
If MI is COPY, try to combine it.
Definition: CombinerHelper.cpp:200
llvm::CombinerHelper::Observer
GISelChangeObserver & Observer
Definition: CombinerHelper.h:113
llvm::CombinerHelper::matchCombineUnmergeZExtToZExt
bool matchCombineUnmergeZExtToZExt(MachineInstr &MI)
Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0.
Definition: CombinerHelper.cpp:1861
llvm::CombinerHelper::matchUndefShuffleVectorMask
bool matchUndefShuffleVectorMask(MachineInstr &MI)
Return true if a G_SHUFFLE_VECTOR instruction MI has an undef mask.
Definition: CombinerHelper.cpp:2323
llvm::CombinerHelper::matchICmpToTrueFalseKnownBits
bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo)
Definition: CombinerHelper.cpp:4148
llvm::CombinerHelper::applyCombineFAbsOfFAbs
void applyCombineFAbsOfFAbs(MachineInstr &MI, Register &Src)
Transform fabs(fabs(x)) to fabs(x).
LowLevelTypeImpl.h
llvm::CombinerHelper::matchCombineMergeUnmerge
bool matchCombineMergeUnmerge(MachineInstr &MI, Register &MatchInfo)
Fold away a merge of an unmerge of the corresponding values.
Definition: CombinerHelper.cpp:1700
llvm::CombinerHelper::KB
GISelKnownBits * KB
Definition: CombinerHelper.h:114
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::CombinerHelper::matchAddSubSameReg
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Transform G_ADD(x, G_SUB(y, x)) to y.
Definition: CombinerHelper.cpp:5875
llvm::InstructionStepsMatchInfo::InstructionStepsMatchInfo
InstructionStepsMatchInfo()=default
llvm::IndexedLoadStoreMatchInfo::Offset
Register Offset
Definition: CombinerHelper.h:58
llvm::CombinerHelper::applyPtrAddImmedChain
void applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo)
Definition: CombinerHelper.cpp:1412
llvm::GStore
Represents a G_STORE.
Definition: GenericMachineInstrs.h:130
llvm::CombinerHelper::matchOverlappingAnd
bool matchOverlappingAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0.
Definition: CombinerHelper.cpp:2786
llvm::CombinerHelper::applyBuildInstructionSteps
void applyBuildInstructionSteps(MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo)
Replace MI with a series of instructions described in MatchInfo.
Definition: CombinerHelper.cpp:2740
llvm::CombinerHelper::matchRedundantAnd
bool matchRedundantAnd(MachineInstr &MI, Register &Replacement)
Definition: CombinerHelper.cpp:2812
llvm::GPtrAdd
Represents a G_PTR_ADD.
Definition: GenericMachineInstrs.h:200
llvm::CombinerHelper::applySimplifyAddToSub
void applySimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo)
Definition: CombinerHelper.cpp:2640
llvm::CombinerHelper::matchTruncStoreMerge
bool matchTruncStoreMerge(MachineInstr &MI, MergeTruncStoresInfo &MatchInfo)
Match a pattern where a wide type scalar value is stored by several narrow stores.
Definition: CombinerHelper.cpp:3621
llvm::CombinerHelper::matchBitfieldExtractFromShr
bool matchBitfieldExtractFromShr(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width.
Definition: CombinerHelper.cpp:4344
llvm::CombinerHelper::tryCombineConcatVectors
bool tryCombineConcatVectors(MachineInstr &MI)
If MI is G_CONCAT_VECTORS, try to combine it.
Definition: CombinerHelper.cpp:221
llvm::CombinerHelper::matchBuildVectorIdentityFold
bool matchBuildVectorIdentityFold(MachineInstr &MI, Register &MatchInfo)
Definition: CombinerHelper.cpp:5891
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::CombinerHelper::matchUndefStore
bool matchUndefStore(MachineInstr &MI)
Return true if a G_STORE instruction MI is storing an undef value.
Definition: CombinerHelper.cpp:2329
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Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:221
llvm::CombinerHelper::matchReassocConstantInnerLHS
bool matchReassocConstantInnerLHS(GPtrAdd &MI, MachineInstr *LHS, MachineInstr *RHS, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4543
llvm::CombinerHelper::matchBitfieldExtractFromSExtInReg
bool matchBitfieldExtractFromSExtInReg(MachineInstr &MI, BuildFnTy &MatchInfo)
Form a G_SBFX from a G_SEXT_INREG fed by a right shift.
Definition: CombinerHelper.cpp:4279
llvm::CombinerHelper::matchUMulHToLShr
bool matchUMulHToLShr(MachineInstr &MI)
Definition: CombinerHelper.cpp:5124
llvm::CombinerHelper::applyBuildFnNoErase
void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo)
Use a function which takes in a MachineIRBuilder to perform a combine.
Definition: CombinerHelper.cpp:4034
llvm::CombinerHelper::matchBitfieldExtractFromShrAnd
bool matchBitfieldExtractFromShrAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: shr (and x, n), k -> ubfx x, pos, width.
Definition: CombinerHelper.cpp:4393
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::CombinerHelper::matchUndefSelectCmp
bool matchUndefSelectCmp(MachineInstr &MI)
Return true if a G_SELECT instruction MI has an undef comparison.
Definition: CombinerHelper.cpp:2335
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uint64_t Addr
Definition: ELFObjHandler.cpp:79
llvm::CombinerHelper::matchSelectToLogical
bool matchSelectToLogical(MachineInstr &MI, BuildFnTy &MatchInfo)
Fold boolean selects to logical operations.
Definition: CombinerHelper.cpp:5791
llvm::CombinerHelper::matchCombineConstPtrAddToI2P
bool matchCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst)
Definition: CombinerHelper.cpp:2099
llvm::CombinerHelper::applyCombineTruncOfShl
void applyCombineTruncOfShl(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Definition: CombinerHelper.cpp:2293
llvm::CombinerHelper::applyRotateOutOfRange
void applyRotateOutOfRange(MachineInstr &MI)
Definition: CombinerHelper.cpp:4133
llvm::ShiftOfShiftedLogic::LogicNonShiftReg
Register LogicNonShiftReg
Definition: CombinerHelper.h:76
llvm::CombinerHelper::Builder
MachineIRBuilder & Builder
Definition: CombinerHelper.h:111
llvm::MergeTruncStoresInfo::LowestIdxStore
GStore * LowestIdxStore
Definition: CombinerHelper.h:84
llvm::CombinerHelper::matchICmpToLHSKnownBits
bool matchICmpToLHSKnownBits(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4201
llvm::CombinerHelper::matchCombineIndexedLoadStore
bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo)
Definition: CombinerHelper.cpp:1048
llvm::CombinerHelper::matchCombineConstantFoldFpUnary
bool matchCombineConstantFoldFpUnary(MachineInstr &MI, Optional< APFloat > &Cst)
Transform fp_instr(cst) to constant result of the fp operation.
Definition: CombinerHelper.cpp:1330
llvm::CombinerHelper::matchCombineShlOfExtend
bool matchCombineShlOfExtend(MachineInstr &MI, RegisterImmPair &MatchData)
Definition: CombinerHelper.cpp:1649
llvm::CombinerHelper::matchConstantOp
bool matchConstantOp(const MachineOperand &MOP, int64_t C)
Return true if MOP is defined by a G_CONSTANT with a value equal to C.
Definition: CombinerHelper.cpp:2466
llvm::CombinerHelper::matchEqualDefs
bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2)
Return true if MOP1 and MOP2 are register operands are defined by equivalent instructions.
Definition: CombinerHelper.cpp:2369
llvm::CombinerHelper::replaceSingleDefInstWithOperand
bool replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx)
Delete MI and replace all of its uses with its OpIdx-th operand.
Definition: CombinerHelper.cpp:2475
llvm::CombinerHelper::matchCombineTruncOfExt
bool matchCombineTruncOfExt(MachineInstr &MI, std::pair< Register, unsigned > &MatchInfo)
Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
Definition: CombinerHelper.cpp:2234
llvm::CombinerHelper::matchCombineMulToShl
bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal)
Transform a multiply by a power-of-2 value to a left shift.
Definition: CombinerHelper.cpp:1624
llvm::PreferredTuple::ExtendOpcode
unsigned ExtendOpcode
Definition: CombinerHelper.h:51
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::CombinerHelper::applyCombineMulByNegativeOne
void applyCombineMulByNegativeOne(MachineInstr &MI)
Transform G_MUL(x, -1) to G_SUB(0, x)
Definition: CombinerHelper.cpp:2205
llvm::CombinerHelper::isLegalOrBeforeLegalizer
bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const
Definition: CombinerHelper.cpp:143
llvm::CombinerHelper::replaceInstWithUndef
bool replaceInstWithUndef(MachineInstr &MI)
Replace an instruction with a G_IMPLICIT_DEF.
Definition: CombinerHelper.cpp:2552
llvm::CombinerHelper::matchCombineInsertVecElts
bool matchCombineInsertVecElts(MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo)
Definition: CombinerHelper.cpp:2580
llvm::CombinerHelper::applySextTruncSextLoad
void applySextTruncSextLoad(MachineInstr &MI)
Definition: CombinerHelper.cpp:827
llvm::CombinerHelper::applyUMulHToLShr
void applyUMulHToLShr(MachineInstr &MI)
Definition: CombinerHelper.cpp:5140
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::CombinerHelper::matchAndOrDisjointMask
bool matchAndOrDisjointMask(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4244
llvm::CombinerHelper::matchReassocConstantInnerRHS
bool matchReassocConstantInnerRHS(GPtrAdd &MI, MachineInstr *RHS, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4519
llvm::IndexedLoadStoreMatchInfo::IsPre
bool IsPre
Definition: CombinerHelper.h:59
llvm::LegalityQuery
The LegalityQuery object bundles together all the information that's needed to decide whether a given...
Definition: LegalizerInfo.h:108
llvm::CombinerHelper::isPredecessor
bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI)
Returns true if DefMI precedes UseMI or they are the same instruction.
Definition: CombinerHelper.cpp:773
llvm::CombinerHelper::matchXorOfAndWithSameReg
bool matchXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Fold (xor (and x, y), y) -> (and (not x), y) {.
Definition: CombinerHelper.cpp:3025
llvm::InstructionStepsMatchInfo::InstrsToBuild
SmallVector< InstructionBuildSteps, 2 > InstrsToBuild
Describes instructions to be built during a combine.
Definition: CombinerHelper.h:102
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::CombinerHelper::matchSDivByConst
bool matchSDivByConst(MachineInstr &MI)
Definition: CombinerHelper.cpp:5022
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:138
llvm::CombinerHelper::matchCombineExtOfExt
bool matchCombineExtOfExt(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Transform [asz]ext([asz]ext(x)) to [asz]ext x.
Definition: CombinerHelper.cpp:2153
llvm::CombinerHelper::replaceRegOpWith
void replaceRegOpWith(MachineRegisterInfo &MRI, MachineOperand &FromRegOp, Register ToReg) const
Replace a single register operand with a new register and inform the observer of the changes.
Definition: CombinerHelper.cpp:171
llvm::CombinerHelper::matchBinOpSameVal
bool matchBinOpSameVal(MachineInstr &MI)
Optimize (x op x) -> x.
Definition: CombinerHelper.cpp:2504
llvm::CombinerHelper::matchBitfieldExtractFromAnd
bool matchBitfieldExtractFromAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: and (lshr x, cst), mask -> ubfx x, cst, width.
Definition: CombinerHelper.cpp:4308
llvm::CombinerHelper::matchOrShiftToFunnelShift
bool matchOrShiftToFunnelShift(MachineInstr &MI, BuildFnTy &MatchInfo)
Definition: CombinerHelper.cpp:4040
llvm::CombinerHelper::applyCombineConstantFoldFpUnary
void applyCombineConstantFoldFpUnary(MachineInstr &MI, Optional< APFloat > &Cst)
Definition: CombinerHelper.cpp:1339
llvm::CombinerHelper::applyCombineExtendingLoads
void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo)
Definition: CombinerHelper.cpp:586
llvm::CombinerHelper::applyAshShlToSextInreg
void applyAshShlToSextInreg(MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo)
Definition: CombinerHelper.cpp:2773
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::CombinerHelper::applyCombineInsertVecElts
void applyCombineInsertVecElts(MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo)
Definition: CombinerHelper.cpp:2621
llvm::CombinerHelper::matchSelectSameVal
bool matchSelectSameVal(MachineInstr &MI)
Optimize (cond ? x : x) -> x.
Definition: CombinerHelper.cpp:2496
llvm::CombinerHelper::matchOperandIsUndef
bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is undef.
Definition: CombinerHelper.cpp:2516
llvm::CombinerHelper::applyShiftImmedChain
void applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo)
Definition: CombinerHelper.cpp:1470
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::CombinerHelper::applySDivByConst
void applySDivByConst(MachineInstr &MI)
Definition: CombinerHelper.cpp:5051
llvm::CombinerHelper::tryEmitMemcpyInline
bool tryEmitMemcpyInline(MachineInstr &MI)
Emit loads and stores that perform the given memcpy.
Definition: CombinerHelper.cpp:1272
llvm::CombinerHelper::matchInsertExtractVecEltOutOfBounds
bool matchInsertExtractVecEltOutOfBounds(MachineInstr &MI)
Return true if a G_{EXTRACT,INSERT}_VECTOR_ELT has an out of range index.
Definition: CombinerHelper.cpp:2341
llvm::CombinerHelper::matchCombineLoadWithAndMask
bool matchCombineLoadWithAndMask(MachineInstr &MI, BuildFnTy &MatchInfo)
Match (and (load x), mask) -> zextload x.
Definition: CombinerHelper.cpp:692
llvm::CombinerHelper::matchShiftOfShiftedLogic
bool matchShiftOfShiftedLogic(MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo)
If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with...
Definition: CombinerHelper.cpp:1503
llvm::CombinerHelper::matchCombineAnyExtTrunc
bool matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg)
Transform anyext(trunc(x)) to x.
Definition: CombinerHelper.cpp:2130
llvm::CombinerHelper::matchMulOBy0
bool matchMulOBy0(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: (G_*MULO x, 0) -> 0 + no carry out.
Definition: CombinerHelper.cpp:4755
llvm::CombinerHelper::matchOperandIsKnownToBeAPowerOfTwo
bool matchOperandIsKnownToBeAPowerOfTwo(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is known to be a power of 2.
Definition: CombinerHelper.cpp:2522
llvm::CombinerHelper::matchCombineFMinMaxNaN
bool matchCombineFMinMaxNaN(MachineInstr &MI, unsigned &Info)
Definition: CombinerHelper.cpp:5847
llvm::CombinerHelper::applyCombineUnmergeMergeToPlainValues
void applyCombineUnmergeMergeToPlainValues(MachineInstr &MI, SmallVectorImpl< Register > &Operands)
Definition: CombinerHelper.cpp:1751
llvm::CombinerHelper::matchSextInRegOfLoad
bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Match sext_inreg(load p), imm -> sextload p.
Definition: CombinerHelper.cpp:834
llvm::CombinerHelper::matchAddEToAddO
bool matchAddEToAddO(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: (G_*ADDE x, y, 0) -> (G_*ADDO x, y) (G_*SUBE x, y, 0) -> (G_*SUBO x, y)
Definition: CombinerHelper.cpp:4791
llvm::CombinerHelper::matchFunnelShiftToRotate
bool matchFunnelShiftToRotate(MachineInstr &MI)
Match an FSHL or FSHR that can be combined to a ROTR or ROTL rotate.
Definition: CombinerHelper.cpp:4094
llvm::PtrAddChain::Bank
const RegisterBank * Bank
Definition: CombinerHelper.h:65
llvm::CombinerHelper::matchSimplifyAddToSub
bool matchSimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo)
Return true if MI is a G_ADD which can be simplified to a G_SUB.
Definition: CombinerHelper.cpp:2560
llvm::CombinerHelper::RBI
const RegisterBankInfo * RBI
Definition: CombinerHelper.h:118
llvm::CombinerHelper::LI
const LegalizerInfo * LI
Definition: CombinerHelper.h:117
llvm::CombinerHelper::applyUDivByConst
void applyUDivByConst(MachineInstr &MI)
Definition: CombinerHelper.cpp:5017
llvm::CombinerHelper::applyFoldBinOpIntoSelect
bool applyFoldBinOpIntoSelect(MachineInstr &MI, const unsigned &SelectOpNo)
SelectOperand is the operand in binary operator MI that is the select to fold.
Definition: CombinerHelper.cpp:3165
llvm::CombinerHelper::matchShiftImmedChain
bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo)
Fold (shift (shift base, x), y) -> (shift base (x+y))
Definition: CombinerHelper.cpp:1425
llvm::CombinerHelper::applyXorOfAndWithSameReg
void applyXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Definition: CombinerHelper.cpp:3056
llvm::CombinerHelper::applyCombineAddP2IToPtrAdd
void applyCombineAddP2IToPtrAdd(MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute)
Definition: CombinerHelper.cpp:2080
llvm::PreferredTuple::MI
MachineInstr * MI
Definition: CombinerHelper.h:52
llvm::CombinerHelper::matchRedundantBinOpInEquality
bool matchRedundantBinOpInEquality(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform: (X + Y) == X -> Y == 0 (X - Y) == X -> Y == 0 (X ^ Y) == X -> Y == 0 (X + Y) !...
Definition: CombinerHelper.cpp:6094
llvm::CombinerHelper::applyCombineConstPtrAddToI2P
void applyCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst)
Definition: CombinerHelper.cpp:2120
llvm::RegisterImmPair::Reg
Register Reg
Definition: CombinerHelper.h:69
SmallVector.h
llvm::IndexedLoadStoreMatchInfo
Definition: CombinerHelper.h:55
llvm::CombinerHelper::matchExtendThroughPhis
bool matchExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI)
Definition: CombinerHelper.cpp:3821
llvm::CombinerHelper::matchCombineShiftToUnmerge
bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize, unsigned &ShiftVal)
Reduce a shift by a constant to an unmerge and a shift on a half sized type.
Definition: CombinerHelper.cpp:1921
llvm::CombinerHelper::getRegBank
const RegisterBank * getRegBank(Register Reg) const
Get the register bank of Reg.
Definition: CombinerHelper.cpp:191
llvm::CombinerHelper::applyCombineCopy
void applyCombineCopy(MachineInstr &MI)
Definition: CombinerHelper.cpp:214
llvm::CombinerHelper::tryCombine
bool tryCombine(MachineInstr &MI)
Try to transform MI by using all of the above combine functions.
Definition: CombinerHelper.cpp:6126
llvm::InstructionBuildSteps::InstructionBuildSteps
InstructionBuildSteps()=default
Operands to be added to the instruction.
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:108
llvm::CombinerHelper::applyCombineDivRem
void applyCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI)
Definition: CombinerHelper.cpp:1174
llvm::CombinerHelper::replaceInstWithConstant
bool replaceInstWithConstant(MachineInstr &MI, int64_t C)
Replace an instruction with a G_CONSTANT with value C.
Definition: CombinerHelper.cpp:2536
llvm::CombinerHelper::matchCombineUnmergeMergeToPlainValues
bool matchCombineUnmergeMergeToPlainValues(MachineInstr &MI, SmallVectorImpl< Register > &Operands)
Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
Definition: CombinerHelper.cpp:1727
llvm::CombinerHelper::applyCombineP2IToI2P
void applyCombineP2IToI2P(MachineInstr &MI, Register &Reg)
Transform PtrToInt(IntToPtr(x)) to x.
Definition: CombinerHelper.cpp:2047
llvm::ShiftOfShiftedLogic::ValSum
uint64_t ValSum
Definition: CombinerHelper.h:77
llvm::CombinerHelper::applyExtractAllEltsFromBuildVector
void applyExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * >> &MatchInfo)
Definition: CombinerHelper.cpp:4015
llvm::CombinerHelper::applyShiftOfShiftedLogic
void applyShiftOfShiftedLogic(MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo)
Definition: CombinerHelper.cpp:1584
llvm::CombinerHelper::matchOperandIsZero
bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is zero.
Definition: CombinerHelper.cpp:2510
llvm::PreferredTuple
Definition: CombinerHelper.h:49
llvm::CombinerHelper::matchCombineExtendingLoads
bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo)
Definition: CombinerHelper.cpp:510
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMA
bool matchCombineFAddFpExtFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z) (fadd (fpext (fmul x,...
Definition: CombinerHelper.cpp:5332
llvm::CombinerHelper::matchSubAddSameReg
bool matchSubAddSameReg(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform: (x + y) - y -> x (x + y) - x -> y x - (y + x) -> 0 - y x - (x + z) -> 0 - z.
Definition: CombinerHelper.cpp:4824
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1182
llvm::CombinerHelper::matchMulOBy2
bool matchMulOBy2(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: (G_UMULO x, 2) -> (G_UADDO x, x) (G_SMULO x, 2) -> (G_SADDO x, x)
Definition: CombinerHelper.cpp:4737
llvm::CombinerHelper::applySextInRegOfLoad
void applySextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Definition: CombinerHelper.cpp:886
llvm::CombinerHelper::applyFsubToFneg
void applyFsubToFneg(MachineInstr &MI, Register &MatchInfo)
Definition: CombinerHelper.cpp:5227
Register.h
llvm::CombinerHelper::matchAllExplicitUsesAreUndef
bool matchAllExplicitUsesAreUndef(MachineInstr &MI)
Return true if all register explicit use operands on MI are defined by a G_IMPLICIT_DEF.
Definition: CombinerHelper.cpp:2316
llvm::CombinerHelper::replaceSingleDefInstWithReg
bool replaceSingleDefInstWithReg(MachineInstr &MI, Register Replacement)
Delete MI and replace all of its uses with Replacement.
Definition: CombinerHelper.cpp:2486
llvm::CombinerHelper::matchExtractAllEltsFromBuildVector
bool matchExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * >> &MatchInfo)
Definition: CombinerHelper.cpp:3973
llvm::ShiftOfShiftedLogic::Logic
MachineInstr * Logic
Definition: CombinerHelper.h:74
llvm::CombinerHelper::applyCombineIndexedLoadStore
void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo)
Definition: CombinerHelper.cpp:1069
llvm::CombinerHelper::matchRedundantOr
bool matchRedundantOr(MachineInstr &MI, Register &Replacement)
Definition: CombinerHelper.cpp:2861
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:51
llvm::CombinerHelper::applyCombineAnyExtTrunc
void applyCombineAnyExtTrunc(MachineInstr &MI, Register &Reg)
llvm::CombinerHelper::matchCombineTruncOfShl
bool matchCombineTruncOfShl(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Transform trunc (shl x, K) to shl (trunc x), K => K < VT.getScalarSizeInBits().
Definition: CombinerHelper.cpp:2269
llvm::tgtok::TrueVal
@ TrueVal
Definition: TGLexer.h:62
llvm::CombinerHelper::applyCombineMulToShl
void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal)
Definition: CombinerHelper.cpp:1636
llvm::CombinerHelper::matchOptBrCondByInvertingCond
bool matchOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond)
If a brcond's true block is not the fallthrough, make it so by inverting the condition and swapping o...
Definition: CombinerHelper.cpp:1206
llvm::CombinerHelper::applyCombineShlOfExtend
void applyCombineShlOfExtend(MachineInstr &MI, const RegisterImmPair &MatchData)
Definition: CombinerHelper.cpp:1686
llvm::CombinerHelper::matchRedundantNegOperands
bool matchRedundantNegOperands(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd x, fneg(y)) -> (fsub x, y) (fadd fneg(x), y) -> (fsub y, x) (fsub x,...
Definition: CombinerHelper.cpp:5157
llvm::CombinerHelper::applyCombineUnmergeWithDeadLanesToTrunc
void applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI)
Definition: CombinerHelper.cpp:1840
llvm::CombinerHelper::matchExtractVecEltBuildVec
bool matchExtractVecEltBuildVec(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:3921
llvm::CombinerHelper::canCombineFMadOrFMA
bool canCombineFMadOrFMA(MachineInstr &MI, bool &AllowFusionGlobally, bool &HasFMAD, bool &Aggressive, bool CanReassociate=false)
Definition: CombinerHelper.cpp:5251
llvm::CombinerHelper::matchCombineFSubFpExtFMulToFMadOrFMA
bool matchCombineFSubFpExtFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), (fneg z)) (fsub (fpext (fmul x,...
Definition: CombinerHelper.cpp:5681
llvm::CombinerHelper::matchUDivByConst
bool matchUDivByConst(MachineInstr &MI)
Combine G_UDIV by constant into a multiply by magic constant.
Definition: CombinerHelper.cpp:4974
llvm::CombinerHelper::replaceRegWith
void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const
MachineRegisterInfo::replaceRegWith() and inform the observer of the changes.
Definition: CombinerHelper.cpp:159
llvm::CombinerHelper::matchCombineFSubFNegFMulToFMadOrFMA
bool matchCombineFSubFNegFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) (fsub (fneg (fmul,...
Definition: CombinerHelper.cpp:5634
llvm::CombinerHelper::replaceInstWithFConstant
bool replaceInstWithFConstant(MachineInstr &MI, double C)
Replace an instruction with a G_FCONSTANT with value C.
Definition: CombinerHelper.cpp:2528
llvm::CombinerHelper::matchCombineFAbsOfFNeg
bool matchCombineFAbsOfFNeg(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform fabs(fneg(x)) to fabs(x).
Definition: CombinerHelper.cpp:2217
llvm::CombinerHelper::applyCombineShuffleVector
void applyCombineShuffleVector(MachineInstr &MI, const ArrayRef< Register > Ops)
Replace MI with a concat_vectors with Ops.
Definition: CombinerHelper.cpp:383
llvm::LLT
Definition: LowLevelTypeImpl.h:39