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include
llvm
CodeGen
MachineSSAContext.h
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//===- MachineSSAContext.h --------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file declares a specialization of the GenericSSAContext<X>
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/// template class for Machine IR.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINESSACONTEXT_H
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#define LLVM_CODEGEN_MACHINESSACONTEXT_H
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#include "
llvm/CodeGen/MachineBasicBlock.h
"
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#include "
llvm/Support/Printable.h
"
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namespace
llvm
{
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class
MachineRegisterInfo;
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class
MachineInstr;
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class
MachineFunction;
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class
Register
;
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template
<
typename
_FunctionT>
class
GenericSSAContext;
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template
<
typename
,
bool
>
class
DominatorTreeBase;
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inline
unsigned
succ_size
(
const
MachineBasicBlock
*BB) {
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return
BB->
succ_size
();
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}
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inline
unsigned
pred_size
(
const
MachineBasicBlock
*BB) {
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return
BB->
pred_size
();
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}
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inline
auto
instrs
(
const
MachineBasicBlock
&BB) {
return
BB.
instrs
(); }
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template
<>
class
GenericSSAContext
<
MachineFunction
> {
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const
MachineRegisterInfo
*
RegInfo
=
nullptr
;
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MachineFunction
*MF;
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public
:
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using
BlockT
=
MachineBasicBlock
;
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using
FunctionT
=
MachineFunction
;
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using
InstructionT
=
MachineInstr
;
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using
ValueRefT
=
Register
;
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using
ConstValueRefT
=
Register
;
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static
const
Register
ValueRefNull
;
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using
UseT
=
MachineOperand
;
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using
DominatorTreeT
=
DominatorTreeBase<BlockT, false>
;
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void
setFunction(
MachineFunction
&Fn);
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MachineFunction
*
getFunction
()
const
{
return
MF; }
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static
MachineBasicBlock
*getEntryBlock(
MachineFunction
&
F
);
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static
void
appendBlockDefs(
SmallVectorImpl<Register>
&defs,
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const
MachineBasicBlock
&
block
);
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static
void
appendBlockTerms
(
SmallVectorImpl<MachineInstr *>
&terms,
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MachineBasicBlock
&
block
);
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static
void
appendBlockTerms(
SmallVectorImpl<const MachineInstr *>
&terms,
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const
MachineBasicBlock
&
block
);
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MachineBasicBlock
*getDefBlock(
Register
)
const
;
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static
bool
isConstantOrUndefValuePhi(
const
MachineInstr
&Phi);
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Printable
print
(
const
MachineBasicBlock
*
Block
)
const
;
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Printable
print
(
const
MachineInstr
*Inst)
const
;
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Printable
print
(
Register
Value
)
const
;
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};
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using
MachineSSAContext
=
GenericSSAContext<MachineFunction>
;
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}
// namespace llvm
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#endif
// LLVM_CODEGEN_MACHINESSACONTEXT_H
F
#define F(x, y, z)
Definition:
MD5.cpp:55
MachineBasicBlock.h
Register
Promote Memory to Register
Definition:
Mem2Reg.cpp:114
Printable.h
block
unify loop Fixup each natural loop to have a single exit block
Definition:
UnifyLoopExits.cpp:72
llvm::DominatorTreeBase
Core dominator tree base class.
Definition:
GenericDomTree.h:243
llvm::GenericSSAContext< MachineFunction >
Definition:
MachineSSAContext.h:37
llvm::GenericSSAContext< MachineFunction >::getFunction
MachineFunction * getFunction() const
Definition:
MachineSSAContext.h:52
llvm::GenericSSAContext< MachineFunction >::ValueRefNull
static const Register ValueRefNull
Definition:
MachineSSAContext.h:47
llvm::GenericSSAContext< MachineFunction >::appendBlockTerms
static void appendBlockTerms(SmallVectorImpl< MachineInstr * > &terms, MachineBasicBlock &block)
llvm::GenericSSAContext
Definition:
GenericSSAContext.h:24
llvm::MachineBasicBlock
Definition:
MachineBasicBlock.h:95
llvm::MachineBasicBlock::pred_size
unsigned pred_size() const
Definition:
MachineBasicBlock.h:369
llvm::MachineBasicBlock::instrs
instr_range instrs()
Definition:
MachineBasicBlock.h:304
llvm::MachineBasicBlock::succ_size
unsigned succ_size() const
Definition:
MachineBasicBlock.h:385
llvm::MachineFunction
Definition:
MachineFunction.h:258
llvm::MachineInstr
Representation of each machine instruction.
Definition:
MachineInstr.h:68
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition:
MachineOperand.h:48
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition:
MachineRegisterInfo.h:51
llvm::Printable
Simple wrapper around std::function<void(raw_ostream&)>.
Definition:
Printable.h:38
llvm::Register
Wrapper class representing virtual and physical registers.
Definition:
Register.h:19
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition:
SmallVector.h:577
llvm::Value
LLVM Value Representation.
Definition:
Value.h:74
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition:
AddressRanges.h:18
llvm::PseudoProbeType::Block
@ Block
llvm::print
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
Definition:
GCNRegPressure.cpp:138
llvm::instrs
auto instrs(const MachineBasicBlock &BB)
Definition:
MachineSSAContext.h:35
llvm::succ_size
unsigned succ_size(const MachineBasicBlock *BB)
Definition:
MachineSSAContext.h:29
llvm::pred_size
unsigned pred_size(const MachineBasicBlock *BB)
Definition:
MachineSSAContext.h:32
RegInfo
Definition:
AMDGPUAsmParser.cpp:2570
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