29#define DEBUG_TYPE "si-lower-sgpr-spills"
67 .
set(MachineFunctionProperties::Property::IsSSA)
68 .
set(MachineFunctionProperties::Property::NoVRegs);
74char SILowerSGPRSpills::ID = 0;
77 "SI lower SGPR spill instructions",
false,
false)
106 Reg, Reg == RI->getReturnAddressReg(MF) ? MVT::i64 : MVT::i32);
112 const bool IsLiveIn =
MRI.isLiveIn(Reg);
119 Indexes->insertMachineInstrInMaps(Inst);
123 LIS->removeAllRegUnitsForPhysReg(Reg);
147 Reg, Reg == RI->getReturnAddressReg(MF) ? MVT::i64 : MVT::i32);
152 "loadRegFromStackSlot didn't insert any code!");
169void SILowerSGPRSpills::calculateSaveRestoreBlocks(
MachineFunction &MF) {
190 SaveBlocks.push_back(&MF.
front());
193 SaveBlocks.push_back(&
MBB);
195 RestoreBlocks.push_back(&
MBB);
209bool SILowerSGPRSpills::spillCalleeSavedRegs(
220 TFI->determineCalleeSavesSGPR(MF, SavedRegs, RS);
223 if (!
F.hasFnAttribute(Attribute::Naked)) {
228 std::vector<CalleeSavedInfo> CSI;
231 for (
unsigned I = 0; CSRegs[
I]; ++
I) {
234 if (SavedRegs.
test(Reg)) {
236 TRI->getMinimalPhysRegClass(Reg, MVT::i32);
238 TRI->getSpillAlign(*RC),
true);
250 assert(SaveBlocks.size() == 1 &&
"shrink wrapping not fully implemented");
281 auto MIB =
BuildMI(*SaveBlock, *InsertBefore, InsertBefore->getDebugLoc(),
282 TII->get(AMDGPU::IMPLICIT_DEF), Reg);
299 BuildMI(*RestoreBlock, *InsertBefore, InsertBefore->getDebugLoc(),
300 TII->get(TargetOpcode::KILL));
310 TII =
ST.getInstrInfo();
311 TRI = &
TII->getRegisterInfo();
313 LIS = getAnalysisIfAvailable<LiveIntervals>();
314 Indexes = getAnalysisIfAvailable<SlotIndexes>();
316 assert(SaveBlocks.empty() && RestoreBlocks.empty());
320 calculateSaveRestoreBlocks(MF);
322 bool HasCSRs = spillCalleeSavedRegs(MF, CalleeSavedFIs);
330 RestoreBlocks.clear();
334 bool MadeChange =
false;
335 bool NewReservedRegs =
false;
336 bool SpilledToVirtVGPRLanes =
false;
340 const bool HasSGPRSpillToVGPR =
TRI->spillSGPRToVGPR() &&
342 if (HasSGPRSpillToVGPR) {
354 if (!
TII->isSGPRSpill(
MI))
357 int FI =
TII->getNamedOperand(
MI, AMDGPU::OpName::addr)->getIndex();
361 if (IsCalleeSaveSGPRSpill) {
373 NewReservedRegs =
true;
374 bool Spilled =
TRI->eliminateSGPRToVGPRSpillFrameIndex(
375 MI, FI,
nullptr, Indexes, LIS,
true);
378 "failed to spill SGPR to physical VGPR lane when allocated");
382 bool Spilled =
TRI->eliminateSGPRToVGPRSpillFrameIndex(
383 MI, FI,
nullptr, Indexes, LIS);
386 "failed to spill SGPR to virtual VGPR lane when allocated");
388 SpilledToVirtVGPRLanes =
true;
394 if (SpilledToVirtVGPRLanes) {
395 extendWWMVirtRegLiveness(MF, LIS);
409 if (
MI.isDebugValue() &&
MI.getOperand(0).isFI() &&
411 SpillFIs[
MI.getOperand(0).getIndex()]) {
412 MI.getOperand(0).ChangeToRegister(
Register(),
false );
427 if (SpilledToVirtVGPRLanes) {
433 if (UnusedLowSGPR &&
TRI->getHWRegIndex(UnusedLowSGPR) <
443 RestoreBlocks.clear();
447 if (NewReservedRegs) {
unsigned const MachineRegisterInfo * MRI
Provides AMDGPU specific target descriptions.
AMD GCN specific subclass of TargetSubtarget.
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static void updateLiveness(MachineFunction &MF, ArrayRef< CalleeSavedInfo > CSI)
static void insertCSRRestores(MachineBasicBlock &RestoreBlock, MutableArrayRef< CalleeSavedInfo > CSI, SlotIndexes *Indexes, LiveIntervals *LIS)
Insert restore code for the callee-saved registers used in the function.
SI lower SGPR spill instructions
static void insertCSRSaves(MachineBasicBlock &SaveBlock, ArrayRef< CalleeSavedInfo > CSI, SlotIndexes *Indexes, LiveIntervals *LIS)
Insert spill code for the callee-saved registers used in the function.
Represent the analysis usage information of a pass.
void setPreservesAll()
Set by analyses that do not transform their input at all.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool test(unsigned Idx) const
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Store the specified register of the given register class to the specified stack frame index.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Load the specified register of the given register class from the specified stack frame index.
void removeAllRegUnitsForPhysReg(MCRegister Reg)
Remove associated live ranges for the register units associated with Reg.
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
LiveInterval & createAndComputeVirtRegInterval(Register Reg)
Wrapper class representing physical registers. Should be passed by value.
void push_back(MachineInstr *MI)
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
MachineBasicBlock * getRestorePoint() const
void setCalleeSavedInfoValid(bool v)
int getObjectIndexEnd() const
Return one past the maximum frame object index.
bool hasStackObjects() const
Return true if there are any stack objects in this function.
uint8_t getStackID(int ObjectIdx) const
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
MachineBasicBlock * getSavePoint() const
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual MachineFunctionProperties getClearedProperties() const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
MachineInstrSpan provides an interface to get an iteration range containing the instruction it was in...
MachineBasicBlock::iterator begin()
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Wrapper class representing virtual and physical registers.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
void setSGPRForEXECCopy(Register Reg)
void setFlag(Register Reg, uint8_t Flag)
bool allocateSGPRSpillToVGPRLane(MachineFunction &MF, int FI, bool IsPrologEpilog=false)
Register getSGPRForEXECCopy() const
bool removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs)
If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.
const ReservedRegSet & getWWMReservedRegs() const
bool hasSpilledSGPRs() const
ArrayRef< Register > getSGPRSpillVGPRs() const
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Information about stack frame layout on the target.
virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetFrameLowering * getFrameLowering() const
virtual const TargetInstrInfo * getInstrInfo() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
char & SILowerSGPRSpillsID
auto reverse(ContainerTy &&C)
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.