LLVM  14.0.0git
SILowerSGPRSpills.cpp
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1 //===-- SILowerSGPRSPills.cpp ---------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Handle SGPR spills. This pass takes the place of PrologEpilogInserter for all
10 // SGPR spills, so must insert CSR SGPR spills as well as expand them.
11 //
12 // This pass must never create new SGPR virtual registers.
13 //
14 // FIXME: Must stop RegScavenger spills in later passes.
15 //
16 //===----------------------------------------------------------------------===//
17 
18 #include "AMDGPU.h"
19 #include "GCNSubtarget.h"
21 #include "SIMachineFunctionInfo.h"
24 #include "llvm/InitializePasses.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "si-lower-sgpr-spills"
29 
31 
32 namespace {
33 
34 class SILowerSGPRSpills : public MachineFunctionPass {
35 private:
36  const SIRegisterInfo *TRI = nullptr;
37  const SIInstrInfo *TII = nullptr;
38  LiveIntervals *LIS = nullptr;
39 
40  // Save and Restore blocks of the current function. Typically there is a
41  // single save block, unless Windows EH funclets are involved.
42  MBBVector SaveBlocks;
43  MBBVector RestoreBlocks;
44 
45 public:
46  static char ID;
47 
48  SILowerSGPRSpills() : MachineFunctionPass(ID) {}
49 
50  void calculateSaveRestoreBlocks(MachineFunction &MF);
51  bool spillCalleeSavedRegs(MachineFunction &MF);
52 
53  bool runOnMachineFunction(MachineFunction &MF) override;
54 
55  void getAnalysisUsage(AnalysisUsage &AU) const override {
56  AU.setPreservesAll();
58  }
59 };
60 
61 } // end anonymous namespace
62 
63 char SILowerSGPRSpills::ID = 0;
64 
65 INITIALIZE_PASS_BEGIN(SILowerSGPRSpills, DEBUG_TYPE,
66  "SI lower SGPR spill instructions", false, false)
69 INITIALIZE_PASS_END(SILowerSGPRSpills, DEBUG_TYPE,
70  "SI lower SGPR spill instructions", false, false)
71 
72 char &llvm::SILowerSGPRSpillsID = SILowerSGPRSpills::ID;
73 
74 /// Insert restore code for the callee-saved registers used in the function.
75 static void insertCSRSaves(MachineBasicBlock &SaveBlock,
77  LiveIntervals *LIS) {
78  MachineFunction &MF = *SaveBlock.getParent();
82 
83  MachineBasicBlock::iterator I = SaveBlock.begin();
84  if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) {
85  const MachineRegisterInfo &MRI = MF.getRegInfo();
86 
87  for (const CalleeSavedInfo &CS : CSI) {
88  // Insert the spill to the stack frame.
89  MCRegister Reg = CS.getReg();
90 
91  MachineInstrSpan MIS(I, &SaveBlock);
92  const TargetRegisterClass *RC =
94 
95  // If this value was already livein, we probably have a direct use of the
96  // incoming register value, so don't kill at the spill point. This happens
97  // since we pass some special inputs (workgroup IDs) in the callee saved
98  // range.
99  const bool IsLiveIn = MRI.isLiveIn(Reg);
100  TII.storeRegToStackSlot(SaveBlock, I, Reg, !IsLiveIn, CS.getFrameIdx(),
101  RC, TRI);
102 
103  if (LIS) {
104  assert(std::distance(MIS.begin(), I) == 1);
105  MachineInstr &Inst = *std::prev(I);
106 
107  LIS->InsertMachineInstrInMaps(Inst);
108  LIS->removeAllRegUnitsForPhysReg(Reg);
109  }
110  }
111  }
112 }
113 
114 /// Insert restore code for the callee-saved registers used in the function.
115 static void insertCSRRestores(MachineBasicBlock &RestoreBlock,
117  LiveIntervals *LIS) {
118  MachineFunction &MF = *RestoreBlock.getParent();
119  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
122 
123  // Restore all registers immediately before the return and any
124  // terminators that precede it.
126 
127  // FIXME: Just emit the readlane/writelane directly
128  if (!TFI->restoreCalleeSavedRegisters(RestoreBlock, I, CSI, TRI)) {
129  for (const CalleeSavedInfo &CI : reverse(CSI)) {
130  unsigned Reg = CI.getReg();
131  const TargetRegisterClass *RC =
133 
134  TII.loadRegFromStackSlot(RestoreBlock, I, Reg, CI.getFrameIdx(), RC, TRI);
135  assert(I != RestoreBlock.begin() &&
136  "loadRegFromStackSlot didn't insert any code!");
137  // Insert in reverse order. loadRegFromStackSlot can insert
138  // multiple instructions.
139 
140  if (LIS) {
141  MachineInstr &Inst = *std::prev(I);
142  LIS->InsertMachineInstrInMaps(Inst);
144  }
145  }
146  }
147 }
148 
149 /// Compute the sets of entry and return blocks for saving and restoring
150 /// callee-saved registers, and placing prolog and epilog code.
151 void SILowerSGPRSpills::calculateSaveRestoreBlocks(MachineFunction &MF) {
152  const MachineFrameInfo &MFI = MF.getFrameInfo();
153 
154  // Even when we do not change any CSR, we still want to insert the
155  // prologue and epilogue of the function.
156  // So set the save points for those.
157 
158  // Use the points found by shrink-wrapping, if any.
159  if (MFI.getSavePoint()) {
160  SaveBlocks.push_back(MFI.getSavePoint());
161  assert(MFI.getRestorePoint() && "Both restore and save must be set");
162  MachineBasicBlock *RestoreBlock = MFI.getRestorePoint();
163  // If RestoreBlock does not have any successor and is not a return block
164  // then the end point is unreachable and we do not need to insert any
165  // epilogue.
166  if (!RestoreBlock->succ_empty() || RestoreBlock->isReturnBlock())
167  RestoreBlocks.push_back(RestoreBlock);
168  return;
169  }
170 
171  // Save refs to entry and return blocks.
172  SaveBlocks.push_back(&MF.front());
173  for (MachineBasicBlock &MBB : MF) {
174  if (MBB.isEHFuncletEntry())
175  SaveBlocks.push_back(&MBB);
176  if (MBB.isReturnBlock())
177  RestoreBlocks.push_back(&MBB);
178  }
179 }
180 
181 // TODO: To support shrink wrapping, this would need to copy
182 // PrologEpilogInserter's updateLiveness.
184  MachineBasicBlock &EntryBB = MF.front();
185 
186  for (const CalleeSavedInfo &CSIReg : CSI)
187  EntryBB.addLiveIn(CSIReg.getReg());
188  EntryBB.sortUniqueLiveIns();
189 }
190 
191 bool SILowerSGPRSpills::spillCalleeSavedRegs(MachineFunction &MF) {
193  const Function &F = MF.getFunction();
194  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
195  const SIFrameLowering *TFI = ST.getFrameLowering();
196  MachineFrameInfo &MFI = MF.getFrameInfo();
197  RegScavenger *RS = nullptr;
198 
199  // Determine which of the registers in the callee save list should be saved.
200  BitVector SavedRegs;
201  TFI->determineCalleeSavesSGPR(MF, SavedRegs, RS);
202 
203  // Add the code to save and restore the callee saved registers.
204  if (!F.hasFnAttribute(Attribute::Naked)) {
205  // FIXME: This is a lie. The CalleeSavedInfo is incomplete, but this is
206  // necessary for verifier liveness checks.
207  MFI.setCalleeSavedInfoValid(true);
208 
209  std::vector<CalleeSavedInfo> CSI;
210  const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
211 
212  for (unsigned I = 0; CSRegs[I]; ++I) {
213  MCRegister Reg = CSRegs[I];
214 
215  if (SavedRegs.test(Reg)) {
216  const TargetRegisterClass *RC =
218  int JunkFI = MFI.CreateStackObject(TRI->getSpillSize(*RC),
219  TRI->getSpillAlign(*RC), true);
220 
221  CSI.push_back(CalleeSavedInfo(Reg, JunkFI));
222  }
223  }
224 
225  if (!CSI.empty()) {
226  for (MachineBasicBlock *SaveBlock : SaveBlocks)
227  insertCSRSaves(*SaveBlock, CSI, LIS);
228 
229  // Add live ins to save blocks.
230  assert(SaveBlocks.size() == 1 && "shrink wrapping not fully implemented");
231  updateLiveness(MF, CSI);
232 
233  for (MachineBasicBlock *RestoreBlock : RestoreBlocks)
234  insertCSRRestores(*RestoreBlock, CSI, LIS);
235  return true;
236  }
237  }
238 
239  return false;
240 }
241 
242 bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) {
243  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
244  TII = ST.getInstrInfo();
245  TRI = &TII->getRegisterInfo();
246 
247  LIS = getAnalysisIfAvailable<LiveIntervals>();
248 
249  assert(SaveBlocks.empty() && RestoreBlocks.empty());
250 
251  // First, expose any CSR SGPR spills. This is mostly the same as what PEI
252  // does, but somewhat simpler.
253  calculateSaveRestoreBlocks(MF);
254  bool HasCSRs = spillCalleeSavedRegs(MF);
255 
256  MachineFrameInfo &MFI = MF.getFrameInfo();
259 
260  if (!MFI.hasStackObjects() && !HasCSRs) {
261  SaveBlocks.clear();
262  RestoreBlocks.clear();
263  return false;
264  }
265 
266  bool MadeChange = false;
267  bool NewReservedRegs = false;
268 
269  // TODO: CSR VGPRs will never be spilled to AGPRs. These can probably be
270  // handled as SpilledToReg in regular PrologEpilogInserter.
271  const bool HasSGPRSpillToVGPR = TRI->spillSGPRToVGPR() &&
272  (HasCSRs || FuncInfo->hasSpilledSGPRs());
273  if (HasSGPRSpillToVGPR) {
274  // Process all SGPR spills before frame offsets are finalized. Ideally SGPRs
275  // are spilled to VGPRs, in which case we can eliminate the stack usage.
276  //
277  // This operates under the assumption that only other SGPR spills are users
278  // of the frame index.
279 
280  // To track the spill frame indices handled in this pass.
281  BitVector SpillFIs(MFI.getObjectIndexEnd(), false);
282 
283  for (MachineBasicBlock &MBB : MF) {
285  if (!TII->isSGPRSpill(MI))
286  continue;
287 
288  int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex();
290  if (FuncInfo->allocateSGPRSpillToVGPR(MF, FI)) {
291  NewReservedRegs = true;
292  bool Spilled = TRI->eliminateSGPRToVGPRSpillFrameIndex(MI, FI,
293  nullptr, LIS);
294  (void)Spilled;
295  assert(Spilled && "failed to spill SGPR to VGPR when allocated");
296  SpillFIs.set(FI);
297  }
298  }
299  }
300 
301  // FIXME: Adding to live-ins redundant with reserving registers.
302  for (MachineBasicBlock &MBB : MF) {
303  for (auto SSpill : FuncInfo->getSGPRSpillVGPRs())
304  MBB.addLiveIn(SSpill.VGPR);
306 
307  // FIXME: The dead frame indices are replaced with a null register from
308  // the debug value instructions. We should instead, update it with the
309  // correct register value. But not sure the register value alone is
310  // adequate to lower the DIExpression. It should be worked out later.
311  for (MachineInstr &MI : MBB) {
312  if (MI.isDebugValue() && MI.getOperand(0).isFI() &&
313  SpillFIs[MI.getOperand(0).getIndex()]) {
314  MI.getOperand(0).ChangeToRegister(Register(), false /*isDef*/);
315  }
316  }
317  }
318 
319  // All those frame indices which are dead by now should be removed from the
320  // function frame. Otherwise, there is a side effect such as re-mapping of
321  // free frame index ids by the later pass(es) like "stack slot coloring"
322  // which in turn could mess-up with the book keeping of "frame index to VGPR
323  // lane".
324  FuncInfo->removeDeadFrameIndices(MFI);
325 
326  MadeChange = true;
327  }
328 
329  SaveBlocks.clear();
330  RestoreBlocks.clear();
331 
332  // Updated the reserved registers with any VGPRs added for SGPR spills.
333  if (NewReservedRegs)
335 
336  return MadeChange;
337 }
llvm::SIMachineFunctionInfo::getSGPRSpillVGPRs
ArrayRef< SGPRSpillVGPR > getSGPRSpillVGPRs() const
Definition: SIMachineFunctionInfo.h:525
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
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Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::SILowerSGPRSpillsID
char & SILowerSGPRSpillsID
Definition: SILowerSGPRSpills.cpp:72
SIMachineFunctionInfo.h
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MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
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Definition: Function.h:62
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MachineInstrSpan provides an interface to get an iteration range containing the instruction it was in...
Definition: MachineBasicBlock.h:1198
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::MachineBasicBlock::isEHFuncletEntry
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
Definition: MachineBasicBlock.h:569
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This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1177
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Definition: VirtRegMap.h:33
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::SIMachineFunctionInfo::allocateSGPRSpillToVGPR
bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI)
Reserve a slice of a VGPR to support spilling for FrameIndex FI.
Definition: SIMachineFunctionInfo.cpp:264
llvm::MachineBasicBlock::isReturnBlock
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
Definition: MachineBasicBlock.h:822
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::LiveIntervals::removeAllRegUnitsForPhysReg
void removeAllRegUnitsForPhysReg(MCRegister Reg)
Remove associated live ranges for the register units associated with Reg.
Definition: LiveIntervals.h:425
llvm::reverse
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
Definition: STLExtras.h:414
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:393
updateLiveness
static void updateLiveness(MachineFunction &MF, ArrayRef< CalleeSavedInfo > CSI)
Definition: SILowerSGPRSpills.cpp:183
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::MachineFrameInfo::hasStackObjects
bool hasStackObjects() const
Return true if there are any stack objects in this function.
Definition: MachineFrameInfo.h:348
llvm::MachineBasicBlock::push_back
void push_back(MachineInstr *MI)
Definition: MachineBasicBlock.h:860
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:835
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:651
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:305
GCNSubtarget.h
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:739
llvm::MachineFrameInfo::setCalleeSavedInfoValid
void setCalleeSavedInfoValid(bool v)
Definition: MachineFrameInfo.h:770
llvm::LiveIntervals::InsertMachineInstrInMaps
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
Definition: LiveIntervals.h:266
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
false
Definition: StackSlotColoring.cpp:142
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::TargetFrameLowering::spillCalleeSavedRegisters
virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
Definition: TargetFrameLowering.h:243
llvm::MachineFrameInfo::getRestorePoint
MachineBasicBlock * getRestorePoint() const
Definition: MachineFrameInfo.h:774
llvm::MachineFrameInfo::getStackID
uint8_t getStackID(int ObjectIdx) const
Definition: MachineFrameInfo.h:699
llvm::MachineInstrSpan::begin
MachineBasicBlock::iterator begin()
Definition: MachineBasicBlock.h:1209
llvm::MachineRegisterInfo::freezeReservedRegs
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Definition: MachineRegisterInfo.cpp:505
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::BitVector
Definition: BitVector.h:74
llvm::SIFrameLowering
Definition: SIFrameLowering.h:16
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::SIMachineFunctionInfo::hasSpilledSGPRs
bool hasSpilledSGPRs() const
Definition: SIMachineFunctionInfo.h:782
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:288
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
insertCSRSaves
static void insertCSRSaves(MachineBasicBlock &SaveBlock, ArrayRef< CalleeSavedInfo > CSI, LiveIntervals *LIS)
Insert restore code for the callee-saved registers used in the function.
Definition: SILowerSGPRSpills.cpp:75
llvm::instructions
inst_range instructions(Function *F)
Definition: InstIterator.h:133
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:282
AMDGPUMCTargetDesc.h
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
LiveIntervals.h
insertCSRRestores
static void insertCSRRestores(MachineBasicBlock &RestoreBlock, MutableArrayRef< CalleeSavedInfo > CSI, LiveIntervals *LIS)
Insert restore code for the callee-saved registers used in the function.
Definition: SILowerSGPRSpills.cpp:115
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::HexagonInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
Definition: HexagonInstrInfo.cpp:954
llvm::MachineRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
Definition: MachineRegisterInfo.cpp:619
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetFrameLowering::restoreCalleeSavedRegisters
virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
Definition: TargetFrameLowering.h:257
llvm::make_early_inc_range
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:642
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:657
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:229
DEBUG_TYPE
#define DEBUG_TYPE
Definition: SILowerSGPRSpills.cpp:28
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:351
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:241
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::HexagonInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
Definition: HexagonInstrInfo.cpp:999
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MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:371
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineFrameInfo::getSavePoint
MachineBasicBlock * getSavePoint() const
Definition: MachineFrameInfo.h:772
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:447
llvm::MachineRegisterInfo::isLiveIn
bool isLiveIn(Register Reg) const
Definition: MachineRegisterInfo.cpp:434
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:607
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:93
llvm::AnalysisUsage::setPreservesAll
void setPreservesAll()
Set by analyses that do not transform their input at all.
Definition: PassAnalysisSupport.h:130
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:34
llvm::MachineBasicBlock::sortUniqueLiveIns
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
Definition: MachineBasicBlock.cpp:585
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@ i32
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llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::TargetStackID::SGPRSpill
@ SGPRSpill
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Definition: SIInstrInfo.h:38
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::SIMachineFunctionInfo::removeDeadFrameIndices
void removeDeadFrameIndices(MachineFrameInfo &MFI)
Definition: SIMachineFunctionInfo.cpp:403
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iterator begin()
Definition: MachineBasicBlock.h:272
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INITIALIZE_PASS_BEGIN(SILowerSGPRSpills, DEBUG_TYPE, "SI lower SGPR spill instructions", false, false) INITIALIZE_PASS_END(SILowerSGPRSpills
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:335
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:211
spill
the custom lowered code happens to be but we shouldn t have to custom lower anything This is probably related to< 2 x i64 > ops being so bad LLVM currently generates stack realignment when it is not necessary needed The problem is that we need to know about stack alignment too before RA runs At that point we don t whether there will be vector spill
Definition: README-SSE.txt:489
RegisterScavenging.h
llvm::MachineInstrBundleIterator< MachineInstr >
InitializePasses.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38