LLVM  15.0.0git
SILowerSGPRSpills.cpp
Go to the documentation of this file.
1 //===-- SILowerSGPRSPills.cpp ---------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Handle SGPR spills. This pass takes the place of PrologEpilogInserter for all
10 // SGPR spills, so must insert CSR SGPR spills as well as expand them.
11 //
12 // This pass must never create new SGPR virtual registers.
13 //
14 // FIXME: Must stop RegScavenger spills in later passes.
15 //
16 //===----------------------------------------------------------------------===//
17 
18 #include "AMDGPU.h"
19 #include "GCNSubtarget.h"
21 #include "SIMachineFunctionInfo.h"
25 #include "llvm/InitializePasses.h"
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "si-lower-sgpr-spills"
30 
32 
33 namespace {
34 
35 class SILowerSGPRSpills : public MachineFunctionPass {
36 private:
37  const SIRegisterInfo *TRI = nullptr;
38  const SIInstrInfo *TII = nullptr;
39  LiveIntervals *LIS = nullptr;
40 
41  // Save and Restore blocks of the current function. Typically there is a
42  // single save block, unless Windows EH funclets are involved.
43  MBBVector SaveBlocks;
44  MBBVector RestoreBlocks;
45 
46 public:
47  static char ID;
48 
49  SILowerSGPRSpills() : MachineFunctionPass(ID) {}
50 
51  void calculateSaveRestoreBlocks(MachineFunction &MF);
52  bool spillCalleeSavedRegs(MachineFunction &MF);
53 
54  bool runOnMachineFunction(MachineFunction &MF) override;
55 
56  void getAnalysisUsage(AnalysisUsage &AU) const override {
57  AU.setPreservesAll();
59  }
60 };
61 
62 } // end anonymous namespace
63 
64 char SILowerSGPRSpills::ID = 0;
65 
66 INITIALIZE_PASS_BEGIN(SILowerSGPRSpills, DEBUG_TYPE,
67  "SI lower SGPR spill instructions", false, false)
70 INITIALIZE_PASS_END(SILowerSGPRSpills, DEBUG_TYPE,
71  "SI lower SGPR spill instructions", false, false)
72 
73 char &llvm::SILowerSGPRSpillsID = SILowerSGPRSpills::ID;
74 
75 /// Insert spill code for the callee-saved registers used in the function.
76 static void insertCSRSaves(MachineBasicBlock &SaveBlock,
78  LiveIntervals *LIS) {
79  MachineFunction &MF = *SaveBlock.getParent();
84  const SIRegisterInfo *RI = ST.getRegisterInfo();
85 
86  MachineBasicBlock::iterator I = SaveBlock.begin();
87  if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) {
88  const MachineRegisterInfo &MRI = MF.getRegInfo();
89 
90  for (const CalleeSavedInfo &CS : CSI) {
91  // Insert the spill to the stack frame.
92  MCRegister Reg = CS.getReg();
93 
94  MachineInstrSpan MIS(I, &SaveBlock);
96  Reg, Reg == RI->getReturnAddressReg(MF) ? MVT::i64 : MVT::i32);
97 
98  // If this value was already livein, we probably have a direct use of the
99  // incoming register value, so don't kill at the spill point. This happens
100  // since we pass some special inputs (workgroup IDs) in the callee saved
101  // range.
102  const bool IsLiveIn = MRI.isLiveIn(Reg);
103  TII.storeRegToStackSlot(SaveBlock, I, Reg, !IsLiveIn, CS.getFrameIdx(),
104  RC, TRI);
105 
106  if (LIS) {
107  assert(std::distance(MIS.begin(), I) == 1);
108  MachineInstr &Inst = *std::prev(I);
109 
110  LIS->InsertMachineInstrInMaps(Inst);
111  LIS->removeAllRegUnitsForPhysReg(Reg);
112  }
113  }
114  }
115 }
116 
117 /// Insert restore code for the callee-saved registers used in the function.
118 static void insertCSRRestores(MachineBasicBlock &RestoreBlock,
120  LiveIntervals *LIS) {
121  MachineFunction &MF = *RestoreBlock.getParent();
122  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
125  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
126  const SIRegisterInfo *RI = ST.getRegisterInfo();
127  // Restore all registers immediately before the return and any
128  // terminators that precede it.
130 
131  // FIXME: Just emit the readlane/writelane directly
132  if (!TFI->restoreCalleeSavedRegisters(RestoreBlock, I, CSI, TRI)) {
133  for (const CalleeSavedInfo &CI : reverse(CSI)) {
134  Register Reg = CI.getReg();
136  Reg, Reg == RI->getReturnAddressReg(MF) ? MVT::i64 : MVT::i32);
137 
138  TII.loadRegFromStackSlot(RestoreBlock, I, Reg, CI.getFrameIdx(), RC, TRI);
139  assert(I != RestoreBlock.begin() &&
140  "loadRegFromStackSlot didn't insert any code!");
141  // Insert in reverse order. loadRegFromStackSlot can insert
142  // multiple instructions.
143 
144  if (LIS) {
145  MachineInstr &Inst = *std::prev(I);
146  LIS->InsertMachineInstrInMaps(Inst);
148  }
149  }
150  }
151 }
152 
153 /// Compute the sets of entry and return blocks for saving and restoring
154 /// callee-saved registers, and placing prolog and epilog code.
155 void SILowerSGPRSpills::calculateSaveRestoreBlocks(MachineFunction &MF) {
156  const MachineFrameInfo &MFI = MF.getFrameInfo();
157 
158  // Even when we do not change any CSR, we still want to insert the
159  // prologue and epilogue of the function.
160  // So set the save points for those.
161 
162  // Use the points found by shrink-wrapping, if any.
163  if (MFI.getSavePoint()) {
164  SaveBlocks.push_back(MFI.getSavePoint());
165  assert(MFI.getRestorePoint() && "Both restore and save must be set");
166  MachineBasicBlock *RestoreBlock = MFI.getRestorePoint();
167  // If RestoreBlock does not have any successor and is not a return block
168  // then the end point is unreachable and we do not need to insert any
169  // epilogue.
170  if (!RestoreBlock->succ_empty() || RestoreBlock->isReturnBlock())
171  RestoreBlocks.push_back(RestoreBlock);
172  return;
173  }
174 
175  // Save refs to entry and return blocks.
176  SaveBlocks.push_back(&MF.front());
177  for (MachineBasicBlock &MBB : MF) {
178  if (MBB.isEHFuncletEntry())
179  SaveBlocks.push_back(&MBB);
180  if (MBB.isReturnBlock())
181  RestoreBlocks.push_back(&MBB);
182  }
183 }
184 
185 // TODO: To support shrink wrapping, this would need to copy
186 // PrologEpilogInserter's updateLiveness.
188  MachineBasicBlock &EntryBB = MF.front();
189 
190  for (const CalleeSavedInfo &CSIReg : CSI)
191  EntryBB.addLiveIn(CSIReg.getReg());
192  EntryBB.sortUniqueLiveIns();
193 }
194 
195 bool SILowerSGPRSpills::spillCalleeSavedRegs(MachineFunction &MF) {
197  const Function &F = MF.getFunction();
198  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
199  const SIFrameLowering *TFI = ST.getFrameLowering();
200  MachineFrameInfo &MFI = MF.getFrameInfo();
201  RegScavenger *RS = nullptr;
202 
203  // Determine which of the registers in the callee save list should be saved.
204  BitVector SavedRegs;
205  TFI->determineCalleeSavesSGPR(MF, SavedRegs, RS);
206 
207  // Add the code to save and restore the callee saved registers.
208  if (!F.hasFnAttribute(Attribute::Naked)) {
209  // FIXME: This is a lie. The CalleeSavedInfo is incomplete, but this is
210  // necessary for verifier liveness checks.
211  MFI.setCalleeSavedInfoValid(true);
212 
213  std::vector<CalleeSavedInfo> CSI;
214  const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
215 
216  for (unsigned I = 0; CSRegs[I]; ++I) {
217  MCRegister Reg = CSRegs[I];
218 
219  if (SavedRegs.test(Reg)) {
220  const TargetRegisterClass *RC =
222  int JunkFI = MFI.CreateStackObject(TRI->getSpillSize(*RC),
223  TRI->getSpillAlign(*RC), true);
224 
225  CSI.push_back(CalleeSavedInfo(Reg, JunkFI));
226  }
227  }
228 
229  if (!CSI.empty()) {
230  for (MachineBasicBlock *SaveBlock : SaveBlocks)
231  insertCSRSaves(*SaveBlock, CSI, LIS);
232 
233  // Add live ins to save blocks.
234  assert(SaveBlocks.size() == 1 && "shrink wrapping not fully implemented");
235  updateLiveness(MF, CSI);
236 
237  for (MachineBasicBlock *RestoreBlock : RestoreBlocks)
238  insertCSRRestores(*RestoreBlock, CSI, LIS);
239  return true;
240  }
241  }
242 
243  return false;
244 }
245 
246 bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) {
247  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
248  TII = ST.getInstrInfo();
249  TRI = &TII->getRegisterInfo();
250 
251  LIS = getAnalysisIfAvailable<LiveIntervals>();
252 
253  assert(SaveBlocks.empty() && RestoreBlocks.empty());
254 
255  // First, expose any CSR SGPR spills. This is mostly the same as what PEI
256  // does, but somewhat simpler.
257  calculateSaveRestoreBlocks(MF);
258  bool HasCSRs = spillCalleeSavedRegs(MF);
259 
260  MachineFrameInfo &MFI = MF.getFrameInfo();
263 
264  if (!MFI.hasStackObjects() && !HasCSRs) {
265  SaveBlocks.clear();
266  RestoreBlocks.clear();
267  return false;
268  }
269 
270  bool MadeChange = false;
271  bool NewReservedRegs = false;
272 
273  // TODO: CSR VGPRs will never be spilled to AGPRs. These can probably be
274  // handled as SpilledToReg in regular PrologEpilogInserter.
275  const bool HasSGPRSpillToVGPR = TRI->spillSGPRToVGPR() &&
276  (HasCSRs || FuncInfo->hasSpilledSGPRs());
277  if (HasSGPRSpillToVGPR) {
278  // Process all SGPR spills before frame offsets are finalized. Ideally SGPRs
279  // are spilled to VGPRs, in which case we can eliminate the stack usage.
280  //
281  // This operates under the assumption that only other SGPR spills are users
282  // of the frame index.
283 
284  // To track the spill frame indices handled in this pass.
285  BitVector SpillFIs(MFI.getObjectIndexEnd(), false);
286 
287  for (MachineBasicBlock &MBB : MF) {
289  if (!TII->isSGPRSpill(MI))
290  continue;
291 
292  int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex();
294  if (FuncInfo->allocateSGPRSpillToVGPR(MF, FI)) {
295  NewReservedRegs = true;
296  bool Spilled = TRI->eliminateSGPRToVGPRSpillFrameIndex(MI, FI,
297  nullptr, LIS);
298  (void)Spilled;
299  assert(Spilled && "failed to spill SGPR to VGPR when allocated");
300  SpillFIs.set(FI);
301  }
302  }
303  }
304 
305  // FIXME: Adding to live-ins redundant with reserving registers.
306  for (MachineBasicBlock &MBB : MF) {
307  for (auto SSpill : FuncInfo->getSGPRSpillVGPRs())
308  MBB.addLiveIn(SSpill.VGPR);
310 
311  // FIXME: The dead frame indices are replaced with a null register from
312  // the debug value instructions. We should instead, update it with the
313  // correct register value. But not sure the register value alone is
314  // adequate to lower the DIExpression. It should be worked out later.
315  for (MachineInstr &MI : MBB) {
316  if (MI.isDebugValue() && MI.getOperand(0).isFI() &&
317  SpillFIs[MI.getOperand(0).getIndex()]) {
318  MI.getOperand(0).ChangeToRegister(Register(), false /*isDef*/);
319  }
320  }
321  }
322 
323  // All those frame indices which are dead by now should be removed from the
324  // function frame. Otherwise, there is a side effect such as re-mapping of
325  // free frame index ids by the later pass(es) like "stack slot coloring"
326  // which in turn could mess-up with the book keeping of "frame index to VGPR
327  // lane".
328  FuncInfo->removeDeadFrameIndices(MFI, /*ResetSGPRSpillStackIDs*/ false);
329 
330  MadeChange = true;
331  }
332 
333  SaveBlocks.clear();
334  RestoreBlocks.clear();
335 
336  // Updated the reserved registers with any VGPRs added for SGPR spills.
337  if (NewReservedRegs)
339 
340  return MadeChange;
341 }
llvm::SIMachineFunctionInfo::getSGPRSpillVGPRs
ArrayRef< SGPRSpillVGPR > getSGPRSpillVGPRs() const
Definition: SIMachineFunctionInfo.h:560
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::SILowerSGPRSpillsID
char & SILowerSGPRSpillsID
Definition: SILowerSGPRSpills.cpp:73
SIMachineFunctionInfo.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::Function
Definition: Function.h:60
llvm::MachineInstrSpan
MachineInstrSpan provides an interface to get an iteration range containing the instruction it was in...
Definition: MachineBasicBlock.h:1213
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::MachineBasicBlock::isEHFuncletEntry
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
Definition: MachineBasicBlock.h:575
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::SIMachineFunctionInfo::allocateSGPRSpillToVGPR
bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI)
Reserve a slice of a VGPR to support spilling for FrameIndex FI.
Definition: SIMachineFunctionInfo.cpp:286
llvm::MachineBasicBlock::isReturnBlock
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
Definition: MachineBasicBlock.h:837
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::LiveIntervals::removeAllRegUnitsForPhysReg
void removeAllRegUnitsForPhysReg(MCRegister Reg)
Remove associated live ranges for the register units associated with Reg.
Definition: LiveIntervals.h:425
llvm::reverse
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
Definition: STLExtras.h:380
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:409
updateLiveness
static void updateLiveness(MachineFunction &MF, ArrayRef< CalleeSavedInfo > CSI)
Definition: SILowerSGPRSpills.cpp:187
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:103
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::MachineFrameInfo::hasStackObjects
bool hasStackObjects() const
Return true if there are any stack objects in this function.
Definition: MachineFrameInfo.h:349
llvm::MachineBasicBlock::push_back
void push_back(MachineInstr *MI)
Definition: MachineBasicBlock.h:875
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:865
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:306
GCNSubtarget.h
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:754
llvm::MachineFrameInfo::setCalleeSavedInfoValid
void setCalleeSavedInfoValid(bool v)
Definition: MachineFrameInfo.h:794
llvm::LiveIntervals::InsertMachineInstrInMaps
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
Definition: LiveIntervals.h:266
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
false
Definition: StackSlotColoring.cpp:141
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::TargetFrameLowering::spillCalleeSavedRegisters
virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
Definition: TargetFrameLowering.h:255
llvm::MachineFrameInfo::getRestorePoint
MachineBasicBlock * getRestorePoint() const
Definition: MachineFrameInfo.h:798
llvm::MachineFrameInfo::getStackID
uint8_t getStackID(int ObjectIdx) const
Definition: MachineFrameInfo.h:723
llvm::MachineInstrSpan::begin
MachineBasicBlock::iterator begin()
Definition: MachineBasicBlock.h:1224
llvm::MachineRegisterInfo::freezeReservedRegs
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Definition: MachineRegisterInfo.cpp:503
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::BitVector
Definition: BitVector.h:75
llvm::SIFrameLowering
Definition: SIFrameLowering.h:16
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::SIMachineFunctionInfo::hasSpilledSGPRs
bool hasSpilledSGPRs() const
Definition: SIMachineFunctionInfo.h:813
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:289
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
insertCSRSaves
static void insertCSRSaves(MachineBasicBlock &SaveBlock, ArrayRef< CalleeSavedInfo > CSI, LiveIntervals *LIS)
Insert spill code for the callee-saved registers used in the function.
Definition: SILowerSGPRSpills.cpp:76
llvm::instructions
inst_range instructions(Function *F)
Definition: InstIterator.h:133
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:283
AMDGPUMCTargetDesc.h
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
LiveIntervals.h
insertCSRRestores
static void insertCSRRestores(MachineBasicBlock &RestoreBlock, MutableArrayRef< CalleeSavedInfo > CSI, LiveIntervals *LIS)
Insert restore code for the callee-saved registers used in the function.
Definition: SILowerSGPRSpills.cpp:118
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::HexagonInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
Definition: HexagonInstrInfo.cpp:955
llvm::MachineRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
Definition: MachineRegisterInfo.cpp:617
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetFrameLowering::restoreCalleeSavedRegisters
virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
Definition: TargetFrameLowering.h:269
llvm::make_early_inc_range
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:618
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
DEBUG_TYPE
#define DEBUG_TYPE
Definition: SILowerSGPRSpills.cpp:29
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:357
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:238
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::HexagonInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
Definition: HexagonInstrInfo.cpp:1000
AMDGPU.h
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:377
llvm::SIMachineFunctionInfo::removeDeadFrameIndices
bool removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs)
If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.
Definition: SIMachineFunctionInfo.cpp:425
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineFrameInfo::getSavePoint
MachineBasicBlock * getSavePoint() const
Definition: MachineFrameInfo.h:796
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:454
llvm::MachineRegisterInfo::isLiveIn
bool isLiveIn(Register Reg) const
Definition: MachineRegisterInfo.cpp:432
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:94
llvm::AnalysisUsage::setPreservesAll
void setPreservesAll()
Set by analyses that do not transform their input at all.
Definition: PassAnalysisSupport.h:130
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:33
llvm::MachineBasicBlock::sortUniqueLiveIns
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
Definition: MachineBasicBlock.cpp:582
MachineFrameInfo.h
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::TargetStackID::SGPRSpill
@ SGPRSpill
Definition: TargetFrameLowering.h:29
llvm::SIInstrInfo
Definition: SIInstrInfo.h:44
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:278
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(SILowerSGPRSpills, DEBUG_TYPE, "SI lower SGPR spill instructions", false, false) INITIALIZE_PASS_END(SILowerSGPRSpills
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:349
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:212
spill
the custom lowered code happens to be but we shouldn t have to custom lower anything This is probably related to< 2 x i64 > ops being so bad LLVM currently generates stack realignment when it is not necessary needed The problem is that we need to know about stack alignment too before RA runs At that point we don t whether there will be vector spill
Definition: README-SSE.txt:489
RegisterScavenging.h
llvm::MachineInstrBundleIterator< MachineInstr >
InitializePasses.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38