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36 #define DEBUG_TYPE "amdgpu-pre-ra-optimizations"
59 return "AMDGPU Pre-RA optimizations";
72 "AMDGPU Pre-RA optimizations",
false,
false)
77 char GCNPreRAOptimizations::
ID = 0;
82 return new GCNPreRAOptimizations();
85 bool GCNPreRAOptimizations::processReg(
Register Reg) {
94 switch (
I.getOpcode()) {
97 case AMDGPU::V_ACCVGPR_WRITE_B32_e64:
107 Register SrcReg =
I.getOperand(1).getReg();
120 Register SrcSubReg =
I.getOperand(1).getSubReg();
122 if (SrcSubReg !=
Def.getOperand(0).getSubReg())
125 if (
Def.getOpcode() == AMDGPU::V_ACCVGPR_WRITE_B32_e64) {
133 I.getOperand(1).setReg(DefSrcMO.
getReg());
134 I.getOperand(1).setSubReg(DefSrcMO.
getSubReg());
139 ModifiedRegs.
insert(SrcReg);
150 case AMDGPU::S_MOV_B32:
151 if (
I.getOperand(0).getReg() !=
Reg || !
I.getOperand(1).isImm() ||
152 I.getNumOperands() != 2)
155 switch (
I.getOperand(0).getSubReg()) {
162 Init |=
I.getOperand(1).getImm() & 0xffffffff;
168 Init |=
static_cast<uint64_t>(
I.getOperand(1).getImm()) << 32;
178 for (
Register RegToUpdate : ModifiedRegs) {
179 LIS->removeInterval(RegToUpdate);
180 LIS->createAndComputeVirtRegInterval(RegToUpdate);
195 LIS->getInstructionIndex(*Def0)))
198 LIS->RemoveMachineInstrFromMaps(*Def0);
199 LIS->RemoveMachineInstrFromMaps(*Def1);
201 TII->get(AMDGPU::S_MOV_B64_IMM_PSEUDO),
Reg)
206 LIS->InsertMachineInstrInMaps(*NewI);
207 LIS->removeInterval(
Reg);
208 LIS->createAndComputeVirtRegInterval(
Reg);
215 bool GCNPreRAOptimizations::runOnMachineFunction(
MachineFunction &MF) {
220 TII =
ST.getInstrInfo();
222 LIS = &getAnalysis<LiveIntervals>();
223 TRI =
ST.getRegisterInfo();
225 bool Changed =
false;
229 if (!LIS->hasInterval(
Reg))
233 (
ST.hasGFX90AInsts() || !
TRI->isAGPRClass(RC)))
236 Changed |= processReg(
Reg);
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void initializeGCNPreRAOptimizationsPass(PassRegistry &)
unsigned getSizeInBits() const
Return the size of the physical register in bits if we are able to determine it.
Reg
All possible values of the reg field in the ModR/M byte.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
INITIALIZE_PASS_BEGIN(GCNPreRAOptimizations, DEBUG_TYPE, "AMDGPU Pre-RA optimizations", false, false) INITIALIZE_PASS_END(GCNPreRAOptimizations
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
unsigned const TargetRegisterInfo * TRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
FunctionPass * createGCNPreRAOptimizationsPass()
static bool isEarlierInstr(SlotIndex A, SlotIndex B)
isEarlierInstr - Return true if A refers to an instruction earlier than B.
Represent the analysis usage information of a pass.
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
iterator_range< def_instr_iterator > def_instructions(Register Reg) const
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Register getReg() const
getReg - Returns the register number.
SI optimize exec mask operations pre RA
StringRef - Represent a constant reference to a string, i.e.
const MachineBasicBlock * getParent() const
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
unsigned getSubReg() const
Function & getFunction()
Return the LLVM function that this machine code represents.
void setPreservesAll()
Set by analyses that do not transform their input at all.
const MCRegisterClass * MC
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
char & GCNPreRAOptimizationsID
FunctionPass class - This class is used to implement most global optimizations.
AnalysisUsage & addRequired()
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.