LLVM 19.0.0git
AMDGPUResourceUsageAnalysis.cpp
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1//===- AMDGPUResourceUsageAnalysis.h ---- analysis of resources -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// \brief Analyzes how many registers and other resources are used by
11/// functions.
12///
13/// The results of this analysis are used to fill the register usage, flat
14/// usage, etc. into hardware registers.
15///
16/// The analysis takes callees into account. E.g. if a function A that needs 10
17/// VGPRs calls a function B that needs 20 VGPRs, querying the VGPR usage of A
18/// will return 20.
19/// It is assumed that an indirect call can go into any function except
20/// hardware-entrypoints. Therefore the register usage of functions with
21/// indirect calls is estimated as the maximum of all non-entrypoint functions
22/// in the module.
23///
24//===----------------------------------------------------------------------===//
25
27#include "AMDGPU.h"
28#include "GCNSubtarget.h"
34#include "llvm/IR/GlobalAlias.h"
35#include "llvm/IR/GlobalValue.h"
37
38using namespace llvm;
39using namespace llvm::AMDGPU;
40
41#define DEBUG_TYPE "amdgpu-resource-usage"
42
45
46// In code object v4 and older, we need to tell the runtime some amount ahead of
47// time if we don't know the true stack size. Assume a smaller number if this is
48// only due to dynamic / non-entry block allocas.
50 "amdgpu-assume-external-call-stack-size",
51 cl::desc("Assumed stack use of any external call (in bytes)"), cl::Hidden,
52 cl::init(16384));
53
55 "amdgpu-assume-dynamic-stack-object-size",
56 cl::desc("Assumed extra stack use if there are any "
57 "variable sized objects (in bytes)"),
58 cl::Hidden, cl::init(4096));
59
61 "Function register usage analysis", true, true)
62
63static const Function *getCalleeFunction(const MachineOperand &Op) {
64 if (Op.isImm()) {
65 assert(Op.getImm() == 0);
66 return nullptr;
67 }
68 if (auto *GA = dyn_cast<GlobalAlias>(Op.getGlobal()))
69 return cast<Function>(GA->getOperand(0));
70 return cast<Function>(Op.getGlobal());
71}
72
74 const SIInstrInfo &TII, unsigned Reg) {
75 for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
76 if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
77 return true;
78 }
79
80 return false;
81}
82
84 const GCNSubtarget &ST) const {
85 return NumExplicitSGPR +
87 ST.getTargetID().isXnackOnOrAny());
88}
89
91 const GCNSubtarget &ST, int32_t ArgNumAGPR, int32_t ArgNumVGPR) const {
92 return AMDGPU::getTotalNumVGPRs(ST.hasGFX90AInsts(), ArgNumAGPR, ArgNumVGPR);
93}
94
96 const GCNSubtarget &ST) const {
97 return getTotalNumVGPRs(ST, NumAGPR, NumVGPR);
98}
99
101 auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
102 if (!TPC)
103 return false;
104
105 MachineModuleInfo &MMI = getAnalysis<MachineModuleInfoWrapperPass>().getMMI();
106 const TargetMachine &TM = TPC->getTM<TargetMachine>();
107 const MCSubtargetInfo &STI = *TM.getMCSubtargetInfo();
108 bool HasIndirectCall = false;
109
110 CallGraph CG = CallGraph(M);
111 auto End = po_end(&CG);
112
113 // By default, for code object v5 and later, track only the minimum scratch
114 // size
115 uint32_t AssumedStackSizeForDynamicSizeObjects =
117 uint32_t AssumedStackSizeForExternalCall = clAssumedStackSizeForExternalCall;
119 STI.getTargetTriple().getOS() == Triple::AMDPAL) {
120 if (clAssumedStackSizeForDynamicSizeObjects.getNumOccurrences() == 0)
121 AssumedStackSizeForDynamicSizeObjects = 0;
122 if (clAssumedStackSizeForExternalCall.getNumOccurrences() == 0)
123 AssumedStackSizeForExternalCall = 0;
124 }
125
126 for (auto IT = po_begin(&CG); IT != End; ++IT) {
127 Function *F = IT->getFunction();
128 if (!F || F->isDeclaration())
129 continue;
130
132 assert(MF && "function must have been generated already");
133
134 auto CI =
135 CallGraphResourceInfo.insert(std::pair(F, SIFunctionResourceInfo()));
136 SIFunctionResourceInfo &Info = CI.first->second;
137 assert(CI.second && "should only be called once per function");
138 Info = analyzeResourceUsage(*MF, TM, AssumedStackSizeForDynamicSizeObjects,
139 AssumedStackSizeForExternalCall);
140 HasIndirectCall |= Info.HasIndirectCall;
141 }
142
143 // It's possible we have unreachable functions in the module which weren't
144 // visited by the PO traversal. Make sure we have some resource counts to
145 // report.
146 for (const auto &IT : CG) {
147 const Function *F = IT.first;
148 if (!F || F->isDeclaration())
149 continue;
150
151 auto CI =
152 CallGraphResourceInfo.insert(std::pair(F, SIFunctionResourceInfo()));
153 if (!CI.second) // Skip already visited functions
154 continue;
155
156 SIFunctionResourceInfo &Info = CI.first->second;
158 assert(MF && "function must have been generated already");
159 Info = analyzeResourceUsage(*MF, TM, AssumedStackSizeForDynamicSizeObjects,
160 AssumedStackSizeForExternalCall);
161 HasIndirectCall |= Info.HasIndirectCall;
162 }
163
164 if (HasIndirectCall)
165 propagateIndirectCallRegisterUsage();
166
167 return false;
168}
169
171AMDGPUResourceUsageAnalysis::analyzeResourceUsage(
172 const MachineFunction &MF, const TargetMachine &TM,
173 uint32_t AssumedStackSizeForDynamicSizeObjects,
174 uint32_t AssumedStackSizeForExternalCall) const {
175 SIFunctionResourceInfo Info;
176
178 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
179 const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
180 const MachineRegisterInfo &MRI = MF.getRegInfo();
181 const SIInstrInfo *TII = ST.getInstrInfo();
182 const SIRegisterInfo &TRI = TII->getRegisterInfo();
183
184 Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
185 MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI) ||
186 MRI.isLiveIn(MFI->getPreloadedReg(
188
189 // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
190 // instructions aren't used to access the scratch buffer. Inline assembly may
191 // need it though.
192 //
193 // If we only have implicit uses of flat_scr on flat instructions, it is not
194 // really needed.
195 if (Info.UsesFlatScratch && !MFI->getUserSGPRInfo().hasFlatScratchInit() &&
196 (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
197 !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
198 !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
199 Info.UsesFlatScratch = false;
200 }
201
202 Info.PrivateSegmentSize = FrameInfo.getStackSize();
203
204 // Assume a big number if there are any unknown sized objects.
205 Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
206 if (Info.HasDynamicallySizedStack)
207 Info.PrivateSegmentSize += AssumedStackSizeForDynamicSizeObjects;
208
209 if (MFI->isStackRealigned())
210 Info.PrivateSegmentSize += FrameInfo.getMaxAlign().value();
211
212 Info.UsesVCC =
213 MRI.isPhysRegUsed(AMDGPU::VCC_LO) || MRI.isPhysRegUsed(AMDGPU::VCC_HI);
214
215 // If there are no calls, MachineRegisterInfo can tell us the used register
216 // count easily.
217 // A tail call isn't considered a call for MachineFrameInfo's purposes.
218 if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
219 MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
220 for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
221 if (MRI.isPhysRegUsed(Reg)) {
222 HighestVGPRReg = Reg;
223 break;
224 }
225 }
226
227 if (ST.hasMAIInsts()) {
228 MCPhysReg HighestAGPRReg = AMDGPU::NoRegister;
229 for (MCPhysReg Reg : reverse(AMDGPU::AGPR_32RegClass.getRegisters())) {
230 if (MRI.isPhysRegUsed(Reg)) {
231 HighestAGPRReg = Reg;
232 break;
233 }
234 }
235 Info.NumAGPR = HighestAGPRReg == AMDGPU::NoRegister
236 ? 0
237 : TRI.getHWRegIndex(HighestAGPRReg) + 1;
238 }
239
240 MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
241 for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
242 if (MRI.isPhysRegUsed(Reg)) {
243 HighestSGPRReg = Reg;
244 break;
245 }
246 }
247
248 // We found the maximum register index. They start at 0, so add one to get
249 // the number of registers.
250 Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister
251 ? 0
252 : TRI.getHWRegIndex(HighestVGPRReg) + 1;
253 Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister
254 ? 0
255 : TRI.getHWRegIndex(HighestSGPRReg) + 1;
256
257 return Info;
258 }
259
260 int32_t MaxVGPR = -1;
261 int32_t MaxAGPR = -1;
262 int32_t MaxSGPR = -1;
263 uint64_t CalleeFrameSize = 0;
264
265 for (const MachineBasicBlock &MBB : MF) {
266 for (const MachineInstr &MI : MBB) {
267 // TODO: Check regmasks? Do they occur anywhere except calls?
268 for (const MachineOperand &MO : MI.operands()) {
269 unsigned Width = 0;
270 bool IsSGPR = false;
271 bool IsAGPR = false;
272
273 if (!MO.isReg())
274 continue;
275
276 Register Reg = MO.getReg();
277 switch (Reg) {
278 case AMDGPU::EXEC:
279 case AMDGPU::EXEC_LO:
280 case AMDGPU::EXEC_HI:
281 case AMDGPU::SCC:
282 case AMDGPU::M0:
283 case AMDGPU::M0_LO16:
284 case AMDGPU::M0_HI16:
285 case AMDGPU::SRC_SHARED_BASE_LO:
286 case AMDGPU::SRC_SHARED_BASE:
287 case AMDGPU::SRC_SHARED_LIMIT_LO:
288 case AMDGPU::SRC_SHARED_LIMIT:
289 case AMDGPU::SRC_PRIVATE_BASE_LO:
290 case AMDGPU::SRC_PRIVATE_BASE:
291 case AMDGPU::SRC_PRIVATE_LIMIT_LO:
292 case AMDGPU::SRC_PRIVATE_LIMIT:
293 case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
294 case AMDGPU::SGPR_NULL:
295 case AMDGPU::SGPR_NULL64:
296 case AMDGPU::MODE:
297 continue;
298
299 case AMDGPU::NoRegister:
300 assert(MI.isDebugInstr() &&
301 "Instruction uses invalid noreg register");
302 continue;
303
304 case AMDGPU::VCC:
305 case AMDGPU::VCC_LO:
306 case AMDGPU::VCC_HI:
307 case AMDGPU::VCC_LO_LO16:
308 case AMDGPU::VCC_LO_HI16:
309 case AMDGPU::VCC_HI_LO16:
310 case AMDGPU::VCC_HI_HI16:
311 Info.UsesVCC = true;
312 continue;
313
314 case AMDGPU::FLAT_SCR:
315 case AMDGPU::FLAT_SCR_LO:
316 case AMDGPU::FLAT_SCR_HI:
317 continue;
318
319 case AMDGPU::XNACK_MASK:
320 case AMDGPU::XNACK_MASK_LO:
321 case AMDGPU::XNACK_MASK_HI:
322 llvm_unreachable("xnack_mask registers should not be used");
323
324 case AMDGPU::LDS_DIRECT:
325 llvm_unreachable("lds_direct register should not be used");
326
327 case AMDGPU::TBA:
328 case AMDGPU::TBA_LO:
329 case AMDGPU::TBA_HI:
330 case AMDGPU::TMA:
331 case AMDGPU::TMA_LO:
332 case AMDGPU::TMA_HI:
333 llvm_unreachable("trap handler registers should not be used");
334
335 case AMDGPU::SRC_VCCZ:
336 llvm_unreachable("src_vccz register should not be used");
337
338 case AMDGPU::SRC_EXECZ:
339 llvm_unreachable("src_execz register should not be used");
340
341 case AMDGPU::SRC_SCC:
342 llvm_unreachable("src_scc register should not be used");
343
344 default:
345 break;
346 }
347
348 if (AMDGPU::SGPR_32RegClass.contains(Reg) ||
349 AMDGPU::SGPR_LO16RegClass.contains(Reg) ||
350 AMDGPU::SGPR_HI16RegClass.contains(Reg)) {
351 IsSGPR = true;
352 Width = 1;
353 } else if (AMDGPU::VGPR_32RegClass.contains(Reg) ||
354 AMDGPU::VGPR_16RegClass.contains(Reg)) {
355 IsSGPR = false;
356 Width = 1;
357 } else if (AMDGPU::AGPR_32RegClass.contains(Reg) ||
358 AMDGPU::AGPR_LO16RegClass.contains(Reg)) {
359 IsSGPR = false;
360 IsAGPR = true;
361 Width = 1;
362 } else if (AMDGPU::SGPR_64RegClass.contains(Reg)) {
363 IsSGPR = true;
364 Width = 2;
365 } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
366 IsSGPR = false;
367 Width = 2;
368 } else if (AMDGPU::AReg_64RegClass.contains(Reg)) {
369 IsSGPR = false;
370 IsAGPR = true;
371 Width = 2;
372 } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
373 IsSGPR = false;
374 Width = 3;
375 } else if (AMDGPU::SReg_96RegClass.contains(Reg)) {
376 IsSGPR = true;
377 Width = 3;
378 } else if (AMDGPU::AReg_96RegClass.contains(Reg)) {
379 IsSGPR = false;
380 IsAGPR = true;
381 Width = 3;
382 } else if (AMDGPU::SGPR_128RegClass.contains(Reg)) {
383 IsSGPR = true;
384 Width = 4;
385 } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
386 IsSGPR = false;
387 Width = 4;
388 } else if (AMDGPU::AReg_128RegClass.contains(Reg)) {
389 IsSGPR = false;
390 IsAGPR = true;
391 Width = 4;
392 } else if (AMDGPU::VReg_160RegClass.contains(Reg)) {
393 IsSGPR = false;
394 Width = 5;
395 } else if (AMDGPU::SReg_160RegClass.contains(Reg)) {
396 IsSGPR = true;
397 Width = 5;
398 } else if (AMDGPU::AReg_160RegClass.contains(Reg)) {
399 IsSGPR = false;
400 IsAGPR = true;
401 Width = 5;
402 } else if (AMDGPU::VReg_192RegClass.contains(Reg)) {
403 IsSGPR = false;
404 Width = 6;
405 } else if (AMDGPU::SReg_192RegClass.contains(Reg)) {
406 IsSGPR = true;
407 Width = 6;
408 } else if (AMDGPU::AReg_192RegClass.contains(Reg)) {
409 IsSGPR = false;
410 IsAGPR = true;
411 Width = 6;
412 } else if (AMDGPU::VReg_224RegClass.contains(Reg)) {
413 IsSGPR = false;
414 Width = 7;
415 } else if (AMDGPU::SReg_224RegClass.contains(Reg)) {
416 IsSGPR = true;
417 Width = 7;
418 } else if (AMDGPU::AReg_224RegClass.contains(Reg)) {
419 IsSGPR = false;
420 IsAGPR = true;
421 Width = 7;
422 } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
423 IsSGPR = true;
424 Width = 8;
425 } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
426 IsSGPR = false;
427 Width = 8;
428 } else if (AMDGPU::AReg_256RegClass.contains(Reg)) {
429 IsSGPR = false;
430 IsAGPR = true;
431 Width = 8;
432 } else if (AMDGPU::VReg_288RegClass.contains(Reg)) {
433 IsSGPR = false;
434 Width = 9;
435 } else if (AMDGPU::SReg_288RegClass.contains(Reg)) {
436 IsSGPR = true;
437 Width = 9;
438 } else if (AMDGPU::AReg_288RegClass.contains(Reg)) {
439 IsSGPR = false;
440 IsAGPR = true;
441 Width = 9;
442 } else if (AMDGPU::VReg_320RegClass.contains(Reg)) {
443 IsSGPR = false;
444 Width = 10;
445 } else if (AMDGPU::SReg_320RegClass.contains(Reg)) {
446 IsSGPR = true;
447 Width = 10;
448 } else if (AMDGPU::AReg_320RegClass.contains(Reg)) {
449 IsSGPR = false;
450 IsAGPR = true;
451 Width = 10;
452 } else if (AMDGPU::VReg_352RegClass.contains(Reg)) {
453 IsSGPR = false;
454 Width = 11;
455 } else if (AMDGPU::SReg_352RegClass.contains(Reg)) {
456 IsSGPR = true;
457 Width = 11;
458 } else if (AMDGPU::AReg_352RegClass.contains(Reg)) {
459 IsSGPR = false;
460 IsAGPR = true;
461 Width = 11;
462 } else if (AMDGPU::VReg_384RegClass.contains(Reg)) {
463 IsSGPR = false;
464 Width = 12;
465 } else if (AMDGPU::SReg_384RegClass.contains(Reg)) {
466 IsSGPR = true;
467 Width = 12;
468 } else if (AMDGPU::AReg_384RegClass.contains(Reg)) {
469 IsSGPR = false;
470 IsAGPR = true;
471 Width = 12;
472 } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
473 IsSGPR = true;
474 Width = 16;
475 } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
476 IsSGPR = false;
477 Width = 16;
478 } else if (AMDGPU::AReg_512RegClass.contains(Reg)) {
479 IsSGPR = false;
480 IsAGPR = true;
481 Width = 16;
482 } else if (AMDGPU::SReg_1024RegClass.contains(Reg)) {
483 IsSGPR = true;
484 Width = 32;
485 } else if (AMDGPU::VReg_1024RegClass.contains(Reg)) {
486 IsSGPR = false;
487 Width = 32;
488 } else if (AMDGPU::AReg_1024RegClass.contains(Reg)) {
489 IsSGPR = false;
490 IsAGPR = true;
491 Width = 32;
492 } else {
493 // We only expect TTMP registers or registers that do not belong to
494 // any RC.
495 assert((AMDGPU::TTMP_32RegClass.contains(Reg) ||
496 AMDGPU::TTMP_64RegClass.contains(Reg) ||
497 AMDGPU::TTMP_128RegClass.contains(Reg) ||
498 AMDGPU::TTMP_256RegClass.contains(Reg) ||
499 AMDGPU::TTMP_512RegClass.contains(Reg) ||
500 !TRI.getPhysRegBaseClass(Reg)) &&
501 "Unknown register class");
502 }
503 unsigned HWReg = TRI.getHWRegIndex(Reg);
504 int MaxUsed = HWReg + Width - 1;
505 if (IsSGPR) {
506 MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
507 } else if (IsAGPR) {
508 MaxAGPR = MaxUsed > MaxAGPR ? MaxUsed : MaxAGPR;
509 } else {
510 MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
511 }
512 }
513
514 if (MI.isCall()) {
515 // Pseudo used just to encode the underlying global. Is there a better
516 // way to track this?
517
518 const MachineOperand *CalleeOp =
519 TII->getNamedOperand(MI, AMDGPU::OpName::callee);
520
521 const Function *Callee = getCalleeFunction(*CalleeOp);
523 CallGraphResourceInfo.end();
524
525 // Avoid crashing on undefined behavior with an illegal call to a
526 // kernel. If a callsite's calling convention doesn't match the
527 // function's, it's undefined behavior. If the callsite calling
528 // convention does match, that would have errored earlier.
529 if (Callee && AMDGPU::isEntryFunctionCC(Callee->getCallingConv()))
530 report_fatal_error("invalid call to entry function");
531
532 bool IsIndirect = !Callee || Callee->isDeclaration();
533 if (!IsIndirect)
534 I = CallGraphResourceInfo.find(Callee);
535
536 // FIXME: Call site could have norecurse on it
537 if (!Callee || !Callee->doesNotRecurse()) {
538 Info.HasRecursion = true;
539
540 // TODO: If we happen to know there is no stack usage in the
541 // callgraph, we don't need to assume an infinitely growing stack.
542 if (!MI.isReturn()) {
543 // We don't need to assume an unknown stack size for tail calls.
544
545 // FIXME: This only benefits in the case where the kernel does not
546 // directly call the tail called function. If a kernel directly
547 // calls a tail recursive function, we'll assume maximum stack size
548 // based on the regular call instruction.
549 CalleeFrameSize = std::max(
550 CalleeFrameSize,
551 static_cast<uint64_t>(AssumedStackSizeForExternalCall));
552 }
553 }
554
555 if (IsIndirect || I == CallGraphResourceInfo.end()) {
556 CalleeFrameSize =
557 std::max(CalleeFrameSize,
558 static_cast<uint64_t>(AssumedStackSizeForExternalCall));
559
560 // Register usage of indirect calls gets handled later
561 Info.UsesVCC = true;
562 Info.UsesFlatScratch = ST.hasFlatAddressSpace();
563 Info.HasDynamicallySizedStack = true;
564 Info.HasIndirectCall = true;
565 } else {
566 // We force CodeGen to run in SCC order, so the callee's register
567 // usage etc. should be the cumulative usage of all callees.
568 MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
569 MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
570 MaxAGPR = std::max(I->second.NumAGPR - 1, MaxAGPR);
571 CalleeFrameSize =
572 std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
573 Info.UsesVCC |= I->second.UsesVCC;
574 Info.UsesFlatScratch |= I->second.UsesFlatScratch;
575 Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
576 Info.HasRecursion |= I->second.HasRecursion;
577 Info.HasIndirectCall |= I->second.HasIndirectCall;
578 }
579 }
580 }
581 }
582
583 Info.NumExplicitSGPR = MaxSGPR + 1;
584 Info.NumVGPR = MaxVGPR + 1;
585 Info.NumAGPR = MaxAGPR + 1;
586 Info.PrivateSegmentSize += CalleeFrameSize;
587
588 return Info;
589}
590
591void AMDGPUResourceUsageAnalysis::propagateIndirectCallRegisterUsage() {
592 // Collect the maximum number of registers from non-hardware-entrypoints.
593 // All these functions are potential targets for indirect calls.
594 int32_t NonKernelMaxSGPRs = 0;
595 int32_t NonKernelMaxVGPRs = 0;
596 int32_t NonKernelMaxAGPRs = 0;
597
598 for (const auto &I : CallGraphResourceInfo) {
599 if (!AMDGPU::isEntryFunctionCC(I.getFirst()->getCallingConv())) {
600 auto &Info = I.getSecond();
601 NonKernelMaxSGPRs = std::max(NonKernelMaxSGPRs, Info.NumExplicitSGPR);
602 NonKernelMaxVGPRs = std::max(NonKernelMaxVGPRs, Info.NumVGPR);
603 NonKernelMaxAGPRs = std::max(NonKernelMaxAGPRs, Info.NumAGPR);
604 }
605 }
606
607 // Add register usage for functions with indirect calls.
608 // For calls to unknown functions, we assume the maximum register usage of
609 // all non-hardware-entrypoints in the current module.
610 for (auto &I : CallGraphResourceInfo) {
611 auto &Info = I.getSecond();
612 if (Info.HasIndirectCall) {
613 Info.NumExplicitSGPR = std::max(Info.NumExplicitSGPR, NonKernelMaxSGPRs);
614 Info.NumVGPR = std::max(Info.NumVGPR, NonKernelMaxVGPRs);
615 Info.NumAGPR = std::max(Info.NumAGPR, NonKernelMaxAGPRs);
616 }
617 }
618}
unsigned const MachineRegisterInfo * MRI
aarch64 promote const
static cl::opt< uint32_t > clAssumedStackSizeForDynamicSizeObjects("amdgpu-assume-dynamic-stack-object-size", cl::desc("Assumed extra stack use if there are any " "variable sized objects (in bytes)"), cl::Hidden, cl::init(4096))
static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI, const SIInstrInfo &TII, unsigned Reg)
static cl::opt< uint32_t > clAssumedStackSizeForExternalCall("amdgpu-assume-external-call-stack-size", cl::desc("Assumed stack use of any external call (in bytes)"), cl::Hidden, cl::init(16384))
#define DEBUG_TYPE
Analyzes how many registers and other resources are used by functions.
MachineBasicBlock & MBB
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::values(clEnumValN(DefaultIT, "arm-default-it", "Generate any type of IT block"), clEnumValN(RestrictedIT, "arm-restrict-it", "Disallow complex IT blocks")))
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
This file provides interfaces used to build and manipulate a call graph, which is a very useful tool ...
bool End
Definition: ELF_riscv.cpp:480
AMD GCN specific subclass of TargetSubtarget.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Target-Independent Code Generator Pass Configuration Options pass.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
The basic data container for the call graph of a Module of IR.
Definition: CallGraph.h:72
This class represents an Operation in the Expression.
Generic base class for all target subtargets.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Representation of each machine instruction.
Definition: MachineInstr.h:69
This class contains meta information specific to a module.
MachineFunction * getMachineFunction(const Function &F) const
Returns the MachineFunction associated to IR function F if there is one, otherwise nullptr.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
GCNUserSGPRUsageInfo & getUserSGPRInfo()
MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
bool isEntryFunctionCC(CallingConv::ID CC)
unsigned getAMDHSACodeObjectVersion(const Module &M)
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
char & AMDGPUResourceUsageAnalysisID
po_iterator< T > po_begin(const T &G)
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:419
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
po_iterator< T > po_end(const T &G)
int32_t getTotalNumVGPRs(const GCNSubtarget &ST, int32_t NumAGPR, int32_t NumVGPR) const
bool runOnModule(Module &M) override
runOnModule - Virtual method overriden by subclasses to process the module being operated on.