LLVM  14.0.0git
AMDGPUPostLegalizerCombiner.cpp
Go to the documentation of this file.
1 //=== lib/CodeGen/GlobalISel/AMDGPUPostLegalizerCombiner.cpp ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass does combining of machine instructions at the generic MI level,
10 // after the legalizer.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AMDGPU.h"
15 #include "AMDGPUCombinerHelper.h"
16 #include "AMDGPULegalizerInfo.h"
17 #include "GCNSubtarget.h"
27 
28 #define DEBUG_TYPE "amdgpu-postlegalizer-combiner"
29 
30 using namespace llvm;
31 using namespace MIPatternMatch;
32 
34 protected:
39 
40 public:
42  AMDGPUCombinerHelper &Helper)
43  : B(B), MF(B.getMF()), MRI(*B.getMRI()), Helper(Helper){};
44 
51  };
52 
53  // TODO: Make sure fmin_legacy/fmax_legacy don't canonicalize
54  bool matchFMinFMaxLegacy(MachineInstr &MI, FMinFMaxLegacyInfo &Info);
55  void applySelectFCmpToFMinToFMaxLegacy(MachineInstr &MI,
56  const FMinFMaxLegacyInfo &Info);
57 
58  bool matchUCharToFloat(MachineInstr &MI);
59  void applyUCharToFloat(MachineInstr &MI);
60 
61  // FIXME: Should be able to have 2 separate matchdatas rather than custom
62  // struct boilerplate.
65  unsigned ShiftOffset;
66  };
67 
68  bool matchCvtF32UByteN(MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo);
69  void applyCvtF32UByteN(MachineInstr &MI,
70  const CvtF32UByteMatchInfo &MatchInfo);
71 
72  bool matchRemoveFcanonicalize(MachineInstr &MI, Register &Reg);
73 };
74 
77  // FIXME: Combines should have subtarget predicates, and we shouldn't need
78  // this here.
79  if (!MF.getSubtarget<GCNSubtarget>().hasFminFmaxLegacy())
80  return false;
81 
82  // FIXME: Type predicate on pattern
83  if (MRI.getType(MI.getOperand(0).getReg()) != LLT::scalar(32))
84  return false;
85 
86  Register Cond = MI.getOperand(1).getReg();
87  if (!MRI.hasOneNonDBGUse(Cond) ||
88  !mi_match(Cond, MRI,
89  m_GFCmp(m_Pred(Info.Pred), m_Reg(Info.LHS), m_Reg(Info.RHS))))
90  return false;
91 
92  Info.True = MI.getOperand(2).getReg();
93  Info.False = MI.getOperand(3).getReg();
94 
95  if (!(Info.LHS == Info.True && Info.RHS == Info.False) &&
96  !(Info.LHS == Info.False && Info.RHS == Info.True))
97  return false;
98 
99  switch (Info.Pred) {
100  case CmpInst::FCMP_FALSE:
101  case CmpInst::FCMP_OEQ:
102  case CmpInst::FCMP_ONE:
103  case CmpInst::FCMP_ORD:
104  case CmpInst::FCMP_UNO:
105  case CmpInst::FCMP_UEQ:
106  case CmpInst::FCMP_UNE:
107  case CmpInst::FCMP_TRUE:
108  return false;
109  default:
110  return true;
111  }
112 }
113 
116  B.setInstrAndDebugLoc(MI);
117  auto buildNewInst = [&MI, this](unsigned Opc, Register X, Register Y) {
118  B.buildInstr(Opc, {MI.getOperand(0)}, {X, Y}, MI.getFlags());
119  };
120 
121  switch (Info.Pred) {
122  case CmpInst::FCMP_ULT:
123  case CmpInst::FCMP_ULE:
124  if (Info.LHS == Info.True)
125  buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.RHS, Info.LHS);
126  else
127  buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.LHS, Info.RHS);
128  break;
129  case CmpInst::FCMP_OLE:
130  case CmpInst::FCMP_OLT: {
131  // We need to permute the operands to get the correct NaN behavior. The
132  // selected operand is the second one based on the failing compare with NaN,
133  // so permute it based on the compare type the hardware uses.
134  if (Info.LHS == Info.True)
135  buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.LHS, Info.RHS);
136  else
137  buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.RHS, Info.LHS);
138  break;
139  }
140  case CmpInst::FCMP_UGE:
141  case CmpInst::FCMP_UGT: {
142  if (Info.LHS == Info.True)
143  buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.RHS, Info.LHS);
144  else
145  buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.LHS, Info.RHS);
146  break;
147  }
148  case CmpInst::FCMP_OGT:
149  case CmpInst::FCMP_OGE: {
150  if (Info.LHS == Info.True)
151  buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.LHS, Info.RHS);
152  else
153  buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.RHS, Info.LHS);
154  break;
155  }
156  default:
157  llvm_unreachable("predicate should not have matched");
158  }
159 
160  MI.eraseFromParent();
161 }
162 
164  Register DstReg = MI.getOperand(0).getReg();
165 
166  // TODO: We could try to match extracting the higher bytes, which would be
167  // easier if i8 vectors weren't promoted to i32 vectors, particularly after
168  // types are legalized. v4i8 -> v4f32 is probably the only case to worry
169  // about in practice.
170  LLT Ty = MRI.getType(DstReg);
171  if (Ty == LLT::scalar(32) || Ty == LLT::scalar(16)) {
172  Register SrcReg = MI.getOperand(1).getReg();
173  unsigned SrcSize = MRI.getType(SrcReg).getSizeInBits();
174  assert(SrcSize == 16 || SrcSize == 32 || SrcSize == 64);
175  const APInt Mask = APInt::getHighBitsSet(SrcSize, SrcSize - 8);
176  return Helper.getKnownBits()->maskedValueIsZero(SrcReg, Mask);
177  }
178 
179  return false;
180 }
181 
183  B.setInstrAndDebugLoc(MI);
184 
185  const LLT S32 = LLT::scalar(32);
186 
187  Register DstReg = MI.getOperand(0).getReg();
188  Register SrcReg = MI.getOperand(1).getReg();
189  LLT Ty = MRI.getType(DstReg);
190  LLT SrcTy = MRI.getType(SrcReg);
191  if (SrcTy != S32)
192  SrcReg = B.buildAnyExtOrTrunc(S32, SrcReg).getReg(0);
193 
194  if (Ty == S32) {
195  B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {DstReg},
196  {SrcReg}, MI.getFlags());
197  } else {
198  auto Cvt0 = B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {S32},
199  {SrcReg}, MI.getFlags());
200  B.buildFPTrunc(DstReg, Cvt0, MI.getFlags());
201  }
202 
203  MI.eraseFromParent();
204 }
205 
207  MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo) {
208  Register SrcReg = MI.getOperand(1).getReg();
209 
210  // Look through G_ZEXT.
211  mi_match(SrcReg, MRI, m_GZExt(m_Reg(SrcReg)));
212 
213  Register Src0;
214  int64_t ShiftAmt;
215  bool IsShr = mi_match(SrcReg, MRI, m_GLShr(m_Reg(Src0), m_ICst(ShiftAmt)));
216  if (IsShr || mi_match(SrcReg, MRI, m_GShl(m_Reg(Src0), m_ICst(ShiftAmt)))) {
217  const unsigned Offset = MI.getOpcode() - AMDGPU::G_AMDGPU_CVT_F32_UBYTE0;
218 
219  unsigned ShiftOffset = 8 * Offset;
220  if (IsShr)
221  ShiftOffset += ShiftAmt;
222  else
223  ShiftOffset -= ShiftAmt;
224 
225  MatchInfo.CvtVal = Src0;
226  MatchInfo.ShiftOffset = ShiftOffset;
227  return ShiftOffset < 32 && ShiftOffset >= 8 && (ShiftOffset % 8) == 0;
228  }
229 
230  // TODO: Simplify demanded bits.
231  return false;
232 }
233 
235  MachineInstr &MI, const CvtF32UByteMatchInfo &MatchInfo) {
236  B.setInstrAndDebugLoc(MI);
237  unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8;
238 
239  const LLT S32 = LLT::scalar(32);
240  Register CvtSrc = MatchInfo.CvtVal;
241  LLT SrcTy = MRI.getType(MatchInfo.CvtVal);
242  if (SrcTy != S32) {
243  assert(SrcTy.isScalar() && SrcTy.getSizeInBits() >= 8);
244  CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0);
245  }
246 
247  assert(MI.getOpcode() != NewOpc);
248  B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags());
249  MI.eraseFromParent();
250 }
251 
254  const SITargetLowering *TLI = static_cast<const SITargetLowering *>(
255  MF.getSubtarget().getTargetLowering());
256  Reg = MI.getOperand(1).getReg();
257  return TLI->isCanonicalized(Reg, MF);
258 }
259 
261 protected:
264 
265 public:
267  AMDGPUCombinerHelper &Helper,
268  AMDGPUPostLegalizerCombinerHelper &PostLegalizerHelper)
269  : Helper(Helper), PostLegalizerHelper(PostLegalizerHelper) {}
270 };
271 
272 #define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
273 #include "AMDGPUGenPostLegalizeGICombiner.inc"
274 #undef AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
275 
276 namespace {
277 #define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
278 #include "AMDGPUGenPostLegalizeGICombiner.inc"
279 #undef AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
280 
281 class AMDGPUPostLegalizerCombinerInfo final : public CombinerInfo {
282  GISelKnownBits *KB;
284 
285 public:
286  AMDGPUGenPostLegalizerCombinerHelperRuleConfig GeneratedRuleCfg;
287 
288  AMDGPUPostLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
289  const AMDGPULegalizerInfo *LI,
291  : CombinerInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true,
292  /*LegalizerInfo*/ LI, EnableOpt, OptSize, MinSize),
293  KB(KB), MDT(MDT) {
294  if (!GeneratedRuleCfg.parseCommandLineOption())
295  report_fatal_error("Invalid rule identifier");
296  }
297 
298  bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
299  MachineIRBuilder &B) const override;
300 };
301 
303  MachineInstr &MI,
304  MachineIRBuilder &B) const {
305  AMDGPUCombinerHelper Helper(Observer, B, KB, MDT, LInfo);
306  AMDGPUPostLegalizerCombinerHelper PostLegalizerHelper(B, Helper);
307  AMDGPUGenPostLegalizerCombinerHelper Generated(GeneratedRuleCfg, Helper,
308  PostLegalizerHelper);
309 
310  if (Generated.tryCombineAll(Observer, MI, B))
311  return true;
312 
313  switch (MI.getOpcode()) {
314  case TargetOpcode::G_SHL:
315  case TargetOpcode::G_LSHR:
316  case TargetOpcode::G_ASHR:
317  // On some subtargets, 64-bit shift is a quarter rate instruction. In the
318  // common case, splitting this into a move and a 32-bit shift is faster and
319  // the same code size.
320  return Helper.tryCombineShiftToUnmerge(MI, 32);
321  }
322 
323  return false;
324 }
325 
326 #define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
327 #include "AMDGPUGenPostLegalizeGICombiner.inc"
328 #undef AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
329 
330 // Pass boilerplate
331 // ================
332 
333 class AMDGPUPostLegalizerCombiner : public MachineFunctionPass {
334 public:
335  static char ID;
336 
337  AMDGPUPostLegalizerCombiner(bool IsOptNone = false);
338 
339  StringRef getPassName() const override {
340  return "AMDGPUPostLegalizerCombiner";
341  }
342 
343  bool runOnMachineFunction(MachineFunction &MF) override;
344 
345  void getAnalysisUsage(AnalysisUsage &AU) const override;
346 private:
347  bool IsOptNone;
348 };
349 } // end anonymous namespace
350 
351 void AMDGPUPostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
353  AU.setPreservesCFG();
357  if (!IsOptNone) {
360  }
362 }
363 
364 AMDGPUPostLegalizerCombiner::AMDGPUPostLegalizerCombiner(bool IsOptNone)
365  : MachineFunctionPass(ID), IsOptNone(IsOptNone) {
366  initializeAMDGPUPostLegalizerCombinerPass(*PassRegistry::getPassRegistry());
367 }
368 
369 bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
370  if (MF.getProperties().hasProperty(
371  MachineFunctionProperties::Property::FailedISel))
372  return false;
373  auto *TPC = &getAnalysis<TargetPassConfig>();
374  const Function &F = MF.getFunction();
375  bool EnableOpt =
376  MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
377 
378  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
379  const AMDGPULegalizerInfo *LI
380  = static_cast<const AMDGPULegalizerInfo *>(ST.getLegalizerInfo());
381 
382  GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
383  MachineDominatorTree *MDT =
384  IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>();
385  AMDGPUPostLegalizerCombinerInfo PCInfo(EnableOpt, F.hasOptSize(),
386  F.hasMinSize(), LI, KB, MDT);
387  Combiner C(PCInfo, TPC);
388  return C.combineMachineInstrs(MF, /*CSEInfo*/ nullptr);
389 }
390 
392 INITIALIZE_PASS_BEGIN(AMDGPUPostLegalizerCombiner, DEBUG_TYPE,
393  "Combine AMDGPU machine instrs after legalization",
394  false, false)
397 INITIALIZE_PASS_END(AMDGPUPostLegalizerCombiner, DEBUG_TYPE,
398  "Combine AMDGPU machine instrs after legalization", false,
399  false)
400 
401 namespace llvm {
403  return new AMDGPUPostLegalizerCombiner(IsOptNone);
404 }
405 } // end namespace llvm
AMDGPUCombinerHelper
Definition: AMDGPUCombinerHelper.h:20
MIPatternMatch.h
llvm::CmpInst::FCMP_ULE
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
Definition: InstrTypes.h:736
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:188
CombinerInfo.h
llvm::MachineFunctionProperties::hasProperty
bool hasProperty(Property P) const
Definition: MachineFunction.h:169
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::initializeAMDGPUPostLegalizerCombinerPass
void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &)
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:721
llvm::MIPatternMatch::m_Reg
operand_type_match m_Reg()
Definition: MIPatternMatch.h:152
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MIPatternMatch::m_GShl
BinaryOp_match< LHS, RHS, TargetOpcode::G_SHL, false > m_GShl(const LHS &L, const RHS &R)
Definition: MIPatternMatch.h:382
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
AMDGPUPostLegalizerCombinerHelper::matchCvtF32UByteN
bool matchCvtF32UByteN(MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo)
Definition: AMDGPUPostLegalizerCombiner.cpp:206
llvm::Function
Definition: Function.h:62
AMDGPUPostLegalizerCombinerHelper::FMinFMaxLegacyInfo
Definition: AMDGPUPostLegalizerCombiner.cpp:45
llvm::MIPatternMatch::m_GLShr
BinaryOp_match< LHS, RHS, TargetOpcode::G_LSHR, false > m_GLShr(const LHS &L, const RHS &R)
Definition: MIPatternMatch.h:388
AMDGPUPostLegalizerCombinerHelperState
Definition: AMDGPUPostLegalizerCombiner.cpp:260
llvm::CmpInst::FCMP_ONE
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
Definition: InstrTypes.h:729
GISelKnownBits.h
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
AMDGPUPostLegalizerCombinerHelperState::AMDGPUPostLegalizerCombinerHelperState
AMDGPUPostLegalizerCombinerHelperState(AMDGPUCombinerHelper &Helper, AMDGPUPostLegalizerCombinerHelper &PostLegalizerHelper)
Definition: AMDGPUPostLegalizerCombiner.cpp:266
llvm::createAMDGPUPostLegalizeCombiner
FunctionPass * createAMDGPUPostLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPostLegalizerCombiner.cpp:402
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::getSelectionDAGFallbackAnalysisUsage
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:870
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::CombinerInfo
Definition: CombinerInfo.h:27
llvm::CmpInst::FCMP_OGT
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:725
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
llvm::AMDGPULegalizerInfo
This class provides the information for the target register banks.
Definition: AMDGPULegalizerInfo.h:32
AMDGPUPostLegalizerCombinerHelper::matchRemoveFcanonicalize
bool matchRemoveFcanonicalize(MachineInstr &MI, Register &Reg)
Definition: AMDGPUPostLegalizerCombiner.cpp:252
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::CmpInst::FCMP_ULT
@ FCMP_ULT
1 1 0 0 True if unordered or less than
Definition: InstrTypes.h:735
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(AMDGPUPostLegalizerCombiner, DEBUG_TYPE, "Combine AMDGPU machine instrs after legalization", false, false) INITIALIZE_PASS_END(AMDGPUPostLegalizerCombiner
AMDGPUPostLegalizerCombinerHelper::AMDGPUPostLegalizerCombinerHelper
AMDGPUPostLegalizerCombinerHelper(MachineIRBuilder &B, AMDGPUCombinerHelper &Helper)
Definition: AMDGPUPostLegalizerCombiner.cpp:41
llvm::GISelKnownBitsAnalysis
To use KnownBitsInfo analysis in a pass, KnownBitsInfo &Info = getAnalysis<GISelKnownBitsInfoAnalysis...
Definition: GISelKnownBits.h:113
TargetMachine.h
llvm::MIPatternMatch::m_GZExt
UnaryOp_match< SrcTy, TargetOpcode::G_ZEXT > m_GZExt(const SrcTy &Src)
Definition: MIPatternMatch.h:439
GCNSubtarget.h
AMDGPUPostLegalizerCombinerHelper::applyUCharToFloat
void applyUCharToFloat(MachineInstr &MI)
Definition: AMDGPUPostLegalizerCombiner.cpp:182
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:153
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::CmpInst::FCMP_UGE
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
Definition: InstrTypes.h:734
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:725
false
Definition: StackSlotColoring.cpp:142
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::CmpInst::FCMP_UNO
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition: InstrTypes.h:731
AMDGPUPostLegalizerCombinerHelper::applyCvtF32UByteN
void applyCvtF32UByteN(MachineInstr &MI, const CvtF32UByteMatchInfo &MatchInfo)
Definition: AMDGPUPostLegalizerCombiner.cpp:234
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::APInt::getHighBitsSet
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
Definition: APInt.h:279
AMDGPUPostLegalizerCombinerHelperState::PostLegalizerHelper
AMDGPUPostLegalizerCombinerHelper & PostLegalizerHelper
Definition: AMDGPUPostLegalizerCombiner.cpp:263
DEBUG_TYPE
#define DEBUG_TYPE
Definition: AMDGPUPostLegalizerCombiner.cpp:28
llvm::CmpInst::FCMP_OEQ
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:724
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::CmpInst::FCMP_OLT
@ FCMP_OLT
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:727
llvm::MIPatternMatch::m_Pred
bind_ty< CmpInst::Predicate > m_Pred(CmpInst::Predicate &P)
Definition: MIPatternMatch.h:254
AMDGPUPostLegalizerCombinerHelper::Helper
AMDGPUCombinerHelper & Helper
Definition: AMDGPUPostLegalizerCombiner.cpp:38
llvm::None
const NoneType None
Definition: None.h:23
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
AMDGPUPostLegalizerCombinerHelper::matchUCharToFloat
bool matchUCharToFloat(MachineInstr &MI)
Definition: AMDGPUPostLegalizerCombiner.cpp:163
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::CmpInst::FCMP_FALSE
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:723
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:634
AMDGPUPostLegalizerCombinerHelper::FMinFMaxLegacyInfo::False
Register False
Definition: AMDGPUPostLegalizerCombiner.cpp:49
Combine
Hexagon Vector Combine
Definition: HexagonVectorCombine.cpp:1524
AMDGPUMCTargetDesc.h
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:212
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::Combiner
Definition: Combiner.h:27
AMDGPUPostLegalizerCombinerHelper::matchFMinFMaxLegacy
bool matchFMinFMaxLegacy(MachineInstr &MI, FMinFMaxLegacyInfo &Info)
Definition: AMDGPUPostLegalizerCombiner.cpp:75
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
TargetPassConfig.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::CmpInst::FCMP_OGE
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:726
llvm::LLT::isScalar
bool isScalar() const
Definition: LowLevelTypeImpl.h:119
llvm::AMDGPUSubtarget::hasFminFmaxLegacy
bool hasFminFmaxLegacy() const
Definition: AMDGPUSubtarget.h:184
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:234
CombinerHelper.h
AMDGPUPostLegalizerCombinerHelper::MF
MachineFunction & MF
Definition: AMDGPUPostLegalizerCombiner.cpp:36
AMDGPUPostLegalizerCombinerHelper::FMinFMaxLegacyInfo::Pred
CmpInst::Predicate Pred
Definition: AMDGPUPostLegalizerCombiner.cpp:50
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:253
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
AMDGPU.h
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:417
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
Combiner.h
AMDGPUPostLegalizerCombinerHelper::applySelectFCmpToFMinToFMaxLegacy
void applySelectFCmpToFMinToFMaxLegacy(MachineInstr &MI, const FMinFMaxLegacyInfo &Info)
Definition: AMDGPUPostLegalizerCombiner.cpp:114
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::CmpInst::FCMP_UGT
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
Definition: InstrTypes.h:733
AMDGPUPostLegalizerCombinerHelper::B
MachineIRBuilder & B
Definition: AMDGPUPostLegalizerCombiner.cpp:35
AMDGPUPostLegalizerCombinerHelper::FMinFMaxLegacyInfo::True
Register True
Definition: AMDGPUPostLegalizerCombiner.cpp:48
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:600
llvm::MIPatternMatch::m_GFCmp
CompareOp_match< Pred, LHS, RHS, TargetOpcode::G_FCMP > m_GFCmp(const Pred &P, const LHS &L, const RHS &R)
Definition: MIPatternMatch.h:527
AMDGPUPostLegalizerCombinerHelper::CvtF32UByteMatchInfo::ShiftOffset
unsigned ShiftOffset
Definition: AMDGPUPostLegalizerCombiner.cpp:65
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:630
llvm::SITargetLowering
Definition: SIISelLowering.h:31
legalization
Combine AMDGPU machine instrs after legalization
Definition: AMDGPUPostLegalizerCombiner.cpp:398
AMDGPUPostLegalizerCombinerHelper
Definition: AMDGPUPostLegalizerCombiner.cpp:33
AMDGPUPostLegalizerCombinerHelperState::Helper
AMDGPUCombinerHelper & Helper
Definition: AMDGPUPostLegalizerCombiner.cpp:262
AMDGPUPostLegalizerCombinerHelper::FMinFMaxLegacyInfo::RHS
Register RHS
Definition: AMDGPUPostLegalizerCombiner.cpp:47
AMDGPUPostLegalizerCombinerHelper::CvtF32UByteMatchInfo::CvtVal
Register CvtVal
Definition: AMDGPUPostLegalizerCombiner.cpp:64
llvm::MIPatternMatch::m_ICst
ConstantMatch m_ICst(int64_t &Cst)
Definition: MIPatternMatch.h:74
AMDGPUPostLegalizerCombinerHelper::MRI
MachineRegisterInfo & MRI
Definition: AMDGPUPostLegalizerCombiner.cpp:37
AMDGPUPostLegalizerCombinerHelper::FMinFMaxLegacyInfo::LHS
Register LHS
Definition: AMDGPUPostLegalizerCombiner.cpp:46
AMDGPULegalizerInfo.h
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
AMDGPUCombinerHelper.h
llvm::CmpInst::FCMP_UNE
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:737
AMDGPUPostLegalizerCombinerHelper::CvtF32UByteMatchInfo
Definition: AMDGPUPostLegalizerCombiner.cpp:63
llvm::CmpInst::FCMP_OLE
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:728
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::MIPatternMatch::mi_match
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
Definition: MIPatternMatch.h:24
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:46
combine
vector combine
Definition: VectorCombine.cpp:1217
llvm::CmpInst::FCMP_TRUE
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:738
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:43
llvm::CmpInst::FCMP_ORD
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
Definition: InstrTypes.h:730
llvm::SITargetLowering::isCanonicalized
bool isCanonicalized(SelectionDAG &DAG, SDValue Op, unsigned MaxDepth=5) const
Definition: SIISelLowering.cpp:9670
llvm::CmpInst::FCMP_UEQ
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
Definition: InstrTypes.h:732
machine
coro Split coroutine into a set of functions driving its state machine
Definition: CoroSplit.cpp:2275
MachineDominators.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::LLT
Definition: LowLevelTypeImpl.h:40