LLVM  15.0.0git
AMDGPUPostLegalizerCombiner.cpp
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1 //=== lib/CodeGen/GlobalISel/AMDGPUPostLegalizerCombiner.cpp ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass does combining of machine instructions at the generic MI level,
10 // after the legalizer.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AMDGPU.h"
15 #include "AMDGPUCombinerHelper.h"
16 #include "AMDGPULegalizerInfo.h"
17 #include "GCNSubtarget.h"
26 #include "llvm/IR/IntrinsicsAMDGPU.h"
28 
29 #define DEBUG_TYPE "amdgpu-postlegalizer-combiner"
30 
31 using namespace llvm;
32 using namespace MIPatternMatch;
33 
35 protected:
40 
41 public:
43  AMDGPUCombinerHelper &Helper)
44  : B(B), MF(B.getMF()), MRI(*B.getMRI()), Helper(Helper){};
45 
52  };
53 
54  // TODO: Make sure fmin_legacy/fmax_legacy don't canonicalize
55  bool matchFMinFMaxLegacy(MachineInstr &MI, FMinFMaxLegacyInfo &Info);
56  void applySelectFCmpToFMinToFMaxLegacy(MachineInstr &MI,
57  const FMinFMaxLegacyInfo &Info);
58 
59  bool matchUCharToFloat(MachineInstr &MI);
60  void applyUCharToFloat(MachineInstr &MI);
61 
62  bool matchRcpSqrtToRsq(MachineInstr &MI,
63  std::function<void(MachineIRBuilder &)> &MatchInfo);
64 
65  // FIXME: Should be able to have 2 separate matchdatas rather than custom
66  // struct boilerplate.
69  unsigned ShiftOffset;
70  };
71 
72  bool matchCvtF32UByteN(MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo);
73  void applyCvtF32UByteN(MachineInstr &MI,
74  const CvtF32UByteMatchInfo &MatchInfo);
75 
76  bool matchRemoveFcanonicalize(MachineInstr &MI, Register &Reg);
77 };
78 
81  // FIXME: Combines should have subtarget predicates, and we shouldn't need
82  // this here.
84  return false;
85 
86  // FIXME: Type predicate on pattern
87  if (MRI.getType(MI.getOperand(0).getReg()) != LLT::scalar(32))
88  return false;
89 
90  Register Cond = MI.getOperand(1).getReg();
91  if (!MRI.hasOneNonDBGUse(Cond) ||
92  !mi_match(Cond, MRI,
93  m_GFCmp(m_Pred(Info.Pred), m_Reg(Info.LHS), m_Reg(Info.RHS))))
94  return false;
95 
96  Info.True = MI.getOperand(2).getReg();
97  Info.False = MI.getOperand(3).getReg();
98 
99  if (!(Info.LHS == Info.True && Info.RHS == Info.False) &&
100  !(Info.LHS == Info.False && Info.RHS == Info.True))
101  return false;
102 
103  switch (Info.Pred) {
104  case CmpInst::FCMP_FALSE:
105  case CmpInst::FCMP_OEQ:
106  case CmpInst::FCMP_ONE:
107  case CmpInst::FCMP_ORD:
108  case CmpInst::FCMP_UNO:
109  case CmpInst::FCMP_UEQ:
110  case CmpInst::FCMP_UNE:
111  case CmpInst::FCMP_TRUE:
112  return false;
113  default:
114  return true;
115  }
116 }
117 
120  B.setInstrAndDebugLoc(MI);
121  auto buildNewInst = [&MI, this](unsigned Opc, Register X, Register Y) {
122  B.buildInstr(Opc, {MI.getOperand(0)}, {X, Y}, MI.getFlags());
123  };
124 
125  switch (Info.Pred) {
126  case CmpInst::FCMP_ULT:
127  case CmpInst::FCMP_ULE:
128  if (Info.LHS == Info.True)
129  buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.RHS, Info.LHS);
130  else
131  buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.LHS, Info.RHS);
132  break;
133  case CmpInst::FCMP_OLE:
134  case CmpInst::FCMP_OLT: {
135  // We need to permute the operands to get the correct NaN behavior. The
136  // selected operand is the second one based on the failing compare with NaN,
137  // so permute it based on the compare type the hardware uses.
138  if (Info.LHS == Info.True)
139  buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.LHS, Info.RHS);
140  else
141  buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.RHS, Info.LHS);
142  break;
143  }
144  case CmpInst::FCMP_UGE:
145  case CmpInst::FCMP_UGT: {
146  if (Info.LHS == Info.True)
147  buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.RHS, Info.LHS);
148  else
149  buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.LHS, Info.RHS);
150  break;
151  }
152  case CmpInst::FCMP_OGT:
153  case CmpInst::FCMP_OGE: {
154  if (Info.LHS == Info.True)
155  buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.LHS, Info.RHS);
156  else
157  buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.RHS, Info.LHS);
158  break;
159  }
160  default:
161  llvm_unreachable("predicate should not have matched");
162  }
163 
164  MI.eraseFromParent();
165 }
166 
168  Register DstReg = MI.getOperand(0).getReg();
169 
170  // TODO: We could try to match extracting the higher bytes, which would be
171  // easier if i8 vectors weren't promoted to i32 vectors, particularly after
172  // types are legalized. v4i8 -> v4f32 is probably the only case to worry
173  // about in practice.
174  LLT Ty = MRI.getType(DstReg);
175  if (Ty == LLT::scalar(32) || Ty == LLT::scalar(16)) {
176  Register SrcReg = MI.getOperand(1).getReg();
177  unsigned SrcSize = MRI.getType(SrcReg).getSizeInBits();
178  assert(SrcSize == 16 || SrcSize == 32 || SrcSize == 64);
179  const APInt Mask = APInt::getHighBitsSet(SrcSize, SrcSize - 8);
180  return Helper.getKnownBits()->maskedValueIsZero(SrcReg, Mask);
181  }
182 
183  return false;
184 }
185 
187  B.setInstrAndDebugLoc(MI);
188 
189  const LLT S32 = LLT::scalar(32);
190 
191  Register DstReg = MI.getOperand(0).getReg();
192  Register SrcReg = MI.getOperand(1).getReg();
193  LLT Ty = MRI.getType(DstReg);
194  LLT SrcTy = MRI.getType(SrcReg);
195  if (SrcTy != S32)
196  SrcReg = B.buildAnyExtOrTrunc(S32, SrcReg).getReg(0);
197 
198  if (Ty == S32) {
199  B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {DstReg},
200  {SrcReg}, MI.getFlags());
201  } else {
202  auto Cvt0 = B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {S32},
203  {SrcReg}, MI.getFlags());
204  B.buildFPTrunc(DstReg, Cvt0, MI.getFlags());
205  }
206 
207  MI.eraseFromParent();
208 }
209 
211  MachineInstr &MI, std::function<void(MachineIRBuilder &)> &MatchInfo) {
212 
213  auto getRcpSrc = [=](const MachineInstr &MI) {
214  MachineInstr *ResMI = nullptr;
215  if (MI.getOpcode() == TargetOpcode::G_INTRINSIC &&
216  MI.getIntrinsicID() == Intrinsic::amdgcn_rcp)
217  ResMI = MRI.getVRegDef(MI.getOperand(2).getReg());
218 
219  return ResMI;
220  };
221 
222  auto getSqrtSrc = [=](const MachineInstr &MI) {
223  MachineInstr *SqrtSrcMI = nullptr;
224  mi_match(MI.getOperand(0).getReg(), MRI, m_GFSqrt(m_MInstr(SqrtSrcMI)));
225  return SqrtSrcMI;
226  };
227 
228  MachineInstr *RcpSrcMI = nullptr, *SqrtSrcMI = nullptr;
229  // rcp(sqrt(x))
230  if ((RcpSrcMI = getRcpSrc(MI)) && (SqrtSrcMI = getSqrtSrc(*RcpSrcMI))) {
231  MatchInfo = [SqrtSrcMI, &MI](MachineIRBuilder &B) {
232  B.buildIntrinsic(Intrinsic::amdgcn_rsq, {MI.getOperand(0)}, false)
233  .addUse(SqrtSrcMI->getOperand(0).getReg())
234  .setMIFlags(MI.getFlags());
235  };
236  return true;
237  }
238 
239  // sqrt(rcp(x))
240  if ((SqrtSrcMI = getSqrtSrc(MI)) && (RcpSrcMI = getRcpSrc(*SqrtSrcMI))) {
241  MatchInfo = [RcpSrcMI, &MI](MachineIRBuilder &B) {
242  B.buildIntrinsic(Intrinsic::amdgcn_rsq, {MI.getOperand(0)}, false)
243  .addUse(RcpSrcMI->getOperand(0).getReg())
244  .setMIFlags(MI.getFlags());
245  };
246  return true;
247  }
248 
249  return false;
250 }
251 
253  MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo) {
254  Register SrcReg = MI.getOperand(1).getReg();
255 
256  // Look through G_ZEXT.
257  mi_match(SrcReg, MRI, m_GZExt(m_Reg(SrcReg)));
258 
259  Register Src0;
260  int64_t ShiftAmt;
261  bool IsShr = mi_match(SrcReg, MRI, m_GLShr(m_Reg(Src0), m_ICst(ShiftAmt)));
262  if (IsShr || mi_match(SrcReg, MRI, m_GShl(m_Reg(Src0), m_ICst(ShiftAmt)))) {
263  const unsigned Offset = MI.getOpcode() - AMDGPU::G_AMDGPU_CVT_F32_UBYTE0;
264 
265  unsigned ShiftOffset = 8 * Offset;
266  if (IsShr)
267  ShiftOffset += ShiftAmt;
268  else
269  ShiftOffset -= ShiftAmt;
270 
271  MatchInfo.CvtVal = Src0;
272  MatchInfo.ShiftOffset = ShiftOffset;
273  return ShiftOffset < 32 && ShiftOffset >= 8 && (ShiftOffset % 8) == 0;
274  }
275 
276  // TODO: Simplify demanded bits.
277  return false;
278 }
279 
281  MachineInstr &MI, const CvtF32UByteMatchInfo &MatchInfo) {
282  B.setInstrAndDebugLoc(MI);
283  unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8;
284 
285  const LLT S32 = LLT::scalar(32);
286  Register CvtSrc = MatchInfo.CvtVal;
287  LLT SrcTy = MRI.getType(MatchInfo.CvtVal);
288  if (SrcTy != S32) {
289  assert(SrcTy.isScalar() && SrcTy.getSizeInBits() >= 8);
290  CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0);
291  }
292 
293  assert(MI.getOpcode() != NewOpc);
294  B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags());
295  MI.eraseFromParent();
296 }
297 
300  const SITargetLowering *TLI = static_cast<const SITargetLowering *>(
302  Reg = MI.getOperand(1).getReg();
303  return TLI->isCanonicalized(Reg, MF);
304 }
305 
307 protected:
310 
311 public:
313  AMDGPUCombinerHelper &Helper,
314  AMDGPUPostLegalizerCombinerHelper &PostLegalizerHelper)
315  : Helper(Helper), PostLegalizerHelper(PostLegalizerHelper) {}
316 };
317 
318 #define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
319 #include "AMDGPUGenPostLegalizeGICombiner.inc"
320 #undef AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
321 
322 namespace {
323 #define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
324 #include "AMDGPUGenPostLegalizeGICombiner.inc"
325 #undef AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
326 
327 class AMDGPUPostLegalizerCombinerInfo final : public CombinerInfo {
328  GISelKnownBits *KB;
330 
331 public:
332  AMDGPUGenPostLegalizerCombinerHelperRuleConfig GeneratedRuleCfg;
333 
334  AMDGPUPostLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
335  const AMDGPULegalizerInfo *LI,
337  : CombinerInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true,
338  /*LegalizerInfo*/ LI, EnableOpt, OptSize, MinSize),
339  KB(KB), MDT(MDT) {
340  if (!GeneratedRuleCfg.parseCommandLineOption())
341  report_fatal_error("Invalid rule identifier");
342  }
343 
344  bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
345  MachineIRBuilder &B) const override;
346 };
347 
349  MachineInstr &MI,
350  MachineIRBuilder &B) const {
351  AMDGPUCombinerHelper Helper(Observer, B, KB, MDT, LInfo);
352  AMDGPUPostLegalizerCombinerHelper PostLegalizerHelper(B, Helper);
353  AMDGPUGenPostLegalizerCombinerHelper Generated(GeneratedRuleCfg, Helper,
354  PostLegalizerHelper);
355 
356  if (Generated.tryCombineAll(Observer, MI, B))
357  return true;
358 
359  switch (MI.getOpcode()) {
360  case TargetOpcode::G_SHL:
361  case TargetOpcode::G_LSHR:
362  case TargetOpcode::G_ASHR:
363  // On some subtargets, 64-bit shift is a quarter rate instruction. In the
364  // common case, splitting this into a move and a 32-bit shift is faster and
365  // the same code size.
366  return Helper.tryCombineShiftToUnmerge(MI, 32);
367  }
368 
369  return false;
370 }
371 
372 #define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
373 #include "AMDGPUGenPostLegalizeGICombiner.inc"
374 #undef AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
375 
376 // Pass boilerplate
377 // ================
378 
379 class AMDGPUPostLegalizerCombiner : public MachineFunctionPass {
380 public:
381  static char ID;
382 
383  AMDGPUPostLegalizerCombiner(bool IsOptNone = false);
384 
385  StringRef getPassName() const override {
386  return "AMDGPUPostLegalizerCombiner";
387  }
388 
389  bool runOnMachineFunction(MachineFunction &MF) override;
390 
391  void getAnalysisUsage(AnalysisUsage &AU) const override;
392 private:
393  bool IsOptNone;
394 };
395 } // end anonymous namespace
396 
397 void AMDGPUPostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
399  AU.setPreservesCFG();
403  if (!IsOptNone) {
406  }
408 }
409 
410 AMDGPUPostLegalizerCombiner::AMDGPUPostLegalizerCombiner(bool IsOptNone)
411  : MachineFunctionPass(ID), IsOptNone(IsOptNone) {
412  initializeAMDGPUPostLegalizerCombinerPass(*PassRegistry::getPassRegistry());
413 }
414 
415 bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
416  if (MF.getProperties().hasProperty(
417  MachineFunctionProperties::Property::FailedISel))
418  return false;
419  auto *TPC = &getAnalysis<TargetPassConfig>();
420  const Function &F = MF.getFunction();
421  bool EnableOpt =
422  MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
423 
424  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
425  const AMDGPULegalizerInfo *LI
426  = static_cast<const AMDGPULegalizerInfo *>(ST.getLegalizerInfo());
427 
428  GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
429  MachineDominatorTree *MDT =
430  IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>();
431  AMDGPUPostLegalizerCombinerInfo PCInfo(EnableOpt, F.hasOptSize(),
432  F.hasMinSize(), LI, KB, MDT);
433  Combiner C(PCInfo, TPC);
434  return C.combineMachineInstrs(MF, /*CSEInfo*/ nullptr);
435 }
436 
438 INITIALIZE_PASS_BEGIN(AMDGPUPostLegalizerCombiner, DEBUG_TYPE,
439  "Combine AMDGPU machine instrs after legalization",
440  false, false)
443 INITIALIZE_PASS_END(AMDGPUPostLegalizerCombiner, DEBUG_TYPE,
444  "Combine AMDGPU machine instrs after legalization", false,
445  false)
446 
447 namespace llvm {
449  return new AMDGPUPostLegalizerCombiner(IsOptNone);
450 }
451 } // end namespace llvm
AMDGPUCombinerHelper
Definition: AMDGPUCombinerHelper.h:20
MIPatternMatch.h
llvm::CmpInst::FCMP_ULE
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
Definition: InstrTypes.h:734
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:186
CombinerInfo.h
llvm::MachineFunctionProperties::hasProperty
bool hasProperty(Property P) const
Definition: MachineFunction.h:176
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::GISelKnownBits::maskedValueIsZero
bool maskedValueIsZero(Register Val, const APInt &Mask)
Definition: GISelKnownBits.h:78
llvm::initializeAMDGPUPostLegalizerCombinerPass
void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &)
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::MIPatternMatch::m_Reg
operand_type_match m_Reg()
Definition: MIPatternMatch.h:252
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MIPatternMatch::m_GShl
BinaryOp_match< LHS, RHS, TargetOpcode::G_SHL, false > m_GShl(const LHS &L, const RHS &R)
Definition: MIPatternMatch.h:482
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
AMDGPUPostLegalizerCombinerHelper::matchCvtF32UByteN
bool matchCvtF32UByteN(MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo)
Definition: AMDGPUPostLegalizerCombiner.cpp:252
llvm::Function
Definition: Function.h:60
AMDGPUPostLegalizerCombinerHelper::FMinFMaxLegacyInfo
Definition: AMDGPUPostLegalizerCombiner.cpp:46
llvm::MIPatternMatch::m_GLShr
BinaryOp_match< LHS, RHS, TargetOpcode::G_LSHR, false > m_GLShr(const LHS &L, const RHS &R)
Definition: MIPatternMatch.h:488
AMDGPUPostLegalizerCombinerHelper::matchRcpSqrtToRsq
bool matchRcpSqrtToRsq(MachineInstr &MI, std::function< void(MachineIRBuilder &)> &MatchInfo)
Definition: AMDGPUPostLegalizerCombiner.cpp:210
llvm::CombinerHelper::getKnownBits
GISelKnownBits * getKnownBits() const
Definition: CombinerHelper.h:125
AMDGPUPostLegalizerCombinerHelperState
Definition: AMDGPUPostLegalizerCombiner.cpp:306
llvm::CmpInst::FCMP_ONE
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
Definition: InstrTypes.h:727
GISelKnownBits.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
AMDGPUPostLegalizerCombinerHelperState::AMDGPUPostLegalizerCombinerHelperState
AMDGPUPostLegalizerCombinerHelperState(AMDGPUCombinerHelper &Helper, AMDGPUPostLegalizerCombinerHelper &PostLegalizerHelper)
Definition: AMDGPUPostLegalizerCombiner.cpp:312
llvm::createAMDGPUPostLegalizeCombiner
FunctionPass * createAMDGPUPostLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPostLegalizerCombiner.cpp:448
llvm::CombinerHelper::tryCombineShiftToUnmerge
bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount)
Definition: CombinerHelper.cpp:1971
llvm::getSelectionDAGFallbackAnalysisUsage
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:879
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::CombinerInfo
Definition: CombinerInfo.h:26
llvm::CmpInst::FCMP_OGT
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:723
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:103
llvm::AMDGPULegalizerInfo
This class provides the information for the target register banks.
Definition: AMDGPULegalizerInfo.h:31
AMDGPUPostLegalizerCombinerHelper::matchRemoveFcanonicalize
bool matchRemoveFcanonicalize(MachineInstr &MI, Register &Reg)
Definition: AMDGPUPostLegalizerCombiner.cpp:298
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::CmpInst::FCMP_ULT
@ FCMP_ULT
1 1 0 0 True if unordered or less than
Definition: InstrTypes.h:733
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(AMDGPUPostLegalizerCombiner, DEBUG_TYPE, "Combine AMDGPU machine instrs after legalization", false, false) INITIALIZE_PASS_END(AMDGPUPostLegalizerCombiner
AMDGPUPostLegalizerCombinerHelper::AMDGPUPostLegalizerCombinerHelper
AMDGPUPostLegalizerCombinerHelper(MachineIRBuilder &B, AMDGPUCombinerHelper &Helper)
Definition: AMDGPUPostLegalizerCombiner.cpp:42
llvm::GISelKnownBitsAnalysis
To use KnownBitsInfo analysis in a pass, KnownBitsInfo &Info = getAnalysis<GISelKnownBitsInfoAnalysis...
Definition: GISelKnownBits.h:113
TargetMachine.h
llvm::MIPatternMatch::m_GZExt
UnaryOp_match< SrcTy, TargetOpcode::G_ZEXT > m_GZExt(const SrcTy &Src)
Definition: MIPatternMatch.h:539
GCNSubtarget.h
AMDGPUPostLegalizerCombinerHelper::applyUCharToFloat
void applyUCharToFloat(MachineInstr &MI)
Definition: AMDGPUPostLegalizerCombiner.cpp:186
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::CmpInst::FCMP_UGE
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
Definition: InstrTypes.h:732
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:731
false
Definition: StackSlotColoring.cpp:141
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
llvm::CmpInst::FCMP_UNO
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition: InstrTypes.h:729
AMDGPUPostLegalizerCombinerHelper::applyCvtF32UByteN
void applyCvtF32UByteN(MachineInstr &MI, const CvtF32UByteMatchInfo &MatchInfo)
Definition: AMDGPUPostLegalizerCombiner.cpp:280
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::APInt::getHighBitsSet
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
Definition: APInt.h:279
AMDGPUPostLegalizerCombinerHelperState::PostLegalizerHelper
AMDGPUPostLegalizerCombinerHelper & PostLegalizerHelper
Definition: AMDGPUPostLegalizerCombiner.cpp:309
DEBUG_TYPE
#define DEBUG_TYPE
Definition: AMDGPUPostLegalizerCombiner.cpp:29
llvm::CmpInst::FCMP_OEQ
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:722
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::CmpInst::FCMP_OLT
@ FCMP_OLT
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:725
llvm::MIPatternMatch::m_MInstr
bind_ty< MachineInstr * > m_MInstr(MachineInstr *&MI)
Definition: MIPatternMatch.h:352
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::MIPatternMatch::m_Pred
bind_ty< CmpInst::Predicate > m_Pred(CmpInst::Predicate &P)
Definition: MIPatternMatch.h:354
AMDGPUPostLegalizerCombinerHelper::Helper
AMDGPUCombinerHelper & Helper
Definition: AMDGPUPostLegalizerCombiner.cpp:39
llvm::None
const NoneType None
Definition: None.h:24
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
AMDGPUPostLegalizerCombinerHelper::matchUCharToFloat
bool matchUCharToFloat(MachineInstr &MI)
Definition: AMDGPUPostLegalizerCombiner.cpp:167
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::CmpInst::FCMP_FALSE
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:721
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
AMDGPUPostLegalizerCombinerHelper::FMinFMaxLegacyInfo::False
Register False
Definition: AMDGPUPostLegalizerCombiner.cpp:50
Combine
Hexagon Vector Combine
Definition: HexagonVectorCombine.cpp:1527
AMDGPUMCTargetDesc.h
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:219
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::Combiner
Definition: Combiner.h:26
AMDGPUPostLegalizerCombinerHelper::matchFMinFMaxLegacy
bool matchFMinFMaxLegacy(MachineInstr &MI, FMinFMaxLegacyInfo &Info)
Definition: AMDGPUPostLegalizerCombiner.cpp:79
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
TargetPassConfig.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::CmpInst::FCMP_OGE
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:724
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::LLT::isScalar
bool isScalar() const
Definition: LowLevelTypeImpl.h:118
llvm::AMDGPUSubtarget::hasFminFmaxLegacy
bool hasFminFmaxLegacy() const
Definition: AMDGPUSubtarget.h:188
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:241
CombinerHelper.h
AMDGPUPostLegalizerCombinerHelper::MF
MachineFunction & MF
Definition: AMDGPUPostLegalizerCombiner.cpp:37
AMDGPUPostLegalizerCombinerHelper::FMinFMaxLegacyInfo::Pred
CmpInst::Predicate Pred
Definition: AMDGPUPostLegalizerCombiner.cpp:51
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:178
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:263
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
AMDGPU.h
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:415
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
Combiner.h
AMDGPUPostLegalizerCombinerHelper::applySelectFCmpToFMinToFMaxLegacy
void applySelectFCmpToFMinToFMaxLegacy(MachineInstr &MI, const FMinFMaxLegacyInfo &Info)
Definition: AMDGPUPostLegalizerCombiner.cpp:118
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::CmpInst::FCMP_UGT
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
Definition: InstrTypes.h:731
AMDGPUPostLegalizerCombinerHelper::B
MachineIRBuilder & B
Definition: AMDGPUPostLegalizerCombiner.cpp:36
AMDGPUPostLegalizerCombinerHelper::FMinFMaxLegacyInfo::True
Register True
Definition: AMDGPUPostLegalizerCombiner.cpp:49
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
llvm::MIPatternMatch::m_ICst
ConstantMatch< APInt > m_ICst(APInt &Cst)
Definition: MIPatternMatch.h:90
llvm::MIPatternMatch::m_GFCmp
CompareOp_match< Pred, LHS, RHS, TargetOpcode::G_FCMP > m_GFCmp(const Pred &P, const LHS &L, const RHS &R)
Definition: MIPatternMatch.h:632
AMDGPUPostLegalizerCombinerHelper::CvtF32UByteMatchInfo::ShiftOffset
unsigned ShiftOffset
Definition: AMDGPUPostLegalizerCombiner.cpp:69
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:636
llvm::MIPatternMatch::m_GFSqrt
UnaryOp_match< SrcTy, TargetOpcode::G_FSQRT > m_GFSqrt(const SrcTy &Src)
Definition: MIPatternMatch.h:593
llvm::SITargetLowering
Definition: SIISelLowering.h:31
legalization
Combine AMDGPU machine instrs after legalization
Definition: AMDGPUPostLegalizerCombiner.cpp:444
AMDGPUPostLegalizerCombinerHelper
Definition: AMDGPUPostLegalizerCombiner.cpp:34
AMDGPUPostLegalizerCombinerHelperState::Helper
AMDGPUCombinerHelper & Helper
Definition: AMDGPUPostLegalizerCombiner.cpp:308
AMDGPUPostLegalizerCombinerHelper::FMinFMaxLegacyInfo::RHS
Register RHS
Definition: AMDGPUPostLegalizerCombiner.cpp:48
AMDGPUPostLegalizerCombinerHelper::CvtF32UByteMatchInfo::CvtVal
Register CvtVal
Definition: AMDGPUPostLegalizerCombiner.cpp:68
AMDGPUPostLegalizerCombinerHelper::MRI
MachineRegisterInfo & MRI
Definition: AMDGPUPostLegalizerCombiner.cpp:38
AMDGPUPostLegalizerCombinerHelper::FMinFMaxLegacyInfo::LHS
Register LHS
Definition: AMDGPUPostLegalizerCombiner.cpp:47
AMDGPULegalizerInfo.h
llvm::TargetSubtargetInfo::getTargetLowering
virtual const TargetLowering * getTargetLowering() const
Definition: TargetSubtargetInfo.h:97
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:740
AMDGPUCombinerHelper.h
llvm::CmpInst::FCMP_UNE
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:735
AMDGPUPostLegalizerCombinerHelper::CvtF32UByteMatchInfo
Definition: AMDGPUPostLegalizerCombiner.cpp:67
llvm::CmpInst::FCMP_OLE
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:726
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::MIPatternMatch::mi_match
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
Definition: MIPatternMatch.h:25
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:51
combine
vector combine
Definition: VectorCombine.cpp:1548
llvm::CmpInst::FCMP_TRUE
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:736
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
llvm::CmpInst::FCMP_ORD
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
Definition: InstrTypes.h:728
llvm::SITargetLowering::isCanonicalized
bool isCanonicalized(SelectionDAG &DAG, SDValue Op, unsigned MaxDepth=5) const
Definition: SIISelLowering.cpp:9840
llvm::CmpInst::FCMP_UEQ
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
Definition: InstrTypes.h:730
MachineDominators.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::LLT
Definition: LowLevelTypeImpl.h:39