LLVM 24.0.0git
GCNCreateVOPD.cpp
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1//===- GCNCreateVOPD.cpp - Create VOPD Instructions ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Combine VALU pairs into VOPD instructions
11/// Only works on wave32
12/// Has register requirements, we reject creating VOPD if the requirements are
13/// not met.
14/// shouldCombineVOPD mutator in postRA machine scheduler puts candidate
15/// instructions for VOPD back-to-back
16///
17//
18//===----------------------------------------------------------------------===//
19
20#include "AMDGPU.h"
21#include "GCNSubtarget.h"
22#include "GCNVOPDUtils.h"
23#include "SIInstrInfo.h"
25#include "llvm/ADT/Statistic.h"
30#include "llvm/Support/Debug.h"
31
32#define DEBUG_TYPE "gcn-create-vopd"
33STATISTIC(NumVOPDCreated, "Number of VOPD Insts Created.");
34
35using namespace llvm;
36
37namespace {
38
39class GCNCreateVOPD {
40private:
41 class VOPDCombineInfo {
42 public:
43 VOPDCombineInfo() = default;
44 VOPDCombineInfo(MachineInstr *First, MachineInstr *Second,
45 bool VOPD3 = false)
46 : FirstMI(First), SecondMI(Second), IsVOPD3(VOPD3) {}
47
48 MachineInstr *FirstMI;
49 MachineInstr *SecondMI;
50 bool IsVOPD3;
51 };
52
53public:
54 const GCNSubtarget *ST = nullptr;
55
56 bool doReplace(const SIInstrInfo *SII, VOPDCombineInfo &CI) {
57 auto *FirstMI = CI.FirstMI;
58 auto *SecondMI = CI.SecondMI;
59 unsigned Opc1 = FirstMI->getOpcode();
60 unsigned Opc2 = SecondMI->getOpcode();
61 unsigned EncodingFamily =
63 int NewOpcode = AMDGPU::getVOPDFull(AMDGPU::getVOPDOpcode(Opc1, CI.IsVOPD3),
64 AMDGPU::getVOPDOpcode(Opc2, CI.IsVOPD3),
65 EncodingFamily, CI.IsVOPD3);
66 assert(NewOpcode != -1 &&
67 "Should have previously determined this as a possible VOPD\n");
68
69 auto VOPDInst = BuildMI(*FirstMI->getParent(), FirstMI,
70 FirstMI->getDebugLoc(), SII->get(NewOpcode))
71 .setMIFlags(FirstMI->getFlags() | SecondMI->getFlags());
72
73 namespace VOPD = AMDGPU::VOPD;
74 MachineInstr *MI[] = {FirstMI, SecondMI};
75 auto InstInfo =
76 AMDGPU::getVOPDInstInfo(FirstMI->getDesc(), SecondMI->getDesc());
77
78 for (auto CompIdx : VOPD::COMPONENTS) {
79 auto MCOprIdx = InstInfo[CompIdx].getIndexOfDstInMCOperands();
80 VOPDInst.add(MI[CompIdx]->getOperand(MCOprIdx));
81 }
82
83 const AMDGPU::OpName Mods[2][3] = {
84 {AMDGPU::OpName::src0X_modifiers, AMDGPU::OpName::vsrc1X_modifiers,
85 AMDGPU::OpName::vsrc2X_modifiers},
86 {AMDGPU::OpName::src0Y_modifiers, AMDGPU::OpName::vsrc1Y_modifiers,
87 AMDGPU::OpName::vsrc2Y_modifiers}};
88 const AMDGPU::OpName SrcMods[3] = {AMDGPU::OpName::src0_modifiers,
89 AMDGPU::OpName::src1_modifiers,
90 AMDGPU::OpName::src2_modifiers};
91 const unsigned VOPDOpc = VOPDInst->getOpcode();
92
93 for (auto CompIdx : VOPD::COMPONENTS) {
94 auto CompSrcOprNum = InstInfo[CompIdx].getCompSrcOperandsNum();
95 bool IsVOP3 = SII->isVOP3(*MI[CompIdx]);
96 for (unsigned CompSrcIdx = 0; CompSrcIdx < CompSrcOprNum; ++CompSrcIdx) {
97 if (AMDGPU::hasNamedOperand(VOPDOpc, Mods[CompIdx][CompSrcIdx])) {
98 const MachineOperand *Mod =
99 SII->getNamedOperand(*MI[CompIdx], SrcMods[CompSrcIdx]);
100 VOPDInst.addImm(Mod ? Mod->getImm() : 0);
101 }
102 auto MCOprIdx =
103 InstInfo[CompIdx].getIndexOfSrcInMCOperands(CompSrcIdx, IsVOP3);
104 VOPDInst.add(MI[CompIdx]->getOperand(MCOprIdx));
105 }
106 if (MI[CompIdx]->getOpcode() == AMDGPU::V_CNDMASK_B32_e32 && CI.IsVOPD3)
107 VOPDInst.addReg(AMDGPU::VCC_LO);
108 }
109
110 if (CI.IsVOPD3) {
111 if (unsigned BitOp2 = AMDGPU::getBitOp2(Opc2))
112 VOPDInst.addImm(BitOp2);
113 }
114
115 SII->fixImplicitOperands(*VOPDInst);
116 for (auto CompIdx : VOPD::COMPONENTS)
117 VOPDInst.copyImplicitOps(*MI[CompIdx]);
118
119 LLVM_DEBUG(dbgs() << "VOPD Fused: " << *VOPDInst << " from\tX: "
120 << *CI.FirstMI << "\tY: " << *CI.SecondMI << "\n");
121
122 for (auto CompIdx : VOPD::COMPONENTS)
123 MI[CompIdx]->eraseFromParent();
124
125 ++NumVOPDCreated;
126 return true;
127 }
128
129 bool run(MachineFunction &MF) {
130 ST = &MF.getSubtarget<GCNSubtarget>();
131 if (!AMDGPU::hasVOPD(*ST) || !ST->isWave32())
132 return false;
133 LLVM_DEBUG(dbgs() << "CreateVOPD Pass:\n");
134
135 const SIInstrInfo *SII = ST->getInstrInfo();
136 bool Changed = false;
137
138 SmallVector<VOPDCombineInfo> ReplaceCandidates;
139
140 for (auto &MBB : MF) {
141 auto MII = MBB.begin(), E = MBB.end();
142 while (MII != E) {
143 auto *FirstMI = &*MII;
144 MII = next_nodbg(MII, MBB.end());
145 if (MII == MBB.end())
146 break;
147 if (FirstMI->isDebugInstr())
148 continue;
149 auto *SecondMI = &*MII;
150
151 if (auto Match = tryMatchVOPDPair(*SII, *FirstMI, *SecondMI)) {
152 ReplaceCandidates.push_back(
153 VOPDCombineInfo(Match->MIX, Match->MIY, Match->IsVOPD3));
154 ++MII;
155 }
156 }
157 }
158 for (auto &CI : ReplaceCandidates) {
159 Changed |= doReplace(SII, CI);
160 }
161
162 return Changed;
163 }
164};
165
166class GCNCreateVOPDLegacy : public MachineFunctionPass {
167public:
168 static char ID;
169 GCNCreateVOPDLegacy() : MachineFunctionPass(ID) {}
170
171 void getAnalysisUsage(AnalysisUsage &AU) const override {
172 AU.setPreservesCFG();
174 }
175
176 StringRef getPassName() const override {
177 return "GCN Create VOPD Instructions";
178 }
179 bool runOnMachineFunction(MachineFunction &MF) override {
180 if (skipFunction(MF.getFunction()))
181 return false;
182
183 return GCNCreateVOPD().run(MF);
184 }
185};
186
187} // namespace
188
196
197char GCNCreateVOPDLegacy::ID = 0;
198
199char &llvm::GCNCreateVOPDID = GCNCreateVOPDLegacy::ID;
200
201INITIALIZE_PASS(GCNCreateVOPDLegacy, DEBUG_TYPE, "GCN Create VOPD Instructions",
202 false, false)
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MachineBasicBlock & MBB
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
AMD GCN specific subclass of TargetSubtarget.
#define DEBUG_TYPE
IRTranslator LLVM IR MI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
Interface definition for SIInstrInfo.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition Statistic.h:171
#define LLVM_DEBUG(...)
Definition Debug.h:119
LLVM_ABI void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition Pass.cpp:278
Represents analyses that only rely on functions' control flow.
Definition Analysis.h:73
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &AM)
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Representation of each machine instruction.
A set of analyses that are preserved following a run of a transformation pass.
Definition Analysis.h:112
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
Definition Analysis.h:118
PreservedAnalyses & preserveSet()
Mark an analysis set as preserved.
Definition Analysis.h:151
const GCNSubtarget & getSubtarget() const
static bool isVOP3(const MCInstrDesc &Desc)
void fixImplicitOperands(MachineInstr &MI) const
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, AMDGPU::OpName OperandName) const
Returns the operand named Op.
void push_back(const T &Elt)
Changed
unsigned getVOPDOpcode(unsigned Opc, bool VOPD3)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, OpName NamedIdx)
unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST)
unsigned getBitOp2(unsigned Opc)
VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
bool hasVOPD(const MCSubtargetInfo &STI)
int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily, bool VOPD3)
DXILDebugInfoMap run(Module &M)
unsigned getOpcode(const VPValue *V)
Return the instruction opcode for the recipe defining V or 0 for unsupported recipes and VPValues not...
This is an optimization pass for GlobalISel generic memory operations.
IterT next_nodbg(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It, then continue incrementing it while it points to a debug instruction.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
AnalysisManager< MachineFunction > MachineFunctionAnalysisManager
LLVM_ABI PreservedAnalyses getMachineFunctionPassPreservedAnalyses()
Returns the minimum set of Analyses that all machine function passes must preserve.
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition Debug.cpp:209
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
@ Mod
The access may modify the value stored in memory.
Definition ModRef.h:34
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.
Definition ModRef.h:74
char & GCNCreateVOPDID
std::optional< VOPDMatchInfo > tryMatchVOPDPair(const SIInstrInfo &TII, MachineInstr &FirstMI, MachineInstr &SecondMI)
Check whether FirstMI and SecondMI can be combined into a VOPD instruction.