Go to the documentation of this file.
35 #define DEBUG_TYPE "gcn-vopd-utils"
40 namespace VOPD = AMDGPU::VOPD;
49 for (
auto &Literal : UniqueLiterals) {
50 if (Literal->isIdenticalTo(
Op))
53 UniqueLiterals.push_back(&
Op);
58 MII != FirstMI.
getParent()->instr_end(); ++MII) {
59 if (&*MII == &SecondMI)
63 }() &&
"Expected FirstMI to precede SecondMI");
65 for (
const auto &
Use : SecondMI.
uses())
69 auto getVRegIdx = [&](
unsigned OpcodeIdx,
unsigned OperandIdx) {
87 UniqueScalarRegs.push_back(Src0.
getReg());
94 if (InstInfo[CompIdx].hasMandatoryLiteral()) {
95 auto CompOprIdx = InstInfo[CompIdx].getMandatoryLiteralCompOperandIndex();
96 addLiteral(
MI.getOperand(CompOprIdx));
98 if (
MI.getDesc().hasImplicitUseOfPhysReg(AMDGPU::VCC))
99 UniqueScalarRegs.push_back(AMDGPU::VCC_LO);
102 if (UniqueLiterals.size() > 1)
104 if ((UniqueLiterals.size() + UniqueScalarRegs.size()) > 2)
106 if (InstInfo.hasInvalidOperand(getVRegIdx))
109 LLVM_DEBUG(
dbgs() <<
"VOPD Reg Constraints Passed\n\tX: " << FirstMI
110 <<
"\n\tY: " << SecondMI <<
"\n");
127 return SecondCanBeVOPD.Y;
132 if (!((FirstCanBeVOPD.X && SecondCanBeVOPD.Y) ||
133 (FirstCanBeVOPD.Y && SecondCanBeVOPD.X)))
155 LLVM_DEBUG(
dbgs() <<
"Target does not support VOPDPairingMutation\n");
159 std::vector<SUnit>::iterator ISUI, JSUI;
160 for (ISUI = DAG->
SUnits.begin(); ISUI != DAG->
SUnits.end(); ++ISUI) {
167 for (JSUI = ISUI + 1; JSUI != DAG->
SUnits.end(); ++JSUI) {
168 if (JSUI->isBoundaryNode())
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
This is an optimization pass for GlobalISel generic memory operations.
bool hasVOPD(const MCSubtargetInfo &STI)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool checkVOPDRegConstraints(const SIInstrInfo &TII, const MachineInstr &FirstMI, const MachineInstr &SecondMI)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
unsigned const TargetRegisterInfo * TRI
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetInstrInfo - Interface to description of machine instruction set.
void apply(Opt *O, const Mod &M, const Mods &... Ms)
const HexagonInstrInfo * TII
VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
MachineOperand class - Representation of each machine instruction operand.
bool fuseInstructionPair(ScheduleDAGInstrs &DAG, SUnit &FirstSU, SUnit &SecondSU)
Create an artificial edge between FirstSU and SecondSU.
static bool shouldScheduleVOPDAdjacent(const TargetInstrInfo &TII, const TargetSubtargetInfo &TSI, const MachineInstr *FirstMI, const MachineInstr &SecondMI)
Check if the instr pair, FirstMI and SecondMI, should be scheduled together.
Promote Memory to Register
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII, const TargetSubtargetInfo &TSI, const MachineInstr *FirstMI, const MachineInstr &SecondMI)
Check if the instr pair, FirstMI and SecondMI, should be fused together.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Register getReg() const
getReg - Returns the register number.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
MachineFunction & MF
Machine function.
std::unique_ptr< ScheduleDAGMutation > createVOPDPairingMutation()
const MachineBasicBlock * getParent() const
TargetSubtargetInfo - Generic base class for all target subtargets.
constexpr unsigned COMPONENTS[]
unsigned const MachineRegisterInfo * MRI
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register.
bool hasLessThanNumFused(const SUnit &SU, unsigned FuseLimit)
Checks if the number of cluster edges between SU and its predecessors is less than FuseLimit.
std::vector< SUnit > SUnits
The scheduling units.
const TargetInstrInfo * TII
Target instruction information.
Mutate the DAG as a postpass after normal DAG building.
CanBeVOPD getCanBeVOPD(unsigned Opc)
A ScheduleDAG for scheduling lists of MachineInstr.
A Use represents the edge between a Value definition and its users.
std::function< bool(const TargetInstrInfo &TII, const TargetSubtargetInfo &TSI, const MachineInstr *FirstMI, const MachineInstr &SecondMI)> ShouldSchedulePredTy
Check if the instr pair, FirstMI and SecondMI, should be fused together.