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28 if (FirstMI ==
nullptr)
39 case AArch64::ADDSWri:
40 case AArch64::ADDSWrr:
41 case AArch64::ADDSXri:
42 case AArch64::ADDSXrr:
43 case AArch64::ANDSWri:
44 case AArch64::ANDSWrr:
45 case AArch64::ANDSXri:
46 case AArch64::ANDSXrr:
47 case AArch64::SUBSWri:
48 case AArch64::SUBSWrr:
49 case AArch64::SUBSXri:
50 case AArch64::SUBSXrr:
51 case AArch64::BICSWrr:
52 case AArch64::BICSXrr:
54 case AArch64::ADDSWrs:
55 case AArch64::ADDSXrs:
56 case AArch64::ANDSWrs:
57 case AArch64::ANDSXrs:
58 case AArch64::SUBSWrs:
59 case AArch64::SUBSXrs:
60 case AArch64::BICSWrs:
61 case AArch64::BICSXrs:
63 return !AArch64InstrInfo::hasShiftedReg(*FirstMI);
72 if (SecondMI.
getOpcode() != AArch64::CBZW &&
79 if (FirstMI ==
nullptr)
100 case AArch64::SUBWrr:
101 case AArch64::SUBXri:
102 case AArch64::SUBXrr:
104 case AArch64::ADDWrs:
105 case AArch64::ADDXrs:
106 case AArch64::ANDWrs:
107 case AArch64::ANDXrs:
108 case AArch64::SUBWrs:
109 case AArch64::SUBXrs:
110 case AArch64::BICWrs:
111 case AArch64::BICXrs:
113 return !AArch64InstrInfo::hasShiftedReg(*FirstMI);
125 case AArch64::AESMCrr:
126 case AArch64::AESMCrrTied:
127 return FirstMI ==
nullptr || FirstMI->
getOpcode() == AArch64::AESErr;
129 case AArch64::AESIMCrr:
130 case AArch64::AESIMCrrTied:
131 return FirstMI ==
nullptr || FirstMI->
getOpcode() == AArch64::AESDrr;
140 if (SecondMI.
getOpcode() != AArch64::EORv16i8)
144 if (FirstMI ==
nullptr)
148 case AArch64::AESErr:
149 case AArch64::AESDrr:
150 case AArch64::PMULLv16i8:
151 case AArch64::PMULLv8i8:
152 case AArch64::PMULLv1i64:
153 case AArch64::PMULLv2i64:
174 if ((FirstMI ==
nullptr || FirstMI->
getOpcode() == AArch64::MOVZWi) &&
175 (SecondMI.
getOpcode() == AArch64::MOVKWi &&
180 if((FirstMI ==
nullptr || FirstMI->
getOpcode() == AArch64::MOVZXi) &&
181 (SecondMI.
getOpcode() == AArch64::MOVKXi &&
186 if ((FirstMI ==
nullptr ||
187 (FirstMI->
getOpcode() == AArch64::MOVKXi &&
189 (SecondMI.
getOpcode() == AArch64::MOVKXi &&
200 case AArch64::STRBBui:
201 case AArch64::STRBui:
202 case AArch64::STRDui:
203 case AArch64::STRHHui:
204 case AArch64::STRHui:
205 case AArch64::STRQui:
206 case AArch64::STRSui:
207 case AArch64::STRWui:
208 case AArch64::STRXui:
209 case AArch64::LDRBBui:
210 case AArch64::LDRBui:
211 case AArch64::LDRDui:
212 case AArch64::LDRHHui:
213 case AArch64::LDRHui:
214 case AArch64::LDRQui:
215 case AArch64::LDRSui:
216 case AArch64::LDRWui:
217 case AArch64::LDRXui:
218 case AArch64::LDRSBWui:
219 case AArch64::LDRSBXui:
220 case AArch64::LDRSHWui:
221 case AArch64::LDRSHXui:
222 case AArch64::LDRSWui:
224 if (FirstMI ==
nullptr)
242 if (SecondMI.
getOpcode() == AArch64::CSELWr) {
244 if (FirstMI ==
nullptr)
249 case AArch64::SUBSWrs:
250 return !AArch64InstrInfo::hasShiftedReg(*FirstMI);
251 case AArch64::SUBSWrx:
252 return !AArch64InstrInfo::hasExtendedReg(*FirstMI);
253 case AArch64::SUBSWrr:
254 case AArch64::SUBSWri:
260 if (SecondMI.
getOpcode() == AArch64::CSELXr) {
262 if (FirstMI ==
nullptr)
267 case AArch64::SUBSXrs:
268 return !AArch64InstrInfo::hasShiftedReg(*FirstMI);
269 case AArch64::SUBSXrx:
270 case AArch64::SUBSXrx64:
271 return !AArch64InstrInfo::hasExtendedReg(*FirstMI);
272 case AArch64::SUBSXrr:
273 case AArch64::SUBSXri:
284 if (AArch64InstrInfo::hasShiftedReg(SecondMI))
289 case AArch64::ADDWrr:
290 case AArch64::ADDXrr:
291 case AArch64::SUBWrr:
292 case AArch64::SUBXrr:
293 case AArch64::ADDWrs:
294 case AArch64::ADDXrs:
295 case AArch64::SUBWrs:
296 case AArch64::SUBXrs:
298 case AArch64::ANDWrr:
299 case AArch64::ANDXrr:
300 case AArch64::BICWrr:
301 case AArch64::BICXrr:
302 case AArch64::EONWrr:
303 case AArch64::EONXrr:
304 case AArch64::EORWrr:
305 case AArch64::EORXrr:
306 case AArch64::ORNWrr:
307 case AArch64::ORNXrr:
308 case AArch64::ORRWrr:
309 case AArch64::ORRXrr:
310 case AArch64::ANDWrs:
311 case AArch64::ANDXrs:
312 case AArch64::BICWrs:
313 case AArch64::BICXrs:
314 case AArch64::EONWrs:
315 case AArch64::EONXrs:
316 case AArch64::EORWrs:
317 case AArch64::EORXrs:
318 case AArch64::ORNWrs:
319 case AArch64::ORNXrs:
320 case AArch64::ORRWrs:
321 case AArch64::ORRXrs:
323 if (FirstMI ==
nullptr)
328 case AArch64::ADDWrr:
329 case AArch64::ADDXrr:
330 case AArch64::ADDSWrr:
331 case AArch64::ADDSXrr:
332 case AArch64::SUBWrr:
333 case AArch64::SUBXrr:
334 case AArch64::SUBSWrr:
335 case AArch64::SUBSXrr:
337 case AArch64::ADDWrs:
338 case AArch64::ADDXrs:
339 case AArch64::ADDSWrs:
340 case AArch64::ADDSXrs:
341 case AArch64::SUBWrs:
342 case AArch64::SUBXrs:
343 case AArch64::SUBSWrs:
344 case AArch64::SUBSXrs:
345 return !AArch64InstrInfo::hasShiftedReg(*FirstMI);
350 case AArch64::ADDSWrr:
351 case AArch64::ADDSXrr:
352 case AArch64::SUBSWrr:
353 case AArch64::SUBSXrr:
354 case AArch64::ADDSWrs:
355 case AArch64::ADDSXrs:
356 case AArch64::SUBSWrs:
357 case AArch64::SUBSXrs:
359 if (FirstMI ==
nullptr)
364 case AArch64::ADDWrr:
365 case AArch64::ADDXrr:
366 case AArch64::SUBWrr:
367 case AArch64::SUBXrr:
369 case AArch64::ADDWrs:
370 case AArch64::ADDXrs:
371 case AArch64::SUBWrs:
372 case AArch64::SUBXrs:
373 return !AArch64InstrInfo::hasShiftedReg(*FirstMI);
392 if (
ST.hasCmpBccFusion() ||
ST.hasArithmeticBccFusion()) {
393 bool CmpOnly = !
ST.hasArithmeticBccFusion();
399 if (
ST.hasFuseAES() &&
isAESPair(FirstMI, SecondMI))
417 std::unique_ptr<ScheduleDAGMutation>
static bool isArithmeticBccPair(const MachineInstr *FirstMI, const MachineInstr &SecondMI, bool CmpOnly)
CMN, CMP, TST followed by Bcc.
This is an optimization pass for GlobalISel generic memory operations.
static bool isAddressLdStPair(const MachineInstr *FirstMI, const MachineInstr &SecondMI)
Fuse address generation and loads or stores.
static bool isArithmeticCbzPair(const MachineInstr *FirstMI, const MachineInstr &SecondMI)
ALU operations followed by CBZ/CBNZ.
static bool isArithmeticLogicPair(const MachineInstr *FirstMI, const MachineInstr &SecondMI)
TargetInstrInfo - Interface to description of machine instruction set.
const MachineOperand & getOperand(unsigned i) const
const HexagonInstrInfo * TII
static bool isAESPair(const MachineInstr *FirstMI, const MachineInstr &SecondMI)
static bool isAdrpAddPair(const MachineInstr *FirstMI, const MachineInstr &SecondMI)
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
std::unique_ptr< ScheduleDAGMutation > createMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent)
Create a DAG scheduling mutation to pair instructions back to back for instructions that benefit acco...
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII, const TargetSubtargetInfo &TSI, const MachineInstr *FirstMI, const MachineInstr &SecondMI)
Check if the instr pair, FirstMI and SecondMI, should be fused together.
Representation of each machine instruction.
Register getReg() const
getReg - Returns the register number.
static bool isLiteralsPair(const MachineInstr *FirstMI, const MachineInstr &SecondMI)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
TargetSubtargetInfo - Generic base class for all target subtargets.
static bool isCryptoEORPair(const MachineInstr *FirstMI, const MachineInstr &SecondMI)
AESE/AESD/PMULL + EOR.
std::unique_ptr< ScheduleDAGMutation > createAArch64MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAArch64MacroFusionDAGMutation()); to AArch64PassConf...
static bool isCCSelectPair(const MachineInstr *FirstMI, const MachineInstr &SecondMI)
Compare and conditional select.