Go to the documentation of this file.
19 "stackmap and patchpoint intrinsics.");
38 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
40 const unsigned NumArgRegs =
std::size(ArgRegs);
48 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
63 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
65 const unsigned NumArgRegs =
std::size(ArgRegs);
68 int RegsLeft = NumArgRegs - RegNum;
72 if (RegNum != NumArgRegs && RegsLeft < 4) {
73 for (
int i = 0;
i < RegsLeft;
i++) {
87 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
91 const unsigned NumArgRegs =
std::size(ArgRegs);
97 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
114 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 };
124 if (HiRegList[
i] ==
Reg)
129 assert(
T == LoRegList[
i] &&
"Could not allocate register");
143 static const MCPhysReg HiRegList[] = { PPC::R3 };
153 if (HiRegList[
i] ==
Reg)
162 #include "PPCGenCallingConv.inc"
static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
This is an optimization pass for GlobalISel generic memory operations.
static bool CC_PPC32_SPE_CustomSplitFP64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
CCState - This class holds information needed while lowering arguments and return values.
void addLoc(const CCValAssign &V)
Reg
All possible values of the reg field in the ModR/M byte.
static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
bool CC_PPC_AnyReg_Error(unsigned &, MVT &, MVT &, CCValAssign::LocInfo &, ISD::ArgFlagsTy &, CCState &)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
static bool CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
static bool CC_PPC32_SPE_RetF64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)