| AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII) | llvm::AMDGPUDisassembler | |
| CommentStream | llvm::MCDisassembler | mutable |
| convertDPP8Inst(MCInst &MI) const | llvm::AMDGPUDisassembler | |
| convertEXPInst(MCInst &MI) const | llvm::AMDGPUDisassembler | |
| convertFMAanyK(MCInst &MI, int ImmLitIdx) const | llvm::AMDGPUDisassembler | |
| convertMacDPPInst(MCInst &MI) const | llvm::AMDGPUDisassembler | |
| convertMIMGInst(MCInst &MI) const | llvm::AMDGPUDisassembler | |
| convertSDWAInst(MCInst &MI) const | llvm::AMDGPUDisassembler | |
| convertTrue16OpSel(MCInst &MI) const | llvm::AMDGPUDisassembler | |
| convertVINTERPInst(MCInst &MI) const | llvm::AMDGPUDisassembler | |
| convertVOP3DPPInst(MCInst &MI) const | llvm::AMDGPUDisassembler | |
| convertVOP3PDPPInst(MCInst &MI) const | llvm::AMDGPUDisassembler | |
| convertVOPCDPPInst(MCInst &MI) const | llvm::AMDGPUDisassembler | |
| createRegOperand(unsigned int RegId) const | llvm::AMDGPUDisassembler | inline |
| createRegOperand(unsigned RegClassID, unsigned Val) const | llvm::AMDGPUDisassembler | inline |
| createSRegOperand(unsigned SRegClassID, unsigned Val) const | llvm::AMDGPUDisassembler | inline |
| createVGPR16Operand(unsigned RegIdx, bool IsHi) const | llvm::AMDGPUDisassembler | |
| decodeBoolReg(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const | llvm::AMDGPUDisassembler | |
| decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const | llvm::AMDGPUDisassembler | |
| decodeCOMPUTE_PGM_RSRC3(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const | llvm::AMDGPUDisassembler | |
| decodeDpp8FI(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeFPImmed(unsigned ImmWidth, unsigned Imm, AMDGPU::OperandSemantics Sema) | llvm::AMDGPUDisassembler | static |
| decodeIntImmed(unsigned Imm) | llvm::AMDGPUDisassembler | static |
| decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const | llvm::AMDGPUDisassembler | |
| decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const | llvm::AMDGPUDisassembler | |
| decodeLiteralConstant(bool ExtendFP64) const | llvm::AMDGPUDisassembler | |
| decodeMandatoryLiteralConstant(unsigned Imm) const | llvm::AMDGPUDisassembler | |
| decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0, AMDGPU::OperandSemantics Sema=AMDGPU::OperandSemantics::INT) const | llvm::AMDGPUDisassembler | |
| decodeSDWASrc(const OpWidthTy Width, unsigned Val, unsigned ImmWidth, AMDGPU::OperandSemantics Sema) const | llvm::AMDGPUDisassembler | |
| decodeSDWASrc16(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeSDWASrc32(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeSDWAVopcDst(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeSpecialReg32(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeSpecialReg64(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeSplitBarrier(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0, AMDGPU::OperandSemantics Sema=AMDGPU::OperandSemantics::INT) const | llvm::AMDGPUDisassembler | |
| DecodeStatus enum name | llvm::MCDisassembler | |
| decodeVersionImm(unsigned Imm) const | llvm::AMDGPUDisassembler | |
| decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const | llvm::AMDGPUDisassembler | |
| errOperand(unsigned V, const Twine &ErrMsg) const | llvm::AMDGPUDisassembler | inline |
| Fail enum value | llvm::MCDisassembler | |
| getAgprClassId(const OpWidthTy Width) const | llvm::AMDGPUDisassembler | |
| getContext() const | llvm::MCDisassembler | inline |
| getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override | llvm::AMDGPUDisassembler | virtual |
| getMCII() const | llvm::AMDGPUDisassembler | inline |
| getRegClassName(unsigned RegClassID) const | llvm::AMDGPUDisassembler | |
| getSgprClassId(const OpWidthTy Width) const | llvm::AMDGPUDisassembler | |
| getSubtargetInfo() const | llvm::MCDisassembler | inline |
| getTtmpClassId(const OpWidthTy Width) const | llvm::AMDGPUDisassembler | |
| getTTmpIdx(unsigned Val) const | llvm::AMDGPUDisassembler | |
| getVgprClassId(const OpWidthTy Width) const | llvm::AMDGPUDisassembler | |
| hasArchitectedFlatScratch() const | llvm::AMDGPUDisassembler | |
| hasKernargPreload() const | llvm::AMDGPUDisassembler | |
| isGFX10() const | llvm::AMDGPUDisassembler | |
| isGFX10Plus() const | llvm::AMDGPUDisassembler | |
| isGFX11() const | llvm::AMDGPUDisassembler | |
| isGFX11Plus() const | llvm::AMDGPUDisassembler | |
| isGFX12() const | llvm::AMDGPUDisassembler | |
| isGFX12Plus() const | llvm::AMDGPUDisassembler | |
| isGFX9() const | llvm::AMDGPUDisassembler | |
| isGFX90A() const | llvm::AMDGPUDisassembler | |
| isGFX9Plus() const | llvm::AMDGPUDisassembler | |
| isMacDPP(MCInst &MI) const | llvm::AMDGPUDisassembler | |
| isVI() const | llvm::AMDGPUDisassembler | |
| MCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) | llvm::MCDisassembler | inline |
| onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address) const override | llvm::AMDGPUDisassembler | virtual |
| OPW1024 enum value | llvm::AMDGPUDisassembler | |
| OPW128 enum value | llvm::AMDGPUDisassembler | |
| OPW16 enum value | llvm::AMDGPUDisassembler | |
| OPW160 enum value | llvm::AMDGPUDisassembler | |
| OPW256 enum value | llvm::AMDGPUDisassembler | |
| OPW288 enum value | llvm::AMDGPUDisassembler | |
| OPW32 enum value | llvm::AMDGPUDisassembler | |
| OPW320 enum value | llvm::AMDGPUDisassembler | |
| OPW352 enum value | llvm::AMDGPUDisassembler | |
| OPW384 enum value | llvm::AMDGPUDisassembler | |
| OPW512 enum value | llvm::AMDGPUDisassembler | |
| OPW64 enum value | llvm::AMDGPUDisassembler | |
| OPW96 enum value | llvm::AMDGPUDisassembler | |
| OPW_FIRST_ enum value | llvm::AMDGPUDisassembler | |
| OPW_LAST_ enum value | llvm::AMDGPUDisassembler | |
| OpWidthTy enum name | llvm::AMDGPUDisassembler | |
| OPWV216 enum value | llvm::AMDGPUDisassembler | |
| OPWV232 enum value | llvm::AMDGPUDisassembler | |
| setABIVersion(unsigned Version) override | llvm::AMDGPUDisassembler | virtual |
| setSymbolizer(std::unique_ptr< MCSymbolizer > Symzer) | llvm::MCDisassembler | |
| SoftFail enum value | llvm::MCDisassembler | |
| STI | llvm::MCDisassembler | protected |
| Success enum value | llvm::MCDisassembler | |
| suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const | llvm::MCDisassembler | virtual |
| Symbolizer | llvm::MCDisassembler | protected |
| tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const | llvm::MCDisassembler | |
| tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const | llvm::MCDisassembler | |
| tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const | llvm::AMDGPUDisassembler | inline |
| tryDecodeInst(const uint8_t *Table1, const uint8_t *Table2, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const | llvm::AMDGPUDisassembler | inline |
| ~AMDGPUDisassembler() override=default | llvm::AMDGPUDisassembler | |
| ~MCDisassembler() | llvm::MCDisassembler | virtual |
