LLVM  10.0.0svn
Enumerations
llvm::AMDGPU::DPP Namespace Reference

Enumerations

enum  DppCtrl : unsigned {
  QUAD_PERM_FIRST = 0, QUAD_PERM_ID = 0xE4, QUAD_PERM_LAST = 0xFF, DPP_UNUSED1 = 0x100,
  ROW_SHL0 = 0x100, ROW_SHL_FIRST = 0x101, ROW_SHL_LAST = 0x10F, DPP_UNUSED2 = 0x110,
  ROW_SHR0 = 0x110, ROW_SHR_FIRST = 0x111, ROW_SHR_LAST = 0x11F, DPP_UNUSED3 = 0x120,
  ROW_ROR0 = 0x120, ROW_ROR_FIRST = 0x121, ROW_ROR_LAST = 0x12F, WAVE_SHL1 = 0x130,
  DPP_UNUSED4_FIRST = 0x131, DPP_UNUSED4_LAST = 0x133, WAVE_ROL1 = 0x134, DPP_UNUSED5_FIRST = 0x135,
  DPP_UNUSED5_LAST = 0x137, WAVE_SHR1 = 0x138, DPP_UNUSED6_FIRST = 0x139, DPP_UNUSED6_LAST = 0x13B,
  WAVE_ROR1 = 0x13C, DPP_UNUSED7_FIRST = 0x13D, DPP_UNUSED7_LAST = 0x13F, ROW_MIRROR = 0x140,
  ROW_HALF_MIRROR = 0x141, BCAST15 = 0x142, BCAST31 = 0x143, DPP_UNUSED8_FIRST = 0x144,
  DPP_UNUSED8_LAST = 0x14F, ROW_SHARE_FIRST = 0x150, ROW_SHARE_LAST = 0x15F, ROW_XMASK_FIRST = 0x160,
  ROW_XMASK_LAST = 0x16F, DPP_LAST = ROW_XMASK_LAST
}
 
enum  DppFiMode { DPP_FI_0 = 0, DPP_FI_1 = 1, DPP8_FI_0 = 0xE9, DPP8_FI_1 = 0xEA }
 

Enumeration Type Documentation

◆ DppCtrl

Enumerator
QUAD_PERM_FIRST 
QUAD_PERM_ID 
QUAD_PERM_LAST 
DPP_UNUSED1 
ROW_SHL0 
ROW_SHL_FIRST 
ROW_SHL_LAST 
DPP_UNUSED2 
ROW_SHR0 
ROW_SHR_FIRST 
ROW_SHR_LAST 
DPP_UNUSED3 
ROW_ROR0 
ROW_ROR_FIRST 
ROW_ROR_LAST 
WAVE_SHL1 
DPP_UNUSED4_FIRST 
DPP_UNUSED4_LAST 
WAVE_ROL1 
DPP_UNUSED5_FIRST 
DPP_UNUSED5_LAST 
WAVE_SHR1 
DPP_UNUSED6_FIRST 
DPP_UNUSED6_LAST 
WAVE_ROR1 
DPP_UNUSED7_FIRST 
DPP_UNUSED7_LAST 
ROW_MIRROR 
ROW_HALF_MIRROR 
BCAST15 
BCAST31 
DPP_UNUSED8_FIRST 
DPP_UNUSED8_LAST 
ROW_SHARE_FIRST 
ROW_SHARE_LAST 
ROW_XMASK_FIRST 
ROW_XMASK_LAST 
DPP_LAST 

Definition at line 448 of file SIDefines.h.

◆ DppFiMode

Enumerator
DPP_FI_0 
DPP_FI_1 
DPP8_FI_0 
DPP8_FI_1 

Definition at line 489 of file SIDefines.h.