LLVM 19.0.0git
AMDGPUELFObjectWriter.cpp
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1//===- AMDGPUELFObjectWriter.cpp - AMDGPU ELF Writer ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "AMDGPUFixupKinds.h"
10#include "AMDGPUMCTargetDesc.h"
11#include "llvm/MC/MCContext.h"
13#include "llvm/MC/MCValue.h"
14
15using namespace llvm;
16
17namespace {
18
19class AMDGPUELFObjectWriter : public MCELFObjectTargetWriter {
20public:
21 AMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend);
22
23protected:
24 unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
25 const MCFixup &Fixup, bool IsPCRel) const override;
26};
27
28
29} // end anonymous namespace
30
31AMDGPUELFObjectWriter::AMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI,
32 bool HasRelocationAddend)
33 : MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_AMDGPU,
34 HasRelocationAddend) {}
35
36unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
37 const MCValue &Target,
38 const MCFixup &Fixup,
39 bool IsPCRel) const {
40 if (const auto *SymA = Target.getSymA()) {
41 // SCRATCH_RSRC_DWORD[01] is a special global variable that represents
42 // the scratch buffer.
43 if (SymA->getSymbol().getName() == "SCRATCH_RSRC_DWORD0" ||
44 SymA->getSymbol().getName() == "SCRATCH_RSRC_DWORD1")
45 return ELF::R_AMDGPU_ABS32_LO;
46 }
47
48 switch (Target.getAccessVariant()) {
49 default:
50 break;
52 return ELF::R_AMDGPU_GOTPCREL;
54 return ELF::R_AMDGPU_GOTPCREL32_LO;
56 return ELF::R_AMDGPU_GOTPCREL32_HI;
58 return ELF::R_AMDGPU_REL32_LO;
60 return ELF::R_AMDGPU_REL32_HI;
62 return ELF::R_AMDGPU_REL64;
64 return ELF::R_AMDGPU_ABS32_LO;
66 return ELF::R_AMDGPU_ABS32_HI;
67 }
68
69 MCFixupKind Kind = Fixup.getKind();
72 switch (Kind) {
73 default: break;
74 case FK_PCRel_4:
75 return ELF::R_AMDGPU_REL32;
76 case FK_Data_4:
77 case FK_SecRel_4:
78 return IsPCRel ? ELF::R_AMDGPU_REL32 : ELF::R_AMDGPU_ABS32;
79 case FK_Data_8:
80 return IsPCRel ? ELF::R_AMDGPU_REL64 : ELF::R_AMDGPU_ABS64;
81 }
82
83 if (Fixup.getTargetKind() == AMDGPU::fixup_si_sopp_br) {
84 const auto *SymA = Target.getSymA();
85 assert(SymA);
86
87 if (SymA->getSymbol().isUndefined()) {
88 Ctx.reportError(Fixup.getLoc(), Twine("undefined label '") +
89 SymA->getSymbol().getName() + "'");
90 return ELF::R_AMDGPU_NONE;
91 }
92 return ELF::R_AMDGPU_REL16;
93 }
94
95 llvm_unreachable("unhandled relocation type");
96}
97
98std::unique_ptr<MCObjectTargetWriter>
99llvm::createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI,
100 bool HasRelocationAddend) {
101 return std::make_unique<AMDGPUELFObjectWriter>(Is64Bit, OSABI,
102 HasRelocationAddend);
103}
Provides AMDGPU specific target descriptions.
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Context object for machine code objects.
Definition: MCContext.h:76
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1064
virtual unsigned getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const =0
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
This represents an "assembler immediate".
Definition: MCValue.h:36
Target - Wrapper for Target specific information.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_si_sopp_br
16-bit PC relative fixup for SOPP branch instructions.
@ EM_AMDGPU
Definition: ELF.h:316
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
std::unique_ptr< MCObjectTargetWriter > createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend)
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:50
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_SecRel_4
A four-byte section relative fixup.
Definition: MCFixup.h:42