21 AMDGPUELFObjectWriter(
bool Is64Bit,
uint8_t OSABI,
bool HasRelocationAddend);
31AMDGPUELFObjectWriter::AMDGPUELFObjectWriter(
bool Is64Bit,
uint8_t OSABI,
32 bool HasRelocationAddend)
34 HasRelocationAddend) {}
36unsigned AMDGPUELFObjectWriter::getRelocType(
MCContext &Ctx,
40 if (
const auto *SymA =
Target.getSymA()) {
43 if (SymA->getSymbol().getName() ==
"SCRATCH_RSRC_DWORD0" ||
44 SymA->getSymbol().getName() ==
"SCRATCH_RSRC_DWORD1")
45 return ELF::R_AMDGPU_ABS32_LO;
48 switch (
Target.getAccessVariant()) {
52 return ELF::R_AMDGPU_GOTPCREL;
54 return ELF::R_AMDGPU_GOTPCREL32_LO;
56 return ELF::R_AMDGPU_GOTPCREL32_HI;
58 return ELF::R_AMDGPU_REL32_LO;
60 return ELF::R_AMDGPU_REL32_HI;
62 return ELF::R_AMDGPU_REL64;
64 return ELF::R_AMDGPU_ABS32_LO;
66 return ELF::R_AMDGPU_ABS32_HI;
75 return ELF::R_AMDGPU_REL32;
78 return IsPCRel ? ELF::R_AMDGPU_REL32 : ELF::R_AMDGPU_ABS32;
80 return IsPCRel ? ELF::R_AMDGPU_REL64 : ELF::R_AMDGPU_ABS64;
84 const auto *SymA =
Target.getSymA();
87 if (SymA->getSymbol().isUndefined()) {
89 SymA->getSymbol().getName() +
"'");
90 return ELF::R_AMDGPU_NONE;
92 return ELF::R_AMDGPU_REL16;
98std::unique_ptr<MCObjectTargetWriter>
100 bool HasRelocationAddend) {
101 return std::make_unique<AMDGPUELFObjectWriter>(Is64Bit, OSABI,
102 HasRelocationAddend);
Provides AMDGPU specific target descriptions.
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Context object for machine code objects.
void reportError(SMLoc L, const Twine &Msg)
virtual unsigned getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const =0
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
@ VK_AMDGPU_GOTPCREL32_LO
@ VK_AMDGPU_GOTPCREL32_HI
This represents an "assembler immediate".
Target - Wrapper for Target specific information.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_si_sopp_br
16-bit PC relative fixup for SOPP branch instructions.
This is an optimization pass for GlobalISel generic memory operations.
std::unique_ptr< MCObjectTargetWriter > createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend)
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_PCRel_4
A four-byte pc relative fixup.
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
@ FK_Data_8
A eight-byte fixup.
@ FK_Data_4
A four-byte fixup.
@ FK_SecRel_4
A four-byte section relative fixup.