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37 :
MRI(mri), MCII(mcii) {}
38 R600MCCodeEmitter(
const R600MCCodeEmitter &) =
delete;
39 R600MCCodeEmitter &operator=(
const R600MCCodeEmitter &) =
delete;
56 unsigned getHWReg(
unsigned regNo)
const;
63 verifyInstructionPredicates(
const MCInst &
MI,
95 verifyInstructionPredicates(
MI,
100 MI.getOpcode() == R600::FETCH_CLAUSE ||
101 MI.getOpcode() == R600::ALU_CLAUSE ||
102 MI.getOpcode() == R600::BUNDLE ||
103 MI.getOpcode() == R600::KILL) {
105 }
else if (
IS_VTX(Desc)) {
107 uint32_t InstWord2 =
MI.getOperand(2).getImm();
109 InstWord2 |= 1 << 19;
112 Emit(InstWord01, OS);
115 }
else if (
IS_TEX(Desc)) {
116 int64_t
Sampler =
MI.getOperand(14).getImm();
118 int64_t SrcSelect[4] = {
119 MI.getOperand(2).getImm(),
120 MI.getOperand(3).getImm(),
121 MI.getOperand(4).getImm(),
122 MI.getOperand(5).getImm()
125 MI.getOperand(6).getImm() & 0x1F,
126 MI.getOperand(7).getImm() & 0x1F,
127 MI.getOperand(8).getImm() & 0x1F
144 uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
145 Inst &= ~(0x3FFULL << 39);
146 Inst |= ISAOpCode << 1;
170 return MRI.getEncodingValue(MO.
getReg());
181 const unsigned offset = (&MO == &
MI.getOperand(0)) ? 0 : 4;
190 #define ENABLE_INSTR_PREDICATE_VERIFIER
191 #include "R600GenMCCodeEmitter.inc"
This is an optimization pass for GlobalISel generic memory operations.
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Container class for subtarget features.
Instances of this class represent a single low-level machine instruction.
static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr)
@ FK_SecRel_4
A four-byte section relative fixup.
Describe properties that are true of each instruction in the target description file.
const FeatureBitset & getFeatureBits() const
This class implements an extremely fast bulk output stream that can only output to a stream.
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
#define HAS_NATIVE_OPERANDS(Flags)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCCodeEmitter * createR600MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
Interface to description of machine instruction set.
MCCodeEmitter - Generic instruction encoding interface.
const MCExpr * getExpr() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Instances of this class represent operands of the MCInst class.
Generic base class for all target subtargets.
LLVM Value Representation.
unsigned getReg() const
Returns the register number.
#define HW_REG_MASK
Defines for extracting register information from register encoding.