#include "Target/AMDGPU/SIRegisterInfo.h"
Definition at line 56 of file SIRegisterInfo.h.
◆ SpilledReg() [1/2]
llvm::SIRegisterInfo::SpilledReg::SpilledReg |
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default |
◆ SpilledReg() [2/2]
llvm::SIRegisterInfo::SpilledReg::SpilledReg |
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Register |
R, |
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int |
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inline |
◆ hasLane()
bool llvm::SIRegisterInfo::SpilledReg::hasLane |
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inline |
◆ hasReg()
bool llvm::SIRegisterInfo::SpilledReg::hasReg |
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inline |
◆ Lane
int llvm::SIRegisterInfo::SpilledReg::Lane = -1 |
◆ VGPR
Register llvm::SIRegisterInfo::SpilledReg::VGPR |
The documentation for this struct was generated from the following file: