LLVM 24.0.0git
AMDGPUTargetStreamer.cpp
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1//===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides AMDGPU specific target streamer methods.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AMDGPUTargetStreamer.h"
14#include "AMDGPUMCExpr.h"
15#include "AMDGPUMCKernelDescriptor.h"
16#include "AMDGPUMCTargetDesc.h"
17#include "AMDGPUPTNote.h"
18#include "Utils/AMDGPUBaseInfo.h"
19#include "Utils/AMDKernelCodeTUtils.h"
20#include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h"
21#include "llvm/BinaryFormat/ELF.h"
22#include "llvm/MC/MCAsmInfo.h"
23#include "llvm/MC/MCAssembler.h"
24#include "llvm/MC/MCContext.h"
25#include "llvm/MC/MCELFObjectWriter.h"
26#include "llvm/MC/MCELFStreamer.h"
27#include "llvm/MC/MCSubtargetInfo.h"
28#include "llvm/MC/StringTableBuilder.h"
29#include "llvm/Support/AMDGPUMetadata.h"
30#include "llvm/Support/AMDGPUObjLinkingInfo.h"
31#include "llvm/Support/AMDHSAKernelDescriptor.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/FormattedStream.h"
34#include "llvm/TargetParser/AMDGPUTargetParser.h"
35
36using namespace llvm;
37using namespace llvm::AMDGPU;
38
39//===----------------------------------------------------------------------===//
40// AMDGPUTargetStreamer
41//===----------------------------------------------------------------------===//
42
43static cl::opt<unsigned>
44 ForceGenericVersion("amdgpu-force-generic-version",
45 cl::desc("Force a specific generic_v<N> flag to be "
46 "added. For testing purposes only."),
47 cl::ReallyHidden, cl::init(0));
48
49void AMDGPUTargetStreamer::initializeTargetID(const MCSubtargetInfo &STI,
50 bool ApplyFeatureString) {
51 assert(TargetID == std::nullopt && "TargetID can only be initialized once");
52 // Apply xnack/sramecc from subtarget features only in MC contexts
53 // (assembler), not in codegen where they come from module flags
54 TargetID = AMDGPU::createAMDGPUTargetID(
55 STI, ApplyFeatureString ? STI.getFeatureString() : "");
56}
57
58bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) {
59 msgpack::Document HSAMetadataDoc;
60 if (!HSAMetadataDoc.fromYAML(HSAMetadataString))
61 return false;
62 return EmitHSAMetadata(HSAMetadataDoc, false);
63}
64
65StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) {
66 AMDGPU::GPUKind AK;
67
68 // clang-format off
69 switch (ElfMach) {
70 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break;
71 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break;
72 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break;
73 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break;
74 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break;
75 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break;
76 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break;
77 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break;
78 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break;
79 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break;
80 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break;
81 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break;
82 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break;
83 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break;
84 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break;
85 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break;
86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break;
87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break;
88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break;
89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break;
90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break;
91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break;
92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break;
93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break;
94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break;
95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break;
96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break;
97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break;
98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break;
99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break;
100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break;
101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break;
102 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break;
103 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break;
104 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break;
105 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break;
106 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A: AK = GK_GFX90A; break;
107 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break;
108 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX942: AK = GK_GFX942; break;
109 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX950: AK = GK_GFX950; break;
110 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break;
111 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break;
112 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break;
113 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013: AK = GK_GFX1013; break;
114 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break;
115 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break;
116 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break;
117 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: AK = GK_GFX1033; break;
118 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034: AK = GK_GFX1034; break;
119 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035: AK = GK_GFX1035; break;
120 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036: AK = GK_GFX1036; break;
121 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100: AK = GK_GFX1100; break;
122 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101: AK = GK_GFX1101; break;
123 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102: AK = GK_GFX1102; break;
124 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103: AK = GK_GFX1103; break;
125 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1150: AK = GK_GFX1150; break;
126 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1151: AK = GK_GFX1151; break;
127 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1152: AK = GK_GFX1152; break;
128 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1153: AK = GK_GFX1153; break;
129 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1154: AK = GK_GFX1154; break;
130 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1170: AK = GK_GFX1170; break;
131 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1171: AK = GK_GFX1171; break;
132 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1172: AK = GK_GFX1172; break;
133 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1200: AK = GK_GFX1200; break;
134 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1201: AK = GK_GFX1201; break;
135 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1250_STRICT: AK = GK_GFX1250_STRICT; break;
136 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1250: AK = GK_GFX1250; break;
137 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1251: AK = GK_GFX1251; break;
138 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1310: AK = GK_GFX1310; break;
139 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC: AK = GK_GFX9_GENERIC; break;
140 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX9_4_GENERIC: AK = GK_GFX9_4_GENERIC; break;
141 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERIC: AK = GK_GFX10_1_GENERIC; break;
142 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_3_GENERIC: AK = GK_GFX10_3_GENERIC; break;
143 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX11_GENERIC: AK = GK_GFX11_GENERIC; break;
144 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX11_7_GENERIC: AK = GK_GFX11_7_GENERIC; break;
145 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX12_GENERIC: AK = GK_GFX12_GENERIC; break;
146 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX12_5_GENERIC: AK = GK_GFX12_5_GENERIC; break;
147 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX13_GENERIC: AK = GK_GFX13_GENERIC; break;
148 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break;
149 default: AK = GK_NONE; break;
150 }
151 // clang-format on
152
153 StringRef GPUName = getArchNameAMDGCN(AK);
154 if (GPUName != "")
155 return GPUName;
156 return getArchNameR600(AK);
157}
158
159unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) {
160 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU);
161 if (AK == AMDGPU::GPUKind::GK_NONE)
162 AK = parseArchR600(GPU);
163
164 // clang-format off
165 switch (AK) {
166 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600;
167 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630;
168 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880;
169 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670;
170 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710;
171 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730;
172 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770;
173 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR;
174 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS;
175 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER;
176 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD;
177 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO;
178 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS;
179 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS;
180 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN;
181 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS;
182 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600;
183 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601;
184 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602;
185 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700;
186 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701;
187 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702;
188 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703;
189 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704;
190 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705;
191 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801;
192 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802;
193 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803;
194 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805;
195 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810;
196 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900;
197 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902;
198 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904;
199 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906;
200 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908;
201 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909;
202 case GK_GFX90A: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A;
203 case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C;
204 case GK_GFX942: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX942;
205 case GK_GFX950: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX950;
206 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010;
207 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011;
208 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012;
209 case GK_GFX1013: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013;
210 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030;
211 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031;
212 case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032;
213 case GK_GFX1033: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033;
214 case GK_GFX1034: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034;
215 case GK_GFX1035: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035;
216 case GK_GFX1036: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036;
217 case GK_GFX1100: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100;
218 case GK_GFX1101: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101;
219 case GK_GFX1102: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102;
220 case GK_GFX1103: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103;
221 case GK_GFX1150: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1150;
222 case GK_GFX1151: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1151;
223 case GK_GFX1152: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1152;
224 case GK_GFX1153: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1153;
225 case GK_GFX1154: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1154;
226 case GK_GFX1170: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1170;
227 case GK_GFX1171: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1171;
228 case GK_GFX1172: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1172;
229 case GK_GFX1200: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1200;
230 case GK_GFX1201: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1201;
231 case GK_GFX1250_STRICT: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1250_STRICT;
232 case GK_GFX1250: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1250;
233 case GK_GFX1251: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1251;
234 case GK_GFX1310: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1310;
235 case GK_GFX9_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC;
236 case GK_GFX9_4_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX9_4_GENERIC;
237 case GK_GFX10_1_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERIC;
238 case GK_GFX10_3_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_3_GENERIC;
239 case GK_GFX11_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX11_GENERIC;
240 case GK_GFX11_7_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX11_7_GENERIC;
241 case GK_GFX12_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX12_GENERIC;
242 case GK_GFX12_5_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX12_5_GENERIC;
243 case GK_GFX13_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX13_GENERIC;
244 case GK_GENERIC:
245 case GK_GENERIC_HSA:
246 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE;
247 }
248 // clang-format on
249
250 llvm_unreachable("unknown GPU");
251}
252
253//===----------------------------------------------------------------------===//
254// AMDGPUTargetAsmStreamer
255//===----------------------------------------------------------------------===//
256
260
261// A hook for emitting stuff at the end.
262// We use it for emitting the accumulated PAL metadata as directives.
263// The PAL metadata is reset after it is emitted.
264void AMDGPUTargetAsmStreamer::finish() {
265 std::string S;
266 getPALMetadata()->toString(S);
267 OS << S;
268
269 // Reset the pal metadata so its data will not affect a compilation that
270 // reuses this object.
271 getPALMetadata()->reset();
272}
273
274void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() {
275 OS << "\t.amdgcn_target \"" << *getTargetID() << "\"\n";
276}
277
278void AMDGPUTargetAsmStreamer::EmitDirectiveAMDHSACodeObjectVersion(
279 unsigned COV) {
280 AMDGPUTargetStreamer::EmitDirectiveAMDHSACodeObjectVersion(COV);
281 OS << "\t.amdhsa_code_object_version " << COV << '\n';
282}
283
284void AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(AMDGPUMCKernelCodeT &Header) {
285 auto FoldAndPrint = [&](const MCExpr *Expr, raw_ostream &OS,
286 const MCAsmInfo *MAI) {
287 printAMDGPUMCExpr(foldAMDGPUMCExpr(Expr, getContext()), OS, MAI);
288 };
289
290 OS << "\t.amd_kernel_code_t\n";
291 Header.EmitKernelCodeT(OS, getContext(), FoldAndPrint);
292 OS << "\t.end_amd_kernel_code_t\n";
293}
294
295void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
296 unsigned Type) {
297 switch (Type) {
298 default:
299 llvm_unreachable("Invalid AMDGPU symbol type");
300 case ELF::STT_AMDGPU_HSA_KERNEL:
301 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n';
302 break;
303 }
304}
305
306void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size,
307 Align Alignment) {
308 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", "
309 << Alignment.value() << '\n';
310}
311
312void AMDGPUTargetAsmStreamer::EmitMCResourceInfo(
313 const MCSymbol *NumVGPR, const MCSymbol *NumAGPR,
314 const MCSymbol *NumExplicitSGPR, const MCSymbol *NumNamedBarrier,
315 const MCSymbol *PrivateSegmentSize, const MCSymbol *UsesVCC,
316 const MCSymbol *UsesFlatScratch, const MCSymbol *HasDynamicallySizedStack,
317 const MCSymbol *HasRecursion, const MCSymbol *HasIndirectCall) {
318#define PRINT_RES_INFO(ARG) \
319 OS << "\t.set "; \
320 ARG->print(OS, &getContext().getAsmInfo()); \
321 OS << ", "; \
322 getContext().getAsmInfo().printExpr(OS, *ARG->getVariableValue()); \
323 Streamer.addBlankLine();
324
325 PRINT_RES_INFO(NumVGPR);
326 PRINT_RES_INFO(NumAGPR);
327 PRINT_RES_INFO(NumExplicitSGPR);
328 PRINT_RES_INFO(NumNamedBarrier);
329 PRINT_RES_INFO(PrivateSegmentSize);
330 PRINT_RES_INFO(UsesVCC);
331 PRINT_RES_INFO(UsesFlatScratch);
332 PRINT_RES_INFO(HasDynamicallySizedStack);
333 PRINT_RES_INFO(HasRecursion);
334 PRINT_RES_INFO(HasIndirectCall);
335#undef PRINT_RES_INFO
336}
337
338void AMDGPUTargetAsmStreamer::EmitMCResourceMaximums(
339 const MCSymbol *MaxVGPR, const MCSymbol *MaxAGPR, const MCSymbol *MaxSGPR,
340 const MCSymbol *MaxNamedBarrier) {
341#define PRINT_RES_INFO(ARG) \
342 OS << "\t.set "; \
343 ARG->print(OS, &getContext().getAsmInfo()); \
344 OS << ", "; \
345 getContext().getAsmInfo().printExpr(OS, *ARG->getVariableValue()); \
346 Streamer.addBlankLine();
347
348 PRINT_RES_INFO(MaxVGPR);
349 PRINT_RES_INFO(MaxAGPR);
350 PRINT_RES_INFO(MaxSGPR);
351 PRINT_RES_INFO(MaxNamedBarrier);
352#undef PRINT_RES_INFO
353}
354
355bool AMDGPUTargetAsmStreamer::EmitISAVersion() {
356 OS << "\t.amd_amdgpu_isa \"" << getTargetID() << "\"\n";
357 return true;
358}
359
360bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc,
361 bool Strict) {
362 HSAMD::V3::MetadataVerifier Verifier(Strict);
363 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
364 return false;
365
366 std::string HSAMetadataString;
367 raw_string_ostream StrOS(HSAMetadataString);
368 HSAMetadataDoc.toYAML(StrOS);
369
370 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n';
371 OS << StrOS.str() << '\n';
372 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n';
373 return true;
374}
375
376bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
377 const uint32_t Encoded_s_code_end = 0xbf9f0000;
378 const uint32_t Encoded_s_nop = 0xbf800000;
379 uint32_t Encoded_pad = Encoded_s_code_end;
380
381 // Instruction cache line size in bytes.
382 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
383 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
384
385 // Extra padding amount in bytes to support prefetch mode 3.
386 unsigned FillSize = 3 * CacheLineSize;
387
388 if (AMDGPU::isGFX90A(STI)) {
389 Encoded_pad = Encoded_s_nop;
390 FillSize = 16 * CacheLineSize;
391 }
392
393 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n';
394 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n';
395 return true;
396}
397
398void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
399 const MCSubtargetInfo &STI, StringRef KernelName,
400 const MCKernelDescriptor &KD, const MCExpr *NextVGPR,
401 const MCExpr *NextSGPR, const MCExpr *ReserveVCC,
402 const MCExpr *ReserveFlatScr) {
403 IsaVersion IVersion = getIsaVersion(STI.getCPU());
404 const MCAsmInfo &MAI = getContext().getAsmInfo();
405
406 OS << "\t.amdhsa_kernel " << KernelName << '\n';
407
408 auto PrintField = [&](const MCExpr *Expr, uint32_t Shift, uint32_t Mask,
409 StringRef Directive) {
410 OS << "\t\t" << Directive << ' ';
411 const MCExpr *ShiftedAndMaskedExpr =
412 MCKernelDescriptor::bits_get(Expr, Shift, Mask, getContext());
413 const MCExpr *New = foldAMDGPUMCExpr(ShiftedAndMaskedExpr, getContext());
414 printAMDGPUMCExpr(New, OS, &MAI);
415 OS << '\n';
416 };
417
418 auto EmitMCExpr = [&](const MCExpr *Value) {
419 const MCExpr *NewExpr = foldAMDGPUMCExpr(Value, getContext());
420 printAMDGPUMCExpr(NewExpr, OS, &MAI);
421 };
422
423 OS << "\t\t.amdhsa_group_segment_fixed_size ";
424 EmitMCExpr(KD.group_segment_fixed_size);
425 OS << '\n';
426
427 OS << "\t\t.amdhsa_private_segment_fixed_size ";
428 EmitMCExpr(KD.private_segment_fixed_size);
429 OS << '\n';
430
431 OS << "\t\t.amdhsa_kernarg_size ";
432 EmitMCExpr(KD.kernarg_size);
433 OS << '\n';
434
435 if (isGFX1250Plus(STI)) {
436 PrintField(KD.compute_pgm_rsrc2,
437 amdhsa::COMPUTE_PGM_RSRC2_GFX125_USER_SGPR_COUNT_SHIFT,
438 amdhsa::COMPUTE_PGM_RSRC2_GFX125_USER_SGPR_COUNT,
439 ".amdhsa_user_sgpr_count");
440 } else {
441 PrintField(KD.compute_pgm_rsrc2,
442 amdhsa::COMPUTE_PGM_RSRC2_GFX6_GFX120_USER_SGPR_COUNT_SHIFT,
443 amdhsa::COMPUTE_PGM_RSRC2_GFX6_GFX120_USER_SGPR_COUNT,
444 ".amdhsa_user_sgpr_count");
445 }
446
447 if (!hasArchitectedFlatScratch(STI))
448 PrintField(
449 KD.kernel_code_properties,
450 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT,
451 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER,
452 ".amdhsa_user_sgpr_private_segment_buffer");
453 PrintField(KD.kernel_code_properties,
454 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_SHIFT,
455 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR,
456 ".amdhsa_user_sgpr_dispatch_ptr");
457 PrintField(KD.kernel_code_properties,
458 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_SHIFT,
459 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR,
460 ".amdhsa_user_sgpr_queue_ptr");
461 PrintField(KD.kernel_code_properties,
462 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT,
463 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR,
464 ".amdhsa_user_sgpr_kernarg_segment_ptr");
465 PrintField(KD.kernel_code_properties,
466 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID_SHIFT,
467 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID,
468 ".amdhsa_user_sgpr_dispatch_id");
469 if (!hasArchitectedFlatScratch(STI))
470 PrintField(KD.kernel_code_properties,
471 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT,
472 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT,
473 ".amdhsa_user_sgpr_flat_scratch_init");
474 if (hasKernargPreload(STI)) {
475 PrintField(KD.kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_LENGTH_SHIFT,
476 amdhsa::KERNARG_PRELOAD_SPEC_LENGTH,
477 ".amdhsa_user_sgpr_kernarg_preload_length");
478 PrintField(KD.kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_OFFSET_SHIFT,
479 amdhsa::KERNARG_PRELOAD_SPEC_OFFSET,
480 ".amdhsa_user_sgpr_kernarg_preload_offset");
481 }
482 PrintField(
483 KD.kernel_code_properties,
484 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT,
485 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE,
486 ".amdhsa_user_sgpr_private_segment_size");
487 if (IVersion.Major >= 10)
488 PrintField(KD.kernel_code_properties,
489 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_SHIFT,
490 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
491 ".amdhsa_wavefront_size32");
492 if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5)
493 PrintField(KD.kernel_code_properties,
494 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK_SHIFT,
495 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK,
496 ".amdhsa_uses_dynamic_stack");
497 PrintField(KD.compute_pgm_rsrc2,
498 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT_SHIFT,
499 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT,
500 (hasArchitectedFlatScratch(STI)
501 ? ".amdhsa_enable_private_segment"
502 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"));
503 PrintField(KD.compute_pgm_rsrc2,
504 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT,
505 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X,
506 ".amdhsa_system_sgpr_workgroup_id_x");
507 PrintField(KD.compute_pgm_rsrc2,
508 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y_SHIFT,
509 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y,
510 ".amdhsa_system_sgpr_workgroup_id_y");
511 PrintField(KD.compute_pgm_rsrc2,
512 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z_SHIFT,
513 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z,
514 ".amdhsa_system_sgpr_workgroup_id_z");
515 PrintField(KD.compute_pgm_rsrc2,
516 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO_SHIFT,
517 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO,
518 ".amdhsa_system_sgpr_workgroup_info");
519 PrintField(KD.compute_pgm_rsrc2,
520 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID_SHIFT,
521 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID,
522 ".amdhsa_system_vgpr_workitem_id");
523
524 // These directives are required.
525 OS << "\t\t.amdhsa_next_free_vgpr ";
526 EmitMCExpr(NextVGPR);
527 OS << '\n';
528
529 OS << "\t\t.amdhsa_next_free_sgpr ";
530 EmitMCExpr(NextSGPR);
531 OS << '\n';
532
533 if (AMDGPU::isGFX90A(STI)) {
534 // MCExpr equivalent of taking the (accum_offset + 1) * 4.
535 const MCExpr *accum_bits = MCKernelDescriptor::bits_get(
536 KD.compute_pgm_rsrc3,
537 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET_SHIFT,
538 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET, getContext());
539 accum_bits = MCBinaryExpr::createAdd(
540 accum_bits, MCConstantExpr::create(1, getContext()), getContext());
541 accum_bits = MCBinaryExpr::createMul(
542 accum_bits, MCConstantExpr::create(4, getContext()), getContext());
543 OS << "\t\t.amdhsa_accum_offset ";
544 const MCExpr *New = foldAMDGPUMCExpr(accum_bits, getContext());
545 printAMDGPUMCExpr(New, OS, &MAI);
546 OS << '\n';
547 }
548
549 if (isGFX1250Plus(STI))
550 PrintField(KD.compute_pgm_rsrc3,
551 amdhsa::COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT_SHIFT,
552 amdhsa::COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT,
553 ".amdhsa_named_barrier_count");
554
555 OS << "\t\t.amdhsa_reserve_vcc ";
556 EmitMCExpr(ReserveVCC);
557 OS << '\n';
558
559 if (IVersion.Major >= 7 && !hasArchitectedFlatScratch(STI)) {
560 OS << "\t\t.amdhsa_reserve_flat_scratch ";
561 EmitMCExpr(ReserveFlatScr);
562 OS << '\n';
563 }
564
565 switch (CodeObjectVersion) {
566 default:
567 break;
568 case AMDGPU::AMDHSA_COV4:
569 case AMDGPU::AMDHSA_COV5:
570 if (STI.hasFeature(AMDGPU::FeatureSupportsXNACK)) {
571 bool XnackOn = getTargetID()->isXnackOnOrAny() ||
572 STI.hasFeature(AMDGPU::FeatureXNACK);
573 OS << "\t\t.amdhsa_reserve_xnack_mask " << XnackOn << '\n';
574 }
575 break;
576 }
577
578 PrintField(KD.compute_pgm_rsrc1,
579 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32_SHIFT,
580 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32,
581 ".amdhsa_float_round_mode_32");
582 PrintField(KD.compute_pgm_rsrc1,
583 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64_SHIFT,
584 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64,
585 ".amdhsa_float_round_mode_16_64");
586 PrintField(KD.compute_pgm_rsrc1,
587 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32_SHIFT,
588 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32,
589 ".amdhsa_float_denorm_mode_32");
590 PrintField(KD.compute_pgm_rsrc1,
591 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64_SHIFT,
592 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64,
593 ".amdhsa_float_denorm_mode_16_64");
594 if (STI.hasFeature(AMDGPU::FeatureDX10ClampAndIEEEMode)) {
595 PrintField(KD.compute_pgm_rsrc1,
596 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP_SHIFT,
597 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP,
598 ".amdhsa_dx10_clamp");
599 PrintField(KD.compute_pgm_rsrc1,
600 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE_SHIFT,
601 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE,
602 ".amdhsa_ieee_mode");
603 }
604 if (IVersion.Major >= 9) {
605 PrintField(KD.compute_pgm_rsrc1,
606 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL_SHIFT,
607 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL,
608 ".amdhsa_fp16_overflow");
609 }
610 if (AMDGPU::isGFX90A(STI))
611 PrintField(KD.compute_pgm_rsrc3,
612 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT,
613 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, ".amdhsa_tg_split");
614 if (AMDGPU::supportsWGP(STI))
615 PrintField(KD.compute_pgm_rsrc1,
616 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE_SHIFT,
617 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE,
618 ".amdhsa_workgroup_processor_mode");
619 if (IVersion.Major >= 10) {
620 PrintField(KD.compute_pgm_rsrc1,
621 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED_SHIFT,
622 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED,
623 ".amdhsa_memory_ordered");
624 PrintField(KD.compute_pgm_rsrc1,
625 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS_SHIFT,
626 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS,
627 ".amdhsa_forward_progress");
628 }
629 if (IVersion.Major >= 10 && IVersion.Major < 12) {
630 PrintField(KD.compute_pgm_rsrc3,
631 amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT_SHIFT,
632 amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT,
633 ".amdhsa_shared_vgpr_count");
634 }
635 if (IVersion.Major == 11) {
636 PrintField(KD.compute_pgm_rsrc3,
637 amdhsa::COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE_SHIFT,
638 amdhsa::COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE,
639 ".amdhsa_inst_pref_size");
640 }
641 if (IVersion.Major >= 12) {
642 PrintField(KD.compute_pgm_rsrc3,
643 amdhsa::COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE_SHIFT,
644 amdhsa::COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE,
645 ".amdhsa_inst_pref_size");
646 PrintField(KD.compute_pgm_rsrc1,
647 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN_SHIFT,
648 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN,
649 ".amdhsa_round_robin_scheduling");
650 }
651 PrintField(
652 KD.compute_pgm_rsrc2,
653 amdhsa::
654 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_SHIFT,
655 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION,
656 ".amdhsa_exception_fp_ieee_invalid_op");
657 PrintField(
658 KD.compute_pgm_rsrc2,
659 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_SHIFT,
660 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE,
661 ".amdhsa_exception_fp_denorm_src");
662 PrintField(
663 KD.compute_pgm_rsrc2,
664 amdhsa::
665 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_SHIFT,
666 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO,
667 ".amdhsa_exception_fp_ieee_div_zero");
668 PrintField(
669 KD.compute_pgm_rsrc2,
670 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_SHIFT,
671 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW,
672 ".amdhsa_exception_fp_ieee_overflow");
673 PrintField(
674 KD.compute_pgm_rsrc2,
675 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_SHIFT,
676 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW,
677 ".amdhsa_exception_fp_ieee_underflow");
678 PrintField(
679 KD.compute_pgm_rsrc2,
680 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_SHIFT,
681 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT,
682 ".amdhsa_exception_fp_ieee_inexact");
683 PrintField(
684 KD.compute_pgm_rsrc2,
685 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO_SHIFT,
686 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO,
687 ".amdhsa_exception_int_div_zero");
688
689 OS << "\t.end_amdhsa_kernel\n";
690}
691
692namespace {
693/// Callback type invoked by \c forEachInfoScope for each function scope in
694/// the canonical iteration order. The scope is emitted exactly once per
695/// unique \p Sym regardless of how many flat entries reference it.
696using InfoScopeEmitter = function_ref<void(
697 MCSymbol *Sym, const AMDGPU::FuncInfo *Info, ArrayRef<MCSymbol *> Uses,
698 ArrayRef<MCSymbol *> Calls, ArrayRef<StringRef> IndirectCallTypeIds,
699 ArrayRef<StringRef> TypeIds)>;
700
701/// Group the flat edge lists in \p Data by source function symbol and drive
702/// per-scope emission. A scope is opened for every function with attached
703/// info and for every function that appears only as an edge source; each
704/// scope is emitted exactly once. Both the asm and ELF streamers share this
705/// iteration logic and only differ in the per-scope emission callback.
706static void forEachInfoScope(const AMDGPU::InfoSectionData &Data,
707 InfoScopeEmitter Emit) {
708 DenseMap<MCSymbol *, SmallVector<MCSymbol *, 2>> FuncUses;
709 DenseMap<MCSymbol *, SmallVector<MCSymbol *, 4>> FuncCalls;
710 DenseMap<MCSymbol *, SmallVector<StringRef, 2>> FuncIndirectCalls;
711 DenseMap<MCSymbol *, SmallVector<StringRef, 1>> FuncTypeIds;
712 for (const auto &[Func, Res] : Data.Uses)
713 FuncUses[Func].push_back(Res);
714 for (const auto &[Src, Dst] : Data.Calls)
715 FuncCalls[Src].push_back(Dst);
716 for (const auto &[Func, TypeId] : Data.IndirectCalls)
717 FuncIndirectCalls[Func].push_back(TypeId);
718 for (const auto &[Sym, TypeId] : Data.TypeIds)
719 FuncTypeIds[Sym].push_back(TypeId);
720
721 DenseSet<MCSymbol *> Emitted;
722 auto EmitIfNew = [&](MCSymbol *Sym, const AMDGPU::FuncInfo *Info) {
723 if (!Emitted.insert(Sym).second)
724 return;
725 ArrayRef<MCSymbol *> Uses, Calls;
726 ArrayRef<StringRef> IndirectCallTypeIds, TypeIds;
727 if (auto It = FuncUses.find(Sym); It != FuncUses.end())
728 Uses = It->second;
729 if (auto It = FuncCalls.find(Sym); It != FuncCalls.end())
730 Calls = It->second;
731 if (auto It = FuncIndirectCalls.find(Sym); It != FuncIndirectCalls.end())
732 IndirectCallTypeIds = It->second;
733 if (auto It = FuncTypeIds.find(Sym); It != FuncTypeIds.end())
734 TypeIds = It->second;
735 Emit(Sym, Info, Uses, Calls, IndirectCallTypeIds, TypeIds);
736 };
737
738 for (const AMDGPU::FuncInfo &Func : Data.Funcs)
739 EmitIfNew(Func.Sym, &Func);
740 // Emit scopes for functions that only appear as edge sources (e.g. typeid
741 // tags on address-taken declarations, or callers of external functions).
742 for (const auto &[Sym, TypeId] : Data.TypeIds)
743 EmitIfNew(Sym, nullptr);
744 for (const auto &[Sym, Res] : Data.Uses)
745 EmitIfNew(Sym, nullptr);
746 for (const auto &[Sym, Dst] : Data.Calls)
747 EmitIfNew(Sym, nullptr);
748 for (const auto &[Sym, TypeId] : Data.IndirectCalls)
749 EmitIfNew(Sym, nullptr);
750}
751} // namespace
752
753void AMDGPUTargetAsmStreamer::emitAMDGPUInfo(
754 const AMDGPU::InfoSectionData &Data) {
755 forEachInfoScope(Data, [&](MCSymbol *Sym, const AMDGPU::FuncInfo *Info,
756 ArrayRef<MCSymbol *> Uses,
757 ArrayRef<MCSymbol *> Calls,
758 ArrayRef<StringRef> IndirectCallTypeIds,
759 ArrayRef<StringRef> TypeIds) {
760 OS << "\t.amdgpu_info " << Sym->getName() << '\n';
761 if (Info) {
762 AMDGPU::FuncInfoFlags Flags{};
763 if (Info->UsesVCC)
764 Flags |= AMDGPU::FuncInfoFlags::FUNC_USES_VCC;
765 if (Info->UsesFlatScratch)
766 Flags |= AMDGPU::FuncInfoFlags::FUNC_USES_FLAT_SCRATCH;
767 if (Info->HasDynStack)
768 Flags |= AMDGPU::FuncInfoFlags::FUNC_HAS_DYN_STACK;
769 OS << "\t\t.amdgpu_flags " << llvm::to_underlying(Flags) << '\n';
770 OS << "\t\t.amdgpu_num_sgpr " << Info->NumSGPR << '\n';
771 OS << "\t\t.amdgpu_num_vgpr " << Info->NumArchVGPR << '\n';
772 if (Info->NumAccVGPR)
773 OS << "\t\t.amdgpu_num_agpr " << Info->NumAccVGPR << '\n';
774 OS << "\t\t.amdgpu_private_segment_size " << Info->PrivateSegmentSize
775 << '\n';
776 }
777 for (MCSymbol *Res : Uses)
778 OS << "\t\t.amdgpu_use " << Res->getName() << '\n';
779 for (MCSymbol *Dst : Calls)
780 OS << "\t\t.amdgpu_call " << Dst->getName() << '\n';
781 for (StringRef TypeId : IndirectCallTypeIds)
782 OS << "\t\t.amdgpu_indirect_call \"" << TypeId << "\"\n";
783 for (StringRef TypeId : TypeIds)
784 OS << "\t\t.amdgpu_typeid \"" << TypeId << "\"\n";
785 OS << "\t.end_amdgpu_info\n\n";
786 });
787}
788
789//===----------------------------------------------------------------------===//
790// AMDGPUTargetELFStreamer
791//===----------------------------------------------------------------------===//
792
796
797MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() {
798 return static_cast<MCELFStreamer &>(Streamer);
799}
800
801// A hook for emitting stuff at the end.
802// We use it for emitting the accumulated PAL metadata as a .note record.
803// The PAL metadata is reset after it is emitted.
804void AMDGPUTargetELFStreamer::finish() {
805 ELFObjectWriter &W = getStreamer().getWriter();
806 W.setELFHeaderEFlags(getEFlags());
807 W.setOverrideABIVersion(
808 getELFABIVersion(STI.getTargetTriple(), CodeObjectVersion));
809
810 std::string Blob;
811 const char *Vendor = getPALMetadata()->getVendor();
812 unsigned Type = getPALMetadata()->getType();
813 getPALMetadata()->toBlob(Type, Blob);
814 if (Blob.empty())
815 return;
816 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type,
817 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); });
818
819 // Reset the pal metadata so its data will not affect a compilation that
820 // reuses this object.
821 getPALMetadata()->reset();
822}
823
824void AMDGPUTargetELFStreamer::EmitNote(
825 StringRef Name, const MCExpr *DescSZ, unsigned NoteType,
826 function_ref<void(MCELFStreamer &)> EmitDesc) {
827 auto &S = getStreamer();
828 auto &Context = S.getContext();
829
830 auto NameSZ = Name.size() + 1;
831
832 unsigned NoteFlags = 0;
833 // TODO Apparently, this is currently needed for OpenCL as mentioned in
834 // https://reviews.llvm.org/D74995
835 if (isHsaAbi(STI))
836 NoteFlags = ELF::SHF_ALLOC;
837
838 S.pushSection();
839 S.switchSection(
840 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags));
841 S.emitInt32(NameSZ); // namesz
842 S.emitValue(DescSZ, 4); // descz
843 S.emitInt32(NoteType); // type
844 S.emitBytes(Name); // name
845 S.emitInt8(0); // null terminator
846 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
847 EmitDesc(S); // desc
848 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
849 S.popSection();
850}
851
852unsigned AMDGPUTargetELFStreamer::getEFlags() {
853 switch (STI.getTargetTriple().getArch()) {
854 default:
855 llvm_unreachable("Unsupported Arch");
856 case Triple::r600:
857 return getEFlagsR600();
858 case Triple::amdgpu:
859 return getEFlagsAMDGCN();
860 }
861}
862
863unsigned AMDGPUTargetELFStreamer::getEFlagsR600() {
864 assert(STI.getTargetTriple().getArch() == Triple::r600);
865
866 return getElfMach(STI.getCPU());
867}
868
869unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() {
870 assert(STI.getTargetTriple().isAMDGCN());
871
872 switch (STI.getTargetTriple().getOS()) {
873 default:
874 // TODO: Why are some tests have "mingw" listed as OS?
875 // llvm_unreachable("Unsupported OS");
876 case Triple::UnknownOS:
877 return getEFlagsUnknownOS();
878 case Triple::AMDHSA:
879 return getEFlagsAMDHSA();
880 case Triple::AMDPAL:
881 return getEFlagsAMDPAL();
882 case Triple::Mesa3D:
883 return getEFlagsMesa3D();
884 }
885}
886
887unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() {
888 // TODO: Why are some tests have "mingw" listed as OS?
889 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS);
890
891 return getEFlagsV3();
892}
893
894unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() {
895 assert(isHsaAbi(STI));
896
897 if (CodeObjectVersion >= 6)
898 return getEFlagsV6();
899 return getEFlagsV4();
900}
901
902unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() {
903 assert(STI.getTargetTriple().getOS() == Triple::AMDPAL);
904
905 return getEFlagsV3();
906}
907
908unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() {
909 assert(STI.getTargetTriple().getOS() == Triple::Mesa3D);
910
911 return getEFlagsV3();
912}
913
914unsigned AMDGPUTargetELFStreamer::getEFlagsV3() {
915 unsigned EFlagsV3 = 0;
916
917 // mach.
918 EFlagsV3 |= getElfMach(STI.getCPU());
919
920 // xnack.
921 if (getTargetID()->isXnackOnOrAny())
922 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_XNACK_V3;
923 // sramecc.
924 if (getTargetID()->isSramEccOnOrAny())
925 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_V3;
926
927 return EFlagsV3;
928}
929
930unsigned AMDGPUTargetELFStreamer::getEFlagsV4() {
931 unsigned EFlagsV4 = 0;
932
933 // mach.
934 EFlagsV4 |= getElfMach(STI.getCPU());
935
936 // xnack.
937 switch (getTargetID()->getXnackSetting()) {
938 case AMDGPU::TargetIDSetting::Unsupported:
939 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4;
940 break;
941 case AMDGPU::TargetIDSetting::Any:
942 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4;
943 break;
944 case AMDGPU::TargetIDSetting::Off:
945 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4;
946 break;
947 case AMDGPU::TargetIDSetting::On:
948 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4;
949 break;
950 }
951 // sramecc.
952 switch (getTargetID()->getSramEccSetting()) {
953 case AMDGPU::TargetIDSetting::Unsupported:
954 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4;
955 break;
956 case AMDGPU::TargetIDSetting::Any:
957 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4;
958 break;
959 case AMDGPU::TargetIDSetting::Off:
960 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4;
961 break;
962 case AMDGPU::TargetIDSetting::On:
963 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4;
964 break;
965 }
966
967 return EFlagsV4;
968}
969
970unsigned AMDGPUTargetELFStreamer::getEFlagsV6() {
971 unsigned Flags = getEFlagsV4();
972
973 unsigned Version = ForceGenericVersion;
974 if (!Version) {
975 switch (parseArchAMDGCN(STI.getCPU())) {
976 case AMDGPU::GK_GFX9_GENERIC:
977 Version = GenericVersion::GFX9;
978 break;
979 case AMDGPU::GK_GFX9_4_GENERIC:
980 Version = GenericVersion::GFX9_4;
981 break;
982 case AMDGPU::GK_GFX10_1_GENERIC:
983 Version = GenericVersion::GFX10_1;
984 break;
985 case AMDGPU::GK_GFX10_3_GENERIC:
986 Version = GenericVersion::GFX10_3;
987 break;
988 case AMDGPU::GK_GFX11_GENERIC:
989 Version = GenericVersion::GFX11;
990 break;
991 case AMDGPU::GK_GFX11_7_GENERIC:
992 Version = GenericVersion::GFX11_7;
993 break;
994 case AMDGPU::GK_GFX12_GENERIC:
995 Version = GenericVersion::GFX12;
996 break;
997 case AMDGPU::GK_GFX12_5_GENERIC:
998 Version = GenericVersion::GFX12_5;
999 break;
1000 case AMDGPU::GK_GFX13_GENERIC:
1001 Version = GenericVersion::GFX13;
1002 break;
1003 default:
1004 break;
1005 }
1006 }
1007
1008 // Versions start at 1.
1009 if (Version) {
1010 if (Version > ELF::EF_AMDGPU_GENERIC_VERSION_MAX)
1011 report_fatal_error("Cannot encode generic code object version " +
1012 Twine(Version) +
1013 " - no ELF flag can represent this version!");
1014 Flags |= (Version << ELF::EF_AMDGPU_GENERIC_VERSION_OFFSET);
1015 }
1016
1017 return Flags;
1018}
1019
1020void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {}
1021
1022void AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(AMDGPUMCKernelCodeT &Header) {
1023 MCStreamer &OS = getStreamer();
1024 OS.pushSection();
1025 Header.EmitKernelCodeT(OS, getContext());
1026 OS.popSection();
1027}
1028
1029void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
1030 unsigned Type) {
1031 auto *Symbol = static_cast<MCSymbolELF *>(
1032 getStreamer().getContext().getOrCreateSymbol(SymbolName));
1033 Symbol->setType(Type);
1034}
1035
1036void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size,
1037 Align Alignment) {
1038 auto *SymbolELF = static_cast<MCSymbolELF *>(Symbol);
1039 SymbolELF->setType(ELF::STT_OBJECT);
1040
1041 if (!SymbolELF->isBindingSet())
1042 SymbolELF->setBinding(ELF::STB_GLOBAL);
1043
1044 if (SymbolELF->declareCommon(Size, Alignment)) {
1045 report_fatal_error("Symbol: " + Symbol->getName() +
1046 " redeclared as different type");
1047 }
1048
1049 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS);
1050 SymbolELF->setSize(MCConstantExpr::create(Size, getContext()));
1051}
1052
1053bool AMDGPUTargetELFStreamer::EmitISAVersion() {
1054 // Create two labels to mark the beginning and end of the desc field
1055 // and a MCExpr to calculate the size of the desc field.
1056 auto &Context = getContext();
1057 auto *DescBegin = Context.createTempSymbol();
1058 auto *DescEnd = Context.createTempSymbol();
1059 auto *DescSZ = MCBinaryExpr::createSub(
1060 MCSymbolRefExpr::create(DescEnd, Context),
1061 MCSymbolRefExpr::create(DescBegin, Context), Context);
1062
1063 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_ISA_NAME,
1064 [&](MCELFStreamer &OS) {
1065 OS.emitLabel(DescBegin);
1066
1067 SmallString<32> Str;
1068 raw_svector_ostream StrOS(Str);
1069 StrOS << *getTargetID();
1070
1071 OS.emitBytes(StrOS.str());
1072 OS.emitLabel(DescEnd);
1073 });
1074 return true;
1075}
1076
1077bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc,
1078 bool Strict) {
1079 HSAMD::V3::MetadataVerifier Verifier(Strict);
1080 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
1081 return false;
1082
1083 std::string HSAMetadataString;
1084 HSAMetadataDoc.writeToBlob(HSAMetadataString);
1085
1086 // Create two labels to mark the beginning and end of the desc field
1087 // and a MCExpr to calculate the size of the desc field.
1088 auto &Context = getContext();
1089 auto *DescBegin = Context.createTempSymbol();
1090 auto *DescEnd = Context.createTempSymbol();
1091 auto *DescSZ = MCBinaryExpr::createSub(
1092 MCSymbolRefExpr::create(DescEnd, Context),
1093 MCSymbolRefExpr::create(DescBegin, Context), Context);
1094
1095 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA,
1096 [&](MCELFStreamer &OS) {
1097 OS.emitLabel(DescBegin);
1098 OS.emitBytes(HSAMetadataString);
1099 OS.emitLabel(DescEnd);
1100 });
1101 return true;
1102}
1103
1104bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
1105 const uint32_t Encoded_s_code_end = 0xbf9f0000;
1106 const uint32_t Encoded_s_nop = 0xbf800000;
1107 uint32_t Encoded_pad = Encoded_s_code_end;
1108
1109 // Instruction cache line size in bytes.
1110 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
1111 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
1112
1113 // Extra padding amount in bytes to support prefetch mode 3.
1114 unsigned FillSize = 3 * CacheLineSize;
1115
1116 if (AMDGPU::isGFX90A(STI)) {
1117 Encoded_pad = Encoded_s_nop;
1118 FillSize = 16 * CacheLineSize;
1119 }
1120
1121 MCStreamer &OS = getStreamer();
1122 OS.pushSection();
1123 OS.emitValueToAlignment(Align(CacheLineSize), Encoded_pad, 4);
1124 for (unsigned I = 0; I < FillSize; I += 4)
1125 OS.emitInt32(Encoded_pad);
1126 OS.popSection();
1127 return true;
1128}
1129
1130void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor(
1131 const MCSubtargetInfo &STI, StringRef KernelName,
1132 const MCKernelDescriptor &KernelDescriptor, const MCExpr *NextVGPR,
1133 const MCExpr *NextSGPR, const MCExpr *ReserveVCC,
1134 const MCExpr *ReserveFlatScr) {
1135 auto &Streamer = getStreamer();
1136 auto &Context = Streamer.getContext();
1137
1138 auto *KernelCodeSymbol =
1139 static_cast<MCSymbolELF *>(Context.getOrCreateSymbol(Twine(KernelName)));
1140 auto *KernelDescriptorSymbol = static_cast<MCSymbolELF *>(
1141 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd")));
1142
1143 // Copy kernel descriptor symbol's binding, other and visibility from the
1144 // kernel code symbol.
1145 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding());
1146 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther());
1147 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility());
1148 // Kernel descriptor symbol's type and size are fixed.
1149 KernelDescriptorSymbol->setType(ELF::STT_OBJECT);
1150 KernelDescriptorSymbol->setSize(
1151 MCConstantExpr::create(sizeof(amdhsa::kernel_descriptor_t), Context));
1152
1153 // The visibility of the kernel code symbol must be protected or less to allow
1154 // static relocations from the kernel descriptor to be used.
1155 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT)
1156 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED);
1157
1158 Streamer.emitLabel(KernelDescriptorSymbol);
1159 Streamer.emitValue(
1160 KernelDescriptor.group_segment_fixed_size,
1161 sizeof(amdhsa::kernel_descriptor_t::group_segment_fixed_size));
1162 Streamer.emitValue(
1163 KernelDescriptor.private_segment_fixed_size,
1164 sizeof(amdhsa::kernel_descriptor_t::private_segment_fixed_size));
1165 Streamer.emitValue(KernelDescriptor.kernarg_size,
1166 sizeof(amdhsa::kernel_descriptor_t::kernarg_size));
1167
1168 for (uint32_t i = 0; i < sizeof(amdhsa::kernel_descriptor_t::reserved0); ++i)
1169 Streamer.emitInt8(0u);
1170
1171 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The
1172 // expression being created is:
1173 // (start of kernel code) - (start of kernel descriptor)
1174 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
1175 Streamer.emitValue(
1176 MCBinaryExpr::createSub(
1177 MCSymbolRefExpr::create(KernelCodeSymbol, AMDGPUMCExpr::S_REL64,
1178 Context),
1179 MCSymbolRefExpr::create(KernelDescriptorSymbol, Context), Context),
1180 sizeof(amdhsa::kernel_descriptor_t::kernel_code_entry_byte_offset));
1181 for (uint32_t i = 0; i < sizeof(amdhsa::kernel_descriptor_t::reserved1); ++i)
1182 Streamer.emitInt8(0u);
1183 Streamer.emitValue(KernelDescriptor.compute_pgm_rsrc3,
1184 sizeof(amdhsa::kernel_descriptor_t::compute_pgm_rsrc3));
1185 Streamer.emitValue(KernelDescriptor.compute_pgm_rsrc1,
1186 sizeof(amdhsa::kernel_descriptor_t::compute_pgm_rsrc1));
1187 Streamer.emitValue(KernelDescriptor.compute_pgm_rsrc2,
1188 sizeof(amdhsa::kernel_descriptor_t::compute_pgm_rsrc2));
1189 Streamer.emitValue(
1190 KernelDescriptor.kernel_code_properties,
1191 sizeof(amdhsa::kernel_descriptor_t::kernel_code_properties));
1192 Streamer.emitValue(KernelDescriptor.kernarg_preload,
1193 sizeof(amdhsa::kernel_descriptor_t::kernarg_preload));
1194 for (uint32_t i = 0; i < sizeof(amdhsa::kernel_descriptor_t::reserved3); ++i)
1195 Streamer.emitInt8(0u);
1196}
1197
1198void AMDGPUTargetELFStreamer::emitAMDGPUInfo(
1199 const AMDGPU::InfoSectionData &Data) {
1200 MCELFStreamer &S = getStreamer();
1201 MCContext &Context = S.getContext();
1202
1203 StringTableBuilder StrTab(StringTableBuilder::ELF);
1204 auto getOrAddString = [&](StringRef Str) -> uint32_t {
1205 if (Str.empty())
1206 return UINT32_MAX;
1207 return StrTab.add(Str);
1208 };
1209
1210 auto EmitU32Entry = [&](AMDGPU::InfoKind Kind, uint32_t Val) {
1211 S.emitInt8(static_cast<uint8_t>(Kind));
1212 S.emitInt8(4);
1213 S.emitInt32(Val);
1214 };
1215 auto EmitSymEntry = [&](AMDGPU::InfoKind Kind, MCSymbol *Sym) {
1216 S.emitInt8(static_cast<uint8_t>(Kind));
1217 S.emitInt8(8);
1218 S.emitValue(MCSymbolRefExpr::create(Sym, Context), 8);
1219 };
1220
1221 S.pushSection();
1222 MCSectionELF *InfoSec = Context.getELFSection(
1223 ".amdgpu.info", ELF::SHT_PROGBITS, ELF::SHF_EXCLUDE);
1224 S.switchSection(InfoSec);
1225
1226 forEachInfoScope(Data, [&](MCSymbol *Sym, const AMDGPU::FuncInfo *Info,
1227 ArrayRef<MCSymbol *> Uses,
1228 ArrayRef<MCSymbol *> Calls,
1229 ArrayRef<StringRef> IndirectCallTypeIds,
1230 ArrayRef<StringRef> TypeIds) {
1231 EmitSymEntry(AMDGPU::InfoKind::INFO_FUNC, Sym);
1232
1233 if (Info) {
1234 AMDGPU::FuncInfoFlags Flags{};
1235 if (Info->UsesVCC)
1236 Flags |= AMDGPU::FuncInfoFlags::FUNC_USES_VCC;
1237 if (Info->UsesFlatScratch)
1238 Flags |= AMDGPU::FuncInfoFlags::FUNC_USES_FLAT_SCRATCH;
1239 if (Info->HasDynStack)
1240 Flags |= AMDGPU::FuncInfoFlags::FUNC_HAS_DYN_STACK;
1241 EmitU32Entry(AMDGPU::InfoKind::INFO_FLAGS, llvm::to_underlying(Flags));
1242 EmitU32Entry(AMDGPU::InfoKind::INFO_NUM_SGPR, Info->NumSGPR);
1243 EmitU32Entry(AMDGPU::InfoKind::INFO_NUM_VGPR, Info->NumArchVGPR);
1244 // INFO_NUM_AGPR is only emitted when the function actually uses AGPRs,
1245 // since AGPRs are not available on all architectures.
1246 if (Info->NumAccVGPR)
1247 EmitU32Entry(AMDGPU::InfoKind::INFO_NUM_AGPR, Info->NumAccVGPR);
1248 EmitU32Entry(AMDGPU::InfoKind::INFO_PRIVATE_SEGMENT_SIZE,
1249 Info->PrivateSegmentSize);
1250 }
1251
1252 for (MCSymbol *Res : Uses)
1253 EmitSymEntry(AMDGPU::InfoKind::INFO_USE, Res);
1254 for (MCSymbol *Dst : Calls)
1255 EmitSymEntry(AMDGPU::InfoKind::INFO_CALL, Dst);
1256 for (StringRef TypeId : IndirectCallTypeIds) {
1257 EmitU32Entry(AMDGPU::InfoKind::INFO_INDIRECT_CALL,
1258 getOrAddString(TypeId));
1259 }
1260 for (StringRef TypeId : TypeIds)
1261 EmitU32Entry(AMDGPU::InfoKind::INFO_TYPEID, getOrAddString(TypeId));
1262 });
1263
1264 if (!StrTab.empty()) {
1265 StrTab.finalizeInOrder();
1266 MCSectionELF *Sec = Context.getELFSection(".amdgpu.strtab", ELF::SHT_STRTAB,
1267 ELF::SHF_EXCLUDE);
1268 S.switchSection(Sec);
1269 SmallString<128> Buf;
1270 raw_svector_ostream OS(Buf);
1271 StrTab.write(OS);
1272 S.emitBytes(Buf);
1273 }
1274
1275 S.popSection();
1276}
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
AMDGPUMCKernelDescriptor.h
AMDHSA kernel descriptor MCExpr struct for use in MC layer.
AMDGPUMCTargetDesc.h
Provides AMDGPU specific target descriptions.
AMDGPUMetadataVerifier.h
This is a verifier for AMDGPU HSA metadata, which can verify both well-typed metadata and untyped met...
AMDGPUMetadata.h
AMDGPU metadata definitions and in-memory representations.
AMDGPUObjLinkingInfo.h
Enums shared between the AMDGPU backend (LLVM) and the ELF linker (LLD) for the .amdgpu....
AMDGPUPTNote.h
Enums and constants for AMDGPU PT_NOTE sections.
ForceGenericVersion
static cl::opt< unsigned > ForceGenericVersion("amdgpu-force-generic-version", cl::desc("Force a specific generic_v<N> flag to be " "added. For testing purposes only."), cl::ReallyHidden, cl::init(0))
PRINT_RES_INFO
#define PRINT_RES_INFO(ARG)
AMDHSAKernelDescriptor.h
AMDHSA kernel descriptor definitions.
AMDKernelCodeTUtils.h
MC layer struct for AMDGPUMCKernelCodeT, provides MCExpr functionality where required.
I
#define I(x, y, z)
Definition MD5.cpp:57
Uses
Remove Loads Into Fake Uses
Definition RemoveLoadsIntoFakeUses.cpp:78
Verifier
verify safepoint Safepoint IR Verifier
Definition SafepointIRVerifier.cpp:246
CacheLineSize
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
llvm::AMDGPUPALMetadata::getVendor
const char * getVendor() const
Definition AMDGPUPALMetadata.cpp:1014
llvm::AMDGPUPALMetadata::toBlob
void toBlob(unsigned Type, std::string &S)
Definition AMDGPUPALMetadata.cpp:864
llvm::AMDGPUPALMetadata::toString
void toString(std::string &S)
Definition AMDGPUPALMetadata.cpp:811
llvm::AMDGPUTargetAsmStreamer::emitAMDGPUInfo
void emitAMDGPUInfo(const AMDGPU::InfoSectionData &Data) override
Definition AMDGPUTargetStreamer.cpp:753
llvm::AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer
AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
Definition AMDGPUTargetStreamer.cpp:257
llvm::AMDGPUTargetAsmStreamer::EmitHSAMetadata
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
Definition AMDGPUTargetStreamer.cpp:360
llvm::AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
Definition AMDGPUTargetStreamer.cpp:295
llvm::AMDGPUTargetAsmStreamer::EmitDirectiveAMDHSACodeObjectVersion
void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV) override
Definition AMDGPUTargetStreamer.cpp:278
llvm::AMDGPUTargetAsmStreamer::EmitMCResourceMaximums
void EmitMCResourceMaximums(const MCSymbol *MaxVGPR, const MCSymbol *MaxAGPR, const MCSymbol *MaxSGPR, const MCSymbol *MaxNamedBarrier) override
Definition AMDGPUTargetStreamer.cpp:338
llvm::AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT
void EmitAMDKernelCodeT(AMDGPU::AMDGPUMCKernelCodeT &Header) override
Definition AMDGPUTargetStreamer.cpp:284
llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const AMDGPU::MCKernelDescriptor &KernelDescriptor, const MCExpr *NextVGPR, const MCExpr *NextSGPR, const MCExpr *ReserveVCC, const MCExpr *ReserveFlatScr) override
Definition AMDGPUTargetStreamer.cpp:398
llvm::AMDGPUTargetAsmStreamer::EmitMCResourceInfo
void EmitMCResourceInfo(const MCSymbol *NumVGPR, const MCSymbol *NumAGPR, const MCSymbol *NumExplicitSGPR, const MCSymbol *NumNamedBarrier, const MCSymbol *PrivateSegmentSize, const MCSymbol *UsesVCC, const MCSymbol *UsesFlatScratch, const MCSymbol *HasDynamicallySizedStack, const MCSymbol *HasRecursion, const MCSymbol *HasIndirectCall) override
Definition AMDGPUTargetStreamer.cpp:312
llvm::AMDGPUTargetAsmStreamer::EmitCodeEnd
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
Definition AMDGPUTargetStreamer.cpp:376
llvm::AMDGPUTargetAsmStreamer::emitAMDGPULDS
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
Definition AMDGPUTargetStreamer.cpp:306
llvm::AMDGPUTargetELFStreamer::EmitCodeEnd
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
Definition AMDGPUTargetStreamer.cpp:1104
llvm::AMDGPUTargetELFStreamer::EmitAMDKernelCodeT
void EmitAMDKernelCodeT(AMDGPU::AMDGPUMCKernelCodeT &Header) override
Definition AMDGPUTargetStreamer.cpp:1022
llvm::AMDGPUTargetELFStreamer::EmitHSAMetadata
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
Definition AMDGPUTargetStreamer.cpp:1077
llvm::AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer
AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition AMDGPUTargetStreamer.cpp:793
llvm::AMDGPUTargetELFStreamer::emitAMDGPULDS
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
Definition AMDGPUTargetStreamer.cpp:1036
llvm::AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const AMDGPU::MCKernelDescriptor &KernelDescriptor, const MCExpr *NextVGPR, const MCExpr *NextSGPR, const MCExpr *ReserveVCC, const MCExpr *ReserveFlatScr) override
Definition AMDGPUTargetStreamer.cpp:1130
llvm::AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
Definition AMDGPUTargetStreamer.cpp:1029
llvm::AMDGPUTargetELFStreamer::emitAMDGPUInfo
void emitAMDGPUInfo(const AMDGPU::InfoSectionData &Data) override
Definition AMDGPUTargetStreamer.cpp:1198
llvm::AMDGPUTargetStreamer::EmitHSAMetadata
virtual bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict)
Emit HSA Metadata.
Definition AMDGPUTargetStreamer.h:112
llvm::AMDGPUTargetStreamer::getPALMetadata
AMDGPUPALMetadata * getPALMetadata()
Definition AMDGPUTargetStreamer.h:72
llvm::AMDGPUTargetStreamer::initializeTargetID
void initializeTargetID(const MCSubtargetInfo &STI, bool ApplyFeatureString=false)
Definition AMDGPUTargetStreamer.cpp:49
llvm::AMDGPUTargetStreamer::EmitDirectiveAMDHSACodeObjectVersion
virtual void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV)
Definition AMDGPUTargetStreamer.h:76
llvm::AMDGPUTargetStreamer::EmitHSAMetadataV3
virtual bool EmitHSAMetadataV3(StringRef HSAMetadataString)
Definition AMDGPUTargetStreamer.cpp:58
llvm::AMDGPUTargetStreamer::getElfMach
static unsigned getElfMach(StringRef GPU)
Definition AMDGPUTargetStreamer.cpp:159
llvm::AMDGPUTargetStreamer::getTargetID
const std::optional< AMDGPU::TargetID > & getTargetID() const
Definition AMDGPUTargetStreamer.h:136
llvm::AMDGPUTargetStreamer::TargetID
std::optional< AMDGPU::TargetID > TargetID
Definition AMDGPUTargetStreamer.h:60
llvm::AMDGPUTargetStreamer::getArchNameFromElfMach
static StringRef getArchNameFromElfMach(unsigned ElfMach)
Definition AMDGPUTargetStreamer.cpp:65
llvm::ArrayRef
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
llvm::DenseMapBase::find
iterator find(const_arg_type_t< KeyT > Val)
Definition DenseMap.h:223
llvm::DenseMapBase::end
iterator end()
Definition DenseMap.h:141
llvm::DenseSet
Implements a dense probed hash-table based set.
Definition DenseSet.h:281
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition MCAsmInfo.h:67
llvm::MCBinaryExpr::createAdd
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition MCExpr.h:342
llvm::MCBinaryExpr::createMul
static const MCBinaryExpr * createMul(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition MCExpr.h:397
llvm::MCBinaryExpr::createSub
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition MCExpr.h:427
llvm::MCConstantExpr::create
static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition MCExpr.cpp:212
llvm::MCContext
Context object for machine code objects.
Definition MCContext.h:83
llvm::MCContext::getOrCreateSymbol
LLVM_ABI MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition MCContext.cpp:208
llvm::MCContext::getAsmInfo
const MCAsmInfo & getAsmInfo() const
Definition MCContext.h:409
llvm::MCELFStreamer::getWriter
ELFObjectWriter & getWriter()
Definition MCELFStreamer.cpp:49
llvm::MCELFStreamer::emitLabel
void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc()) override
Emit a label for Symbol into the current section.
Definition MCELFStreamer.cpp:62
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition MCExpr.h:34
llvm::MCObjectStreamer::emitBytes
void emitBytes(StringRef Data) override
Emit the bytes in Data into the output.
Definition MCObjectStreamer.cpp:681
llvm::MCSectionELF
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition MCSectionELF.h:27
llvm::MCStreamer
Streaming machine code generation interface.
Definition MCStreamer.h:222
llvm::MCStreamer::popSection
virtual bool popSection()
Restore the current and previous section from the section stack.
Definition MCStreamer.cpp:1571
llvm::MCStreamer::getContext
MCContext & getContext() const
Definition MCStreamer.h:326
llvm::MCStreamer::emitValue
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition MCStreamer.cpp:176
llvm::MCStreamer::emitValueToAlignment
virtual void emitValueToAlignment(Align Alignment, int64_t Fill=0, uint8_t FillLen=1, unsigned MaxBytesToEmit=0)
Emit some number of copies of Value until the byte alignment ByteAlignment is reached.
Definition MCStreamer.cpp:1548
llvm::MCStreamer::pushSection
void pushSection()
Save the current and previous section on the section stack.
Definition MCStreamer.h:460
llvm::MCStreamer::switchSection
virtual void switchSection(MCSection *Section, uint32_t Subsec=0)
Set the current section where code is being emitted to Section.
Definition MCStreamer.cpp:1586
llvm::MCStreamer::emitInt32
void emitInt32(uint64_t Value)
Definition MCStreamer.h:769
llvm::MCStreamer::emitInt8
void emitInt8(uint64_t Value)
Definition MCStreamer.h:767
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:141
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition MCSubtargetInfo.h:188
llvm::MCSubtargetInfo::getFeatureString
StringRef getFeatureString() const
Definition MCSubtargetInfo.h:186
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition MCSubtargetInfo.h:177
llvm::MCSubtargetInfo::getCPU
StringRef getCPU() const
Definition MCSubtargetInfo.h:178
llvm::MCSymbolELF::setBinding
LLVM_ABI void setBinding(unsigned Binding) const
Definition MCSymbolELF.cpp:43
llvm::MCSymbolELF::setType
LLVM_ABI void setType(unsigned Type) const
Definition MCSymbolELF.cpp:92
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition MCExpr.h:213
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition MCSymbol.h:42
llvm::MCSymbol::getName
StringRef getName() const
getName - Get the symbol name.
Definition MCSymbol.h:188
llvm::SmallString
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition SmallString.h:26
llvm::StringRef
Represent a constant reference to a string, i.e.
Definition StringRef.h:56
llvm::StringTableBuilder
Utility for building string tables with deduplicated suffixes.
Definition StringTableBuilder.h:25
llvm::StringTableBuilder::finalizeInOrder
LLVM_ABI void finalizeInOrder()
Finalize the string table without reording it.
Definition StringTableBuilder.cpp:134
llvm::StringTableBuilder::add
LLVM_ABI size_t add(CachedHashStringRef S, uint8_t Priority=0)
Add a string to the builder.
Definition StringTableBuilder.cpp:220
llvm::StringTableBuilder::write
LLVM_ABI void write(raw_ostream &OS) const
Definition StringTableBuilder.cpp:61
llvm::Triple::getArch
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition Triple.h:513
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition Twine.h:82
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:46
llvm::Value
LLVM Value Representation.
Definition Value.h:75
llvm::formatted_raw_ostream
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Definition FormattedStream.h:31
llvm::function_ref
An efficient, type-erasing, non-owning reference to a callable.
Definition STLFunctionalExtras.h:37
llvm::msgpack::Document
Simple in-memory representation of a document of msgpack objects with ability to find and create arra...
Definition MsgPackDocument.h:293
llvm::msgpack::Document::getRoot
DocNode & getRoot()
Get ref to the document's root element.
Definition MsgPackDocument.h:317
llvm::msgpack::Document::toYAML
LLVM_ABI void toYAML(raw_ostream &OS)
Convert MsgPack Document to YAML text.
Definition MsgPackDocumentYAML.cpp:247
llvm::msgpack::Document::writeToBlob
LLVM_ABI void writeToBlob(std::string &Blob)
Write a MsgPack document to a binary MsgPack blob.
Definition MsgPackDocument.cpp:355
llvm::msgpack::Document::fromYAML
LLVM_ABI bool fromYAML(StringRef S)
Read YAML text into the MsgPack document. Returns false on failure.
Definition MsgPackDocumentYAML.cpp:253
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition raw_ostream.h:664
llvm::raw_string_ostream::str
std::string & str()
Returns the string's reference.
Definition raw_ostream.h:682
llvm::raw_svector_ostream
A raw_ostream that writes to an SmallVector or SmallString.
Definition raw_ostream.h:694
llvm::raw_svector_ostream::str
StringRef str() const
Return a StringRef for the vector contents.
Definition raw_ostream.h:723
uint32_t
uint8_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::AMDGPU::ElfNote::NoteNameV2
const char NoteNameV2[]
Definition AMDGPUPTNote.h:26
llvm::AMDGPU::ElfNote::SectionName
const char SectionName[]
Definition AMDGPUPTNote.h:24
llvm::AMDGPU::ElfNote::NoteNameV3
const char NoteNameV3[]
Definition AMDGPUPTNote.h:27
llvm::AMDGPU::GenericVersion::GFX12_5
static constexpr unsigned GFX12_5
Definition AMDGPUBaseInfo.h:66
llvm::AMDGPU::GenericVersion::GFX9_4
static constexpr unsigned GFX9_4
Definition AMDGPUBaseInfo.h:60
llvm::AMDGPU::GenericVersion::GFX10_1
static constexpr unsigned GFX10_1
Definition AMDGPUBaseInfo.h:61
llvm::AMDGPU::GenericVersion::GFX10_3
static constexpr unsigned GFX10_3
Definition AMDGPUBaseInfo.h:62
llvm::AMDGPU::GenericVersion::GFX11
static constexpr unsigned GFX11
Definition AMDGPUBaseInfo.h:63
llvm::AMDGPU::GenericVersion::GFX9
static constexpr unsigned GFX9
Definition AMDGPUBaseInfo.h:59
llvm::AMDGPU::GenericVersion::GFX12
static constexpr unsigned GFX12
Definition AMDGPUBaseInfo.h:65
llvm::AMDGPU::GenericVersion::GFX13
static constexpr unsigned GFX13
Definition AMDGPUBaseInfo.h:67
llvm::AMDGPU::GenericVersion::GFX11_7
static constexpr unsigned GFX11_7
Definition AMDGPUBaseInfo.h:64
llvm::AMDGPU::HSAMD::V3::AssemblerDirectiveBegin
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
Definition AMDGPUMetadata.h:466
llvm::AMDGPU::HSAMD::V3::AssemblerDirectiveEnd
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
Definition AMDGPUMetadata.h:468
llvm::AMDGPU::getArchNameR600
LLVM_ABI StringRef getArchNameR600(GPUKind AK)
Definition AMDGPUTargetParser.cpp:300
llvm::AMDGPU::FuncInfoFlags
FuncInfoFlags
Per-function flags packed into INFO_FLAGS entries.
Definition AMDGPUObjLinkingInfo.h:64
llvm::AMDGPU::printAMDGPUMCExpr
void printAMDGPUMCExpr(const MCExpr *Expr, raw_ostream &OS, const MCAsmInfo *MAI)
Definition AMDGPUMCExpr.cpp:750
llvm::AMDGPU::isHsaAbi
bool isHsaAbi(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:209
llvm::AMDGPU::createAMDGPUTargetID
TargetID createAMDGPUTargetID(const MCSubtargetInfo &STI, StringRef FeatureString)
Construct TargetID from MCSubtargetInfo.
Definition AMDGPUBaseInfo.cpp:1087
llvm::AMDGPU::getIsaVersion
LLVM_ABI IsaVersion getIsaVersion(StringRef GPU)
Definition AMDGPUTargetParser.cpp:368
llvm::AMDGPU::GPUKind
GPUKind
GPU kinds supported by the AMDGPU target.
Definition AMDGPUTargetParser.h:35
llvm::AMDGPU::isGFX90A
bool isGFX90A(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2647
llvm::AMDGPU::parseArchAMDGCN
LLVM_ABI GPUKind parseArchAMDGCN(StringRef CPU)
Definition AMDGPUTargetParser.cpp:305
llvm::AMDGPU::hasArchitectedFlatScratch
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2655
llvm::AMDGPU::isGFX11Plus
bool isGFX11Plus(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2583
llvm::AMDGPU::foldAMDGPUMCExpr
const MCExpr * foldAMDGPUMCExpr(const MCExpr *Expr, MCContext &Ctx)
Definition AMDGPUMCExpr.cpp:741
llvm::AMDGPU::InfoKind
InfoKind
Entry kind values for the .amdgpu.info section.
Definition AMDGPUObjLinkingInfo.h:32
llvm::AMDGPU::InfoKind::INFO_INDIRECT_CALL
@ INFO_INDIRECT_CALL
Indirect call edge: the function contains an indirect call whose callee is expected to match the type...
Definition AMDGPUObjLinkingInfo.h:56
llvm::AMDGPU::InfoKind::INFO_FLAGS
@ INFO_FLAGS
Bitfield of FuncInfoFlags properties for the function. [u32].
Definition AMDGPUObjLinkingInfo.h:38
llvm::AMDGPU::InfoKind::INFO_FUNC
@ INFO_FUNC
Opens a new function scope.
Definition AMDGPUObjLinkingInfo.h:36
llvm::AMDGPU::InfoKind::INFO_NUM_SGPR
@ INFO_NUM_SGPR
Number of SGPRs explicitly used by the function. [u32].
Definition AMDGPUObjLinkingInfo.h:40
llvm::AMDGPU::InfoKind::INFO_NUM_VGPR
@ INFO_NUM_VGPR
Number of architectural VGPRs used by the function. [u32].
Definition AMDGPUObjLinkingInfo.h:42
llvm::AMDGPU::InfoKind::INFO_CALL
@ INFO_CALL
Direct call edge: the function calls the callee identified by the 8-byte relocated symbol.
Definition AMDGPUObjLinkingInfo.h:52
llvm::AMDGPU::InfoKind::INFO_NUM_AGPR
@ INFO_NUM_AGPR
Number of accumulator VGPRs (AGPRs) used by the function. [u32].
Definition AMDGPUObjLinkingInfo.h:44
llvm::AMDGPU::InfoKind::INFO_TYPEID
@ INFO_TYPEID
Function type ID: tags an address-taken function with a type-ID string (at the given ....
Definition AMDGPUObjLinkingInfo.h:60
llvm::AMDGPU::InfoKind::INFO_PRIVATE_SEGMENT_SIZE
@ INFO_PRIVATE_SEGMENT_SIZE
Private (scratch) memory size in bytes required by the function. [u32].
Definition AMDGPUObjLinkingInfo.h:46
llvm::AMDGPU::InfoKind::INFO_USE
@ INFO_USE
Dependency edge: the function uses the resource identified by the 8-byte relocated symbol (e....
Definition AMDGPUObjLinkingInfo.h:49
llvm::AMDGPU::getArchNameAMDGCN
LLVM_ABI StringRef getArchNameAMDGCN(GPUKind AK)
Definition AMDGPUTargetParser.cpp:276
llvm::AMDGPU::hasKernargPreload
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2671
llvm::AMDGPU::supportsWGP
bool supportsWGP(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2615
llvm::AMDGPU::isGFX1250Plus
bool isGFX1250Plus(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2605
llvm::AMDGPU::getELFABIVersion
uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion)
Definition AMDGPUBaseInfo.cpp:239
llvm::AMDGPU::parseArchR600
LLVM_ABI GPUKind parseArchR600(StringRef CPU)
Definition AMDGPUTargetParser.cpp:310
llvm::ELF::NT_AMDGPU_METADATA
@ NT_AMDGPU_METADATA
Definition ELF.h:1998
llvm::ELF::SHN_AMDGPU_LDS
@ SHN_AMDGPU_LDS
Definition ELF.h:1981
llvm::ELF::SHF_EXCLUDE
@ SHF_EXCLUDE
Definition ELF.h:1293
llvm::ELF::SHF_ALLOC
@ SHF_ALLOC
Definition ELF.h:1259
llvm::ELF::SHT_STRTAB
@ SHT_STRTAB
Definition ELF.h:1159
llvm::ELF::SHT_PROGBITS
@ SHT_PROGBITS
Definition ELF.h:1157
llvm::ELF::SHT_NOTE
@ SHT_NOTE
Definition ELF.h:1163
llvm::ELF::STB_GLOBAL
@ STB_GLOBAL
Definition ELF.h:1416
llvm::ELF::STT_AMDGPU_HSA_KERNEL
@ STT_AMDGPU_HSA_KERNEL
Definition ELF.h:1441
llvm::ELF::STT_OBJECT
@ STT_OBJECT
Definition ELF.h:1428
llvm::ELF::EF_AMDGPU_GENERIC_VERSION_MAX
@ EF_AMDGPU_GENERIC_VERSION_MAX
Definition ELF.h:933
llvm::ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4
@ EF_AMDGPU_FEATURE_XNACK_ANY_V4
Definition ELF.h:910
llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_V3
@ EF_AMDGPU_FEATURE_SRAMECC_V3
Definition ELF.h:901
llvm::ELF::EF_AMDGPU_GENERIC_VERSION_OFFSET
@ EF_AMDGPU_GENERIC_VERSION_OFFSET
Definition ELF.h:931
llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4
@ EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4
Definition ELF.h:921
llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4
@ EF_AMDGPU_FEATURE_SRAMECC_OFF_V4
Definition ELF.h:925
llvm::ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4
@ EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4
Definition ELF.h:908
llvm::ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4
@ EF_AMDGPU_FEATURE_XNACK_OFF_V4
Definition ELF.h:912
llvm::ELF::EF_AMDGPU_FEATURE_XNACK_V3
@ EF_AMDGPU_FEATURE_XNACK_V3
Definition ELF.h:896
llvm::ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4
@ EF_AMDGPU_FEATURE_XNACK_ON_V4
Definition ELF.h:914
llvm::ELF::EF_AMDGPU_MACH_NONE
@ EF_AMDGPU_MACH_NONE
Definition ELF.h:855
llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4
@ EF_AMDGPU_FEATURE_SRAMECC_ANY_V4
Definition ELF.h:923
llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4
@ EF_AMDGPU_FEATURE_SRAMECC_ON_V4
Definition ELF.h:927
llvm::ELF::NT_AMD_HSA_ISA_NAME
@ NT_AMD_HSA_ISA_NAME
Definition ELF.h:1991
llvm::ELF::STV_PROTECTED
@ STV_PROTECTED
Definition ELF.h:1448
llvm::ELF::STV_DEFAULT
@ STV_DEFAULT
Definition ELF.h:1445
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition CommandLine.h:440
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::report_fatal_error
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
Definition Error.cpp:163
llvm::to_underlying
constexpr std::underlying_type_t< Enum > to_underlying(Enum E)
Returns underlying integer value of an enum.
Definition STLForwardCompat.h:198
llvm::AMDGPU::IsaVersion
Instruction set architecture version.
Definition AMDGPUTargetParser.h:55
llvm::AMDGPU::MCKernelDescriptor::bits_get
static const MCExpr * bits_get(const MCExpr *Src, uint32_t Shift, uint32_t Mask, MCContext &Ctx)
Definition AMDGPUMCKernelDescriptor.cpp:93
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
llvm::amdhsa::kernel_descriptor_t
Definition AMDHSAKernelDescriptor.h:267
llvm::amdhsa::kernel_descriptor_t::group_segment_fixed_size
uint32_t group_segment_fixed_size
Definition AMDHSAKernelDescriptor.h:268
llvm::amdhsa::kernel_descriptor_t::reserved3
uint8_t reserved3[4]
Definition AMDHSAKernelDescriptor.h:279
llvm::amdhsa::kernel_descriptor_t::reserved1
uint8_t reserved1[20]
Definition AMDHSAKernelDescriptor.h:273
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc1
uint32_t compute_pgm_rsrc1
Definition AMDHSAKernelDescriptor.h:275
llvm::amdhsa::kernel_descriptor_t::private_segment_fixed_size
uint32_t private_segment_fixed_size
Definition AMDHSAKernelDescriptor.h:269
llvm::amdhsa::kernel_descriptor_t::kernarg_size
uint32_t kernarg_size
Definition AMDHSAKernelDescriptor.h:270
llvm::amdhsa::kernel_descriptor_t::kernarg_preload
uint16_t kernarg_preload
Definition AMDHSAKernelDescriptor.h:278
llvm::amdhsa::kernel_descriptor_t::reserved0
uint8_t reserved0[4]
Definition AMDHSAKernelDescriptor.h:271
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc2
uint32_t compute_pgm_rsrc2
Definition AMDHSAKernelDescriptor.h:276
llvm::amdhsa::kernel_descriptor_t::kernel_code_properties
uint16_t kernel_code_properties
Definition AMDHSAKernelDescriptor.h:277
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc3
uint32_t compute_pgm_rsrc3
Definition AMDHSAKernelDescriptor.h:274
llvm::amdhsa::kernel_descriptor_t::kernel_code_entry_byte_offset
int64_t kernel_code_entry_byte_offset
Definition AMDHSAKernelDescriptor.h:272
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