LLVM 18.0.0git
AMDGPUTargetStreamer.cpp
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1//===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides AMDGPU specific target streamer methods.
10//
11//===----------------------------------------------------------------------===//
12
14#include "AMDGPUPTNote.h"
15#include "AMDKernelCodeT.h"
20#include "llvm/MC/MCAssembler.h"
21#include "llvm/MC/MCContext.h"
30
31using namespace llvm;
32using namespace llvm::AMDGPU;
33
34//===----------------------------------------------------------------------===//
35// AMDGPUTargetStreamer
36//===----------------------------------------------------------------------===//
37
38static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor,
39 uint32_t &Stepping, bool Sramecc, bool Xnack) {
40 if (Major == 9 && Minor == 0) {
41 switch (Stepping) {
42 case 0:
43 case 2:
44 case 4:
45 case 6:
46 if (Xnack)
47 Stepping++;
48 }
49 }
50}
51
53 HSAMD::Metadata HSAMetadata;
54 if (HSAMD::fromString(HSAMetadataString, HSAMetadata))
55 return false;
56 return EmitHSAMetadata(HSAMetadata);
57}
58
60 msgpack::Document HSAMetadataDoc;
61 if (!HSAMetadataDoc.fromYAML(HSAMetadataString))
62 return false;
63 return EmitHSAMetadata(HSAMetadataDoc, false);
64}
65
68
69 // clang-format off
70 switch (ElfMach) {
71 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break;
72 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break;
82 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break;
131 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break;
132 default: AK = GK_NONE; break;
133 }
134 // clang-format on
135
136 StringRef GPUName = getArchNameAMDGCN(AK);
137 if (GPUName != "")
138 return GPUName;
139 return getArchNameR600(AK);
140}
141
144 if (AK == AMDGPU::GPUKind::GK_NONE)
145 AK = parseArchR600(GPU);
146
147 // clang-format off
148 switch (AK) {
210 }
211 // clang-format on
212
213 llvm_unreachable("unknown GPU");
214}
215
216//===----------------------------------------------------------------------===//
217// AMDGPUTargetAsmStreamer
218//===----------------------------------------------------------------------===//
219
222 : AMDGPUTargetStreamer(S), OS(OS) { }
223
224// A hook for emitting stuff at the end.
225// We use it for emitting the accumulated PAL metadata as directives.
226// The PAL metadata is reset after it is emitted.
228 std::string S;
230 OS << S;
231
232 // Reset the pal metadata so its data will not affect a compilation that
233 // reuses this object.
235}
236
238 OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n";
239}
240
242 uint32_t Major, uint32_t Minor) {
243 OS << "\t.hsa_code_object_version " <<
244 Twine(Major) << "," << Twine(Minor) << '\n';
245}
246
247void
249 uint32_t Minor,
250 uint32_t Stepping,
251 StringRef VendorName,
252 StringRef ArchName) {
253 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny());
254 OS << "\t.hsa_code_object_isa " << Twine(Major) << "," << Twine(Minor) << ","
255 << Twine(Stepping) << ",\"" << VendorName << "\",\"" << ArchName << "\"\n";
256}
257
258void
260 OS << "\t.amd_kernel_code_t\n";
261 dumpAmdKernelCode(&Header, OS, "\t\t");
262 OS << "\t.end_amd_kernel_code_t\n";
263}
264
266 unsigned Type) {
267 switch (Type) {
268 default: llvm_unreachable("Invalid AMDGPU symbol type");
270 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ;
271 break;
272 }
273}
274
276 Align Alignment) {
277 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", "
278 << Alignment.value() << '\n';
279}
280
282 OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n";
283 return true;
284}
285
287 const AMDGPU::HSAMD::Metadata &HSAMetadata) {
288 std::string HSAMetadataString;
289 if (HSAMD::toString(HSAMetadata, HSAMetadataString))
290 return false;
291
292 OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n';
293 OS << HSAMetadataString << '\n';
294 OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n';
295 return true;
296}
297
299 msgpack::Document &HSAMetadataDoc, bool Strict) {
301 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
302 return false;
303
304 std::string HSAMetadataString;
305 raw_string_ostream StrOS(HSAMetadataString);
306 HSAMetadataDoc.toYAML(StrOS);
307
308 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n';
309 OS << StrOS.str() << '\n';
310 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n';
311 return true;
312}
313
315 const uint32_t Encoded_s_code_end = 0xbf9f0000;
316 const uint32_t Encoded_s_nop = 0xbf800000;
317 uint32_t Encoded_pad = Encoded_s_code_end;
318
319 // Instruction cache line size in bytes.
320 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
321 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
322
323 // Extra padding amount in bytes to support prefetch mode 3.
324 unsigned FillSize = 3 * CacheLineSize;
325
326 if (AMDGPU::isGFX90A(STI)) {
327 Encoded_pad = Encoded_s_nop;
328 FillSize = 16 * CacheLineSize;
329 }
330
331 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n';
332 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n';
333 return true;
334}
335
337 const MCSubtargetInfo &STI, StringRef KernelName,
338 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR,
339 bool ReserveVCC, bool ReserveFlatScr, unsigned CodeObjectVersion) {
340 IsaVersion IVersion = getIsaVersion(STI.getCPU());
341
342 OS << "\t.amdhsa_kernel " << KernelName << '\n';
343
344#define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \
345 STREAM << "\t\t" << DIRECTIVE << " " \
346 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
347
348 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size
349 << '\n';
350 OS << "\t\t.amdhsa_private_segment_fixed_size "
351 << KD.private_segment_fixed_size << '\n';
352 OS << "\t\t.amdhsa_kernarg_size " << KD.kernarg_size << '\n';
353
354 PRINT_FIELD(OS, ".amdhsa_user_sgpr_count", KD,
355 compute_pgm_rsrc2,
356 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT);
357
360 OS, ".amdhsa_user_sgpr_private_segment_buffer", KD,
361 kernel_code_properties,
362 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
363 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD,
364 kernel_code_properties,
365 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
366 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD,
367 kernel_code_properties,
368 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
369 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD,
370 kernel_code_properties,
371 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
372 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD,
373 kernel_code_properties,
374 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
376 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD,
377 kernel_code_properties,
378 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
379 if (hasKernargPreload(STI)) {
380 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_preload_length ", KD,
381 kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_LENGTH);
382 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_preload_offset ", KD,
383 kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_OFFSET);
384 }
385 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD,
386 kernel_code_properties,
387 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
388 if (IVersion.Major >= 10)
389 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD,
390 kernel_code_properties,
391 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
392 if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5)
393 PRINT_FIELD(OS, ".amdhsa_uses_dynamic_stack", KD, kernel_code_properties,
394 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK);
395 PRINT_FIELD(OS,
397 ? ".amdhsa_enable_private_segment"
398 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"),
399 KD, compute_pgm_rsrc2,
400 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
401 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD,
402 compute_pgm_rsrc2,
403 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
404 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD,
405 compute_pgm_rsrc2,
406 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
407 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD,
408 compute_pgm_rsrc2,
409 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
410 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD,
411 compute_pgm_rsrc2,
412 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
413 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD,
414 compute_pgm_rsrc2,
415 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
416
417 // These directives are required.
418 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n';
419 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n';
420
421 if (AMDGPU::isGFX90A(STI))
422 OS << "\t\t.amdhsa_accum_offset " <<
424 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4
425 << '\n';
426
427 if (!ReserveVCC)
428 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n';
429 if (IVersion.Major >= 7 && !ReserveFlatScr && !hasArchitectedFlatScratch(STI))
430 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n';
431
432 switch (CodeObjectVersion) {
433 default:
434 break;
437 if (getTargetID()->isXnackSupported())
438 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n';
439 break;
440 }
441
442 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD,
443 compute_pgm_rsrc1,
444 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
445 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD,
446 compute_pgm_rsrc1,
447 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
448 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD,
449 compute_pgm_rsrc1,
450 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
451 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD,
452 compute_pgm_rsrc1,
453 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
454 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD,
455 compute_pgm_rsrc1,
456 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
457 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD,
458 compute_pgm_rsrc1,
459 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
460 if (IVersion.Major >= 9)
461 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD,
462 compute_pgm_rsrc1,
463 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL);
464 if (AMDGPU::isGFX90A(STI))
465 PRINT_FIELD(OS, ".amdhsa_tg_split", KD,
466 compute_pgm_rsrc3,
467 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT);
468 if (IVersion.Major >= 10) {
469 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD,
470 compute_pgm_rsrc1,
471 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE);
472 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD,
473 compute_pgm_rsrc1,
474 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED);
475 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD,
476 compute_pgm_rsrc1,
477 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS);
478 PRINT_FIELD(OS, ".amdhsa_shared_vgpr_count", KD, compute_pgm_rsrc3,
479 amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT);
480 }
482 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD,
483 compute_pgm_rsrc2,
484 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
485 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD,
486 compute_pgm_rsrc2,
487 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
489 OS, ".amdhsa_exception_fp_ieee_div_zero", KD,
490 compute_pgm_rsrc2,
491 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
492 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD,
493 compute_pgm_rsrc2,
494 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
495 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD,
496 compute_pgm_rsrc2,
497 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
498 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD,
499 compute_pgm_rsrc2,
500 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
501 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD,
502 compute_pgm_rsrc2,
503 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
504#undef PRINT_FIELD
505
506 OS << "\t.end_amdhsa_kernel\n";
507}
508
509//===----------------------------------------------------------------------===//
510// AMDGPUTargetELFStreamer
511//===----------------------------------------------------------------------===//
512
514 const MCSubtargetInfo &STI)
515 : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {}
516
518 return static_cast<MCELFStreamer &>(Streamer);
519}
520
521// A hook for emitting stuff at the end.
522// We use it for emitting the accumulated PAL metadata as a .note record.
523// The PAL metadata is reset after it is emitted.
526 MCA.setELFHeaderEFlags(getEFlags());
527
528 std::string Blob;
529 const char *Vendor = getPALMetadata()->getVendor();
530 unsigned Type = getPALMetadata()->getType();
531 getPALMetadata()->toBlob(Type, Blob);
532 if (Blob.empty())
533 return;
534 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type,
535 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); });
536
537 // Reset the pal metadata so its data will not affect a compilation that
538 // reuses this object.
540}
541
542void AMDGPUTargetELFStreamer::EmitNote(
543 StringRef Name, const MCExpr *DescSZ, unsigned NoteType,
544 function_ref<void(MCELFStreamer &)> EmitDesc) {
545 auto &S = getStreamer();
546 auto &Context = S.getContext();
547
548 auto NameSZ = Name.size() + 1;
549
550 unsigned NoteFlags = 0;
551 // TODO Apparently, this is currently needed for OpenCL as mentioned in
552 // https://reviews.llvm.org/D74995
553 if (isHsaAbi(STI))
554 NoteFlags = ELF::SHF_ALLOC;
555
556 S.pushSection();
557 S.switchSection(
558 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags));
559 S.emitInt32(NameSZ); // namesz
560 S.emitValue(DescSZ, 4); // descz
561 S.emitInt32(NoteType); // type
562 S.emitBytes(Name); // name
563 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
564 EmitDesc(S); // desc
565 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
566 S.popSection();
567}
568
569unsigned AMDGPUTargetELFStreamer::getEFlags() {
570 switch (STI.getTargetTriple().getArch()) {
571 default:
572 llvm_unreachable("Unsupported Arch");
573 case Triple::r600:
574 return getEFlagsR600();
575 case Triple::amdgcn:
576 return getEFlagsAMDGCN();
577 }
578}
579
580unsigned AMDGPUTargetELFStreamer::getEFlagsR600() {
582
583 return getElfMach(STI.getCPU());
584}
585
586unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() {
588
589 switch (STI.getTargetTriple().getOS()) {
590 default:
591 // TODO: Why are some tests have "mingw" listed as OS?
592 // llvm_unreachable("Unsupported OS");
594 return getEFlagsUnknownOS();
595 case Triple::AMDHSA:
596 return getEFlagsAMDHSA();
597 case Triple::AMDPAL:
598 return getEFlagsAMDPAL();
599 case Triple::Mesa3D:
600 return getEFlagsMesa3D();
601 }
602}
603
604unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() {
605 // TODO: Why are some tests have "mingw" listed as OS?
606 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS);
607
608 return getEFlagsV3();
609}
610
611unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() {
612 assert(isHsaAbi(STI));
613
614 if (std::optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) {
615 switch (*HsaAbiVer) {
617 return getEFlagsV3();
620 return getEFlagsV4();
621 }
622 }
623
624 llvm_unreachable("HSA OS ABI Version identification must be defined");
625}
626
627unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() {
629
630 return getEFlagsV3();
631}
632
633unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() {
635
636 return getEFlagsV3();
637}
638
639unsigned AMDGPUTargetELFStreamer::getEFlagsV3() {
640 unsigned EFlagsV3 = 0;
641
642 // mach.
643 EFlagsV3 |= getElfMach(STI.getCPU());
644
645 // xnack.
646 if (getTargetID()->isXnackOnOrAny())
648 // sramecc.
649 if (getTargetID()->isSramEccOnOrAny())
651
652 return EFlagsV3;
653}
654
655unsigned AMDGPUTargetELFStreamer::getEFlagsV4() {
656 unsigned EFlagsV4 = 0;
657
658 // mach.
659 EFlagsV4 |= getElfMach(STI.getCPU());
660
661 // xnack.
662 switch (getTargetID()->getXnackSetting()) {
665 break;
668 break;
671 break;
674 break;
675 }
676 // sramecc.
677 switch (getTargetID()->getSramEccSetting()) {
680 break;
683 break;
686 break;
689 break;
690 }
691
692 return EFlagsV4;
693}
694
696
698 uint32_t Major, uint32_t Minor) {
699
702 OS.emitInt32(Major);
703 OS.emitInt32(Minor);
704 });
705}
706
707void
709 uint32_t Minor,
710 uint32_t Stepping,
711 StringRef VendorName,
712 StringRef ArchName) {
713 uint16_t VendorNameSize = VendorName.size() + 1;
714 uint16_t ArchNameSize = ArchName.size() + 1;
715
716 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) +
717 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) +
718 VendorNameSize + ArchNameSize;
719
720 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny());
723 OS.emitInt16(VendorNameSize);
724 OS.emitInt16(ArchNameSize);
725 OS.emitInt32(Major);
726 OS.emitInt32(Minor);
727 OS.emitInt32(Stepping);
728 OS.emitBytes(VendorName);
729 OS.emitInt8(0); // NULL terminate VendorName
730 OS.emitBytes(ArchName);
731 OS.emitInt8(0); // NULL terminate ArchName
732 });
733}
734
735void
737
739 OS.pushSection();
740 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header)));
741 OS.popSection();
742}
743
745 unsigned Type) {
746 MCSymbolELF *Symbol = cast<MCSymbolELF>(
747 getStreamer().getContext().getOrCreateSymbol(SymbolName));
748 Symbol->setType(Type);
749}
750
752 Align Alignment) {
753 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol);
754 SymbolELF->setType(ELF::STT_OBJECT);
755
756 if (!SymbolELF->isBindingSet()) {
757 SymbolELF->setBinding(ELF::STB_GLOBAL);
758 SymbolELF->setExternal(true);
759 }
760
761 if (SymbolELF->declareCommon(Size, Alignment, true)) {
762 report_fatal_error("Symbol: " + Symbol->getName() +
763 " redeclared as different type");
764 }
765
766 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS);
768}
769
771 // Create two labels to mark the beginning and end of the desc field
772 // and a MCExpr to calculate the size of the desc field.
773 auto &Context = getContext();
774 auto *DescBegin = Context.createTempSymbol();
775 auto *DescEnd = Context.createTempSymbol();
776 auto *DescSZ = MCBinaryExpr::createSub(
779
781 [&](MCELFStreamer &OS) {
782 OS.emitLabel(DescBegin);
783 OS.emitBytes(getTargetID()->toString());
784 OS.emitLabel(DescEnd);
785 });
786 return true;
787}
788
790 bool Strict) {
792 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
793 return false;
794
795 std::string HSAMetadataString;
796 HSAMetadataDoc.writeToBlob(HSAMetadataString);
797
798 // Create two labels to mark the beginning and end of the desc field
799 // and a MCExpr to calculate the size of the desc field.
800 auto &Context = getContext();
801 auto *DescBegin = Context.createTempSymbol();
802 auto *DescEnd = Context.createTempSymbol();
803 auto *DescSZ = MCBinaryExpr::createSub(
806
808 [&](MCELFStreamer &OS) {
809 OS.emitLabel(DescBegin);
810 OS.emitBytes(HSAMetadataString);
811 OS.emitLabel(DescEnd);
812 });
813 return true;
814}
815
817 const AMDGPU::HSAMD::Metadata &HSAMetadata) {
818 std::string HSAMetadataString;
819 if (HSAMD::toString(HSAMetadata, HSAMetadataString))
820 return false;
821
822 // Create two labels to mark the beginning and end of the desc field
823 // and a MCExpr to calculate the size of the desc field.
824 auto &Context = getContext();
825 auto *DescBegin = Context.createTempSymbol();
826 auto *DescEnd = Context.createTempSymbol();
827 auto *DescSZ = MCBinaryExpr::createSub(
830
832 [&](MCELFStreamer &OS) {
833 OS.emitLabel(DescBegin);
834 OS.emitBytes(HSAMetadataString);
835 OS.emitLabel(DescEnd);
836 });
837 return true;
838}
839
841 const MCSubtargetInfo &STI) {
842 for (int i = 0; i < 64; ++i) {
843 OS << "\ts_nop 0\n";
844 }
845 return true;
846}
847
849 const MCSubtargetInfo &STI) {
850 const uint32_t Encoded_s_nop = 0xbf800000;
852 for (int i = 0; i < 64; ++i) {
853 OS.emitInt32(Encoded_s_nop);
854 }
855 return true;
856}
857
859 const uint32_t Encoded_s_code_end = 0xbf9f0000;
860 const uint32_t Encoded_s_nop = 0xbf800000;
861 uint32_t Encoded_pad = Encoded_s_code_end;
862
863 // Instruction cache line size in bytes.
864 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
865 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
866
867 // Extra padding amount in bytes to support prefetch mode 3.
868 unsigned FillSize = 3 * CacheLineSize;
869
870 if (AMDGPU::isGFX90A(STI)) {
871 Encoded_pad = Encoded_s_nop;
872 FillSize = 16 * CacheLineSize;
873 }
874
876 OS.pushSection();
877 OS.emitValueToAlignment(Align(CacheLineSize), Encoded_pad, 4);
878 for (unsigned I = 0; I < FillSize; I += 4)
879 OS.emitInt32(Encoded_pad);
880 OS.popSection();
881 return true;
882}
883
885 const MCSubtargetInfo &STI, StringRef KernelName,
886 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
887 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
888 unsigned CodeObjectVersion) {
889 auto &Streamer = getStreamer();
890 auto &Context = Streamer.getContext();
891
892 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>(
893 Context.getOrCreateSymbol(Twine(KernelName)));
894 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
895 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd")));
896
897 // Copy kernel descriptor symbol's binding, other and visibility from the
898 // kernel code symbol.
899 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding());
900 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther());
901 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility());
902 // Kernel descriptor symbol's type and size are fixed.
903 KernelDescriptorSymbol->setType(ELF::STT_OBJECT);
904 KernelDescriptorSymbol->setSize(
905 MCConstantExpr::create(sizeof(KernelDescriptor), Context));
906
907 // The visibility of the kernel code symbol must be protected or less to allow
908 // static relocations from the kernel descriptor to be used.
909 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT)
910 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED);
911
912 Streamer.emitLabel(KernelDescriptorSymbol);
913 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size);
914 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size);
915 Streamer.emitInt32(KernelDescriptor.kernarg_size);
916
917 for (uint8_t Res : KernelDescriptor.reserved0)
918 Streamer.emitInt8(Res);
919
920 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The
921 // expression being created is:
922 // (start of kernel code) - (start of kernel descriptor)
923 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
926 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context),
928 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context),
929 Context),
930 sizeof(KernelDescriptor.kernel_code_entry_byte_offset));
931 for (uint8_t Res : KernelDescriptor.reserved1)
932 Streamer.emitInt8(Res);
933 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3);
934 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1);
935 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2);
936 Streamer.emitInt16(KernelDescriptor.kernel_code_properties);
937 Streamer.emitInt16(KernelDescriptor.kernarg_preload);
938 for (uint8_t Res : KernelDescriptor.reserved3)
939 Streamer.emitInt8(Res);
940}
This is a verifier for AMDGPU HSA metadata, which can verify both well-typed metadata and untyped met...
AMDGPU metadata definitions and in-memory representations.
Enums and constants for AMDGPU PT_NOTE sections.
#define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME)
static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor, uint32_t &Stepping, bool Sramecc, bool Xnack)
AMDHSA kernel descriptor definitions.
#define AMDHSA_BITS_GET(SRC, MSK)
std::string Name
uint64_t Size
#define I(x, y, z)
Definition: MD5.cpp:58
LLVMContext & Context
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
verify safepoint Safepoint IR Verifier
raw_pwrite_stream & OS
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
const char * getVendor() const
void toBlob(unsigned Type, std::string &S)
void toString(std::string &S)
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, unsigned CodeObjectVersion) override
AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI) override
void EmitDirectiveHSACodeObjectISAV2(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName) override
void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor) override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor) override
AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI) override
void EmitDirectiveHSACodeObjectISAV2(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName) override
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, unsigned CodeObjectVersion) override
virtual bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict)
Emit HSA Metadata.
AMDGPUPALMetadata * getPALMetadata()
virtual bool EmitHSAMetadataV3(StringRef HSAMetadataString)
static unsigned getElfMach(StringRef GPU)
MCContext & getContext() const
static StringRef getArchNameFromElfMach(unsigned ElfMach)
const std::optional< AMDGPU::IsaInfo::AMDGPUTargetID > & getTargetID() const
std::optional< AMDGPU::IsaInfo::AMDGPUTargetID > TargetID
virtual bool EmitHSAMetadataV2(StringRef HSAMetadataString)
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:277
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:613
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
MCAssembler & getAssembler()
Streaming machine code generation interface.
Definition: MCStreamer.h:212
MCContext & getContext() const
Definition: MCStreamer.h:297
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:180
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:424
void emitInt16(uint64_t Value)
Definition: MCStreamer.h:753
void emitInt32(uint64_t Value)
Definition: MCStreamer.h:754
void emitInt8(uint64_t Value)
Definition: MCStreamer.h:752
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
StringRef getCPU() const
unsigned getOther() const
void setVisibility(unsigned Visibility)
void setSize(const MCExpr *SS)
Definition: MCSymbolELF.h:22
bool isBindingSet() const
void setBinding(unsigned Binding) const
Definition: MCSymbolELF.cpp:43
unsigned getVisibility() const
unsigned getBinding() const
Definition: MCSymbolELF.cpp:66
void setType(unsigned Type) const
Definition: MCSymbolELF.cpp:94
void setOther(unsigned Other)
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:389
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
void setExternal(bool Value) const
Definition: MCSymbol.h:407
void setIndex(uint32_t Value) const
Set the (implementation defined) index.
Definition: MCSymbol.h:321
bool declareCommon(uint64_t Size, Align Alignment, bool Target=false)
Declare this symbol as being 'common'.
Definition: MCSymbol.h:375
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:366
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:357
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
An efficient, type-erasing, non-owning reference to a callable.
Simple in-memory representation of a document of msgpack objects with ability to find and create arra...
DocNode & getRoot()
Get ref to the document's root element.
void toYAML(raw_ostream &OS)
Convert MsgPack Document to YAML text.
void writeToBlob(std::string &Blob)
Write a MsgPack document to a binary MsgPack blob.
bool fromYAML(StringRef S)
Read YAML text into the MsgPack document. Returns false on failure.
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:642
std::string & str()
Returns the string's reference.
Definition: raw_ostream.h:660
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const char NoteNameV2[]
Definition: AMDGPUPTNote.h:26
const char SectionName[]
Definition: AMDGPUPTNote.h:24
const char NoteNameV3[]
Definition: AMDGPUPTNote.h:27
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
std::error_code fromString(StringRef String, Metadata &HSAMetadata)
Converts String to HSAMetadata.
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
std::error_code toString(Metadata HSAMetadata, std::string &String)
Converts HSAMetadata to String.
StringRef getArchNameR600(GPUKind AK)
GPUKind
GPU kinds supported by the AMDGPU target.
Definition: TargetParser.h:35
bool isHsaAbi(const MCSubtargetInfo &STI)
IsaVersion getIsaVersion(StringRef GPU)
bool isGFX90A(const MCSubtargetInfo &STI)
GPUKind parseArchAMDGCN(StringRef CPU)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
StringRef getArchNameAMDGCN(GPUKind AK)
std::optional< uint8_t > getHsaAbiVersion(const MCSubtargetInfo *STI)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
GPUKind parseArchR600(StringRef CPU)
@ STB_GLOBAL
Definition: ELF.h:1247
@ ELFABIVERSION_AMDGPU_HSA_V4
Definition: ELF.h:376
@ ELFABIVERSION_AMDGPU_HSA_V5
Definition: ELF.h:377
@ ELFABIVERSION_AMDGPU_HSA_V3
Definition: ELF.h:375
@ SHT_NOTE
Definition: ELF.h:1010
@ NT_AMDGPU_METADATA
Definition: ELF.h:1780
@ NT_AMD_HSA_ISA_NAME
Definition: ELF.h:1773
@ NT_AMD_HSA_ISA_VERSION
Definition: ELF.h:1770
@ NT_AMD_HSA_CODE_OBJECT_VERSION
Definition: ELF.h:1768
@ NT_AMD_HSA_METADATA
Definition: ELF.h:1772
@ EF_AMDGPU_FEATURE_XNACK_ANY_V4
Definition: ELF.h:824
@ EF_AMDGPU_MACH_AMDGCN_GFX703
Definition: ELF.h:747
@ EF_AMDGPU_MACH_AMDGCN_GFX1035
Definition: ELF.h:771
@ EF_AMDGPU_FEATURE_SRAMECC_V3
Definition: ELF.h:815
@ EF_AMDGPU_MACH_AMDGCN_GFX1031
Definition: ELF.h:765
@ EF_AMDGPU_MACH_R600_CAYMAN
Definition: ELF.h:729
@ EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4
Definition: ELF.h:835
@ EF_AMDGPU_MACH_AMDGCN_GFX704
Definition: ELF.h:748
@ EF_AMDGPU_MACH_AMDGCN_GFX902
Definition: ELF.h:755
@ EF_AMDGPU_MACH_AMDGCN_GFX810
Definition: ELF.h:753
@ EF_AMDGPU_MACH_AMDGCN_GFX1036
Definition: ELF.h:779
@ EF_AMDGPU_MACH_AMDGCN_GFX1102
Definition: ELF.h:781
@ EF_AMDGPU_MACH_R600_RV730
Definition: ELF.h:718
@ EF_AMDGPU_MACH_R600_RV710
Definition: ELF.h:717
@ EF_AMDGPU_MACH_AMDGCN_GFX908
Definition: ELF.h:758
@ EF_AMDGPU_MACH_AMDGCN_GFX1011
Definition: ELF.h:762
@ EF_AMDGPU_MACH_R600_CYPRESS
Definition: ELF.h:722
@ EF_AMDGPU_MACH_AMDGCN_GFX1032
Definition: ELF.h:766
@ EF_AMDGPU_MACH_R600_R600
Definition: ELF.h:712
@ EF_AMDGPU_MACH_AMDGCN_GFX940
Definition: ELF.h:774
@ EF_AMDGPU_MACH_AMDGCN_GFX941
Definition: ELF.h:785
@ EF_AMDGPU_MACH_R600_TURKS
Definition: ELF.h:730
@ EF_AMDGPU_MACH_R600_JUNIPER
Definition: ELF.h:723
@ EF_AMDGPU_FEATURE_SRAMECC_OFF_V4
Definition: ELF.h:839
@ EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4
Definition: ELF.h:822
@ EF_AMDGPU_MACH_AMDGCN_GFX601
Definition: ELF.h:743
@ EF_AMDGPU_MACH_AMDGCN_GFX942
Definition: ELF.h:786
@ EF_AMDGPU_MACH_R600_R630
Definition: ELF.h:713
@ EF_AMDGPU_MACH_R600_REDWOOD
Definition: ELF.h:724
@ EF_AMDGPU_MACH_R600_RV770
Definition: ELF.h:719
@ EF_AMDGPU_FEATURE_XNACK_OFF_V4
Definition: ELF.h:826
@ EF_AMDGPU_MACH_AMDGCN_GFX600
Definition: ELF.h:742
@ EF_AMDGPU_FEATURE_XNACK_V3
Definition: ELF.h:810
@ EF_AMDGPU_MACH_AMDGCN_GFX602
Definition: ELF.h:768
@ EF_AMDGPU_MACH_AMDGCN_GFX1101
Definition: ELF.h:780
@ EF_AMDGPU_MACH_AMDGCN_GFX1100
Definition: ELF.h:775
@ EF_AMDGPU_MACH_AMDGCN_GFX1033
Definition: ELF.h:767
@ EF_AMDGPU_MACH_AMDGCN_GFX801
Definition: ELF.h:750
@ EF_AMDGPU_MACH_AMDGCN_GFX705
Definition: ELF.h:769
@ EF_AMDGPU_MACH_AMDGCN_GFX1010
Definition: ELF.h:761
@ EF_AMDGPU_MACH_R600_RV670
Definition: ELF.h:715
@ EF_AMDGPU_MACH_AMDGCN_GFX701
Definition: ELF.h:745
@ EF_AMDGPU_MACH_AMDGCN_GFX1012
Definition: ELF.h:763
@ EF_AMDGPU_MACH_AMDGCN_GFX1151
Definition: ELF.h:784
@ EF_AMDGPU_MACH_AMDGCN_GFX1030
Definition: ELF.h:764
@ EF_AMDGPU_MACH_R600_CEDAR
Definition: ELF.h:721
@ EF_AMDGPU_MACH_AMDGCN_GFX1200
Definition: ELF.h:782
@ EF_AMDGPU_MACH_AMDGCN_GFX700
Definition: ELF.h:744
@ EF_AMDGPU_MACH_AMDGCN_GFX803
Definition: ELF.h:752
@ EF_AMDGPU_MACH_AMDGCN_GFX802
Definition: ELF.h:751
@ EF_AMDGPU_MACH_AMDGCN_GFX90C
Definition: ELF.h:760
@ EF_AMDGPU_FEATURE_XNACK_ON_V4
Definition: ELF.h:828
@ EF_AMDGPU_MACH_AMDGCN_GFX900
Definition: ELF.h:754
@ EF_AMDGPU_MACH_AMDGCN_GFX909
Definition: ELF.h:759
@ EF_AMDGPU_MACH_AMDGCN_GFX906
Definition: ELF.h:757
@ EF_AMDGPU_MACH_NONE
Definition: ELF.h:707
@ EF_AMDGPU_MACH_AMDGCN_GFX1103
Definition: ELF.h:778
@ EF_AMDGPU_MACH_R600_CAICOS
Definition: ELF.h:728
@ EF_AMDGPU_MACH_AMDGCN_GFX90A
Definition: ELF.h:773
@ EF_AMDGPU_MACH_AMDGCN_GFX1034
Definition: ELF.h:772
@ EF_AMDGPU_MACH_AMDGCN_GFX1013
Definition: ELF.h:776
@ EF_AMDGPU_MACH_AMDGCN_GFX904
Definition: ELF.h:756
@ EF_AMDGPU_MACH_R600_RS880
Definition: ELF.h:714
@ EF_AMDGPU_MACH_AMDGCN_GFX805
Definition: ELF.h:770
@ EF_AMDGPU_MACH_AMDGCN_GFX1201
Definition: ELF.h:788
@ EF_AMDGPU_MACH_AMDGCN_GFX1150
Definition: ELF.h:777
@ EF_AMDGPU_MACH_R600_SUMO
Definition: ELF.h:725
@ EF_AMDGPU_MACH_R600_BARTS
Definition: ELF.h:727
@ EF_AMDGPU_FEATURE_SRAMECC_ANY_V4
Definition: ELF.h:837
@ EF_AMDGPU_FEATURE_SRAMECC_ON_V4
Definition: ELF.h:841
@ EF_AMDGPU_MACH_AMDGCN_GFX702
Definition: ELF.h:746
@ STV_PROTECTED
Definition: ELF.h:1279
@ STV_DEFAULT
Definition: ELF.h:1276
@ SHN_AMDGPU_LDS
Definition: ELF.h:1763
@ SHF_ALLOC
Definition: ELF.h:1093
@ STT_AMDGPU_HSA_KERNEL
Definition: ELF.h:1272
@ STT_OBJECT
Definition: ELF.h:1259
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
void dumpAmdKernelCode(const amd_kernel_code_t *C, raw_ostream &OS, const char *tab)
AMD Kernel Code Object (amd_kernel_code_t).
In-memory representation of HSA metadata.
Instruction set architecture version.
Definition: TargetParser.h:117
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85