LLVM 23.0.0git
AMDGPUTargetStreamer.cpp
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1//===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides AMDGPU specific target streamer methods.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AMDGPUTargetStreamer.h"
14#include "AMDGPUMCExpr.h"
15#include "AMDGPUMCKernelDescriptor.h"
16#include "AMDGPUMCTargetDesc.h"
17#include "AMDGPUPTNote.h"
18#include "Utils/AMDGPUBaseInfo.h"
19#include "Utils/AMDKernelCodeTUtils.h"
20#include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h"
21#include "llvm/BinaryFormat/ELF.h"
22#include "llvm/MC/MCAsmInfo.h"
23#include "llvm/MC/MCAssembler.h"
24#include "llvm/MC/MCContext.h"
25#include "llvm/MC/MCELFObjectWriter.h"
26#include "llvm/MC/MCELFStreamer.h"
27#include "llvm/MC/MCSubtargetInfo.h"
28#include "llvm/MC/StringTableBuilder.h"
29#include "llvm/Support/AMDGPUMetadata.h"
30#include "llvm/Support/AMDGPUObjLinkingInfo.h"
31#include "llvm/Support/AMDHSAKernelDescriptor.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/FormattedStream.h"
34#include "llvm/TargetParser/AMDGPUTargetParser.h"
35
36using namespace llvm;
37using namespace llvm::AMDGPU;
38
39//===----------------------------------------------------------------------===//
40// AMDGPUTargetStreamer
41//===----------------------------------------------------------------------===//
42
43static cl::opt<unsigned>
44 ForceGenericVersion("amdgpu-force-generic-version",
45 cl::desc("Force a specific generic_v<N> flag to be "
46 "added. For testing purposes only."),
47 cl::ReallyHidden, cl::init(0));
48
49bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) {
50 msgpack::Document HSAMetadataDoc;
51 if (!HSAMetadataDoc.fromYAML(HSAMetadataString))
52 return false;
53 return EmitHSAMetadata(HSAMetadataDoc, false);
54}
55
56StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) {
57 AMDGPU::GPUKind AK;
58
59 // clang-format off
60 switch (ElfMach) {
61 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break;
62 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break;
63 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break;
64 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break;
65 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break;
66 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break;
67 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break;
68 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break;
69 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break;
70 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break;
71 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break;
72 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break;
73 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break;
74 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break;
75 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break;
76 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break;
77 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break;
78 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break;
79 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break;
80 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break;
81 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break;
82 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break;
83 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break;
84 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break;
85 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break;
86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break;
87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break;
88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break;
89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break;
90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break;
91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break;
92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break;
93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break;
94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break;
95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break;
96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break;
97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A: AK = GK_GFX90A; break;
98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break;
99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX942: AK = GK_GFX942; break;
100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX950: AK = GK_GFX950; break;
101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break;
102 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break;
103 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break;
104 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013: AK = GK_GFX1013; break;
105 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break;
106 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break;
107 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break;
108 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: AK = GK_GFX1033; break;
109 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034: AK = GK_GFX1034; break;
110 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035: AK = GK_GFX1035; break;
111 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036: AK = GK_GFX1036; break;
112 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100: AK = GK_GFX1100; break;
113 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101: AK = GK_GFX1101; break;
114 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102: AK = GK_GFX1102; break;
115 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103: AK = GK_GFX1103; break;
116 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1150: AK = GK_GFX1150; break;
117 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1151: AK = GK_GFX1151; break;
118 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1152: AK = GK_GFX1152; break;
119 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1153: AK = GK_GFX1153; break;
120 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1154: AK = GK_GFX1154; break;
121 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1170: AK = GK_GFX1170; break;
122 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1171: AK = GK_GFX1171; break;
123 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1172: AK = GK_GFX1172; break;
124 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1200: AK = GK_GFX1200; break;
125 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1201: AK = GK_GFX1201; break;
126 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1250: AK = GK_GFX1250; break;
127 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1251: AK = GK_GFX1251; break;
128 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1310: AK = GK_GFX1310; break;
129 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC: AK = GK_GFX9_GENERIC; break;
130 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX9_4_GENERIC: AK = GK_GFX9_4_GENERIC; break;
131 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERIC: AK = GK_GFX10_1_GENERIC; break;
132 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_3_GENERIC: AK = GK_GFX10_3_GENERIC; break;
133 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX11_GENERIC: AK = GK_GFX11_GENERIC; break;
134 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX11_7_GENERIC: AK = GK_GFX11_7_GENERIC; break;
135 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX12_GENERIC: AK = GK_GFX12_GENERIC; break;
136 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX12_5_GENERIC: AK = GK_GFX12_5_GENERIC; break;
137 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX13_GENERIC: AK = GK_GFX13_GENERIC; break;
138 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break;
139 default: AK = GK_NONE; break;
140 }
141 // clang-format on
142
143 StringRef GPUName = getArchNameAMDGCN(AK);
144 if (GPUName != "")
145 return GPUName;
146 return getArchNameR600(AK);
147}
148
149unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) {
150 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU);
151 if (AK == AMDGPU::GPUKind::GK_NONE)
152 AK = parseArchR600(GPU);
153
154 // clang-format off
155 switch (AK) {
156 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600;
157 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630;
158 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880;
159 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670;
160 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710;
161 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730;
162 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770;
163 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR;
164 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS;
165 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER;
166 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD;
167 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO;
168 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS;
169 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS;
170 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN;
171 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS;
172 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600;
173 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601;
174 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602;
175 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700;
176 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701;
177 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702;
178 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703;
179 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704;
180 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705;
181 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801;
182 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802;
183 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803;
184 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805;
185 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810;
186 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900;
187 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902;
188 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904;
189 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906;
190 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908;
191 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909;
192 case GK_GFX90A: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A;
193 case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C;
194 case GK_GFX942: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX942;
195 case GK_GFX950: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX950;
196 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010;
197 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011;
198 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012;
199 case GK_GFX1013: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013;
200 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030;
201 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031;
202 case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032;
203 case GK_GFX1033: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033;
204 case GK_GFX1034: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034;
205 case GK_GFX1035: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035;
206 case GK_GFX1036: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036;
207 case GK_GFX1100: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100;
208 case GK_GFX1101: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101;
209 case GK_GFX1102: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102;
210 case GK_GFX1103: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103;
211 case GK_GFX1150: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1150;
212 case GK_GFX1151: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1151;
213 case GK_GFX1152: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1152;
214 case GK_GFX1153: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1153;
215 case GK_GFX1154: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1154;
216 case GK_GFX1170: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1170;
217 case GK_GFX1171: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1171;
218 case GK_GFX1172: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1172;
219 case GK_GFX1200: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1200;
220 case GK_GFX1201: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1201;
221 case GK_GFX1250: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1250;
222 case GK_GFX1251: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1251;
223 case GK_GFX1310: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1310;
224 case GK_GFX9_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC;
225 case GK_GFX9_4_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX9_4_GENERIC;
226 case GK_GFX10_1_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERIC;
227 case GK_GFX10_3_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_3_GENERIC;
228 case GK_GFX11_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX11_GENERIC;
229 case GK_GFX11_7_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX11_7_GENERIC;
230 case GK_GFX12_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX12_GENERIC;
231 case GK_GFX12_5_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX12_5_GENERIC;
232 case GK_GFX13_GENERIC: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX13_GENERIC;
233 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE;
234 }
235 // clang-format on
236
237 llvm_unreachable("unknown GPU");
238}
239
240//===----------------------------------------------------------------------===//
241// AMDGPUTargetAsmStreamer
242//===----------------------------------------------------------------------===//
243
247
248// A hook for emitting stuff at the end.
249// We use it for emitting the accumulated PAL metadata as directives.
250// The PAL metadata is reset after it is emitted.
251void AMDGPUTargetAsmStreamer::finish() {
252 std::string S;
253 getPALMetadata()->toString(S);
254 OS << S;
255
256 // Reset the pal metadata so its data will not affect a compilation that
257 // reuses this object.
258 getPALMetadata()->reset();
259}
260
261void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() {
262 OS << "\t.amdgcn_target \"" << *getTargetID() << "\"\n";
263}
264
265void AMDGPUTargetAsmStreamer::EmitDirectiveAMDHSACodeObjectVersion(
266 unsigned COV) {
267 AMDGPUTargetStreamer::EmitDirectiveAMDHSACodeObjectVersion(COV);
268 OS << "\t.amdhsa_code_object_version " << COV << '\n';
269}
270
271void AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(AMDGPUMCKernelCodeT &Header) {
272 auto FoldAndPrint = [&](const MCExpr *Expr, raw_ostream &OS,
273 const MCAsmInfo *MAI) {
274 printAMDGPUMCExpr(foldAMDGPUMCExpr(Expr, getContext()), OS, MAI);
275 };
276
277 OS << "\t.amd_kernel_code_t\n";
278 Header.EmitKernelCodeT(OS, getContext(), FoldAndPrint);
279 OS << "\t.end_amd_kernel_code_t\n";
280}
281
282void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
283 unsigned Type) {
284 switch (Type) {
285 default:
286 llvm_unreachable("Invalid AMDGPU symbol type");
287 case ELF::STT_AMDGPU_HSA_KERNEL:
288 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n';
289 break;
290 }
291}
292
293void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size,
294 Align Alignment) {
295 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", "
296 << Alignment.value() << '\n';
297}
298
299void AMDGPUTargetAsmStreamer::EmitMCResourceInfo(
300 const MCSymbol *NumVGPR, const MCSymbol *NumAGPR,
301 const MCSymbol *NumExplicitSGPR, const MCSymbol *NumNamedBarrier,
302 const MCSymbol *PrivateSegmentSize, const MCSymbol *UsesVCC,
303 const MCSymbol *UsesFlatScratch, const MCSymbol *HasDynamicallySizedStack,
304 const MCSymbol *HasRecursion, const MCSymbol *HasIndirectCall) {
305#define PRINT_RES_INFO(ARG) \
306 OS << "\t.set "; \
307 ARG->print(OS, &getContext().getAsmInfo()); \
308 OS << ", "; \
309 getContext().getAsmInfo().printExpr(OS, *ARG->getVariableValue()); \
310 Streamer.addBlankLine();
311
312 PRINT_RES_INFO(NumVGPR);
313 PRINT_RES_INFO(NumAGPR);
314 PRINT_RES_INFO(NumExplicitSGPR);
315 PRINT_RES_INFO(NumNamedBarrier);
316 PRINT_RES_INFO(PrivateSegmentSize);
317 PRINT_RES_INFO(UsesVCC);
318 PRINT_RES_INFO(UsesFlatScratch);
319 PRINT_RES_INFO(HasDynamicallySizedStack);
320 PRINT_RES_INFO(HasRecursion);
321 PRINT_RES_INFO(HasIndirectCall);
322#undef PRINT_RES_INFO
323}
324
325void AMDGPUTargetAsmStreamer::EmitMCResourceMaximums(
326 const MCSymbol *MaxVGPR, const MCSymbol *MaxAGPR, const MCSymbol *MaxSGPR,
327 const MCSymbol *MaxNamedBarrier) {
328#define PRINT_RES_INFO(ARG) \
329 OS << "\t.set "; \
330 ARG->print(OS, &getContext().getAsmInfo()); \
331 OS << ", "; \
332 getContext().getAsmInfo().printExpr(OS, *ARG->getVariableValue()); \
333 Streamer.addBlankLine();
334
335 PRINT_RES_INFO(MaxVGPR);
336 PRINT_RES_INFO(MaxAGPR);
337 PRINT_RES_INFO(MaxSGPR);
338 PRINT_RES_INFO(MaxNamedBarrier);
339#undef PRINT_RES_INFO
340}
341
342bool AMDGPUTargetAsmStreamer::EmitISAVersion() {
343 OS << "\t.amd_amdgpu_isa \"" << getTargetID() << "\"\n";
344 return true;
345}
346
347bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc,
348 bool Strict) {
349 HSAMD::V3::MetadataVerifier Verifier(Strict);
350 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
351 return false;
352
353 std::string HSAMetadataString;
354 raw_string_ostream StrOS(HSAMetadataString);
355 HSAMetadataDoc.toYAML(StrOS);
356
357 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n';
358 OS << StrOS.str() << '\n';
359 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n';
360 return true;
361}
362
363bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
364 const uint32_t Encoded_s_code_end = 0xbf9f0000;
365 const uint32_t Encoded_s_nop = 0xbf800000;
366 uint32_t Encoded_pad = Encoded_s_code_end;
367
368 // Instruction cache line size in bytes.
369 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
370 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
371
372 // Extra padding amount in bytes to support prefetch mode 3.
373 unsigned FillSize = 3 * CacheLineSize;
374
375 if (AMDGPU::isGFX90A(STI)) {
376 Encoded_pad = Encoded_s_nop;
377 FillSize = 16 * CacheLineSize;
378 }
379
380 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n';
381 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n';
382 return true;
383}
384
385void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
386 const MCSubtargetInfo &STI, StringRef KernelName,
387 const MCKernelDescriptor &KD, const MCExpr *NextVGPR,
388 const MCExpr *NextSGPR, const MCExpr *ReserveVCC,
389 const MCExpr *ReserveFlatScr) {
390 IsaVersion IVersion = getIsaVersion(STI.getCPU());
391 const MCAsmInfo &MAI = getContext().getAsmInfo();
392
393 OS << "\t.amdhsa_kernel " << KernelName << '\n';
394
395 auto PrintField = [&](const MCExpr *Expr, uint32_t Shift, uint32_t Mask,
396 StringRef Directive) {
397 OS << "\t\t" << Directive << ' ';
398 const MCExpr *ShiftedAndMaskedExpr =
399 MCKernelDescriptor::bits_get(Expr, Shift, Mask, getContext());
400 const MCExpr *New = foldAMDGPUMCExpr(ShiftedAndMaskedExpr, getContext());
401 printAMDGPUMCExpr(New, OS, &MAI);
402 OS << '\n';
403 };
404
405 auto EmitMCExpr = [&](const MCExpr *Value) {
406 const MCExpr *NewExpr = foldAMDGPUMCExpr(Value, getContext());
407 printAMDGPUMCExpr(NewExpr, OS, &MAI);
408 };
409
410 OS << "\t\t.amdhsa_group_segment_fixed_size ";
411 EmitMCExpr(KD.group_segment_fixed_size);
412 OS << '\n';
413
414 OS << "\t\t.amdhsa_private_segment_fixed_size ";
415 EmitMCExpr(KD.private_segment_fixed_size);
416 OS << '\n';
417
418 OS << "\t\t.amdhsa_kernarg_size ";
419 EmitMCExpr(KD.kernarg_size);
420 OS << '\n';
421
422 if (isGFX1250Plus(STI)) {
423 PrintField(KD.compute_pgm_rsrc2,
424 amdhsa::COMPUTE_PGM_RSRC2_GFX125_USER_SGPR_COUNT_SHIFT,
425 amdhsa::COMPUTE_PGM_RSRC2_GFX125_USER_SGPR_COUNT,
426 ".amdhsa_user_sgpr_count");
427 } else {
428 PrintField(KD.compute_pgm_rsrc2,
429 amdhsa::COMPUTE_PGM_RSRC2_GFX6_GFX120_USER_SGPR_COUNT_SHIFT,
430 amdhsa::COMPUTE_PGM_RSRC2_GFX6_GFX120_USER_SGPR_COUNT,
431 ".amdhsa_user_sgpr_count");
432 }
433
434 if (!hasArchitectedFlatScratch(STI))
435 PrintField(
436 KD.kernel_code_properties,
437 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT,
438 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER,
439 ".amdhsa_user_sgpr_private_segment_buffer");
440 PrintField(KD.kernel_code_properties,
441 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_SHIFT,
442 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR,
443 ".amdhsa_user_sgpr_dispatch_ptr");
444 PrintField(KD.kernel_code_properties,
445 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_SHIFT,
446 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR,
447 ".amdhsa_user_sgpr_queue_ptr");
448 PrintField(KD.kernel_code_properties,
449 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT,
450 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR,
451 ".amdhsa_user_sgpr_kernarg_segment_ptr");
452 PrintField(KD.kernel_code_properties,
453 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID_SHIFT,
454 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID,
455 ".amdhsa_user_sgpr_dispatch_id");
456 if (!hasArchitectedFlatScratch(STI))
457 PrintField(KD.kernel_code_properties,
458 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT,
459 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT,
460 ".amdhsa_user_sgpr_flat_scratch_init");
461 if (hasKernargPreload(STI)) {
462 PrintField(KD.kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_LENGTH_SHIFT,
463 amdhsa::KERNARG_PRELOAD_SPEC_LENGTH,
464 ".amdhsa_user_sgpr_kernarg_preload_length");
465 PrintField(KD.kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_OFFSET_SHIFT,
466 amdhsa::KERNARG_PRELOAD_SPEC_OFFSET,
467 ".amdhsa_user_sgpr_kernarg_preload_offset");
468 }
469 PrintField(
470 KD.kernel_code_properties,
471 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT,
472 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE,
473 ".amdhsa_user_sgpr_private_segment_size");
474 if (IVersion.Major >= 10)
475 PrintField(KD.kernel_code_properties,
476 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_SHIFT,
477 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
478 ".amdhsa_wavefront_size32");
479 if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5)
480 PrintField(KD.kernel_code_properties,
481 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK_SHIFT,
482 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK,
483 ".amdhsa_uses_dynamic_stack");
484 PrintField(KD.compute_pgm_rsrc2,
485 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT_SHIFT,
486 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT,
487 (hasArchitectedFlatScratch(STI)
488 ? ".amdhsa_enable_private_segment"
489 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"));
490 PrintField(KD.compute_pgm_rsrc2,
491 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT,
492 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X,
493 ".amdhsa_system_sgpr_workgroup_id_x");
494 PrintField(KD.compute_pgm_rsrc2,
495 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y_SHIFT,
496 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y,
497 ".amdhsa_system_sgpr_workgroup_id_y");
498 PrintField(KD.compute_pgm_rsrc2,
499 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z_SHIFT,
500 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z,
501 ".amdhsa_system_sgpr_workgroup_id_z");
502 PrintField(KD.compute_pgm_rsrc2,
503 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO_SHIFT,
504 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO,
505 ".amdhsa_system_sgpr_workgroup_info");
506 PrintField(KD.compute_pgm_rsrc2,
507 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID_SHIFT,
508 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID,
509 ".amdhsa_system_vgpr_workitem_id");
510
511 // These directives are required.
512 OS << "\t\t.amdhsa_next_free_vgpr ";
513 EmitMCExpr(NextVGPR);
514 OS << '\n';
515
516 OS << "\t\t.amdhsa_next_free_sgpr ";
517 EmitMCExpr(NextSGPR);
518 OS << '\n';
519
520 if (AMDGPU::isGFX90A(STI)) {
521 // MCExpr equivalent of taking the (accum_offset + 1) * 4.
522 const MCExpr *accum_bits = MCKernelDescriptor::bits_get(
523 KD.compute_pgm_rsrc3,
524 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET_SHIFT,
525 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET, getContext());
526 accum_bits = MCBinaryExpr::createAdd(
527 accum_bits, MCConstantExpr::create(1, getContext()), getContext());
528 accum_bits = MCBinaryExpr::createMul(
529 accum_bits, MCConstantExpr::create(4, getContext()), getContext());
530 OS << "\t\t.amdhsa_accum_offset ";
531 const MCExpr *New = foldAMDGPUMCExpr(accum_bits, getContext());
532 printAMDGPUMCExpr(New, OS, &MAI);
533 OS << '\n';
534 }
535
536 if (isGFX1250Plus(STI))
537 PrintField(KD.compute_pgm_rsrc3,
538 amdhsa::COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT_SHIFT,
539 amdhsa::COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT,
540 ".amdhsa_named_barrier_count");
541
542 OS << "\t\t.amdhsa_reserve_vcc ";
543 EmitMCExpr(ReserveVCC);
544 OS << '\n';
545
546 if (IVersion.Major >= 7 && !hasArchitectedFlatScratch(STI)) {
547 OS << "\t\t.amdhsa_reserve_flat_scratch ";
548 EmitMCExpr(ReserveFlatScr);
549 OS << '\n';
550 }
551
552 switch (CodeObjectVersion) {
553 default:
554 break;
555 case AMDGPU::AMDHSA_COV4:
556 case AMDGPU::AMDHSA_COV5:
557 if (getTargetID()->isXnackSupported())
558 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny()
559 << '\n';
560 break;
561 }
562
563 PrintField(KD.compute_pgm_rsrc1,
564 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32_SHIFT,
565 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32,
566 ".amdhsa_float_round_mode_32");
567 PrintField(KD.compute_pgm_rsrc1,
568 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64_SHIFT,
569 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64,
570 ".amdhsa_float_round_mode_16_64");
571 PrintField(KD.compute_pgm_rsrc1,
572 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32_SHIFT,
573 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32,
574 ".amdhsa_float_denorm_mode_32");
575 PrintField(KD.compute_pgm_rsrc1,
576 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64_SHIFT,
577 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64,
578 ".amdhsa_float_denorm_mode_16_64");
579 if (STI.hasFeature(AMDGPU::FeatureDX10ClampAndIEEEMode)) {
580 PrintField(KD.compute_pgm_rsrc1,
581 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP_SHIFT,
582 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP,
583 ".amdhsa_dx10_clamp");
584 PrintField(KD.compute_pgm_rsrc1,
585 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE_SHIFT,
586 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE,
587 ".amdhsa_ieee_mode");
588 }
589 if (IVersion.Major >= 9) {
590 PrintField(KD.compute_pgm_rsrc1,
591 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL_SHIFT,
592 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL,
593 ".amdhsa_fp16_overflow");
594 }
595 if (AMDGPU::isGFX90A(STI))
596 PrintField(KD.compute_pgm_rsrc3,
597 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT,
598 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, ".amdhsa_tg_split");
599 if (AMDGPU::supportsWGP(STI))
600 PrintField(KD.compute_pgm_rsrc1,
601 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE_SHIFT,
602 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE,
603 ".amdhsa_workgroup_processor_mode");
604 if (IVersion.Major >= 10) {
605 PrintField(KD.compute_pgm_rsrc1,
606 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED_SHIFT,
607 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED,
608 ".amdhsa_memory_ordered");
609 PrintField(KD.compute_pgm_rsrc1,
610 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS_SHIFT,
611 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS,
612 ".amdhsa_forward_progress");
613 }
614 if (IVersion.Major >= 10 && IVersion.Major < 12) {
615 PrintField(KD.compute_pgm_rsrc3,
616 amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT_SHIFT,
617 amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT,
618 ".amdhsa_shared_vgpr_count");
619 }
620 if (IVersion.Major == 11) {
621 PrintField(KD.compute_pgm_rsrc3,
622 amdhsa::COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE_SHIFT,
623 amdhsa::COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE,
624 ".amdhsa_inst_pref_size");
625 }
626 if (IVersion.Major >= 12) {
627 PrintField(KD.compute_pgm_rsrc3,
628 amdhsa::COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE_SHIFT,
629 amdhsa::COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE,
630 ".amdhsa_inst_pref_size");
631 PrintField(KD.compute_pgm_rsrc1,
632 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN_SHIFT,
633 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN,
634 ".amdhsa_round_robin_scheduling");
635 }
636 PrintField(
637 KD.compute_pgm_rsrc2,
638 amdhsa::
639 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_SHIFT,
640 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION,
641 ".amdhsa_exception_fp_ieee_invalid_op");
642 PrintField(
643 KD.compute_pgm_rsrc2,
644 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_SHIFT,
645 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE,
646 ".amdhsa_exception_fp_denorm_src");
647 PrintField(
648 KD.compute_pgm_rsrc2,
649 amdhsa::
650 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_SHIFT,
651 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO,
652 ".amdhsa_exception_fp_ieee_div_zero");
653 PrintField(
654 KD.compute_pgm_rsrc2,
655 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_SHIFT,
656 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW,
657 ".amdhsa_exception_fp_ieee_overflow");
658 PrintField(
659 KD.compute_pgm_rsrc2,
660 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_SHIFT,
661 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW,
662 ".amdhsa_exception_fp_ieee_underflow");
663 PrintField(
664 KD.compute_pgm_rsrc2,
665 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_SHIFT,
666 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT,
667 ".amdhsa_exception_fp_ieee_inexact");
668 PrintField(
669 KD.compute_pgm_rsrc2,
670 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO_SHIFT,
671 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO,
672 ".amdhsa_exception_int_div_zero");
673
674 OS << "\t.end_amdhsa_kernel\n";
675}
676
677namespace {
678/// Callback type invoked by \c forEachInfoScope for each function scope in
679/// the canonical iteration order. The scope is emitted exactly once per
680/// unique \p Sym regardless of how many flat entries reference it.
681using InfoScopeEmitter = function_ref<void(
682 MCSymbol *Sym, const AMDGPU::FuncInfo *Info, ArrayRef<MCSymbol *> Uses,
683 ArrayRef<MCSymbol *> Calls, ArrayRef<StringRef> IndirectCallTypeIds,
684 ArrayRef<StringRef> TypeIds)>;
685
686/// Group the flat edge lists in \p Data by source function symbol and drive
687/// per-scope emission. A scope is opened for every function with attached
688/// info and for every function that appears only as an edge source; each
689/// scope is emitted exactly once. Both the asm and ELF streamers share this
690/// iteration logic and only differ in the per-scope emission callback.
691static void forEachInfoScope(const AMDGPU::InfoSectionData &Data,
692 InfoScopeEmitter Emit) {
693 DenseMap<MCSymbol *, SmallVector<MCSymbol *, 2>> FuncUses;
694 DenseMap<MCSymbol *, SmallVector<MCSymbol *, 4>> FuncCalls;
695 DenseMap<MCSymbol *, SmallVector<StringRef, 2>> FuncIndirectCalls;
696 DenseMap<MCSymbol *, SmallVector<StringRef, 1>> FuncTypeIds;
697 for (const auto &[Func, Res] : Data.Uses)
698 FuncUses[Func].push_back(Res);
699 for (const auto &[Src, Dst] : Data.Calls)
700 FuncCalls[Src].push_back(Dst);
701 for (const auto &[Func, TypeId] : Data.IndirectCalls)
702 FuncIndirectCalls[Func].push_back(TypeId);
703 for (const auto &[Sym, TypeId] : Data.TypeIds)
704 FuncTypeIds[Sym].push_back(TypeId);
705
706 DenseSet<MCSymbol *> Emitted;
707 auto EmitIfNew = [&](MCSymbol *Sym, const AMDGPU::FuncInfo *Info) {
708 if (!Emitted.insert(Sym).second)
709 return;
710 ArrayRef<MCSymbol *> Uses, Calls;
711 ArrayRef<StringRef> IndirectCallTypeIds, TypeIds;
712 if (auto It = FuncUses.find(Sym); It != FuncUses.end())
713 Uses = It->second;
714 if (auto It = FuncCalls.find(Sym); It != FuncCalls.end())
715 Calls = It->second;
716 if (auto It = FuncIndirectCalls.find(Sym); It != FuncIndirectCalls.end())
717 IndirectCallTypeIds = It->second;
718 if (auto It = FuncTypeIds.find(Sym); It != FuncTypeIds.end())
719 TypeIds = It->second;
720 Emit(Sym, Info, Uses, Calls, IndirectCallTypeIds, TypeIds);
721 };
722
723 for (const AMDGPU::FuncInfo &Func : Data.Funcs)
724 EmitIfNew(Func.Sym, &Func);
725 // Emit scopes for functions that only appear as edge sources (e.g. typeid
726 // tags on address-taken declarations, or callers of external functions).
727 for (const auto &[Sym, TypeId] : Data.TypeIds)
728 EmitIfNew(Sym, nullptr);
729 for (const auto &[Sym, Res] : Data.Uses)
730 EmitIfNew(Sym, nullptr);
731 for (const auto &[Sym, Dst] : Data.Calls)
732 EmitIfNew(Sym, nullptr);
733 for (const auto &[Sym, TypeId] : Data.IndirectCalls)
734 EmitIfNew(Sym, nullptr);
735}
736} // namespace
737
738void AMDGPUTargetAsmStreamer::emitAMDGPUInfo(
739 const AMDGPU::InfoSectionData &Data) {
740 forEachInfoScope(Data, [&](MCSymbol *Sym, const AMDGPU::FuncInfo *Info,
741 ArrayRef<MCSymbol *> Uses,
742 ArrayRef<MCSymbol *> Calls,
743 ArrayRef<StringRef> IndirectCallTypeIds,
744 ArrayRef<StringRef> TypeIds) {
745 OS << "\t.amdgpu_info " << Sym->getName() << '\n';
746 if (Info) {
747 AMDGPU::FuncInfoFlags Flags{};
748 if (Info->UsesVCC)
749 Flags |= AMDGPU::FuncInfoFlags::FUNC_USES_VCC;
750 if (Info->UsesFlatScratch)
751 Flags |= AMDGPU::FuncInfoFlags::FUNC_USES_FLAT_SCRATCH;
752 if (Info->HasDynStack)
753 Flags |= AMDGPU::FuncInfoFlags::FUNC_HAS_DYN_STACK;
754 OS << "\t\t.amdgpu_flags " << llvm::to_underlying(Flags) << '\n';
755 OS << "\t\t.amdgpu_num_sgpr " << Info->NumSGPR << '\n';
756 OS << "\t\t.amdgpu_num_vgpr " << Info->NumArchVGPR << '\n';
757 if (Info->NumAccVGPR)
758 OS << "\t\t.amdgpu_num_agpr " << Info->NumAccVGPR << '\n';
759 OS << "\t\t.amdgpu_private_segment_size " << Info->PrivateSegmentSize
760 << '\n';
761 }
762 for (MCSymbol *Res : Uses)
763 OS << "\t\t.amdgpu_use " << Res->getName() << '\n';
764 for (MCSymbol *Dst : Calls)
765 OS << "\t\t.amdgpu_call " << Dst->getName() << '\n';
766 for (StringRef TypeId : IndirectCallTypeIds)
767 OS << "\t\t.amdgpu_indirect_call \"" << TypeId << "\"\n";
768 for (StringRef TypeId : TypeIds)
769 OS << "\t\t.amdgpu_typeid \"" << TypeId << "\"\n";
770 OS << "\t.end_amdgpu_info\n\n";
771 });
772}
773
774//===----------------------------------------------------------------------===//
775// AMDGPUTargetELFStreamer
776//===----------------------------------------------------------------------===//
777
781
782MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() {
783 return static_cast<MCELFStreamer &>(Streamer);
784}
785
786// A hook for emitting stuff at the end.
787// We use it for emitting the accumulated PAL metadata as a .note record.
788// The PAL metadata is reset after it is emitted.
789void AMDGPUTargetELFStreamer::finish() {
790 ELFObjectWriter &W = getStreamer().getWriter();
791 W.setELFHeaderEFlags(getEFlags());
792 W.setOverrideABIVersion(
793 getELFABIVersion(STI.getTargetTriple(), CodeObjectVersion));
794
795 std::string Blob;
796 const char *Vendor = getPALMetadata()->getVendor();
797 unsigned Type = getPALMetadata()->getType();
798 getPALMetadata()->toBlob(Type, Blob);
799 if (Blob.empty())
800 return;
801 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type,
802 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); });
803
804 // Reset the pal metadata so its data will not affect a compilation that
805 // reuses this object.
806 getPALMetadata()->reset();
807}
808
809void AMDGPUTargetELFStreamer::EmitNote(
810 StringRef Name, const MCExpr *DescSZ, unsigned NoteType,
811 function_ref<void(MCELFStreamer &)> EmitDesc) {
812 auto &S = getStreamer();
813 auto &Context = S.getContext();
814
815 auto NameSZ = Name.size() + 1;
816
817 unsigned NoteFlags = 0;
818 // TODO Apparently, this is currently needed for OpenCL as mentioned in
819 // https://reviews.llvm.org/D74995
820 if (isHsaAbi(STI))
821 NoteFlags = ELF::SHF_ALLOC;
822
823 S.pushSection();
824 S.switchSection(
825 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags));
826 S.emitInt32(NameSZ); // namesz
827 S.emitValue(DescSZ, 4); // descz
828 S.emitInt32(NoteType); // type
829 S.emitBytes(Name); // name
830 S.emitInt8(0); // null terminator
831 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
832 EmitDesc(S); // desc
833 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
834 S.popSection();
835}
836
837unsigned AMDGPUTargetELFStreamer::getEFlags() {
838 switch (STI.getTargetTriple().getArch()) {
839 default:
840 llvm_unreachable("Unsupported Arch");
841 case Triple::r600:
842 return getEFlagsR600();
843 case Triple::amdgcn:
844 return getEFlagsAMDGCN();
845 }
846}
847
848unsigned AMDGPUTargetELFStreamer::getEFlagsR600() {
849 assert(STI.getTargetTriple().getArch() == Triple::r600);
850
851 return getElfMach(STI.getCPU());
852}
853
854unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() {
855 assert(STI.getTargetTriple().isAMDGCN());
856
857 switch (STI.getTargetTriple().getOS()) {
858 default:
859 // TODO: Why are some tests have "mingw" listed as OS?
860 // llvm_unreachable("Unsupported OS");
861 case Triple::UnknownOS:
862 return getEFlagsUnknownOS();
863 case Triple::AMDHSA:
864 return getEFlagsAMDHSA();
865 case Triple::AMDPAL:
866 return getEFlagsAMDPAL();
867 case Triple::Mesa3D:
868 return getEFlagsMesa3D();
869 }
870}
871
872unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() {
873 // TODO: Why are some tests have "mingw" listed as OS?
874 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS);
875
876 return getEFlagsV3();
877}
878
879unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() {
880 assert(isHsaAbi(STI));
881
882 if (CodeObjectVersion >= 6)
883 return getEFlagsV6();
884 return getEFlagsV4();
885}
886
887unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() {
888 assert(STI.getTargetTriple().getOS() == Triple::AMDPAL);
889
890 return getEFlagsV3();
891}
892
893unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() {
894 assert(STI.getTargetTriple().getOS() == Triple::Mesa3D);
895
896 return getEFlagsV3();
897}
898
899unsigned AMDGPUTargetELFStreamer::getEFlagsV3() {
900 unsigned EFlagsV3 = 0;
901
902 // mach.
903 EFlagsV3 |= getElfMach(STI.getCPU());
904
905 // xnack.
906 if (getTargetID()->isXnackOnOrAny())
907 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_XNACK_V3;
908 // sramecc.
909 if (getTargetID()->isSramEccOnOrAny())
910 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_V3;
911
912 return EFlagsV3;
913}
914
915unsigned AMDGPUTargetELFStreamer::getEFlagsV4() {
916 unsigned EFlagsV4 = 0;
917
918 // mach.
919 EFlagsV4 |= getElfMach(STI.getCPU());
920
921 // xnack.
922 switch (getTargetID()->getXnackSetting()) {
923 case AMDGPU::TargetIDSetting::Unsupported:
924 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4;
925 break;
926 case AMDGPU::TargetIDSetting::Any:
927 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4;
928 break;
929 case AMDGPU::TargetIDSetting::Off:
930 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4;
931 break;
932 case AMDGPU::TargetIDSetting::On:
933 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4;
934 break;
935 }
936 // sramecc.
937 switch (getTargetID()->getSramEccSetting()) {
938 case AMDGPU::TargetIDSetting::Unsupported:
939 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4;
940 break;
941 case AMDGPU::TargetIDSetting::Any:
942 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4;
943 break;
944 case AMDGPU::TargetIDSetting::Off:
945 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4;
946 break;
947 case AMDGPU::TargetIDSetting::On:
948 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4;
949 break;
950 }
951
952 return EFlagsV4;
953}
954
955unsigned AMDGPUTargetELFStreamer::getEFlagsV6() {
956 unsigned Flags = getEFlagsV4();
957
958 unsigned Version = ForceGenericVersion;
959 if (!Version) {
960 switch (parseArchAMDGCN(STI.getCPU())) {
961 case AMDGPU::GK_GFX9_GENERIC:
962 Version = GenericVersion::GFX9;
963 break;
964 case AMDGPU::GK_GFX9_4_GENERIC:
965 Version = GenericVersion::GFX9_4;
966 break;
967 case AMDGPU::GK_GFX10_1_GENERIC:
968 Version = GenericVersion::GFX10_1;
969 break;
970 case AMDGPU::GK_GFX10_3_GENERIC:
971 Version = GenericVersion::GFX10_3;
972 break;
973 case AMDGPU::GK_GFX11_GENERIC:
974 Version = GenericVersion::GFX11;
975 break;
976 case AMDGPU::GK_GFX11_7_GENERIC:
977 Version = GenericVersion::GFX11_7;
978 break;
979 case AMDGPU::GK_GFX12_GENERIC:
980 Version = GenericVersion::GFX12;
981 break;
982 case AMDGPU::GK_GFX12_5_GENERIC:
983 Version = GenericVersion::GFX12_5;
984 break;
985 case AMDGPU::GK_GFX13_GENERIC:
986 Version = GenericVersion::GFX13;
987 break;
988 default:
989 break;
990 }
991 }
992
993 // Versions start at 1.
994 if (Version) {
995 if (Version > ELF::EF_AMDGPU_GENERIC_VERSION_MAX)
996 report_fatal_error("Cannot encode generic code object version " +
997 Twine(Version) +
998 " - no ELF flag can represent this version!");
999 Flags |= (Version << ELF::EF_AMDGPU_GENERIC_VERSION_OFFSET);
1000 }
1001
1002 return Flags;
1003}
1004
1005void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {}
1006
1007void AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(AMDGPUMCKernelCodeT &Header) {
1008 MCStreamer &OS = getStreamer();
1009 OS.pushSection();
1010 Header.EmitKernelCodeT(OS, getContext());
1011 OS.popSection();
1012}
1013
1014void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
1015 unsigned Type) {
1016 auto *Symbol = static_cast<MCSymbolELF *>(
1017 getStreamer().getContext().getOrCreateSymbol(SymbolName));
1018 Symbol->setType(Type);
1019}
1020
1021void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size,
1022 Align Alignment) {
1023 auto *SymbolELF = static_cast<MCSymbolELF *>(Symbol);
1024 SymbolELF->setType(ELF::STT_OBJECT);
1025
1026 if (!SymbolELF->isBindingSet())
1027 SymbolELF->setBinding(ELF::STB_GLOBAL);
1028
1029 if (SymbolELF->declareCommon(Size, Alignment)) {
1030 report_fatal_error("Symbol: " + Symbol->getName() +
1031 " redeclared as different type");
1032 }
1033
1034 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS);
1035 SymbolELF->setSize(MCConstantExpr::create(Size, getContext()));
1036}
1037
1038bool AMDGPUTargetELFStreamer::EmitISAVersion() {
1039 // Create two labels to mark the beginning and end of the desc field
1040 // and a MCExpr to calculate the size of the desc field.
1041 auto &Context = getContext();
1042 auto *DescBegin = Context.createTempSymbol();
1043 auto *DescEnd = Context.createTempSymbol();
1044 auto *DescSZ = MCBinaryExpr::createSub(
1045 MCSymbolRefExpr::create(DescEnd, Context),
1046 MCSymbolRefExpr::create(DescBegin, Context), Context);
1047
1048 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_ISA_NAME,
1049 [&](MCELFStreamer &OS) {
1050 OS.emitLabel(DescBegin);
1051
1052 SmallString<32> Str;
1053 raw_svector_ostream StrOS(Str);
1054 StrOS << *getTargetID();
1055
1056 OS.emitBytes(StrOS.str());
1057 OS.emitLabel(DescEnd);
1058 });
1059 return true;
1060}
1061
1062bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc,
1063 bool Strict) {
1064 HSAMD::V3::MetadataVerifier Verifier(Strict);
1065 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
1066 return false;
1067
1068 std::string HSAMetadataString;
1069 HSAMetadataDoc.writeToBlob(HSAMetadataString);
1070
1071 // Create two labels to mark the beginning and end of the desc field
1072 // and a MCExpr to calculate the size of the desc field.
1073 auto &Context = getContext();
1074 auto *DescBegin = Context.createTempSymbol();
1075 auto *DescEnd = Context.createTempSymbol();
1076 auto *DescSZ = MCBinaryExpr::createSub(
1077 MCSymbolRefExpr::create(DescEnd, Context),
1078 MCSymbolRefExpr::create(DescBegin, Context), Context);
1079
1080 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA,
1081 [&](MCELFStreamer &OS) {
1082 OS.emitLabel(DescBegin);
1083 OS.emitBytes(HSAMetadataString);
1084 OS.emitLabel(DescEnd);
1085 });
1086 return true;
1087}
1088
1089bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
1090 const uint32_t Encoded_s_code_end = 0xbf9f0000;
1091 const uint32_t Encoded_s_nop = 0xbf800000;
1092 uint32_t Encoded_pad = Encoded_s_code_end;
1093
1094 // Instruction cache line size in bytes.
1095 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
1096 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
1097
1098 // Extra padding amount in bytes to support prefetch mode 3.
1099 unsigned FillSize = 3 * CacheLineSize;
1100
1101 if (AMDGPU::isGFX90A(STI)) {
1102 Encoded_pad = Encoded_s_nop;
1103 FillSize = 16 * CacheLineSize;
1104 }
1105
1106 MCStreamer &OS = getStreamer();
1107 OS.pushSection();
1108 OS.emitValueToAlignment(Align(CacheLineSize), Encoded_pad, 4);
1109 for (unsigned I = 0; I < FillSize; I += 4)
1110 OS.emitInt32(Encoded_pad);
1111 OS.popSection();
1112 return true;
1113}
1114
1115void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor(
1116 const MCSubtargetInfo &STI, StringRef KernelName,
1117 const MCKernelDescriptor &KernelDescriptor, const MCExpr *NextVGPR,
1118 const MCExpr *NextSGPR, const MCExpr *ReserveVCC,
1119 const MCExpr *ReserveFlatScr) {
1120 auto &Streamer = getStreamer();
1121 auto &Context = Streamer.getContext();
1122
1123 auto *KernelCodeSymbol =
1124 static_cast<MCSymbolELF *>(Context.getOrCreateSymbol(Twine(KernelName)));
1125 auto *KernelDescriptorSymbol = static_cast<MCSymbolELF *>(
1126 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd")));
1127
1128 // Copy kernel descriptor symbol's binding, other and visibility from the
1129 // kernel code symbol.
1130 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding());
1131 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther());
1132 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility());
1133 // Kernel descriptor symbol's type and size are fixed.
1134 KernelDescriptorSymbol->setType(ELF::STT_OBJECT);
1135 KernelDescriptorSymbol->setSize(
1136 MCConstantExpr::create(sizeof(amdhsa::kernel_descriptor_t), Context));
1137
1138 // The visibility of the kernel code symbol must be protected or less to allow
1139 // static relocations from the kernel descriptor to be used.
1140 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT)
1141 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED);
1142
1143 Streamer.emitLabel(KernelDescriptorSymbol);
1144 Streamer.emitValue(
1145 KernelDescriptor.group_segment_fixed_size,
1146 sizeof(amdhsa::kernel_descriptor_t::group_segment_fixed_size));
1147 Streamer.emitValue(
1148 KernelDescriptor.private_segment_fixed_size,
1149 sizeof(amdhsa::kernel_descriptor_t::private_segment_fixed_size));
1150 Streamer.emitValue(KernelDescriptor.kernarg_size,
1151 sizeof(amdhsa::kernel_descriptor_t::kernarg_size));
1152
1153 for (uint32_t i = 0; i < sizeof(amdhsa::kernel_descriptor_t::reserved0); ++i)
1154 Streamer.emitInt8(0u);
1155
1156 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The
1157 // expression being created is:
1158 // (start of kernel code) - (start of kernel descriptor)
1159 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
1160 Streamer.emitValue(
1161 MCBinaryExpr::createSub(
1162 MCSymbolRefExpr::create(KernelCodeSymbol, AMDGPUMCExpr::S_REL64,
1163 Context),
1164 MCSymbolRefExpr::create(KernelDescriptorSymbol, Context), Context),
1165 sizeof(amdhsa::kernel_descriptor_t::kernel_code_entry_byte_offset));
1166 for (uint32_t i = 0; i < sizeof(amdhsa::kernel_descriptor_t::reserved1); ++i)
1167 Streamer.emitInt8(0u);
1168 Streamer.emitValue(KernelDescriptor.compute_pgm_rsrc3,
1169 sizeof(amdhsa::kernel_descriptor_t::compute_pgm_rsrc3));
1170 Streamer.emitValue(KernelDescriptor.compute_pgm_rsrc1,
1171 sizeof(amdhsa::kernel_descriptor_t::compute_pgm_rsrc1));
1172 Streamer.emitValue(KernelDescriptor.compute_pgm_rsrc2,
1173 sizeof(amdhsa::kernel_descriptor_t::compute_pgm_rsrc2));
1174 Streamer.emitValue(
1175 KernelDescriptor.kernel_code_properties,
1176 sizeof(amdhsa::kernel_descriptor_t::kernel_code_properties));
1177 Streamer.emitValue(KernelDescriptor.kernarg_preload,
1178 sizeof(amdhsa::kernel_descriptor_t::kernarg_preload));
1179 for (uint32_t i = 0; i < sizeof(amdhsa::kernel_descriptor_t::reserved3); ++i)
1180 Streamer.emitInt8(0u);
1181}
1182
1183void AMDGPUTargetELFStreamer::emitAMDGPUInfo(
1184 const AMDGPU::InfoSectionData &Data) {
1185 MCELFStreamer &S = getStreamer();
1186 MCContext &Context = S.getContext();
1187
1188 StringTableBuilder StrTab(StringTableBuilder::ELF);
1189 auto getOrAddString = [&](StringRef Str) -> uint32_t {
1190 if (Str.empty())
1191 return UINT32_MAX;
1192 return StrTab.add(Str);
1193 };
1194
1195 auto EmitU32Entry = [&](AMDGPU::InfoKind Kind, uint32_t Val) {
1196 S.emitInt8(static_cast<uint8_t>(Kind));
1197 S.emitInt8(4);
1198 S.emitInt32(Val);
1199 };
1200 auto EmitSymEntry = [&](AMDGPU::InfoKind Kind, MCSymbol *Sym) {
1201 S.emitInt8(static_cast<uint8_t>(Kind));
1202 S.emitInt8(8);
1203 S.emitValue(MCSymbolRefExpr::create(Sym, Context), 8);
1204 };
1205
1206 S.pushSection();
1207 MCSectionELF *InfoSec = Context.getELFSection(
1208 ".amdgpu.info", ELF::SHT_PROGBITS, ELF::SHF_EXCLUDE);
1209 S.switchSection(InfoSec);
1210
1211 forEachInfoScope(Data, [&](MCSymbol *Sym, const AMDGPU::FuncInfo *Info,
1212 ArrayRef<MCSymbol *> Uses,
1213 ArrayRef<MCSymbol *> Calls,
1214 ArrayRef<StringRef> IndirectCallTypeIds,
1215 ArrayRef<StringRef> TypeIds) {
1216 EmitSymEntry(AMDGPU::InfoKind::INFO_FUNC, Sym);
1217
1218 if (Info) {
1219 AMDGPU::FuncInfoFlags Flags{};
1220 if (Info->UsesVCC)
1221 Flags |= AMDGPU::FuncInfoFlags::FUNC_USES_VCC;
1222 if (Info->UsesFlatScratch)
1223 Flags |= AMDGPU::FuncInfoFlags::FUNC_USES_FLAT_SCRATCH;
1224 if (Info->HasDynStack)
1225 Flags |= AMDGPU::FuncInfoFlags::FUNC_HAS_DYN_STACK;
1226 EmitU32Entry(AMDGPU::InfoKind::INFO_FLAGS, llvm::to_underlying(Flags));
1227 EmitU32Entry(AMDGPU::InfoKind::INFO_NUM_SGPR, Info->NumSGPR);
1228 EmitU32Entry(AMDGPU::InfoKind::INFO_NUM_VGPR, Info->NumArchVGPR);
1229 // INFO_NUM_AGPR is only emitted when the function actually uses AGPRs,
1230 // since AGPRs are not available on all architectures.
1231 if (Info->NumAccVGPR)
1232 EmitU32Entry(AMDGPU::InfoKind::INFO_NUM_AGPR, Info->NumAccVGPR);
1233 EmitU32Entry(AMDGPU::InfoKind::INFO_PRIVATE_SEGMENT_SIZE,
1234 Info->PrivateSegmentSize);
1235 }
1236
1237 for (MCSymbol *Res : Uses)
1238 EmitSymEntry(AMDGPU::InfoKind::INFO_USE, Res);
1239 for (MCSymbol *Dst : Calls)
1240 EmitSymEntry(AMDGPU::InfoKind::INFO_CALL, Dst);
1241 for (StringRef TypeId : IndirectCallTypeIds) {
1242 EmitU32Entry(AMDGPU::InfoKind::INFO_INDIRECT_CALL,
1243 getOrAddString(TypeId));
1244 }
1245 for (StringRef TypeId : TypeIds)
1246 EmitU32Entry(AMDGPU::InfoKind::INFO_TYPEID, getOrAddString(TypeId));
1247 });
1248
1249 if (!StrTab.empty()) {
1250 StrTab.finalizeInOrder();
1251 MCSectionELF *Sec = Context.getELFSection(".amdgpu.strtab", ELF::SHT_STRTAB,
1252 ELF::SHF_EXCLUDE);
1253 S.switchSection(Sec);
1254 SmallString<128> Buf;
1255 raw_svector_ostream OS(Buf);
1256 StrTab.write(OS);
1257 S.emitBytes(Buf);
1258 }
1259
1260 S.popSection();
1261}
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
AMDGPUMCKernelDescriptor.h
AMDHSA kernel descriptor MCExpr struct for use in MC layer.
AMDGPUMCTargetDesc.h
Provides AMDGPU specific target descriptions.
AMDGPUMetadataVerifier.h
This is a verifier for AMDGPU HSA metadata, which can verify both well-typed metadata and untyped met...
AMDGPUMetadata.h
AMDGPU metadata definitions and in-memory representations.
AMDGPUObjLinkingInfo.h
Enums shared between the AMDGPU backend (LLVM) and the ELF linker (LLD) for the .amdgpu....
AMDGPUPTNote.h
Enums and constants for AMDGPU PT_NOTE sections.
ForceGenericVersion
static cl::opt< unsigned > ForceGenericVersion("amdgpu-force-generic-version", cl::desc("Force a specific generic_v<N> flag to be " "added. For testing purposes only."), cl::ReallyHidden, cl::init(0))
PRINT_RES_INFO
#define PRINT_RES_INFO(ARG)
AMDHSAKernelDescriptor.h
AMDHSA kernel descriptor definitions.
AMDKernelCodeTUtils.h
MC layer struct for AMDGPUMCKernelCodeT, provides MCExpr functionality where required.
I
#define I(x, y, z)
Definition MD5.cpp:57
Uses
Remove Loads Into Fake Uses
Definition RemoveLoadsIntoFakeUses.cpp:78
Verifier
verify safepoint Safepoint IR Verifier
Definition SafepointIRVerifier.cpp:246
CacheLineSize
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
llvm::AMDGPUPALMetadata::getVendor
const char * getVendor() const
Definition AMDGPUPALMetadata.cpp:1014
llvm::AMDGPUPALMetadata::toBlob
void toBlob(unsigned Type, std::string &S)
Definition AMDGPUPALMetadata.cpp:864
llvm::AMDGPUPALMetadata::toString
void toString(std::string &S)
Definition AMDGPUPALMetadata.cpp:811
llvm::AMDGPUTargetAsmStreamer::emitAMDGPUInfo
void emitAMDGPUInfo(const AMDGPU::InfoSectionData &Data) override
Definition AMDGPUTargetStreamer.cpp:738
llvm::AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer
AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
Definition AMDGPUTargetStreamer.cpp:244
llvm::AMDGPUTargetAsmStreamer::EmitHSAMetadata
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
Definition AMDGPUTargetStreamer.cpp:347
llvm::AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
Definition AMDGPUTargetStreamer.cpp:282
llvm::AMDGPUTargetAsmStreamer::EmitDirectiveAMDHSACodeObjectVersion
void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV) override
Definition AMDGPUTargetStreamer.cpp:265
llvm::AMDGPUTargetAsmStreamer::EmitMCResourceMaximums
void EmitMCResourceMaximums(const MCSymbol *MaxVGPR, const MCSymbol *MaxAGPR, const MCSymbol *MaxSGPR, const MCSymbol *MaxNamedBarrier) override
Definition AMDGPUTargetStreamer.cpp:325
llvm::AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT
void EmitAMDKernelCodeT(AMDGPU::AMDGPUMCKernelCodeT &Header) override
Definition AMDGPUTargetStreamer.cpp:271
llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const AMDGPU::MCKernelDescriptor &KernelDescriptor, const MCExpr *NextVGPR, const MCExpr *NextSGPR, const MCExpr *ReserveVCC, const MCExpr *ReserveFlatScr) override
Definition AMDGPUTargetStreamer.cpp:385
llvm::AMDGPUTargetAsmStreamer::EmitMCResourceInfo
void EmitMCResourceInfo(const MCSymbol *NumVGPR, const MCSymbol *NumAGPR, const MCSymbol *NumExplicitSGPR, const MCSymbol *NumNamedBarrier, const MCSymbol *PrivateSegmentSize, const MCSymbol *UsesVCC, const MCSymbol *UsesFlatScratch, const MCSymbol *HasDynamicallySizedStack, const MCSymbol *HasRecursion, const MCSymbol *HasIndirectCall) override
Definition AMDGPUTargetStreamer.cpp:299
llvm::AMDGPUTargetAsmStreamer::EmitCodeEnd
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
Definition AMDGPUTargetStreamer.cpp:363
llvm::AMDGPUTargetAsmStreamer::emitAMDGPULDS
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
Definition AMDGPUTargetStreamer.cpp:293
llvm::AMDGPUTargetELFStreamer::EmitCodeEnd
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
Definition AMDGPUTargetStreamer.cpp:1089
llvm::AMDGPUTargetELFStreamer::EmitAMDKernelCodeT
void EmitAMDKernelCodeT(AMDGPU::AMDGPUMCKernelCodeT &Header) override
Definition AMDGPUTargetStreamer.cpp:1007
llvm::AMDGPUTargetELFStreamer::EmitHSAMetadata
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
Definition AMDGPUTargetStreamer.cpp:1062
llvm::AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer
AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition AMDGPUTargetStreamer.cpp:778
llvm::AMDGPUTargetELFStreamer::emitAMDGPULDS
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
Definition AMDGPUTargetStreamer.cpp:1021
llvm::AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const AMDGPU::MCKernelDescriptor &KernelDescriptor, const MCExpr *NextVGPR, const MCExpr *NextSGPR, const MCExpr *ReserveVCC, const MCExpr *ReserveFlatScr) override
Definition AMDGPUTargetStreamer.cpp:1115
llvm::AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
Definition AMDGPUTargetStreamer.cpp:1014
llvm::AMDGPUTargetELFStreamer::emitAMDGPUInfo
void emitAMDGPUInfo(const AMDGPU::InfoSectionData &Data) override
Definition AMDGPUTargetStreamer.cpp:1183
llvm::AMDGPUTargetStreamer::EmitHSAMetadata
virtual bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict)
Emit HSA Metadata.
Definition AMDGPUTargetStreamer.h:112
llvm::AMDGPUTargetStreamer::getPALMetadata
AMDGPUPALMetadata * getPALMetadata()
Definition AMDGPUTargetStreamer.h:72
llvm::AMDGPUTargetStreamer::EmitDirectiveAMDHSACodeObjectVersion
virtual void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV)
Definition AMDGPUTargetStreamer.h:76
llvm::AMDGPUTargetStreamer::EmitHSAMetadataV3
virtual bool EmitHSAMetadataV3(StringRef HSAMetadataString)
Definition AMDGPUTargetStreamer.cpp:49
llvm::AMDGPUTargetStreamer::getElfMach
static unsigned getElfMach(StringRef GPU)
Definition AMDGPUTargetStreamer.cpp:149
llvm::AMDGPUTargetStreamer::getTargetID
const std::optional< AMDGPU::TargetID > & getTargetID() const
Definition AMDGPUTargetStreamer.h:136
llvm::AMDGPUTargetStreamer::getArchNameFromElfMach
static StringRef getArchNameFromElfMach(unsigned ElfMach)
Definition AMDGPUTargetStreamer.cpp:56
llvm::ArrayRef
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
llvm::DenseMapBase::find
iterator find(const_arg_type_t< KeyT > Val)
Definition DenseMap.h:225
llvm::DenseMapBase::end
iterator end()
Definition DenseMap.h:143
llvm::DenseSet
Implements a dense probed hash-table based set.
Definition DenseSet.h:289
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition MCAsmInfo.h:66
llvm::MCBinaryExpr::createAdd
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition MCExpr.h:342
llvm::MCBinaryExpr::createMul
static const MCBinaryExpr * createMul(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition MCExpr.h:397
llvm::MCBinaryExpr::createSub
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition MCExpr.h:427
llvm::MCConstantExpr::create
static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition MCExpr.cpp:212
llvm::MCContext
Context object for machine code objects.
Definition MCContext.h:83
llvm::MCContext::getOrCreateSymbol
LLVM_ABI MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition MCContext.cpp:208
llvm::MCContext::getAsmInfo
const MCAsmInfo & getAsmInfo() const
Definition MCContext.h:409
llvm::MCELFStreamer::getWriter
ELFObjectWriter & getWriter()
Definition MCELFStreamer.cpp:49
llvm::MCELFStreamer::emitLabel
void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc()) override
Emit a label for Symbol into the current section.
Definition MCELFStreamer.cpp:60
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition MCExpr.h:34
llvm::MCObjectStreamer::emitBytes
void emitBytes(StringRef Data) override
Emit the bytes in Data into the output.
Definition MCObjectStreamer.cpp:667
llvm::MCSectionELF
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition MCSectionELF.h:27
llvm::MCStreamer
Streaming machine code generation interface.
Definition MCStreamer.h:222
llvm::MCStreamer::popSection
virtual bool popSection()
Restore the current and previous section from the section stack.
Definition MCStreamer.cpp:1532
llvm::MCStreamer::getContext
MCContext & getContext() const
Definition MCStreamer.h:326
llvm::MCStreamer::emitValue
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition MCStreamer.cpp:176
llvm::MCStreamer::emitValueToAlignment
virtual void emitValueToAlignment(Align Alignment, int64_t Fill=0, uint8_t FillLen=1, unsigned MaxBytesToEmit=0)
Emit some number of copies of Value until the byte alignment ByteAlignment is reached.
Definition MCStreamer.cpp:1523
llvm::MCStreamer::pushSection
void pushSection()
Save the current and previous section on the section stack.
Definition MCStreamer.h:460
llvm::MCStreamer::switchSection
virtual void switchSection(MCSection *Section, uint32_t Subsec=0)
Set the current section where code is being emitted to Section.
Definition MCStreamer.cpp:1547
llvm::MCStreamer::emitInt32
void emitInt32(uint64_t Value)
Definition MCStreamer.h:767
llvm::MCStreamer::emitInt8
void emitInt8(uint64_t Value)
Definition MCStreamer.h:765
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:103
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition MCSubtargetInfo.h:148
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition MCSubtargetInfo.h:137
llvm::MCSubtargetInfo::getCPU
StringRef getCPU() const
Definition MCSubtargetInfo.h:138
llvm::MCSymbolELF::setBinding
LLVM_ABI void setBinding(unsigned Binding) const
Definition MCSymbolELF.cpp:43
llvm::MCSymbolELF::setType
LLVM_ABI void setType(unsigned Type) const
Definition MCSymbolELF.cpp:92
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition MCExpr.h:213
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition MCSymbol.h:42
llvm::MCSymbol::getName
StringRef getName() const
getName - Get the symbol name.
Definition MCSymbol.h:188
llvm::SmallString
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition SmallString.h:26
llvm::StringRef
Represent a constant reference to a string, i.e.
Definition StringRef.h:56
llvm::StringTableBuilder
Utility for building string tables with deduplicated suffixes.
Definition StringTableBuilder.h:25
llvm::StringTableBuilder::finalizeInOrder
LLVM_ABI void finalizeInOrder()
Finalize the string table without reording it.
Definition StringTableBuilder.cpp:134
llvm::StringTableBuilder::add
LLVM_ABI size_t add(CachedHashStringRef S, uint8_t Priority=0)
Add a string to the builder.
Definition StringTableBuilder.cpp:220
llvm::StringTableBuilder::write
LLVM_ABI void write(raw_ostream &OS) const
Definition StringTableBuilder.cpp:61
llvm::Triple::getArch
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition Triple.h:425
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition Twine.h:82
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:46
llvm::Value
LLVM Value Representation.
Definition Value.h:75
llvm::formatted_raw_ostream
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Definition FormattedStream.h:31
llvm::function_ref
An efficient, type-erasing, non-owning reference to a callable.
Definition STLFunctionalExtras.h:37
llvm::msgpack::Document
Simple in-memory representation of a document of msgpack objects with ability to find and create arra...
Definition MsgPackDocument.h:293
llvm::msgpack::Document::getRoot
DocNode & getRoot()
Get ref to the document's root element.
Definition MsgPackDocument.h:317
llvm::msgpack::Document::toYAML
LLVM_ABI void toYAML(raw_ostream &OS)
Convert MsgPack Document to YAML text.
Definition MsgPackDocumentYAML.cpp:247
llvm::msgpack::Document::writeToBlob
LLVM_ABI void writeToBlob(std::string &Blob)
Write a MsgPack document to a binary MsgPack blob.
Definition MsgPackDocument.cpp:355
llvm::msgpack::Document::fromYAML
LLVM_ABI bool fromYAML(StringRef S)
Read YAML text into the MsgPack document. Returns false on failure.
Definition MsgPackDocumentYAML.cpp:253
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition raw_ostream.h:664
llvm::raw_string_ostream::str
std::string & str()
Returns the string's reference.
Definition raw_ostream.h:682
llvm::raw_svector_ostream
A raw_ostream that writes to an SmallVector or SmallString.
Definition raw_ostream.h:694
llvm::raw_svector_ostream::str
StringRef str() const
Return a StringRef for the vector contents.
Definition raw_ostream.h:723
uint32_t
uint8_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::AMDGPU::ElfNote::NoteNameV2
const char NoteNameV2[]
Definition AMDGPUPTNote.h:26
llvm::AMDGPU::ElfNote::SectionName
const char SectionName[]
Definition AMDGPUPTNote.h:24
llvm::AMDGPU::ElfNote::NoteNameV3
const char NoteNameV3[]
Definition AMDGPUPTNote.h:27
llvm::AMDGPU::GenericVersion::GFX12_5
static constexpr unsigned GFX12_5
Definition AMDGPUBaseInfo.h:64
llvm::AMDGPU::GenericVersion::GFX9_4
static constexpr unsigned GFX9_4
Definition AMDGPUBaseInfo.h:58
llvm::AMDGPU::GenericVersion::GFX10_1
static constexpr unsigned GFX10_1
Definition AMDGPUBaseInfo.h:59
llvm::AMDGPU::GenericVersion::GFX10_3
static constexpr unsigned GFX10_3
Definition AMDGPUBaseInfo.h:60
llvm::AMDGPU::GenericVersion::GFX11
static constexpr unsigned GFX11
Definition AMDGPUBaseInfo.h:61
llvm::AMDGPU::GenericVersion::GFX9
static constexpr unsigned GFX9
Definition AMDGPUBaseInfo.h:57
llvm::AMDGPU::GenericVersion::GFX12
static constexpr unsigned GFX12
Definition AMDGPUBaseInfo.h:63
llvm::AMDGPU::GenericVersion::GFX13
static constexpr unsigned GFX13
Definition AMDGPUBaseInfo.h:65
llvm::AMDGPU::GenericVersion::GFX11_7
static constexpr unsigned GFX11_7
Definition AMDGPUBaseInfo.h:62
llvm::AMDGPU::HSAMD::V3::AssemblerDirectiveBegin
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
Definition AMDGPUMetadata.h:466
llvm::AMDGPU::HSAMD::V3::AssemblerDirectiveEnd
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
Definition AMDGPUMetadata.h:468
llvm::AMDGPU::getArchNameR600
LLVM_ABI StringRef getArchNameR600(GPUKind AK)
Definition AMDGPUTargetParser.cpp:48
llvm::AMDGPU::FuncInfoFlags
FuncInfoFlags
Per-function flags packed into INFO_FLAGS entries.
Definition AMDGPUObjLinkingInfo.h:64
llvm::AMDGPU::GPUKind
GPUKind
GPU kinds supported by the AMDGPU target.
Definition AMDGPUTargetParser.h:33
llvm::AMDGPU::printAMDGPUMCExpr
void printAMDGPUMCExpr(const MCExpr *Expr, raw_ostream &OS, const MCAsmInfo *MAI)
Definition AMDGPUMCExpr.cpp:750
llvm::AMDGPU::isHsaAbi
bool isHsaAbi(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:209
llvm::AMDGPU::getIsaVersion
LLVM_ABI IsaVersion getIsaVersion(StringRef GPU)
Definition AMDGPUTargetParser.cpp:116
llvm::AMDGPU::isGFX90A
bool isGFX90A(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2659
llvm::AMDGPU::parseArchAMDGCN
LLVM_ABI GPUKind parseArchAMDGCN(StringRef CPU)
Definition AMDGPUTargetParser.cpp:59
llvm::AMDGPU::hasArchitectedFlatScratch
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2667
llvm::AMDGPU::isGFX11Plus
bool isGFX11Plus(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2595
llvm::AMDGPU::foldAMDGPUMCExpr
const MCExpr * foldAMDGPUMCExpr(const MCExpr *Expr, MCContext &Ctx)
Definition AMDGPUMCExpr.cpp:741
llvm::AMDGPU::InfoKind
InfoKind
Entry kind values for the .amdgpu.info section.
Definition AMDGPUObjLinkingInfo.h:32
llvm::AMDGPU::InfoKind::INFO_INDIRECT_CALL
@ INFO_INDIRECT_CALL
Indirect call edge: the function contains an indirect call whose callee is expected to match the type...
Definition AMDGPUObjLinkingInfo.h:56
llvm::AMDGPU::InfoKind::INFO_FLAGS
@ INFO_FLAGS
Bitfield of FuncInfoFlags properties for the function. [u32].
Definition AMDGPUObjLinkingInfo.h:38
llvm::AMDGPU::InfoKind::INFO_FUNC
@ INFO_FUNC
Opens a new function scope.
Definition AMDGPUObjLinkingInfo.h:36
llvm::AMDGPU::InfoKind::INFO_NUM_SGPR
@ INFO_NUM_SGPR
Number of SGPRs explicitly used by the function. [u32].
Definition AMDGPUObjLinkingInfo.h:40
llvm::AMDGPU::InfoKind::INFO_NUM_VGPR
@ INFO_NUM_VGPR
Number of architectural VGPRs used by the function. [u32].
Definition AMDGPUObjLinkingInfo.h:42
llvm::AMDGPU::InfoKind::INFO_CALL
@ INFO_CALL
Direct call edge: the function calls the callee identified by the 8-byte relocated symbol.
Definition AMDGPUObjLinkingInfo.h:52
llvm::AMDGPU::InfoKind::INFO_NUM_AGPR
@ INFO_NUM_AGPR
Number of accumulator VGPRs (AGPRs) used by the function. [u32].
Definition AMDGPUObjLinkingInfo.h:44
llvm::AMDGPU::InfoKind::INFO_TYPEID
@ INFO_TYPEID
Function type ID: tags an address-taken function with a type-ID string (at the given ....
Definition AMDGPUObjLinkingInfo.h:60
llvm::AMDGPU::InfoKind::INFO_PRIVATE_SEGMENT_SIZE
@ INFO_PRIVATE_SEGMENT_SIZE
Private (scratch) memory size in bytes required by the function. [u32].
Definition AMDGPUObjLinkingInfo.h:46
llvm::AMDGPU::InfoKind::INFO_USE
@ INFO_USE
Dependency edge: the function uses the resource identified by the 8-byte relocated symbol (e....
Definition AMDGPUObjLinkingInfo.h:49
llvm::AMDGPU::getArchNameAMDGCN
LLVM_ABI StringRef getArchNameAMDGCN(GPUKind AK)
Definition AMDGPUTargetParser.cpp:37
llvm::AMDGPU::hasKernargPreload
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2683
llvm::AMDGPU::supportsWGP
bool supportsWGP(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2623
llvm::AMDGPU::isGFX1250Plus
bool isGFX1250Plus(const MCSubtargetInfo &STI)
Definition AMDGPUBaseInfo.cpp:2613
llvm::AMDGPU::getELFABIVersion
uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion)
Definition AMDGPUBaseInfo.cpp:239
llvm::AMDGPU::parseArchR600
LLVM_ABI GPUKind parseArchR600(StringRef CPU)
Definition AMDGPUTargetParser.cpp:69
llvm::ELF::NT_AMDGPU_METADATA
@ NT_AMDGPU_METADATA
Definition ELF.h:1994
llvm::ELF::SHN_AMDGPU_LDS
@ SHN_AMDGPU_LDS
Definition ELF.h:1977
llvm::ELF::SHF_EXCLUDE
@ SHF_EXCLUDE
Definition ELF.h:1290
llvm::ELF::SHF_ALLOC
@ SHF_ALLOC
Definition ELF.h:1256
llvm::ELF::SHT_STRTAB
@ SHT_STRTAB
Definition ELF.h:1157
llvm::ELF::SHT_PROGBITS
@ SHT_PROGBITS
Definition ELF.h:1155
llvm::ELF::SHT_NOTE
@ SHT_NOTE
Definition ELF.h:1161
llvm::ELF::STB_GLOBAL
@ STB_GLOBAL
Definition ELF.h:1413
llvm::ELF::STT_AMDGPU_HSA_KERNEL
@ STT_AMDGPU_HSA_KERNEL
Definition ELF.h:1438
llvm::ELF::STT_OBJECT
@ STT_OBJECT
Definition ELF.h:1425
llvm::ELF::EF_AMDGPU_GENERIC_VERSION_MAX
@ EF_AMDGPU_GENERIC_VERSION_MAX
Definition ELF.h:932
llvm::ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4
@ EF_AMDGPU_FEATURE_XNACK_ANY_V4
Definition ELF.h:909
llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_V3
@ EF_AMDGPU_FEATURE_SRAMECC_V3
Definition ELF.h:900
llvm::ELF::EF_AMDGPU_GENERIC_VERSION_OFFSET
@ EF_AMDGPU_GENERIC_VERSION_OFFSET
Definition ELF.h:930
llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4
@ EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4
Definition ELF.h:920
llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4
@ EF_AMDGPU_FEATURE_SRAMECC_OFF_V4
Definition ELF.h:924
llvm::ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4
@ EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4
Definition ELF.h:907
llvm::ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4
@ EF_AMDGPU_FEATURE_XNACK_OFF_V4
Definition ELF.h:911
llvm::ELF::EF_AMDGPU_FEATURE_XNACK_V3
@ EF_AMDGPU_FEATURE_XNACK_V3
Definition ELF.h:895
llvm::ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4
@ EF_AMDGPU_FEATURE_XNACK_ON_V4
Definition ELF.h:913
llvm::ELF::EF_AMDGPU_MACH_NONE
@ EF_AMDGPU_MACH_NONE
Definition ELF.h:854
llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4
@ EF_AMDGPU_FEATURE_SRAMECC_ANY_V4
Definition ELF.h:922
llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4
@ EF_AMDGPU_FEATURE_SRAMECC_ON_V4
Definition ELF.h:926
llvm::ELF::NT_AMD_HSA_ISA_NAME
@ NT_AMD_HSA_ISA_NAME
Definition ELF.h:1987
llvm::ELF::STV_PROTECTED
@ STV_PROTECTED
Definition ELF.h:1445
llvm::ELF::STV_DEFAULT
@ STV_DEFAULT
Definition ELF.h:1442
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition CommandLine.h:440
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::report_fatal_error
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
Definition Error.cpp:163
llvm::to_underlying
constexpr std::underlying_type_t< Enum > to_underlying(Enum E)
Returns underlying integer value of an enum.
Definition STLForwardCompat.h:198
llvm::AMDGPU::IsaVersion
Instruction set architecture version.
Definition AMDGPUTargetParser.h:46
llvm::AMDGPU::MCKernelDescriptor::bits_get
static const MCExpr * bits_get(const MCExpr *Src, uint32_t Shift, uint32_t Mask, MCContext &Ctx)
Definition AMDGPUMCKernelDescriptor.cpp:97
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
llvm::Align::value
constexpr uint64_t value() const
This is a hole in the type system and should not be abused.
Definition Alignment.h:77
llvm::amdhsa::kernel_descriptor_t
Definition AMDHSAKernelDescriptor.h:267
llvm::amdhsa::kernel_descriptor_t::group_segment_fixed_size
uint32_t group_segment_fixed_size
Definition AMDHSAKernelDescriptor.h:268
llvm::amdhsa::kernel_descriptor_t::reserved3
uint8_t reserved3[4]
Definition AMDHSAKernelDescriptor.h:279
llvm::amdhsa::kernel_descriptor_t::reserved1
uint8_t reserved1[20]
Definition AMDHSAKernelDescriptor.h:273
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc1
uint32_t compute_pgm_rsrc1
Definition AMDHSAKernelDescriptor.h:275
llvm::amdhsa::kernel_descriptor_t::private_segment_fixed_size
uint32_t private_segment_fixed_size
Definition AMDHSAKernelDescriptor.h:269
llvm::amdhsa::kernel_descriptor_t::kernarg_size
uint32_t kernarg_size
Definition AMDHSAKernelDescriptor.h:270
llvm::amdhsa::kernel_descriptor_t::kernarg_preload
uint16_t kernarg_preload
Definition AMDHSAKernelDescriptor.h:278
llvm::amdhsa::kernel_descriptor_t::reserved0
uint8_t reserved0[4]
Definition AMDHSAKernelDescriptor.h:271
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc2
uint32_t compute_pgm_rsrc2
Definition AMDHSAKernelDescriptor.h:276
llvm::amdhsa::kernel_descriptor_t::kernel_code_properties
uint16_t kernel_code_properties
Definition AMDHSAKernelDescriptor.h:277
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc3
uint32_t compute_pgm_rsrc3
Definition AMDHSAKernelDescriptor.h:274
llvm::amdhsa::kernel_descriptor_t::kernel_code_entry_byte_offset
int64_t kernel_code_entry_byte_offset
Definition AMDHSAKernelDescriptor.h:272
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