39 uint32_t &Stepping,
bool Sramecc,
bool Xnack) {
40 if (Major == 9 && Minor == 0) {
61 if (!HSAMetadataDoc.
fromYAML(HSAMetadataString))
238 OS <<
"\t.amdgcn_target \"" <<
getTargetID()->toString() <<
"\"\n";
243 OS <<
"\t.hsa_code_object_version " <<
254 OS <<
"\t.hsa_code_object_isa " <<
Twine(Major) <<
"," <<
Twine(Minor) <<
","
255 <<
Twine(Stepping) <<
",\"" << VendorName <<
"\",\"" << ArchName <<
"\"\n";
260 OS <<
"\t.amd_kernel_code_t\n";
262 OS <<
"\t.end_amd_kernel_code_t\n";
270 OS <<
"\t.amdgpu_hsa_kernel " << SymbolName <<
'\n' ;
277 OS <<
"\t.amdgpu_lds " << Symbol->getName() <<
", " <<
Size <<
", "
278 << Alignment.
value() <<
'\n';
282 OS <<
"\t.amd_amdgpu_isa \"" <<
getTargetID()->toString() <<
"\"\n";
288 std::string HSAMetadataString;
293 OS << HSAMetadataString <<
'\n';
304 std::string HSAMetadataString;
306 HSAMetadataDoc.
toYAML(StrOS);
309 OS << StrOS.
str() <<
'\n';
315 const uint32_t Encoded_s_code_end = 0xbf9f0000;
316 const uint32_t Encoded_s_nop = 0xbf800000;
317 uint32_t Encoded_pad = Encoded_s_code_end;
327 Encoded_pad = Encoded_s_nop;
331 OS <<
"\t.p2alignl " << Log2CacheLineSize <<
", " << Encoded_pad <<
'\n';
332 OS <<
"\t.fill " << (FillSize / 4) <<
", 4, " << Encoded_pad <<
'\n';
339 bool ReserveVCC,
bool ReserveFlatScr,
unsigned CodeObjectVersion) {
342 OS <<
"\t.amdhsa_kernel " << KernelName <<
'\n';
344#define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \
345 STREAM << "\t\t" << DIRECTIVE << " " \
346 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
350 OS <<
"\t\t.amdhsa_private_segment_fixed_size "
352 OS <<
"\t\t.amdhsa_kernarg_size " << KD.
kernarg_size <<
'\n';
356 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT);
360 OS,
".amdhsa_user_sgpr_private_segment_buffer", KD,
361 kernel_code_properties,
362 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
363 PRINT_FIELD(OS,
".amdhsa_user_sgpr_dispatch_ptr", KD,
364 kernel_code_properties,
365 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
367 kernel_code_properties,
368 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
369 PRINT_FIELD(OS,
".amdhsa_user_sgpr_kernarg_segment_ptr", KD,
370 kernel_code_properties,
371 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
372 PRINT_FIELD(OS,
".amdhsa_user_sgpr_dispatch_id", KD,
373 kernel_code_properties,
374 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
376 PRINT_FIELD(OS,
".amdhsa_user_sgpr_flat_scratch_init", KD,
377 kernel_code_properties,
378 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
380 PRINT_FIELD(OS,
".amdhsa_user_sgpr_kernarg_preload_length ", KD,
381 kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_LENGTH);
382 PRINT_FIELD(OS,
".amdhsa_user_sgpr_kernarg_preload_offset ", KD,
383 kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_OFFSET);
385 PRINT_FIELD(OS,
".amdhsa_user_sgpr_private_segment_size", KD,
386 kernel_code_properties,
387 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
388 if (IVersion.
Major >= 10)
390 kernel_code_properties,
391 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
393 PRINT_FIELD(OS,
".amdhsa_uses_dynamic_stack", KD, kernel_code_properties,
394 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK);
397 ?
".amdhsa_enable_private_segment"
398 :
".amdhsa_system_sgpr_private_segment_wavefront_offset"),
399 KD, compute_pgm_rsrc2,
400 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
401 PRINT_FIELD(OS,
".amdhsa_system_sgpr_workgroup_id_x", KD,
403 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
404 PRINT_FIELD(OS,
".amdhsa_system_sgpr_workgroup_id_y", KD,
406 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
407 PRINT_FIELD(OS,
".amdhsa_system_sgpr_workgroup_id_z", KD,
409 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
410 PRINT_FIELD(OS,
".amdhsa_system_sgpr_workgroup_info", KD,
412 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
413 PRINT_FIELD(OS,
".amdhsa_system_vgpr_workitem_id", KD,
415 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
418 OS <<
"\t\t.amdhsa_next_free_vgpr " << NextVGPR <<
'\n';
419 OS <<
"\t\t.amdhsa_next_free_sgpr " << NextSGPR <<
'\n';
422 OS <<
"\t\t.amdhsa_accum_offset " <<
424 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4
428 OS <<
"\t\t.amdhsa_reserve_vcc " << ReserveVCC <<
'\n';
430 OS <<
"\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr <<
'\n';
432 switch (CodeObjectVersion) {
438 OS <<
"\t\t.amdhsa_reserve_xnack_mask " <<
getTargetID()->isXnackOnOrAny() <<
'\n';
444 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
445 PRINT_FIELD(OS,
".amdhsa_float_round_mode_16_64", KD,
447 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
448 PRINT_FIELD(OS,
".amdhsa_float_denorm_mode_32", KD,
450 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
451 PRINT_FIELD(OS,
".amdhsa_float_denorm_mode_16_64", KD,
453 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
456 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
459 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
460 if (IVersion.
Major >= 9)
463 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL);
467 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT);
468 if (IVersion.
Major >= 10) {
469 PRINT_FIELD(OS,
".amdhsa_workgroup_processor_mode", KD,
471 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE);
474 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED);
477 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS);
478 PRINT_FIELD(OS,
".amdhsa_shared_vgpr_count", KD, compute_pgm_rsrc3,
479 amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT);
482 OS,
".amdhsa_exception_fp_ieee_invalid_op", KD,
484 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
485 PRINT_FIELD(OS,
".amdhsa_exception_fp_denorm_src", KD,
487 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
489 OS,
".amdhsa_exception_fp_ieee_div_zero", KD,
491 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
492 PRINT_FIELD(OS,
".amdhsa_exception_fp_ieee_overflow", KD,
494 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
495 PRINT_FIELD(OS,
".amdhsa_exception_fp_ieee_underflow", KD,
497 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
498 PRINT_FIELD(OS,
".amdhsa_exception_fp_ieee_inexact", KD,
500 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
501 PRINT_FIELD(OS,
".amdhsa_exception_int_div_zero", KD,
503 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
506 OS <<
"\t.end_amdhsa_kernel\n";
542void AMDGPUTargetELFStreamer::EmitNote(
546 auto &
Context = S.getContext();
548 auto NameSZ =
Name.size() + 1;
550 unsigned NoteFlags = 0;
560 S.emitValue(DescSZ, 4);
561 S.emitInt32(NoteType);
563 S.emitValueToAlignment(
Align(4), 0, 1, 0);
565 S.emitValueToAlignment(
Align(4), 0, 1, 0);
569unsigned AMDGPUTargetELFStreamer::getEFlags() {
574 return getEFlagsR600();
576 return getEFlagsAMDGCN();
580unsigned AMDGPUTargetELFStreamer::getEFlagsR600() {
586unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() {
594 return getEFlagsUnknownOS();
596 return getEFlagsAMDHSA();
598 return getEFlagsAMDPAL();
600 return getEFlagsMesa3D();
604unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() {
608 return getEFlagsV3();
611unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() {
615 switch (*HsaAbiVer) {
617 return getEFlagsV3();
620 return getEFlagsV4();
627unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() {
630 return getEFlagsV3();
633unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() {
636 return getEFlagsV3();
639unsigned AMDGPUTargetELFStreamer::getEFlagsV3() {
640 unsigned EFlagsV3 = 0;
655unsigned AMDGPUTargetELFStreamer::getEFlagsV4() {
656 unsigned EFlagsV4 = 0;
716 unsigned DescSZ =
sizeof(VendorNameSize) +
sizeof(ArchNameSize) +
717 sizeof(Major) +
sizeof(Minor) +
sizeof(Stepping) +
718 VendorNameSize + ArchNameSize;
723 OS.emitInt16(VendorNameSize);
724 OS.emitInt16(ArchNameSize);
727 OS.emitInt32(Stepping);
728 OS.emitBytes(VendorName);
730 OS.emitBytes(ArchName);
740 OS.emitBytes(
StringRef((
const char*)&Header,
sizeof(Header)));
748 Symbol->setType(
Type);
753 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol);
763 " redeclared as different type");
774 auto *DescBegin =
Context.createTempSymbol();
775 auto *DescEnd =
Context.createTempSymbol();
782 OS.emitLabel(DescBegin);
784 OS.emitLabel(DescEnd);
795 std::string HSAMetadataString;
801 auto *DescBegin =
Context.createTempSymbol();
802 auto *DescEnd =
Context.createTempSymbol();
809 OS.emitLabel(DescBegin);
810 OS.emitBytes(HSAMetadataString);
811 OS.emitLabel(DescEnd);
818 std::string HSAMetadataString;
825 auto *DescBegin =
Context.createTempSymbol();
826 auto *DescEnd =
Context.createTempSymbol();
833 OS.emitLabel(DescBegin);
834 OS.emitBytes(HSAMetadataString);
835 OS.emitLabel(DescEnd);
842 for (
int i = 0; i < 64; ++i) {
850 const uint32_t Encoded_s_nop = 0xbf800000;
852 for (
int i = 0; i < 64; ++i) {
853 OS.emitInt32(Encoded_s_nop);
859 const uint32_t Encoded_s_code_end = 0xbf9f0000;
860 const uint32_t Encoded_s_nop = 0xbf800000;
861 uint32_t Encoded_pad = Encoded_s_code_end;
871 Encoded_pad = Encoded_s_nop;
878 for (
unsigned I = 0;
I < FillSize;
I += 4)
879 OS.emitInt32(Encoded_pad);
887 uint64_t NextSGPR,
bool ReserveVCC,
bool ReserveFlatScr,
888 unsigned CodeObjectVersion) {
894 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
904 KernelDescriptorSymbol->
setSize(
912 Streamer.
emitLabel(KernelDescriptorSymbol);
917 for (uint8_t Res : KernelDescriptor.
reserved0)
931 for (uint8_t Res : KernelDescriptor.
reserved1)
938 for (uint8_t Res : KernelDescriptor.
reserved3)
Enums and constants for AMDGPU PT_NOTE sections.
#define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME)
static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor, uint32_t &Stepping, bool Sramecc, bool Xnack)
AMDHSA kernel descriptor definitions.
#define AMDHSA_BITS_GET(SRC, MSK)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
verify safepoint Safepoint IR Verifier
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, unsigned CodeObjectVersion) override
AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI) override
bool EmitISAVersion() override
void EmitDirectiveAMDGCNTarget() override
void EmitDirectiveHSACodeObjectISAV2(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName) override
void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor) override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
void EmitDirectiveAMDGCNTarget() override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor) override
AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI) override
void EmitDirectiveHSACodeObjectISAV2(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName) override
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
MCELFStreamer & getStreamer()
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, unsigned CodeObjectVersion) override
bool EmitISAVersion() override
virtual bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict)
Emit HSA Metadata.
AMDGPUPALMetadata * getPALMetadata()
virtual bool EmitHSAMetadataV3(StringRef HSAMetadataString)
static unsigned getElfMach(StringRef GPU)
MCContext & getContext() const
static StringRef getArchNameFromElfMach(unsigned ElfMach)
const std::optional< AMDGPU::IsaInfo::AMDGPUTargetID > & getTargetID() const
std::optional< AMDGPU::IsaInfo::AMDGPUTargetID > TargetID
virtual bool EmitHSAMetadataV2(StringRef HSAMetadataString)
void setELFHeaderEFlags(unsigned Flags)
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Base class for the full range of assembler expressions which are needed for parsing.
MCAssembler & getAssembler()
Streaming machine code generation interface.
MCContext & getContext() const
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
void emitInt16(uint64_t Value)
void emitInt32(uint64_t Value)
void emitInt8(uint64_t Value)
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
unsigned getOther() const
void setVisibility(unsigned Visibility)
void setSize(const MCExpr *SS)
bool isBindingSet() const
void setBinding(unsigned Binding) const
unsigned getVisibility() const
unsigned getBinding() const
void setType(unsigned Type) const
void setOther(unsigned Other)
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
void setExternal(bool Value) const
void setIndex(uint32_t Value) const
Set the (implementation defined) index.
bool declareCommon(uint64_t Size, Align Alignment, bool Target=false)
Declare this symbol as being 'common'.
StringRef - Represent a constant reference to a string, i.e.
constexpr size_t size() const
size - Get the string size.
OSType getOS() const
Get the parsed operating system type of this triple.
ArchType getArch() const
Get the parsed architecture type of this triple.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
An efficient, type-erasing, non-owning reference to a callable.
Simple in-memory representation of a document of msgpack objects with ability to find and create arra...
DocNode & getRoot()
Get ref to the document's root element.
void toYAML(raw_ostream &OS)
Convert MsgPack Document to YAML text.
void writeToBlob(std::string &Blob)
Write a MsgPack document to a binary MsgPack blob.
bool fromYAML(StringRef S)
Read YAML text into the MsgPack document. Returns false on failure.
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
std::error_code fromString(StringRef String, Metadata &HSAMetadata)
Converts String to HSAMetadata.
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
std::error_code toString(Metadata HSAMetadata, std::string &String)
Converts HSAMetadata to String.
StringRef getArchNameR600(GPUKind AK)
GPUKind
GPU kinds supported by the AMDGPU target.
bool isHsaAbi(const MCSubtargetInfo &STI)
IsaVersion getIsaVersion(StringRef GPU)
bool isGFX90A(const MCSubtargetInfo &STI)
GPUKind parseArchAMDGCN(StringRef CPU)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
StringRef getArchNameAMDGCN(GPUKind AK)
std::optional< uint8_t > getHsaAbiVersion(const MCSubtargetInfo *STI)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
GPUKind parseArchR600(StringRef CPU)
@ ELFABIVERSION_AMDGPU_HSA_V4
@ ELFABIVERSION_AMDGPU_HSA_V5
@ ELFABIVERSION_AMDGPU_HSA_V3
@ NT_AMD_HSA_CODE_OBJECT_VERSION
@ EF_AMDGPU_FEATURE_XNACK_ANY_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX703
@ EF_AMDGPU_MACH_AMDGCN_GFX1035
@ EF_AMDGPU_FEATURE_SRAMECC_V3
@ EF_AMDGPU_MACH_AMDGCN_GFX1031
@ EF_AMDGPU_MACH_R600_CAYMAN
@ EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX704
@ EF_AMDGPU_MACH_AMDGCN_GFX902
@ EF_AMDGPU_MACH_AMDGCN_GFX810
@ EF_AMDGPU_MACH_AMDGCN_GFX1036
@ EF_AMDGPU_MACH_AMDGCN_GFX1102
@ EF_AMDGPU_MACH_R600_RV730
@ EF_AMDGPU_MACH_R600_RV710
@ EF_AMDGPU_MACH_AMDGCN_GFX908
@ EF_AMDGPU_MACH_AMDGCN_GFX1011
@ EF_AMDGPU_MACH_R600_CYPRESS
@ EF_AMDGPU_MACH_AMDGCN_GFX1032
@ EF_AMDGPU_MACH_R600_R600
@ EF_AMDGPU_MACH_AMDGCN_GFX940
@ EF_AMDGPU_MACH_AMDGCN_GFX941
@ EF_AMDGPU_MACH_R600_TURKS
@ EF_AMDGPU_MACH_R600_JUNIPER
@ EF_AMDGPU_FEATURE_SRAMECC_OFF_V4
@ EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX601
@ EF_AMDGPU_MACH_AMDGCN_GFX942
@ EF_AMDGPU_MACH_R600_R630
@ EF_AMDGPU_MACH_R600_REDWOOD
@ EF_AMDGPU_MACH_R600_RV770
@ EF_AMDGPU_FEATURE_XNACK_OFF_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX600
@ EF_AMDGPU_FEATURE_XNACK_V3
@ EF_AMDGPU_MACH_AMDGCN_GFX602
@ EF_AMDGPU_MACH_AMDGCN_GFX1101
@ EF_AMDGPU_MACH_AMDGCN_GFX1100
@ EF_AMDGPU_MACH_AMDGCN_GFX1033
@ EF_AMDGPU_MACH_AMDGCN_GFX801
@ EF_AMDGPU_MACH_AMDGCN_GFX705
@ EF_AMDGPU_MACH_AMDGCN_GFX1010
@ EF_AMDGPU_MACH_R600_RV670
@ EF_AMDGPU_MACH_AMDGCN_GFX701
@ EF_AMDGPU_MACH_AMDGCN_GFX1012
@ EF_AMDGPU_MACH_AMDGCN_GFX1151
@ EF_AMDGPU_MACH_AMDGCN_GFX1030
@ EF_AMDGPU_MACH_R600_CEDAR
@ EF_AMDGPU_MACH_AMDGCN_GFX1200
@ EF_AMDGPU_MACH_AMDGCN_GFX700
@ EF_AMDGPU_MACH_AMDGCN_GFX803
@ EF_AMDGPU_MACH_AMDGCN_GFX802
@ EF_AMDGPU_MACH_AMDGCN_GFX90C
@ EF_AMDGPU_FEATURE_XNACK_ON_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX900
@ EF_AMDGPU_MACH_AMDGCN_GFX909
@ EF_AMDGPU_MACH_AMDGCN_GFX906
@ EF_AMDGPU_MACH_AMDGCN_GFX1103
@ EF_AMDGPU_MACH_R600_CAICOS
@ EF_AMDGPU_MACH_AMDGCN_GFX90A
@ EF_AMDGPU_MACH_AMDGCN_GFX1034
@ EF_AMDGPU_MACH_AMDGCN_GFX1013
@ EF_AMDGPU_MACH_AMDGCN_GFX904
@ EF_AMDGPU_MACH_R600_RS880
@ EF_AMDGPU_MACH_AMDGCN_GFX805
@ EF_AMDGPU_MACH_AMDGCN_GFX1201
@ EF_AMDGPU_MACH_AMDGCN_GFX1150
@ EF_AMDGPU_MACH_R600_SUMO
@ EF_AMDGPU_MACH_R600_BARTS
@ EF_AMDGPU_FEATURE_SRAMECC_ANY_V4
@ EF_AMDGPU_FEATURE_SRAMECC_ON_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX702
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
This is an optimization pass for GlobalISel generic memory operations.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
void dumpAmdKernelCode(const amd_kernel_code_t *C, raw_ostream &OS, const char *tab)
AMD Kernel Code Object (amd_kernel_code_t).
Instruction set architecture version.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
uint32_t group_segment_fixed_size
uint32_t compute_pgm_rsrc1
uint32_t private_segment_fixed_size
uint32_t compute_pgm_rsrc2
uint16_t kernel_code_properties
uint32_t compute_pgm_rsrc3
int64_t kernel_code_entry_byte_offset