42 cl::desc(
"Force a specific generic_v<N> flag to be "
43 "added. For testing purposes only."),
48 if (!HSAMetadataDoc.
fromYAML(HSAMetadataString))
233 OS <<
"\t.amdgcn_target \"" <<
getTargetID()->toString() <<
"\"\n";
239 OS <<
"\t.amdhsa_code_object_version " << COV <<
'\n';
244 OS <<
"\t.amd_kernel_code_t\n";
246 OS <<
"\t.end_amd_kernel_code_t\n";
254 OS <<
"\t.amdgpu_hsa_kernel " << SymbolName <<
'\n' ;
261 OS <<
"\t.amdgpu_lds " << Symbol->getName() <<
", " <<
Size <<
", "
262 << Alignment.
value() <<
'\n';
266 OS <<
"\t.amd_amdgpu_isa \"" <<
getTargetID()->toString() <<
"\"\n";
276 std::string HSAMetadataString;
278 HSAMetadataDoc.
toYAML(StrOS);
281 OS << StrOS.
str() <<
'\n';
287 const uint32_t Encoded_s_code_end = 0xbf9f0000;
288 const uint32_t Encoded_s_nop = 0xbf800000;
289 uint32_t Encoded_pad = Encoded_s_code_end;
299 Encoded_pad = Encoded_s_nop;
303 OS <<
"\t.p2alignl " << Log2CacheLineSize <<
", " << Encoded_pad <<
'\n';
304 OS <<
"\t.fill " << (FillSize / 4) <<
", 4, " << Encoded_pad <<
'\n';
311 bool ReserveVCC,
bool ReserveFlatScr) {
314 OS <<
"\t.amdhsa_kernel " << KernelName <<
'\n';
316#define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \
317 STREAM << "\t\t" << DIRECTIVE << " " \
318 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
322 OS <<
"\t\t.amdhsa_private_segment_fixed_size "
324 OS <<
"\t\t.amdhsa_kernarg_size " << KD.
kernarg_size <<
'\n';
328 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT);
332 OS,
".amdhsa_user_sgpr_private_segment_buffer", KD,
333 kernel_code_properties,
334 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
335 PRINT_FIELD(OS,
".amdhsa_user_sgpr_dispatch_ptr", KD,
336 kernel_code_properties,
337 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
339 kernel_code_properties,
340 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
341 PRINT_FIELD(OS,
".amdhsa_user_sgpr_kernarg_segment_ptr", KD,
342 kernel_code_properties,
343 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
344 PRINT_FIELD(OS,
".amdhsa_user_sgpr_dispatch_id", KD,
345 kernel_code_properties,
346 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
348 PRINT_FIELD(OS,
".amdhsa_user_sgpr_flat_scratch_init", KD,
349 kernel_code_properties,
350 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
352 PRINT_FIELD(OS,
".amdhsa_user_sgpr_kernarg_preload_length ", KD,
353 kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_LENGTH);
354 PRINT_FIELD(OS,
".amdhsa_user_sgpr_kernarg_preload_offset ", KD,
355 kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_OFFSET);
357 PRINT_FIELD(OS,
".amdhsa_user_sgpr_private_segment_size", KD,
358 kernel_code_properties,
359 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
360 if (IVersion.
Major >= 10)
362 kernel_code_properties,
363 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
365 PRINT_FIELD(OS,
".amdhsa_uses_dynamic_stack", KD, kernel_code_properties,
366 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK);
369 ?
".amdhsa_enable_private_segment"
370 :
".amdhsa_system_sgpr_private_segment_wavefront_offset"),
371 KD, compute_pgm_rsrc2,
372 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
373 PRINT_FIELD(OS,
".amdhsa_system_sgpr_workgroup_id_x", KD,
375 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
376 PRINT_FIELD(OS,
".amdhsa_system_sgpr_workgroup_id_y", KD,
378 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
379 PRINT_FIELD(OS,
".amdhsa_system_sgpr_workgroup_id_z", KD,
381 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
382 PRINT_FIELD(OS,
".amdhsa_system_sgpr_workgroup_info", KD,
384 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
385 PRINT_FIELD(OS,
".amdhsa_system_vgpr_workitem_id", KD,
387 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
390 OS <<
"\t\t.amdhsa_next_free_vgpr " << NextVGPR <<
'\n';
391 OS <<
"\t\t.amdhsa_next_free_sgpr " << NextSGPR <<
'\n';
394 OS <<
"\t\t.amdhsa_accum_offset " <<
396 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4
400 OS <<
"\t\t.amdhsa_reserve_vcc " << ReserveVCC <<
'\n';
402 OS <<
"\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr <<
'\n';
410 OS <<
"\t\t.amdhsa_reserve_xnack_mask " <<
getTargetID()->isXnackOnOrAny() <<
'\n';
416 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
417 PRINT_FIELD(OS,
".amdhsa_float_round_mode_16_64", KD,
419 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
420 PRINT_FIELD(OS,
".amdhsa_float_denorm_mode_32", KD,
422 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
423 PRINT_FIELD(OS,
".amdhsa_float_denorm_mode_16_64", KD,
425 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
426 if (IVersion.
Major < 12) {
427 PRINT_FIELD(OS,
".amdhsa_dx10_clamp", KD, compute_pgm_rsrc1,
428 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP);
429 PRINT_FIELD(OS,
".amdhsa_ieee_mode", KD, compute_pgm_rsrc1,
430 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE);
432 if (IVersion.
Major >= 9)
435 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL);
439 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT);
440 if (IVersion.
Major >= 10) {
441 PRINT_FIELD(OS,
".amdhsa_workgroup_processor_mode", KD,
443 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE);
446 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED);
449 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS);
451 if (IVersion.
Major >= 10 && IVersion.
Major < 12) {
452 PRINT_FIELD(OS,
".amdhsa_shared_vgpr_count", KD, compute_pgm_rsrc3,
453 amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT);
455 if (IVersion.
Major >= 12)
456 PRINT_FIELD(OS,
".amdhsa_round_robin_scheduling", KD, compute_pgm_rsrc1,
457 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN);
459 OS,
".amdhsa_exception_fp_ieee_invalid_op", KD,
461 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
462 PRINT_FIELD(OS,
".amdhsa_exception_fp_denorm_src", KD,
464 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
466 OS,
".amdhsa_exception_fp_ieee_div_zero", KD,
468 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
469 PRINT_FIELD(OS,
".amdhsa_exception_fp_ieee_overflow", KD,
471 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
472 PRINT_FIELD(OS,
".amdhsa_exception_fp_ieee_underflow", KD,
474 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
475 PRINT_FIELD(OS,
".amdhsa_exception_fp_ieee_inexact", KD,
477 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
478 PRINT_FIELD(OS,
".amdhsa_exception_int_div_zero", KD,
480 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
483 OS <<
"\t.end_amdhsa_kernel\n";
521void AMDGPUTargetELFStreamer::EmitNote(
525 auto &
Context = S.getContext();
527 auto NameSZ =
Name.size() + 1;
529 unsigned NoteFlags = 0;
539 S.emitValue(DescSZ, 4);
540 S.emitInt32(NoteType);
542 S.emitValueToAlignment(
Align(4), 0, 1, 0);
544 S.emitValueToAlignment(
Align(4), 0, 1, 0);
548unsigned AMDGPUTargetELFStreamer::getEFlags() {
553 return getEFlagsR600();
555 return getEFlagsAMDGCN();
559unsigned AMDGPUTargetELFStreamer::getEFlagsR600() {
565unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() {
573 return getEFlagsUnknownOS();
575 return getEFlagsAMDHSA();
577 return getEFlagsAMDPAL();
579 return getEFlagsMesa3D();
583unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() {
587 return getEFlagsV3();
590unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() {
594 return getEFlagsV6();
595 return getEFlagsV4();
598unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() {
601 return getEFlagsV3();
604unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() {
607 return getEFlagsV3();
610unsigned AMDGPUTargetELFStreamer::getEFlagsV3() {
611 unsigned EFlagsV3 = 0;
626unsigned AMDGPUTargetELFStreamer::getEFlagsV4() {
627 unsigned EFlagsV4 = 0;
666unsigned AMDGPUTargetELFStreamer::getEFlagsV6() {
667 unsigned Flags = getEFlagsV4();
694 " - no ELF flag can represent this version!");
708 OS.emitBytes(
StringRef((
const char*)&Header,
sizeof(Header)));
716 Symbol->setType(
Type);
721 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol);
731 " redeclared as different type");
742 auto *DescBegin =
Context.createTempSymbol();
743 auto *DescEnd =
Context.createTempSymbol();
750 OS.emitLabel(DescBegin);
752 OS.emitLabel(DescEnd);
763 std::string HSAMetadataString;
769 auto *DescBegin =
Context.createTempSymbol();
770 auto *DescEnd =
Context.createTempSymbol();
777 OS.emitLabel(DescBegin);
778 OS.emitBytes(HSAMetadataString);
779 OS.emitLabel(DescEnd);
786 const char *TrapInstr = TrapEnabled ?
"\ts_trap 2" :
"\ts_endpgm";
788 <<
" ; Trap with incompatible firmware that doesn't "
789 "support preloading kernel arguments.\n";
790 for (
int i = 0; i < 63; ++i) {
798 const uint32_t Encoded_s_nop = 0xbf800000;
799 const uint32_t Encoded_s_trap = 0xbf920002;
800 const uint32_t Encoded_s_endpgm = 0xbf810000;
801 const uint32_t TrapInstr = TrapEnabled ? Encoded_s_trap : Encoded_s_endpgm;
803 OS.emitInt32(TrapInstr);
804 for (
int i = 0; i < 63; ++i) {
805 OS.emitInt32(Encoded_s_nop);
811 const uint32_t Encoded_s_code_end = 0xbf9f0000;
812 const uint32_t Encoded_s_nop = 0xbf800000;
813 uint32_t Encoded_pad = Encoded_s_code_end;
823 Encoded_pad = Encoded_s_nop;
830 for (
unsigned I = 0;
I < FillSize;
I += 4)
831 OS.emitInt32(Encoded_pad);
839 uint64_t NextSGPR,
bool ReserveVCC,
bool ReserveFlatScr) {
845 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
855 KernelDescriptorSymbol->
setSize(
863 Streamer.
emitLabel(KernelDescriptorSymbol);
868 for (uint8_t Res : KernelDescriptor.
reserved0)
882 for (uint8_t Res : KernelDescriptor.
reserved1)
889 for (uint8_t Res : KernelDescriptor.
reserved3)
Enums and constants for AMDGPU PT_NOTE sections.
static cl::opt< unsigned > ForceGenericVersion("amdgpu-force-generic-version", cl::desc("Force a specific generic_v<N> flag to be " "added. For testing purposes only."), cl::ReallyHidden, cl::init(0))
#define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME)
AMDHSA kernel descriptor definitions.
#define AMDHSA_BITS_GET(SRC, MSK)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
verify safepoint Safepoint IR Verifier
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
bool EmitISAVersion() override
void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV) override
void EmitDirectiveAMDGCNTarget() override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) override
bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI, bool TrapEnabled) override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
void EmitDirectiveAMDGCNTarget() override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
MCELFStreamer & getStreamer()
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI, bool TrapEnabled) override
bool EmitISAVersion() override
virtual bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict)
Emit HSA Metadata.
AMDGPUPALMetadata * getPALMetadata()
virtual void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV)
virtual bool EmitHSAMetadataV3(StringRef HSAMetadataString)
static unsigned getElfMach(StringRef GPU)
MCContext & getContext() const
static StringRef getArchNameFromElfMach(unsigned ElfMach)
const std::optional< AMDGPU::IsaInfo::AMDGPUTargetID > & getTargetID() const
unsigned CodeObjectVersion
MCObjectWriter & getWriter() const
void setELFHeaderEFlags(unsigned Flags)
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Base class for the full range of assembler expressions which are needed for parsing.
MCAssembler & getAssembler()
virtual void setOverrideABIVersion(uint8_t ABIVersion)
ELF only, override the default ABIVersion in the ELF header.
Streaming machine code generation interface.
MCContext & getContext() const
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
void emitInt16(uint64_t Value)
void emitInt32(uint64_t Value)
void emitInt8(uint64_t Value)
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
unsigned getOther() const
void setVisibility(unsigned Visibility)
void setSize(const MCExpr *SS)
bool isBindingSet() const
void setBinding(unsigned Binding) const
unsigned getVisibility() const
unsigned getBinding() const
void setType(unsigned Type) const
void setOther(unsigned Other)
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
void setExternal(bool Value) const
void setIndex(uint32_t Value) const
Set the (implementation defined) index.
bool declareCommon(uint64_t Size, Align Alignment, bool Target=false)
Declare this symbol as being 'common'.
StringRef - Represent a constant reference to a string, i.e.
OSType getOS() const
Get the parsed operating system type of this triple.
ArchType getArch() const
Get the parsed architecture type of this triple.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
An efficient, type-erasing, non-owning reference to a callable.
Simple in-memory representation of a document of msgpack objects with ability to find and create arra...
DocNode & getRoot()
Get ref to the document's root element.
void toYAML(raw_ostream &OS)
Convert MsgPack Document to YAML text.
void writeToBlob(std::string &Blob)
Write a MsgPack document to a binary MsgPack blob.
bool fromYAML(StringRef S)
Read YAML text into the MsgPack document. Returns false on failure.
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static constexpr unsigned GFX10_1
static constexpr unsigned GFX10_3
static constexpr unsigned GFX11
static constexpr unsigned GFX9
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
StringRef getArchNameR600(GPUKind AK)
GPUKind
GPU kinds supported by the AMDGPU target.
bool isHsaAbi(const MCSubtargetInfo &STI)
IsaVersion getIsaVersion(StringRef GPU)
bool isGFX90A(const MCSubtargetInfo &STI)
GPUKind parseArchAMDGCN(StringRef CPU)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
StringRef getArchNameAMDGCN(GPUKind AK)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion)
GPUKind parseArchR600(StringRef CPU)
@ EF_AMDGPU_GENERIC_VERSION_MAX
@ EF_AMDGPU_FEATURE_XNACK_ANY_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX703
@ EF_AMDGPU_MACH_AMDGCN_GFX1035
@ EF_AMDGPU_FEATURE_SRAMECC_V3
@ EF_AMDGPU_MACH_AMDGCN_GFX1031
@ EF_AMDGPU_GENERIC_VERSION_OFFSET
@ EF_AMDGPU_MACH_R600_CAYMAN
@ EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX704
@ EF_AMDGPU_MACH_AMDGCN_GFX902
@ EF_AMDGPU_MACH_AMDGCN_GFX810
@ EF_AMDGPU_MACH_AMDGCN_GFX1036
@ EF_AMDGPU_MACH_AMDGCN_GFX1102
@ EF_AMDGPU_MACH_R600_RV730
@ EF_AMDGPU_MACH_R600_RV710
@ EF_AMDGPU_MACH_AMDGCN_GFX908
@ EF_AMDGPU_MACH_AMDGCN_GFX1011
@ EF_AMDGPU_MACH_R600_CYPRESS
@ EF_AMDGPU_MACH_AMDGCN_GFX1032
@ EF_AMDGPU_MACH_R600_R600
@ EF_AMDGPU_MACH_AMDGCN_GFX940
@ EF_AMDGPU_MACH_AMDGCN_GFX941
@ EF_AMDGPU_MACH_R600_TURKS
@ EF_AMDGPU_MACH_R600_JUNIPER
@ EF_AMDGPU_FEATURE_SRAMECC_OFF_V4
@ EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX601
@ EF_AMDGPU_MACH_AMDGCN_GFX942
@ EF_AMDGPU_MACH_R600_R630
@ EF_AMDGPU_MACH_R600_REDWOOD
@ EF_AMDGPU_MACH_R600_RV770
@ EF_AMDGPU_FEATURE_XNACK_OFF_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX600
@ EF_AMDGPU_FEATURE_XNACK_V3
@ EF_AMDGPU_MACH_AMDGCN_GFX602
@ EF_AMDGPU_MACH_AMDGCN_GFX1101
@ EF_AMDGPU_MACH_AMDGCN_GFX1100
@ EF_AMDGPU_MACH_AMDGCN_GFX1033
@ EF_AMDGPU_MACH_AMDGCN_GFX801
@ EF_AMDGPU_MACH_AMDGCN_GFX705
@ EF_AMDGPU_MACH_AMDGCN_GFX1010
@ EF_AMDGPU_MACH_R600_RV670
@ EF_AMDGPU_MACH_AMDGCN_GFX701
@ EF_AMDGPU_MACH_AMDGCN_GFX10_3_GENERIC
@ EF_AMDGPU_MACH_AMDGCN_GFX1012
@ EF_AMDGPU_MACH_AMDGCN_GFX1151
@ EF_AMDGPU_MACH_AMDGCN_GFX1030
@ EF_AMDGPU_MACH_R600_CEDAR
@ EF_AMDGPU_MACH_AMDGCN_GFX1200
@ EF_AMDGPU_MACH_AMDGCN_GFX700
@ EF_AMDGPU_MACH_AMDGCN_GFX11_GENERIC
@ EF_AMDGPU_MACH_AMDGCN_GFX803
@ EF_AMDGPU_MACH_AMDGCN_GFX802
@ EF_AMDGPU_MACH_AMDGCN_GFX90C
@ EF_AMDGPU_FEATURE_XNACK_ON_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX900
@ EF_AMDGPU_MACH_AMDGCN_GFX909
@ EF_AMDGPU_MACH_AMDGCN_GFX906
@ EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC
@ EF_AMDGPU_MACH_AMDGCN_GFX1103
@ EF_AMDGPU_MACH_R600_CAICOS
@ EF_AMDGPU_MACH_AMDGCN_GFX90A
@ EF_AMDGPU_MACH_AMDGCN_GFX1034
@ EF_AMDGPU_MACH_AMDGCN_GFX1013
@ EF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERIC
@ EF_AMDGPU_MACH_AMDGCN_GFX904
@ EF_AMDGPU_MACH_R600_RS880
@ EF_AMDGPU_MACH_AMDGCN_GFX805
@ EF_AMDGPU_MACH_AMDGCN_GFX1201
@ EF_AMDGPU_MACH_AMDGCN_GFX1150
@ EF_AMDGPU_MACH_R600_SUMO
@ EF_AMDGPU_MACH_R600_BARTS
@ EF_AMDGPU_FEATURE_SRAMECC_ANY_V4
@ EF_AMDGPU_FEATURE_SRAMECC_ON_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX702
initializer< Ty > init(const Ty &Val)
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
This is an optimization pass for GlobalISel generic memory operations.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
void dumpAmdKernelCode(const amd_kernel_code_t *C, raw_ostream &OS, const char *tab)
AMD Kernel Code Object (amd_kernel_code_t).
Instruction set architecture version.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
uint32_t group_segment_fixed_size
uint32_t compute_pgm_rsrc1
uint32_t private_segment_fixed_size
uint32_t compute_pgm_rsrc2
uint16_t kernel_code_properties
uint32_t compute_pgm_rsrc3
int64_t kernel_code_entry_byte_offset