LLVM 17.0.0git
AMDGPUPALMetadata.cpp
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1//===-- AMDGPUPALMetadata.cpp - Accumulate and print AMDGPU PAL metadata -===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10///
11/// This class has methods called by AMDGPUAsmPrinter to accumulate and print
12/// the PAL metadata.
13//
14//===----------------------------------------------------------------------===//
15//
16
17#include "AMDGPUPALMetadata.h"
18#include "AMDGPUPTNote.h"
19#include "SIDefines.h"
22#include "llvm/IR/Constants.h"
23#include "llvm/IR/Module.h"
26
27using namespace llvm;
28using namespace llvm::AMDGPU;
29
30// Read the PAL metadata from IR metadata, where it was put by the frontend.
32 auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata.msgpack");
33 if (NamedMD && NamedMD->getNumOperands()) {
34 // This is the new msgpack format for metadata. It is a NamedMD containing
35 // an MDTuple containing an MDString containing the msgpack data.
36 BlobType = ELF::NT_AMDGPU_METADATA;
37 auto MDN = dyn_cast<MDTuple>(NamedMD->getOperand(0));
38 if (MDN && MDN->getNumOperands()) {
39 if (auto MDS = dyn_cast<MDString>(MDN->getOperand(0)))
40 setFromMsgPackBlob(MDS->getString());
41 }
42 return;
43 }
44 BlobType = ELF::NT_AMD_PAL_METADATA;
45 NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
46 if (!NamedMD || !NamedMD->getNumOperands()) {
47 // Emit msgpack metadata by default
48 BlobType = ELF::NT_AMDGPU_METADATA;
49 return;
50 }
51 // This is the old reg=value pair format for metadata. It is a NamedMD
52 // containing an MDTuple containing a number of MDNodes each of which is an
53 // integer value, and each two integer values forms a key=value pair that we
54 // store as Registers[key]=value in the map.
55 auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
56 if (!Tuple)
57 return;
58 for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
59 auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I));
60 auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
61 if (!Key || !Val)
62 continue;
63 setRegister(Key->getZExtValue(), Val->getZExtValue());
64 }
65}
66
67// Set PAL metadata from a binary blob from the applicable .note record.
68// Returns false if bad format. Blob must remain valid for the lifetime of the
69// Metadata.
71 BlobType = Type;
73 return setFromLegacyBlob(Blob);
74 return setFromMsgPackBlob(Blob);
75}
76
77// Set PAL metadata from legacy (array of key=value pairs) blob.
78bool AMDGPUPALMetadata::setFromLegacyBlob(StringRef Blob) {
79 auto Data = reinterpret_cast<const uint32_t *>(Blob.data());
80 for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I)
81 setRegister(Data[I * 2], Data[I * 2 + 1]);
82 return true;
83}
84
85// Set PAL metadata from msgpack blob.
86bool AMDGPUPALMetadata::setFromMsgPackBlob(StringRef Blob) {
87 msgpack::Reader Reader(Blob);
88 return MsgPackDoc.readFromBlob(Blob, /*Multi=*/false);
89}
90
91// Given the calling convention, calculate the register number for rsrc1. In
92// principle the register number could change in future hardware, but we know
93// it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
94// we can use fixed values.
95static unsigned getRsrc1Reg(CallingConv::ID CC) {
96 switch (CC) {
97 default:
111 }
112}
113
114// Calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
115// with a constant offset to access any non-register shader-specific PAL
116// metadata key.
118 switch (CC) {
120 return PALMD::Key::PS_SCRATCH_SIZE;
122 return PALMD::Key::VS_SCRATCH_SIZE;
124 return PALMD::Key::GS_SCRATCH_SIZE;
126 return PALMD::Key::ES_SCRATCH_SIZE;
128 return PALMD::Key::HS_SCRATCH_SIZE;
130 return PALMD::Key::LS_SCRATCH_SIZE;
131 default:
132 return PALMD::Key::CS_SCRATCH_SIZE;
133 }
134}
135
136// Set the rsrc1 register in the metadata for a particular shader stage.
137// In fact this ORs the value into any previous setting of the register.
140}
141
142// Set the rsrc2 register in the metadata for a particular shader stage.
143// In fact this ORs the value into any previous setting of the register.
145 setRegister(getRsrc1Reg(CC) + 1, Val);
146}
147
148// Set the SPI_PS_INPUT_ENA register in the metadata.
149// In fact this ORs the value into any previous setting of the register.
152}
153
154// Set the SPI_PS_INPUT_ADDR register in the metadata.
155// In fact this ORs the value into any previous setting of the register.
158}
159
160// Get a register from the metadata, or 0 if not currently set.
161unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) {
162 auto Regs = getRegisters();
163 auto It = Regs.find(MsgPackDoc.getNode(Reg));
164 if (It == Regs.end())
165 return 0;
166 auto N = It->second;
167 if (N.getKind() != msgpack::Type::UInt)
168 return 0;
169 return N.getUInt();
170}
171
172// Set a register in the metadata.
173// In fact this ORs the value into any previous setting of the register.
174void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) {
175 if (!isLegacy()) {
176 // In the new MsgPack format, ignore register numbered >= 0x10000000. It
177 // is a PAL ABI pseudo-register in the old non-MsgPack format.
178 if (Reg >= 0x10000000)
179 return;
180 }
181 auto &N = getRegisters()[MsgPackDoc.getNode(Reg)];
182 if (N.getKind() == msgpack::Type::UInt)
183 Val |= N.getUInt();
184 N = N.getDocument()->getNode(Val);
185}
186
187// Set the entry point name for one shader.
189 if (isLegacy())
190 return;
191 // Msgpack format.
192 getHwStage(CC)[".entry_point"] = MsgPackDoc.getNode(Name, /*Copy=*/true);
193}
194
195// Set the number of used vgprs in the metadata. This is an optional
196// advisory record for logging etc; wave dispatch actually uses the rsrc1
197// register for the shader stage to determine the number of vgprs to
198// allocate.
200 if (isLegacy()) {
201 // Old non-msgpack format.
202 unsigned NumUsedVgprsKey = getScratchSizeKey(CC) +
203 PALMD::Key::VS_NUM_USED_VGPRS -
204 PALMD::Key::VS_SCRATCH_SIZE;
205 setRegister(NumUsedVgprsKey, Val);
206 return;
207 }
208 // Msgpack format.
209 getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(Val);
210}
211
212// Set the number of used agprs in the metadata.
214 getHwStage(CC)[".agpr_count"] = Val;
215}
216
217// Set the number of used sgprs in the metadata. This is an optional advisory
218// record for logging etc; wave dispatch actually uses the rsrc1 register for
219// the shader stage to determine the number of sgprs to allocate.
221 if (isLegacy()) {
222 // Old non-msgpack format.
223 unsigned NumUsedSgprsKey = getScratchSizeKey(CC) +
224 PALMD::Key::VS_NUM_USED_SGPRS -
225 PALMD::Key::VS_SCRATCH_SIZE;
226 setRegister(NumUsedSgprsKey, Val);
227 return;
228 }
229 // Msgpack format.
230 getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(Val);
231}
232
233// Set the scratch size in the metadata.
235 if (isLegacy()) {
236 // Old non-msgpack format.
238 return;
239 }
240 // Msgpack format.
241 getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(Val);
242}
243
244// Set the stack frame size of a function in the metadata.
246 unsigned Val) {
247 auto Node = getShaderFunction(MF.getFunction().getName());
248 Node[".stack_frame_size_in_bytes"] = MsgPackDoc.getNode(Val);
249}
250
251// Set the amount of LDS used in bytes in the metadata.
253 unsigned Val) {
254 auto Node = getShaderFunction(MF.getFunction().getName());
255 Node[".lds_size"] = MsgPackDoc.getNode(Val);
256}
257
258// Set the number of used vgprs in the metadata.
260 unsigned Val) {
261 auto Node = getShaderFunction(MF.getFunction().getName());
262 Node[".vgpr_count"] = MsgPackDoc.getNode(Val);
263}
264
265// Set the number of used vgprs in the metadata.
267 unsigned Val) {
268 auto Node = getShaderFunction(MF.getFunction().getName());
269 Node[".sgpr_count"] = MsgPackDoc.getNode(Val);
270}
271
272// Set the hardware register bit in PAL metadata to enable wave32 on the
273// shader of the given calling convention.
275 switch (CC) {
278 break;
281 break;
284 break;
287 break;
291 break;
292 }
293}
294
295// Convert a register number to name, for display by toString().
296// Returns nullptr if none.
297static const char *getRegisterName(unsigned RegNum) {
298 // Table of registers.
299 static const struct RegInfo {
300 unsigned Num;
301 const char *Name;
302 } RegInfoTable[] = {
303 // Registers that code generation sets/modifies metadata for.
304 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS, "SPI_SHADER_PGM_RSRC1_VS"},
305 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS + 1, "SPI_SHADER_PGM_RSRC2_VS"},
306 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS, "SPI_SHADER_PGM_RSRC1_LS"},
307 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1, "SPI_SHADER_PGM_RSRC2_LS"},
308 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS, "SPI_SHADER_PGM_RSRC1_HS"},
309 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1, "SPI_SHADER_PGM_RSRC2_HS"},
310 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES, "SPI_SHADER_PGM_RSRC1_ES"},
311 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, "SPI_SHADER_PGM_RSRC2_ES"},
312 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, "SPI_SHADER_PGM_RSRC1_GS"},
313 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, "SPI_SHADER_PGM_RSRC2_GS"},
314 {PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, "COMPUTE_DISPATCH_INITIATOR"},
315 {PALMD::R_2E12_COMPUTE_PGM_RSRC1, "COMPUTE_PGM_RSRC1"},
316 {PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, "COMPUTE_PGM_RSRC2"},
317 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, "SPI_SHADER_PGM_RSRC1_PS"},
318 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, "SPI_SHADER_PGM_RSRC2_PS"},
319 {PALMD::R_A1B3_SPI_PS_INPUT_ENA, "SPI_PS_INPUT_ENA"},
320 {PALMD::R_A1B4_SPI_PS_INPUT_ADDR, "SPI_PS_INPUT_ADDR"},
321 {PALMD::R_A1B6_SPI_PS_IN_CONTROL, "SPI_PS_IN_CONTROL"},
322 {PALMD::R_A2D5_VGT_SHADER_STAGES_EN, "VGT_SHADER_STAGES_EN"},
323
324 // Registers not known to code generation.
325 {0x2c07, "SPI_SHADER_PGM_RSRC3_PS"},
326 {0x2c46, "SPI_SHADER_PGM_RSRC3_VS"},
327 {0x2c87, "SPI_SHADER_PGM_RSRC3_GS"},
328 {0x2cc7, "SPI_SHADER_PGM_RSRC3_ES"},
329 {0x2d07, "SPI_SHADER_PGM_RSRC3_HS"},
330 {0x2d47, "SPI_SHADER_PGM_RSRC3_LS"},
331
332 {0xa1c3, "SPI_SHADER_POS_FORMAT"},
333 {0xa1b1, "SPI_VS_OUT_CONFIG"},
334 {0xa207, "PA_CL_VS_OUT_CNTL"},
335 {0xa204, "PA_CL_CLIP_CNTL"},
336 {0xa206, "PA_CL_VTE_CNTL"},
337 {0xa2f9, "PA_SU_VTX_CNTL"},
338 {0xa293, "PA_SC_MODE_CNTL_1"},
339 {0xa2a1, "VGT_PRIMITIVEID_EN"},
340 {0x2c81, "SPI_SHADER_PGM_RSRC4_GS"},
341 {0x2e18, "COMPUTE_TMPRING_SIZE"},
342 {0xa1b5, "SPI_INTERP_CONTROL_0"},
343 {0xa1ba, "SPI_TMPRING_SIZE"},
344 {0xa1c4, "SPI_SHADER_Z_FORMAT"},
345 {0xa1c5, "SPI_SHADER_COL_FORMAT"},
346 {0xa203, "DB_SHADER_CONTROL"},
347 {0xa08f, "CB_SHADER_MASK"},
348 {0xa191, "SPI_PS_INPUT_CNTL_0"},
349 {0xa192, "SPI_PS_INPUT_CNTL_1"},
350 {0xa193, "SPI_PS_INPUT_CNTL_2"},
351 {0xa194, "SPI_PS_INPUT_CNTL_3"},
352 {0xa195, "SPI_PS_INPUT_CNTL_4"},
353 {0xa196, "SPI_PS_INPUT_CNTL_5"},
354 {0xa197, "SPI_PS_INPUT_CNTL_6"},
355 {0xa198, "SPI_PS_INPUT_CNTL_7"},
356 {0xa199, "SPI_PS_INPUT_CNTL_8"},
357 {0xa19a, "SPI_PS_INPUT_CNTL_9"},
358 {0xa19b, "SPI_PS_INPUT_CNTL_10"},
359 {0xa19c, "SPI_PS_INPUT_CNTL_11"},
360 {0xa19d, "SPI_PS_INPUT_CNTL_12"},
361 {0xa19e, "SPI_PS_INPUT_CNTL_13"},
362 {0xa19f, "SPI_PS_INPUT_CNTL_14"},
363 {0xa1a0, "SPI_PS_INPUT_CNTL_15"},
364 {0xa1a1, "SPI_PS_INPUT_CNTL_16"},
365 {0xa1a2, "SPI_PS_INPUT_CNTL_17"},
366 {0xa1a3, "SPI_PS_INPUT_CNTL_18"},
367 {0xa1a4, "SPI_PS_INPUT_CNTL_19"},
368 {0xa1a5, "SPI_PS_INPUT_CNTL_20"},
369 {0xa1a6, "SPI_PS_INPUT_CNTL_21"},
370 {0xa1a7, "SPI_PS_INPUT_CNTL_22"},
371 {0xa1a8, "SPI_PS_INPUT_CNTL_23"},
372 {0xa1a9, "SPI_PS_INPUT_CNTL_24"},
373 {0xa1aa, "SPI_PS_INPUT_CNTL_25"},
374 {0xa1ab, "SPI_PS_INPUT_CNTL_26"},
375 {0xa1ac, "SPI_PS_INPUT_CNTL_27"},
376 {0xa1ad, "SPI_PS_INPUT_CNTL_28"},
377 {0xa1ae, "SPI_PS_INPUT_CNTL_29"},
378 {0xa1af, "SPI_PS_INPUT_CNTL_30"},
379 {0xa1b0, "SPI_PS_INPUT_CNTL_31"},
380
381 {0xa2ce, "VGT_GS_MAX_VERT_OUT"},
382 {0xa2ab, "VGT_ESGS_RING_ITEMSIZE"},
383 {0xa290, "VGT_GS_MODE"},
384 {0xa291, "VGT_GS_ONCHIP_CNTL"},
385 {0xa2d7, "VGT_GS_VERT_ITEMSIZE"},
386 {0xa2d8, "VGT_GS_VERT_ITEMSIZE_1"},
387 {0xa2d9, "VGT_GS_VERT_ITEMSIZE_2"},
388 {0xa2da, "VGT_GS_VERT_ITEMSIZE_3"},
389 {0xa298, "VGT_GSVS_RING_OFFSET_1"},
390 {0xa299, "VGT_GSVS_RING_OFFSET_2"},
391 {0xa29a, "VGT_GSVS_RING_OFFSET_3"},
392
393 {0xa2e4, "VGT_GS_INSTANCE_CNT"},
394 {0xa297, "VGT_GS_PER_VS"},
395 {0xa29b, "VGT_GS_OUT_PRIM_TYPE"},
396 {0xa2ac, "VGT_GSVS_RING_ITEMSIZE"},
397
398 {0xa2ad, "VGT_REUSE_OFF"},
399 {0xa1b8, "SPI_BARYC_CNTL"},
400
401 {0x2c4c, "SPI_SHADER_USER_DATA_VS_0"},
402 {0x2c4d, "SPI_SHADER_USER_DATA_VS_1"},
403 {0x2c4e, "SPI_SHADER_USER_DATA_VS_2"},
404 {0x2c4f, "SPI_SHADER_USER_DATA_VS_3"},
405 {0x2c50, "SPI_SHADER_USER_DATA_VS_4"},
406 {0x2c51, "SPI_SHADER_USER_DATA_VS_5"},
407 {0x2c52, "SPI_SHADER_USER_DATA_VS_6"},
408 {0x2c53, "SPI_SHADER_USER_DATA_VS_7"},
409 {0x2c54, "SPI_SHADER_USER_DATA_VS_8"},
410 {0x2c55, "SPI_SHADER_USER_DATA_VS_9"},
411 {0x2c56, "SPI_SHADER_USER_DATA_VS_10"},
412 {0x2c57, "SPI_SHADER_USER_DATA_VS_11"},
413 {0x2c58, "SPI_SHADER_USER_DATA_VS_12"},
414 {0x2c59, "SPI_SHADER_USER_DATA_VS_13"},
415 {0x2c5a, "SPI_SHADER_USER_DATA_VS_14"},
416 {0x2c5b, "SPI_SHADER_USER_DATA_VS_15"},
417 {0x2c5c, "SPI_SHADER_USER_DATA_VS_16"},
418 {0x2c5d, "SPI_SHADER_USER_DATA_VS_17"},
419 {0x2c5e, "SPI_SHADER_USER_DATA_VS_18"},
420 {0x2c5f, "SPI_SHADER_USER_DATA_VS_19"},
421 {0x2c60, "SPI_SHADER_USER_DATA_VS_20"},
422 {0x2c61, "SPI_SHADER_USER_DATA_VS_21"},
423 {0x2c62, "SPI_SHADER_USER_DATA_VS_22"},
424 {0x2c63, "SPI_SHADER_USER_DATA_VS_23"},
425 {0x2c64, "SPI_SHADER_USER_DATA_VS_24"},
426 {0x2c65, "SPI_SHADER_USER_DATA_VS_25"},
427 {0x2c66, "SPI_SHADER_USER_DATA_VS_26"},
428 {0x2c67, "SPI_SHADER_USER_DATA_VS_27"},
429 {0x2c68, "SPI_SHADER_USER_DATA_VS_28"},
430 {0x2c69, "SPI_SHADER_USER_DATA_VS_29"},
431 {0x2c6a, "SPI_SHADER_USER_DATA_VS_30"},
432 {0x2c6b, "SPI_SHADER_USER_DATA_VS_31"},
433
434 {0x2c8c, "SPI_SHADER_USER_DATA_GS_0"},
435 {0x2c8d, "SPI_SHADER_USER_DATA_GS_1"},
436 {0x2c8e, "SPI_SHADER_USER_DATA_GS_2"},
437 {0x2c8f, "SPI_SHADER_USER_DATA_GS_3"},
438 {0x2c90, "SPI_SHADER_USER_DATA_GS_4"},
439 {0x2c91, "SPI_SHADER_USER_DATA_GS_5"},
440 {0x2c92, "SPI_SHADER_USER_DATA_GS_6"},
441 {0x2c93, "SPI_SHADER_USER_DATA_GS_7"},
442 {0x2c94, "SPI_SHADER_USER_DATA_GS_8"},
443 {0x2c95, "SPI_SHADER_USER_DATA_GS_9"},
444 {0x2c96, "SPI_SHADER_USER_DATA_GS_10"},
445 {0x2c97, "SPI_SHADER_USER_DATA_GS_11"},
446 {0x2c98, "SPI_SHADER_USER_DATA_GS_12"},
447 {0x2c99, "SPI_SHADER_USER_DATA_GS_13"},
448 {0x2c9a, "SPI_SHADER_USER_DATA_GS_14"},
449 {0x2c9b, "SPI_SHADER_USER_DATA_GS_15"},
450 {0x2c9c, "SPI_SHADER_USER_DATA_GS_16"},
451 {0x2c9d, "SPI_SHADER_USER_DATA_GS_17"},
452 {0x2c9e, "SPI_SHADER_USER_DATA_GS_18"},
453 {0x2c9f, "SPI_SHADER_USER_DATA_GS_19"},
454 {0x2ca0, "SPI_SHADER_USER_DATA_GS_20"},
455 {0x2ca1, "SPI_SHADER_USER_DATA_GS_21"},
456 {0x2ca2, "SPI_SHADER_USER_DATA_GS_22"},
457 {0x2ca3, "SPI_SHADER_USER_DATA_GS_23"},
458 {0x2ca4, "SPI_SHADER_USER_DATA_GS_24"},
459 {0x2ca5, "SPI_SHADER_USER_DATA_GS_25"},
460 {0x2ca6, "SPI_SHADER_USER_DATA_GS_26"},
461 {0x2ca7, "SPI_SHADER_USER_DATA_GS_27"},
462 {0x2ca8, "SPI_SHADER_USER_DATA_GS_28"},
463 {0x2ca9, "SPI_SHADER_USER_DATA_GS_29"},
464 {0x2caa, "SPI_SHADER_USER_DATA_GS_30"},
465 {0x2cab, "SPI_SHADER_USER_DATA_GS_31"},
466
467 {0x2ccc, "SPI_SHADER_USER_DATA_ES_0"},
468 {0x2ccd, "SPI_SHADER_USER_DATA_ES_1"},
469 {0x2cce, "SPI_SHADER_USER_DATA_ES_2"},
470 {0x2ccf, "SPI_SHADER_USER_DATA_ES_3"},
471 {0x2cd0, "SPI_SHADER_USER_DATA_ES_4"},
472 {0x2cd1, "SPI_SHADER_USER_DATA_ES_5"},
473 {0x2cd2, "SPI_SHADER_USER_DATA_ES_6"},
474 {0x2cd3, "SPI_SHADER_USER_DATA_ES_7"},
475 {0x2cd4, "SPI_SHADER_USER_DATA_ES_8"},
476 {0x2cd5, "SPI_SHADER_USER_DATA_ES_9"},
477 {0x2cd6, "SPI_SHADER_USER_DATA_ES_10"},
478 {0x2cd7, "SPI_SHADER_USER_DATA_ES_11"},
479 {0x2cd8, "SPI_SHADER_USER_DATA_ES_12"},
480 {0x2cd9, "SPI_SHADER_USER_DATA_ES_13"},
481 {0x2cda, "SPI_SHADER_USER_DATA_ES_14"},
482 {0x2cdb, "SPI_SHADER_USER_DATA_ES_15"},
483 {0x2cdc, "SPI_SHADER_USER_DATA_ES_16"},
484 {0x2cdd, "SPI_SHADER_USER_DATA_ES_17"},
485 {0x2cde, "SPI_SHADER_USER_DATA_ES_18"},
486 {0x2cdf, "SPI_SHADER_USER_DATA_ES_19"},
487 {0x2ce0, "SPI_SHADER_USER_DATA_ES_20"},
488 {0x2ce1, "SPI_SHADER_USER_DATA_ES_21"},
489 {0x2ce2, "SPI_SHADER_USER_DATA_ES_22"},
490 {0x2ce3, "SPI_SHADER_USER_DATA_ES_23"},
491 {0x2ce4, "SPI_SHADER_USER_DATA_ES_24"},
492 {0x2ce5, "SPI_SHADER_USER_DATA_ES_25"},
493 {0x2ce6, "SPI_SHADER_USER_DATA_ES_26"},
494 {0x2ce7, "SPI_SHADER_USER_DATA_ES_27"},
495 {0x2ce8, "SPI_SHADER_USER_DATA_ES_28"},
496 {0x2ce9, "SPI_SHADER_USER_DATA_ES_29"},
497 {0x2cea, "SPI_SHADER_USER_DATA_ES_30"},
498 {0x2ceb, "SPI_SHADER_USER_DATA_ES_31"},
499
500 {0x2c0c, "SPI_SHADER_USER_DATA_PS_0"},
501 {0x2c0d, "SPI_SHADER_USER_DATA_PS_1"},
502 {0x2c0e, "SPI_SHADER_USER_DATA_PS_2"},
503 {0x2c0f, "SPI_SHADER_USER_DATA_PS_3"},
504 {0x2c10, "SPI_SHADER_USER_DATA_PS_4"},
505 {0x2c11, "SPI_SHADER_USER_DATA_PS_5"},
506 {0x2c12, "SPI_SHADER_USER_DATA_PS_6"},
507 {0x2c13, "SPI_SHADER_USER_DATA_PS_7"},
508 {0x2c14, "SPI_SHADER_USER_DATA_PS_8"},
509 {0x2c15, "SPI_SHADER_USER_DATA_PS_9"},
510 {0x2c16, "SPI_SHADER_USER_DATA_PS_10"},
511 {0x2c17, "SPI_SHADER_USER_DATA_PS_11"},
512 {0x2c18, "SPI_SHADER_USER_DATA_PS_12"},
513 {0x2c19, "SPI_SHADER_USER_DATA_PS_13"},
514 {0x2c1a, "SPI_SHADER_USER_DATA_PS_14"},
515 {0x2c1b, "SPI_SHADER_USER_DATA_PS_15"},
516 {0x2c1c, "SPI_SHADER_USER_DATA_PS_16"},
517 {0x2c1d, "SPI_SHADER_USER_DATA_PS_17"},
518 {0x2c1e, "SPI_SHADER_USER_DATA_PS_18"},
519 {0x2c1f, "SPI_SHADER_USER_DATA_PS_19"},
520 {0x2c20, "SPI_SHADER_USER_DATA_PS_20"},
521 {0x2c21, "SPI_SHADER_USER_DATA_PS_21"},
522 {0x2c22, "SPI_SHADER_USER_DATA_PS_22"},
523 {0x2c23, "SPI_SHADER_USER_DATA_PS_23"},
524 {0x2c24, "SPI_SHADER_USER_DATA_PS_24"},
525 {0x2c25, "SPI_SHADER_USER_DATA_PS_25"},
526 {0x2c26, "SPI_SHADER_USER_DATA_PS_26"},
527 {0x2c27, "SPI_SHADER_USER_DATA_PS_27"},
528 {0x2c28, "SPI_SHADER_USER_DATA_PS_28"},
529 {0x2c29, "SPI_SHADER_USER_DATA_PS_29"},
530 {0x2c2a, "SPI_SHADER_USER_DATA_PS_30"},
531 {0x2c2b, "SPI_SHADER_USER_DATA_PS_31"},
532
533 {0x2e40, "COMPUTE_USER_DATA_0"},
534 {0x2e41, "COMPUTE_USER_DATA_1"},
535 {0x2e42, "COMPUTE_USER_DATA_2"},
536 {0x2e43, "COMPUTE_USER_DATA_3"},
537 {0x2e44, "COMPUTE_USER_DATA_4"},
538 {0x2e45, "COMPUTE_USER_DATA_5"},
539 {0x2e46, "COMPUTE_USER_DATA_6"},
540 {0x2e47, "COMPUTE_USER_DATA_7"},
541 {0x2e48, "COMPUTE_USER_DATA_8"},
542 {0x2e49, "COMPUTE_USER_DATA_9"},
543 {0x2e4a, "COMPUTE_USER_DATA_10"},
544 {0x2e4b, "COMPUTE_USER_DATA_11"},
545 {0x2e4c, "COMPUTE_USER_DATA_12"},
546 {0x2e4d, "COMPUTE_USER_DATA_13"},
547 {0x2e4e, "COMPUTE_USER_DATA_14"},
548 {0x2e4f, "COMPUTE_USER_DATA_15"},
549
550 {0x2e07, "COMPUTE_NUM_THREAD_X"},
551 {0x2e08, "COMPUTE_NUM_THREAD_Y"},
552 {0x2e09, "COMPUTE_NUM_THREAD_Z"},
553 {0xa2db, "VGT_TF_PARAM"},
554 {0xa2d6, "VGT_LS_HS_CONFIG"},
555 {0xa287, "VGT_HOS_MIN_TESS_LEVEL"},
556 {0xa286, "VGT_HOS_MAX_TESS_LEVEL"},
557 {0xa2f8, "PA_SC_AA_CONFIG"},
558 {0xa310, "PA_SC_SHADER_CONTROL"},
559 {0xa313, "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"},
560
561 {0x2d0c, "SPI_SHADER_USER_DATA_HS_0"},
562 {0x2d0d, "SPI_SHADER_USER_DATA_HS_1"},
563 {0x2d0e, "SPI_SHADER_USER_DATA_HS_2"},
564 {0x2d0f, "SPI_SHADER_USER_DATA_HS_3"},
565 {0x2d10, "SPI_SHADER_USER_DATA_HS_4"},
566 {0x2d11, "SPI_SHADER_USER_DATA_HS_5"},
567 {0x2d12, "SPI_SHADER_USER_DATA_HS_6"},
568 {0x2d13, "SPI_SHADER_USER_DATA_HS_7"},
569 {0x2d14, "SPI_SHADER_USER_DATA_HS_8"},
570 {0x2d15, "SPI_SHADER_USER_DATA_HS_9"},
571 {0x2d16, "SPI_SHADER_USER_DATA_HS_10"},
572 {0x2d17, "SPI_SHADER_USER_DATA_HS_11"},
573 {0x2d18, "SPI_SHADER_USER_DATA_HS_12"},
574 {0x2d19, "SPI_SHADER_USER_DATA_HS_13"},
575 {0x2d1a, "SPI_SHADER_USER_DATA_HS_14"},
576 {0x2d1b, "SPI_SHADER_USER_DATA_HS_15"},
577 {0x2d1c, "SPI_SHADER_USER_DATA_HS_16"},
578 {0x2d1d, "SPI_SHADER_USER_DATA_HS_17"},
579 {0x2d1e, "SPI_SHADER_USER_DATA_HS_18"},
580 {0x2d1f, "SPI_SHADER_USER_DATA_HS_19"},
581 {0x2d20, "SPI_SHADER_USER_DATA_HS_20"},
582 {0x2d21, "SPI_SHADER_USER_DATA_HS_21"},
583 {0x2d22, "SPI_SHADER_USER_DATA_HS_22"},
584 {0x2d23, "SPI_SHADER_USER_DATA_HS_23"},
585 {0x2d24, "SPI_SHADER_USER_DATA_HS_24"},
586 {0x2d25, "SPI_SHADER_USER_DATA_HS_25"},
587 {0x2d26, "SPI_SHADER_USER_DATA_HS_26"},
588 {0x2d27, "SPI_SHADER_USER_DATA_HS_27"},
589 {0x2d28, "SPI_SHADER_USER_DATA_HS_28"},
590 {0x2d29, "SPI_SHADER_USER_DATA_HS_29"},
591 {0x2d2a, "SPI_SHADER_USER_DATA_HS_30"},
592 {0x2d2b, "SPI_SHADER_USER_DATA_HS_31"},
593
594 {0x2d4c, "SPI_SHADER_USER_DATA_LS_0"},
595 {0x2d4d, "SPI_SHADER_USER_DATA_LS_1"},
596 {0x2d4e, "SPI_SHADER_USER_DATA_LS_2"},
597 {0x2d4f, "SPI_SHADER_USER_DATA_LS_3"},
598 {0x2d50, "SPI_SHADER_USER_DATA_LS_4"},
599 {0x2d51, "SPI_SHADER_USER_DATA_LS_5"},
600 {0x2d52, "SPI_SHADER_USER_DATA_LS_6"},
601 {0x2d53, "SPI_SHADER_USER_DATA_LS_7"},
602 {0x2d54, "SPI_SHADER_USER_DATA_LS_8"},
603 {0x2d55, "SPI_SHADER_USER_DATA_LS_9"},
604 {0x2d56, "SPI_SHADER_USER_DATA_LS_10"},
605 {0x2d57, "SPI_SHADER_USER_DATA_LS_11"},
606 {0x2d58, "SPI_SHADER_USER_DATA_LS_12"},
607 {0x2d59, "SPI_SHADER_USER_DATA_LS_13"},
608 {0x2d5a, "SPI_SHADER_USER_DATA_LS_14"},
609 {0x2d5b, "SPI_SHADER_USER_DATA_LS_15"},
610
611 {0xa2aa, "IA_MULTI_VGT_PARAM"},
612 {0xa2a5, "VGT_GS_MAX_PRIMS_PER_SUBGROUP"},
613 {0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"},
614 {0xa2e5, "VGT_STRMOUT_CONFIG"},
615 {0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"},
616 {0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"},
617 {0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"},
618 {0xa2c1, "VGT_STRMOUT_VTX_STRIDE_3"},
619 {0xa316, "VGT_VERTEX_REUSE_BLOCK_CNTL"},
620
621 {0x2e28, "COMPUTE_PGM_RSRC3"},
622 {0x2e2a, "COMPUTE_SHADER_CHKSUM"},
623 {0x2e24, "COMPUTE_USER_ACCUM_0"},
624 {0x2e25, "COMPUTE_USER_ACCUM_1"},
625 {0x2e26, "COMPUTE_USER_ACCUM_2"},
626 {0x2e27, "COMPUTE_USER_ACCUM_3"},
627 {0xa1ff, "GE_MAX_OUTPUT_PER_SUBGROUP"},
628 {0xa2d3, "GE_NGG_SUBGRP_CNTL"},
629 {0xc25f, "GE_STEREO_CNTL"},
630 {0xc262, "GE_USER_VGPR_EN"},
631 {0xc258, "IA_MULTI_VGT_PARAM_PIPED"},
632 {0xa210, "PA_STEREO_CNTL"},
633 {0xa1c2, "SPI_SHADER_IDX_FORMAT"},
634 {0x2c80, "SPI_SHADER_PGM_CHKSUM_GS"},
635 {0x2d00, "SPI_SHADER_PGM_CHKSUM_HS"},
636 {0x2c06, "SPI_SHADER_PGM_CHKSUM_PS"},
637 {0x2c45, "SPI_SHADER_PGM_CHKSUM_VS"},
638 {0x2c88, "SPI_SHADER_PGM_LO_GS"},
639 {0x2cb2, "SPI_SHADER_USER_ACCUM_ESGS_0"},
640 {0x2cb3, "SPI_SHADER_USER_ACCUM_ESGS_1"},
641 {0x2cb4, "SPI_SHADER_USER_ACCUM_ESGS_2"},
642 {0x2cb5, "SPI_SHADER_USER_ACCUM_ESGS_3"},
643 {0x2d32, "SPI_SHADER_USER_ACCUM_LSHS_0"},
644 {0x2d33, "SPI_SHADER_USER_ACCUM_LSHS_1"},
645 {0x2d34, "SPI_SHADER_USER_ACCUM_LSHS_2"},
646 {0x2d35, "SPI_SHADER_USER_ACCUM_LSHS_3"},
647 {0x2c32, "SPI_SHADER_USER_ACCUM_PS_0"},
648 {0x2c33, "SPI_SHADER_USER_ACCUM_PS_1"},
649 {0x2c34, "SPI_SHADER_USER_ACCUM_PS_2"},
650 {0x2c35, "SPI_SHADER_USER_ACCUM_PS_3"},
651 {0x2c72, "SPI_SHADER_USER_ACCUM_VS_0"},
652 {0x2c73, "SPI_SHADER_USER_ACCUM_VS_1"},
653 {0x2c74, "SPI_SHADER_USER_ACCUM_VS_2"},
654 {0x2c75, "SPI_SHADER_USER_ACCUM_VS_3"},
655
656 {0, nullptr}};
657 auto Entry = RegInfoTable;
658 for (; Entry->Num && Entry->Num != RegNum; ++Entry)
659 ;
660 return Entry->Name;
661}
662
663// Convert the accumulated PAL metadata into an asm directive.
665 String.clear();
666 if (!BlobType)
667 return;
669 if (isLegacy()) {
670 if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil)
671 return;
672 // Old linear reg=val format.
673 Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' ';
674 auto Regs = getRegisters();
675 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) {
676 if (I != Regs.begin())
677 Stream << ',';
678 unsigned Reg = I->first.getUInt();
679 unsigned Val = I->second.getUInt();
680 Stream << "0x" << Twine::utohexstr(Reg) << ",0x" << Twine::utohexstr(Val);
681 }
682 Stream << '\n';
683 return;
684 }
685
686 // New msgpack-based format -- output as YAML (with unsigned numbers in hex),
687 // but first change the registers map to use names.
688 MsgPackDoc.setHexMode();
689 auto &RegsObj = refRegisters();
690 auto OrigRegs = RegsObj.getMap();
691 RegsObj = MsgPackDoc.getMapNode();
692 for (auto I : OrigRegs) {
693 auto Key = I.first;
694 if (const char *RegName = getRegisterName(Key.getUInt())) {
695 std::string KeyName = Key.toString();
696 KeyName += " (";
697 KeyName += RegName;
698 KeyName += ')';
699 Key = MsgPackDoc.getNode(KeyName, /*Copy=*/true);
700 }
701 RegsObj.getMap()[Key] = I.second;
702 }
703
704 // Output as YAML.
705 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveBegin << '\n';
706 MsgPackDoc.toYAML(Stream);
707 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveEnd << '\n';
708
709 // Restore original registers map.
710 RegsObj = OrigRegs;
711}
712
713// Convert the accumulated PAL metadata into a binary blob for writing as
714// a .note record of the specified AMD type. Returns an empty blob if
715// there is no PAL metadata,
716void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) {
718 toLegacyBlob(Blob);
719 else if (Type)
720 toMsgPackBlob(Blob);
721}
722
723void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) {
724 Blob.clear();
725 auto Registers = getRegisters();
726 if (Registers.getMap().empty())
727 return;
728 raw_string_ostream OS(Blob);
729 support::endian::Writer EW(OS, support::endianness::little);
730 for (auto I : Registers.getMap()) {
731 EW.write(uint32_t(I.first.getUInt()));
732 EW.write(uint32_t(I.second.getUInt()));
733 }
734}
735
736void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) {
737 Blob.clear();
738 MsgPackDoc.writeToBlob(Blob);
739}
740
741// Set PAL metadata from YAML text. Returns false if failed.
743 BlobType = ELF::NT_AMDGPU_METADATA;
744 if (!MsgPackDoc.fromYAML(S))
745 return false;
746
747 // In the registers map, some keys may be of the form "0xa191
748 // (SPI_PS_INPUT_CNTL_0)", in which case the YAML input code made it a
749 // string. We need to turn it into a number.
750 auto &RegsObj = refRegisters();
751 auto OrigRegs = RegsObj;
752 RegsObj = MsgPackDoc.getMapNode();
753 Registers = RegsObj.getMap();
754 bool Ok = true;
755 for (auto I : OrigRegs.getMap()) {
756 auto Key = I.first;
757 if (Key.getKind() == msgpack::Type::String) {
758 StringRef S = Key.getString();
759 uint64_t Val;
760 if (S.consumeInteger(0, Val)) {
761 Ok = false;
762 errs() << "Unrecognized PAL metadata register key '" << S << "'\n";
763 continue;
764 }
765 Key = MsgPackDoc.getNode(uint64_t(Val));
766 }
767 Registers.getMap()[Key] = I.second;
768 }
769 return Ok;
770}
771
772// Reference (create if necessary) the node for the registers map.
773msgpack::DocNode &AMDGPUPALMetadata::refRegisters() {
774 auto &N =
775 MsgPackDoc.getRoot()
776 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
777 .getArray(/*Convert=*/true)[0]
778 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".registers")];
779 N.getMap(/*Convert=*/true);
780 return N;
781}
782
783// Get (create if necessary) the registers map.
784msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() {
785 if (Registers.isEmpty())
786 Registers = refRegisters();
787 return Registers.getMap();
788}
789
790// Reference (create if necessary) the node for the shader functions map.
791msgpack::DocNode &AMDGPUPALMetadata::refShaderFunctions() {
792 auto &N =
793 MsgPackDoc.getRoot()
794 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
795 .getArray(/*Convert=*/true)[0]
796 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".shader_functions")];
797 N.getMap(/*Convert=*/true);
798 return N;
799}
800
801// Get (create if necessary) the shader functions map.
802msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunctions() {
803 if (ShaderFunctions.isEmpty())
804 ShaderFunctions = refShaderFunctions();
805 return ShaderFunctions.getMap();
806}
807
808// Get (create if necessary) a function in the shader functions map.
809msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunction(StringRef Name) {
810 auto Functions = getShaderFunctions();
811 return Functions[Name].getMap(/*Convert=*/true);
812}
813
814// Return the PAL metadata hardware shader stage name.
815static const char *getStageName(CallingConv::ID CC) {
816 switch (CC) {
818 return ".ps";
820 return ".vs";
822 return ".gs";
824 return ".es";
826 return ".hs";
828 return ".ls";
830 llvm_unreachable("Callable shader has no hardware stage");
831 default:
832 return ".cs";
833 }
834}
835
836// Get (create if necessary) the .hardware_stages entry for the given calling
837// convention.
838msgpack::MapDocNode AMDGPUPALMetadata::getHwStage(unsigned CC) {
839 if (HwStages.isEmpty())
840 HwStages = MsgPackDoc.getRoot()
841 .getMap(/*Convert=*/true)["amdpal.pipelines"]
842 .getArray(/*Convert=*/true)[0]
843 .getMap(/*Convert=*/true)[".hardware_stages"]
844 .getMap(/*Convert=*/true);
845 return HwStages.getMap()[getStageName(CC)].getMap(/*Convert=*/true);
846}
847
848// Get .note record vendor name of metadata blob to be emitted.
849const char *AMDGPUPALMetadata::getVendor() const {
850 return isLegacy() ? ElfNote::NoteNameV2 : ElfNote::NoteNameV3;
851}
852
853// Get .note record type of metadata blob to be emitted:
854// ELF::NT_AMD_PAL_METADATA (legacy key=val format), or
855// ELF::NT_AMDGPU_METADATA (MsgPack format), or
856// 0 (no PAL metadata).
858 return BlobType;
859}
860
861// Return whether the blob type is legacy PAL metadata.
862bool AMDGPUPALMetadata::isLegacy() const {
863 return BlobType == ELF::NT_AMD_PAL_METADATA;
864}
865
866// Set legacy PAL metadata format.
868 BlobType = ELF::NT_AMD_PAL_METADATA;
869}
870
871// Erase all PAL metadata.
873 MsgPackDoc.clear();
874 Registers = MsgPackDoc.getEmptyNode();
875 HwStages = MsgPackDoc.getEmptyNode();
876}
AMDGPU metadata definitions and in-memory representations.
static unsigned getScratchSizeKey(CallingConv::ID CC)
static unsigned getRsrc1Reg(CallingConv::ID CC)
static const char * getStageName(CallingConv::ID CC)
PAL metadata handling.
Enums and constants for AMDGPU PT_NOTE sections.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
std::string Name
#define RegName(no)
#define I(x, y, z)
Definition: MD5.cpp:58
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)
Definition: MIParser.cpp:1397
Module.h This file contains the declarations for the Module class.
#define S_0286D8_PS_W32_EN(x)
Definition: SIDefines.h:1058
#define S_00B800_CS_W32_EN(x)
Definition: SIDefines.h:1060
#define S_028B54_GS_W32_EN(x)
Definition: SIDefines.h:1055
#define S_028B54_VS_W32_EN(x)
Definition: SIDefines.h:1056
#define S_028B54_HS_W32_EN(x)
Definition: SIDefines.h:1054
void setSpiPsInputAddr(unsigned Val)
void setEntryPoint(unsigned CC, StringRef Name)
const char * getVendor() const
void setFunctionScratchSize(const MachineFunction &MF, unsigned Val)
bool setFromString(StringRef S)
void setNumUsedVgprs(unsigned CC, unsigned Val)
unsigned getRegister(unsigned Reg)
bool setFromBlob(unsigned Type, StringRef Blob)
void setFunctionNumUsedSgprs(const MachineFunction &MF, unsigned Val)
void setFunctionLdsSize(const MachineFunction &MF, unsigned Val)
void setScratchSize(unsigned CC, unsigned Val)
void setRegister(unsigned Reg, unsigned Val)
void setRsrc1(unsigned CC, unsigned Val)
void setSpiPsInputEna(unsigned Val)
void setFunctionNumUsedVgprs(const MachineFunction &MF, unsigned Val)
void setNumUsedAgprs(unsigned CC, unsigned Val)
void toBlob(unsigned Type, std::string &S)
void toString(std::string &S)
void setRsrc2(unsigned CC, unsigned Val)
void setNumUsedSgprs(unsigned CC, unsigned Val)
Function & getFunction()
Return the LLVM function that this machine code represents.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool consumeInteger(unsigned Radix, T &Result)
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:498
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:131
static Twine utohexstr(const uint64_t &Val)
Definition: Twine.h:404
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:308
A node in a MsgPack Document.
MapDocNode & getMap(bool Convert=false)
Get a MapDocNode for a map node.
ArrayDocNode & getArray(bool Convert=false)
Get an ArrayDocNode for an array node.
MapDocNode getMapNode()
Create an empty Map node associated with this Document.
DocNode getEmptyNode()
Create an empty node associated with this Document.
DocNode & getRoot()
Get ref to the document's root element.
void clear()
Restore the Document to an empty state.
DocNode getNode()
Create a nil node associated with this Document.
void setHexMode(bool Val=true)
Set whether YAML output uses hex for UInt. Default off.
void toYAML(raw_ostream &OS)
Convert MsgPack Document to YAML text.
void writeToBlob(std::string &Blob)
Write a MsgPack document to a binary MsgPack blob.
bool readFromBlob(StringRef Blob, bool Multi, function_ref< int(DocNode *DestNode, DocNode SrcNode, DocNode MapKey)> Merger=[](DocNode *DestNode, DocNode SrcNode, DocNode MapKey) { return -1;})
Read a document from a binary msgpack blob, merging into anything already in the Document.
bool fromYAML(StringRef S)
Read YAML text into the MsgPack document. Returns false on failure.
A DocNode that is a map.
Reads MessagePack objects from memory, one at a time.
Definition: MsgPackReader.h:99
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:642
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const char NoteNameV2[]
Definition: AMDGPUPTNote.h:26
const char NoteNameV3[]
Definition: AMDGPUPTNote.h:27
constexpr char AssemblerDirective[]
PAL metadata (old linear format) assembler directive.
constexpr char AssemblerDirectiveBegin[]
PAL metadata (new MsgPack format) beginning assembler directive.
constexpr char AssemblerDirectiveEnd[]
PAL metadata (new MsgPack format) ending assembler directive.
@ AMDGPU_CS
Used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:198
@ AMDGPU_VS
Used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (vertex shader if tess...
Definition: CallingConv.h:189
@ AMDGPU_Gfx
Used for AMD graphics targets.
Definition: CallingConv.h:233
@ AMDGPU_HS
Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:207
@ AMDGPU_GS
Used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:192
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:195
@ AMDGPU_ES
Used for AMDPAL shader stage before geometry shader if geometry is in use.
Definition: CallingConv.h:219
@ AMDGPU_LS
Used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:214
@ NT_AMD_PAL_METADATA
Definition: ELF.h:1759
@ NT_AMDGPU_METADATA
Definition: ELF.h:1765
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
#define N
Adapter to write values to a stream in a particular byte order.
Definition: EndianStream.h:52