LLVM 18.0.0git
AMDGPUPALMetadata.cpp
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1//===-- AMDGPUPALMetadata.cpp - Accumulate and print AMDGPU PAL metadata -===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10///
11/// This class has methods called by AMDGPUAsmPrinter to accumulate and print
12/// the PAL metadata.
13//
14//===----------------------------------------------------------------------===//
15//
16
17#include "AMDGPUPALMetadata.h"
18#include "AMDGPUPTNote.h"
19#include "SIDefines.h"
21#include "llvm/IR/Constants.h"
22#include "llvm/IR/Module.h"
25
26using namespace llvm;
27using namespace llvm::AMDGPU;
28
29// Read the PAL metadata from IR metadata, where it was put by the frontend.
31 auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata.msgpack");
32 if (NamedMD && NamedMD->getNumOperands()) {
33 // This is the new msgpack format for metadata. It is a NamedMD containing
34 // an MDTuple containing an MDString containing the msgpack data.
35 BlobType = ELF::NT_AMDGPU_METADATA;
36 auto MDN = dyn_cast<MDTuple>(NamedMD->getOperand(0));
37 if (MDN && MDN->getNumOperands()) {
38 if (auto MDS = dyn_cast<MDString>(MDN->getOperand(0)))
39 setFromMsgPackBlob(MDS->getString());
40 }
41 return;
42 }
43 BlobType = ELF::NT_AMD_PAL_METADATA;
44 NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
45 if (!NamedMD || !NamedMD->getNumOperands()) {
46 // Emit msgpack metadata by default
47 BlobType = ELF::NT_AMDGPU_METADATA;
48 return;
49 }
50 // This is the old reg=value pair format for metadata. It is a NamedMD
51 // containing an MDTuple containing a number of MDNodes each of which is an
52 // integer value, and each two integer values forms a key=value pair that we
53 // store as Registers[key]=value in the map.
54 auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
55 if (!Tuple)
56 return;
57 for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
58 auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I));
59 auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
60 if (!Key || !Val)
61 continue;
62 setRegister(Key->getZExtValue(), Val->getZExtValue());
63 }
64}
65
66// Set PAL metadata from a binary blob from the applicable .note record.
67// Returns false if bad format. Blob must remain valid for the lifetime of the
68// Metadata.
70 BlobType = Type;
72 return setFromLegacyBlob(Blob);
73 return setFromMsgPackBlob(Blob);
74}
75
76// Set PAL metadata from legacy (array of key=value pairs) blob.
77bool AMDGPUPALMetadata::setFromLegacyBlob(StringRef Blob) {
78 auto Data = reinterpret_cast<const uint32_t *>(Blob.data());
79 for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I)
80 setRegister(Data[I * 2], Data[I * 2 + 1]);
81 return true;
82}
83
84// Set PAL metadata from msgpack blob.
85bool AMDGPUPALMetadata::setFromMsgPackBlob(StringRef Blob) {
86 msgpack::Reader Reader(Blob);
87 return MsgPackDoc.readFromBlob(Blob, /*Multi=*/false);
88}
89
90// Given the calling convention, calculate the register number for rsrc1. In
91// principle the register number could change in future hardware, but we know
92// it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
93// we can use fixed values.
94static unsigned getRsrc1Reg(CallingConv::ID CC) {
95 switch (CC) {
96 default:
110 }
111}
112
113// Calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
114// with a constant offset to access any non-register shader-specific PAL
115// metadata key.
117 switch (CC) {
119 return PALMD::Key::PS_SCRATCH_SIZE;
121 return PALMD::Key::VS_SCRATCH_SIZE;
123 return PALMD::Key::GS_SCRATCH_SIZE;
125 return PALMD::Key::ES_SCRATCH_SIZE;
127 return PALMD::Key::HS_SCRATCH_SIZE;
129 return PALMD::Key::LS_SCRATCH_SIZE;
130 default:
131 return PALMD::Key::CS_SCRATCH_SIZE;
132 }
133}
134
135// Set the rsrc1 register in the metadata for a particular shader stage.
136// In fact this ORs the value into any previous setting of the register.
139}
140
141// Set the rsrc2 register in the metadata for a particular shader stage.
142// In fact this ORs the value into any previous setting of the register.
144 setRegister(getRsrc1Reg(CC) + 1, Val);
145}
146
147// Set the SPI_PS_INPUT_ENA register in the metadata.
148// In fact this ORs the value into any previous setting of the register.
151}
152
153// Set the SPI_PS_INPUT_ADDR register in the metadata.
154// In fact this ORs the value into any previous setting of the register.
157}
158
159// Get a register from the metadata, or 0 if not currently set.
160unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) {
161 auto Regs = getRegisters();
162 auto It = Regs.find(MsgPackDoc.getNode(Reg));
163 if (It == Regs.end())
164 return 0;
165 auto N = It->second;
166 if (N.getKind() != msgpack::Type::UInt)
167 return 0;
168 return N.getUInt();
169}
170
171// Set a register in the metadata.
172// In fact this ORs the value into any previous setting of the register.
173void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) {
174 if (!isLegacy()) {
175 // In the new MsgPack format, ignore register numbered >= 0x10000000. It
176 // is a PAL ABI pseudo-register in the old non-MsgPack format.
177 if (Reg >= 0x10000000)
178 return;
179 }
180 auto &N = getRegisters()[MsgPackDoc.getNode(Reg)];
181 if (N.getKind() == msgpack::Type::UInt)
182 Val |= N.getUInt();
183 N = N.getDocument()->getNode(Val);
184}
185
186// Set the entry point name for one shader.
188 if (isLegacy())
189 return;
190 // Msgpack format.
191 getHwStage(CC)[".entry_point"] = MsgPackDoc.getNode(Name, /*Copy=*/true);
192}
193
194// Set the number of used vgprs in the metadata. This is an optional
195// advisory record for logging etc; wave dispatch actually uses the rsrc1
196// register for the shader stage to determine the number of vgprs to
197// allocate.
199 if (isLegacy()) {
200 // Old non-msgpack format.
201 unsigned NumUsedVgprsKey = getScratchSizeKey(CC) +
202 PALMD::Key::VS_NUM_USED_VGPRS -
203 PALMD::Key::VS_SCRATCH_SIZE;
204 setRegister(NumUsedVgprsKey, Val);
205 return;
206 }
207 // Msgpack format.
208 getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(Val);
209}
210
211// Set the number of used agprs in the metadata.
213 getHwStage(CC)[".agpr_count"] = Val;
214}
215
216// Set the number of used sgprs in the metadata. This is an optional advisory
217// record for logging etc; wave dispatch actually uses the rsrc1 register for
218// the shader stage to determine the number of sgprs to allocate.
220 if (isLegacy()) {
221 // Old non-msgpack format.
222 unsigned NumUsedSgprsKey = getScratchSizeKey(CC) +
223 PALMD::Key::VS_NUM_USED_SGPRS -
224 PALMD::Key::VS_SCRATCH_SIZE;
225 setRegister(NumUsedSgprsKey, Val);
226 return;
227 }
228 // Msgpack format.
229 getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(Val);
230}
231
232// Set the scratch size in the metadata.
234 if (isLegacy()) {
235 // Old non-msgpack format.
237 return;
238 }
239 // Msgpack format.
240 getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(Val);
241}
242
243// Set the stack frame size of a function in the metadata.
245 auto Node = getShaderFunction(FnName);
246 Node[".stack_frame_size_in_bytes"] = MsgPackDoc.getNode(Val);
247 Node[".backend_stack_size"] = MsgPackDoc.getNode(Val);
248}
249
250// Set the amount of LDS used in bytes in the metadata.
252 auto Node = getShaderFunction(FnName);
253 Node[".lds_size"] = MsgPackDoc.getNode(Val);
254}
255
256// Set the number of used vgprs in the metadata.
258 unsigned Val) {
259 auto Node = getShaderFunction(FnName);
260 Node[".vgpr_count"] = MsgPackDoc.getNode(Val);
261}
262
263// Set the number of used vgprs in the metadata.
265 unsigned Val) {
266 auto Node = getShaderFunction(FnName);
267 Node[".sgpr_count"] = MsgPackDoc.getNode(Val);
268}
269
270// Set the hardware register bit in PAL metadata to enable wave32 on the
271// shader of the given calling convention.
273 switch (CC) {
276 break;
279 break;
282 break;
285 break;
289 break;
290 }
291}
292
293// Convert a register number to name, for display by toString().
294// Returns nullptr if none.
295static const char *getRegisterName(unsigned RegNum) {
296 // Table of registers.
297 static const struct RegInfo {
298 unsigned Num;
299 const char *Name;
300 } RegInfoTable[] = {
301 // Registers that code generation sets/modifies metadata for.
302 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS, "SPI_SHADER_PGM_RSRC1_VS"},
303 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS + 1, "SPI_SHADER_PGM_RSRC2_VS"},
304 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS, "SPI_SHADER_PGM_RSRC1_LS"},
305 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1, "SPI_SHADER_PGM_RSRC2_LS"},
306 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS, "SPI_SHADER_PGM_RSRC1_HS"},
307 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1, "SPI_SHADER_PGM_RSRC2_HS"},
308 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES, "SPI_SHADER_PGM_RSRC1_ES"},
309 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, "SPI_SHADER_PGM_RSRC2_ES"},
310 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, "SPI_SHADER_PGM_RSRC1_GS"},
311 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, "SPI_SHADER_PGM_RSRC2_GS"},
312 {PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, "COMPUTE_DISPATCH_INITIATOR"},
313 {PALMD::R_2E12_COMPUTE_PGM_RSRC1, "COMPUTE_PGM_RSRC1"},
314 {PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, "COMPUTE_PGM_RSRC2"},
315 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, "SPI_SHADER_PGM_RSRC1_PS"},
316 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, "SPI_SHADER_PGM_RSRC2_PS"},
317 {PALMD::R_A1B3_SPI_PS_INPUT_ENA, "SPI_PS_INPUT_ENA"},
318 {PALMD::R_A1B4_SPI_PS_INPUT_ADDR, "SPI_PS_INPUT_ADDR"},
319 {PALMD::R_A1B6_SPI_PS_IN_CONTROL, "SPI_PS_IN_CONTROL"},
320 {PALMD::R_A2D5_VGT_SHADER_STAGES_EN, "VGT_SHADER_STAGES_EN"},
321
322 // Registers not known to code generation.
323 {0x2c07, "SPI_SHADER_PGM_RSRC3_PS"},
324 {0x2c46, "SPI_SHADER_PGM_RSRC3_VS"},
325 {0x2c87, "SPI_SHADER_PGM_RSRC3_GS"},
326 {0x2cc7, "SPI_SHADER_PGM_RSRC3_ES"},
327 {0x2d07, "SPI_SHADER_PGM_RSRC3_HS"},
328 {0x2d47, "SPI_SHADER_PGM_RSRC3_LS"},
329
330 {0xa1c3, "SPI_SHADER_POS_FORMAT"},
331 {0xa1b1, "SPI_VS_OUT_CONFIG"},
332 {0xa207, "PA_CL_VS_OUT_CNTL"},
333 {0xa204, "PA_CL_CLIP_CNTL"},
334 {0xa206, "PA_CL_VTE_CNTL"},
335 {0xa2f9, "PA_SU_VTX_CNTL"},
336 {0xa293, "PA_SC_MODE_CNTL_1"},
337 {0xa2a1, "VGT_PRIMITIVEID_EN"},
338 {0x2c81, "SPI_SHADER_PGM_RSRC4_GS"},
339 {0x2e18, "COMPUTE_TMPRING_SIZE"},
340 {0xa1b5, "SPI_INTERP_CONTROL_0"},
341 {0xa1ba, "SPI_TMPRING_SIZE"},
342 {0xa1c4, "SPI_SHADER_Z_FORMAT"},
343 {0xa1c5, "SPI_SHADER_COL_FORMAT"},
344 {0xa203, "DB_SHADER_CONTROL"},
345 {0xa08f, "CB_SHADER_MASK"},
346 {0xa191, "SPI_PS_INPUT_CNTL_0"},
347 {0xa192, "SPI_PS_INPUT_CNTL_1"},
348 {0xa193, "SPI_PS_INPUT_CNTL_2"},
349 {0xa194, "SPI_PS_INPUT_CNTL_3"},
350 {0xa195, "SPI_PS_INPUT_CNTL_4"},
351 {0xa196, "SPI_PS_INPUT_CNTL_5"},
352 {0xa197, "SPI_PS_INPUT_CNTL_6"},
353 {0xa198, "SPI_PS_INPUT_CNTL_7"},
354 {0xa199, "SPI_PS_INPUT_CNTL_8"},
355 {0xa19a, "SPI_PS_INPUT_CNTL_9"},
356 {0xa19b, "SPI_PS_INPUT_CNTL_10"},
357 {0xa19c, "SPI_PS_INPUT_CNTL_11"},
358 {0xa19d, "SPI_PS_INPUT_CNTL_12"},
359 {0xa19e, "SPI_PS_INPUT_CNTL_13"},
360 {0xa19f, "SPI_PS_INPUT_CNTL_14"},
361 {0xa1a0, "SPI_PS_INPUT_CNTL_15"},
362 {0xa1a1, "SPI_PS_INPUT_CNTL_16"},
363 {0xa1a2, "SPI_PS_INPUT_CNTL_17"},
364 {0xa1a3, "SPI_PS_INPUT_CNTL_18"},
365 {0xa1a4, "SPI_PS_INPUT_CNTL_19"},
366 {0xa1a5, "SPI_PS_INPUT_CNTL_20"},
367 {0xa1a6, "SPI_PS_INPUT_CNTL_21"},
368 {0xa1a7, "SPI_PS_INPUT_CNTL_22"},
369 {0xa1a8, "SPI_PS_INPUT_CNTL_23"},
370 {0xa1a9, "SPI_PS_INPUT_CNTL_24"},
371 {0xa1aa, "SPI_PS_INPUT_CNTL_25"},
372 {0xa1ab, "SPI_PS_INPUT_CNTL_26"},
373 {0xa1ac, "SPI_PS_INPUT_CNTL_27"},
374 {0xa1ad, "SPI_PS_INPUT_CNTL_28"},
375 {0xa1ae, "SPI_PS_INPUT_CNTL_29"},
376 {0xa1af, "SPI_PS_INPUT_CNTL_30"},
377 {0xa1b0, "SPI_PS_INPUT_CNTL_31"},
378
379 {0xa2ce, "VGT_GS_MAX_VERT_OUT"},
380 {0xa2ab, "VGT_ESGS_RING_ITEMSIZE"},
381 {0xa290, "VGT_GS_MODE"},
382 {0xa291, "VGT_GS_ONCHIP_CNTL"},
383 {0xa2d7, "VGT_GS_VERT_ITEMSIZE"},
384 {0xa2d8, "VGT_GS_VERT_ITEMSIZE_1"},
385 {0xa2d9, "VGT_GS_VERT_ITEMSIZE_2"},
386 {0xa2da, "VGT_GS_VERT_ITEMSIZE_3"},
387 {0xa298, "VGT_GSVS_RING_OFFSET_1"},
388 {0xa299, "VGT_GSVS_RING_OFFSET_2"},
389 {0xa29a, "VGT_GSVS_RING_OFFSET_3"},
390
391 {0xa2e4, "VGT_GS_INSTANCE_CNT"},
392 {0xa297, "VGT_GS_PER_VS"},
393 {0xa29b, "VGT_GS_OUT_PRIM_TYPE"},
394 {0xa2ac, "VGT_GSVS_RING_ITEMSIZE"},
395
396 {0xa2ad, "VGT_REUSE_OFF"},
397 {0xa1b8, "SPI_BARYC_CNTL"},
398
399 {0x2c4c, "SPI_SHADER_USER_DATA_VS_0"},
400 {0x2c4d, "SPI_SHADER_USER_DATA_VS_1"},
401 {0x2c4e, "SPI_SHADER_USER_DATA_VS_2"},
402 {0x2c4f, "SPI_SHADER_USER_DATA_VS_3"},
403 {0x2c50, "SPI_SHADER_USER_DATA_VS_4"},
404 {0x2c51, "SPI_SHADER_USER_DATA_VS_5"},
405 {0x2c52, "SPI_SHADER_USER_DATA_VS_6"},
406 {0x2c53, "SPI_SHADER_USER_DATA_VS_7"},
407 {0x2c54, "SPI_SHADER_USER_DATA_VS_8"},
408 {0x2c55, "SPI_SHADER_USER_DATA_VS_9"},
409 {0x2c56, "SPI_SHADER_USER_DATA_VS_10"},
410 {0x2c57, "SPI_SHADER_USER_DATA_VS_11"},
411 {0x2c58, "SPI_SHADER_USER_DATA_VS_12"},
412 {0x2c59, "SPI_SHADER_USER_DATA_VS_13"},
413 {0x2c5a, "SPI_SHADER_USER_DATA_VS_14"},
414 {0x2c5b, "SPI_SHADER_USER_DATA_VS_15"},
415 {0x2c5c, "SPI_SHADER_USER_DATA_VS_16"},
416 {0x2c5d, "SPI_SHADER_USER_DATA_VS_17"},
417 {0x2c5e, "SPI_SHADER_USER_DATA_VS_18"},
418 {0x2c5f, "SPI_SHADER_USER_DATA_VS_19"},
419 {0x2c60, "SPI_SHADER_USER_DATA_VS_20"},
420 {0x2c61, "SPI_SHADER_USER_DATA_VS_21"},
421 {0x2c62, "SPI_SHADER_USER_DATA_VS_22"},
422 {0x2c63, "SPI_SHADER_USER_DATA_VS_23"},
423 {0x2c64, "SPI_SHADER_USER_DATA_VS_24"},
424 {0x2c65, "SPI_SHADER_USER_DATA_VS_25"},
425 {0x2c66, "SPI_SHADER_USER_DATA_VS_26"},
426 {0x2c67, "SPI_SHADER_USER_DATA_VS_27"},
427 {0x2c68, "SPI_SHADER_USER_DATA_VS_28"},
428 {0x2c69, "SPI_SHADER_USER_DATA_VS_29"},
429 {0x2c6a, "SPI_SHADER_USER_DATA_VS_30"},
430 {0x2c6b, "SPI_SHADER_USER_DATA_VS_31"},
431
432 {0x2c8c, "SPI_SHADER_USER_DATA_GS_0"},
433 {0x2c8d, "SPI_SHADER_USER_DATA_GS_1"},
434 {0x2c8e, "SPI_SHADER_USER_DATA_GS_2"},
435 {0x2c8f, "SPI_SHADER_USER_DATA_GS_3"},
436 {0x2c90, "SPI_SHADER_USER_DATA_GS_4"},
437 {0x2c91, "SPI_SHADER_USER_DATA_GS_5"},
438 {0x2c92, "SPI_SHADER_USER_DATA_GS_6"},
439 {0x2c93, "SPI_SHADER_USER_DATA_GS_7"},
440 {0x2c94, "SPI_SHADER_USER_DATA_GS_8"},
441 {0x2c95, "SPI_SHADER_USER_DATA_GS_9"},
442 {0x2c96, "SPI_SHADER_USER_DATA_GS_10"},
443 {0x2c97, "SPI_SHADER_USER_DATA_GS_11"},
444 {0x2c98, "SPI_SHADER_USER_DATA_GS_12"},
445 {0x2c99, "SPI_SHADER_USER_DATA_GS_13"},
446 {0x2c9a, "SPI_SHADER_USER_DATA_GS_14"},
447 {0x2c9b, "SPI_SHADER_USER_DATA_GS_15"},
448 {0x2c9c, "SPI_SHADER_USER_DATA_GS_16"},
449 {0x2c9d, "SPI_SHADER_USER_DATA_GS_17"},
450 {0x2c9e, "SPI_SHADER_USER_DATA_GS_18"},
451 {0x2c9f, "SPI_SHADER_USER_DATA_GS_19"},
452 {0x2ca0, "SPI_SHADER_USER_DATA_GS_20"},
453 {0x2ca1, "SPI_SHADER_USER_DATA_GS_21"},
454 {0x2ca2, "SPI_SHADER_USER_DATA_GS_22"},
455 {0x2ca3, "SPI_SHADER_USER_DATA_GS_23"},
456 {0x2ca4, "SPI_SHADER_USER_DATA_GS_24"},
457 {0x2ca5, "SPI_SHADER_USER_DATA_GS_25"},
458 {0x2ca6, "SPI_SHADER_USER_DATA_GS_26"},
459 {0x2ca7, "SPI_SHADER_USER_DATA_GS_27"},
460 {0x2ca8, "SPI_SHADER_USER_DATA_GS_28"},
461 {0x2ca9, "SPI_SHADER_USER_DATA_GS_29"},
462 {0x2caa, "SPI_SHADER_USER_DATA_GS_30"},
463 {0x2cab, "SPI_SHADER_USER_DATA_GS_31"},
464
465 {0x2ccc, "SPI_SHADER_USER_DATA_ES_0"},
466 {0x2ccd, "SPI_SHADER_USER_DATA_ES_1"},
467 {0x2cce, "SPI_SHADER_USER_DATA_ES_2"},
468 {0x2ccf, "SPI_SHADER_USER_DATA_ES_3"},
469 {0x2cd0, "SPI_SHADER_USER_DATA_ES_4"},
470 {0x2cd1, "SPI_SHADER_USER_DATA_ES_5"},
471 {0x2cd2, "SPI_SHADER_USER_DATA_ES_6"},
472 {0x2cd3, "SPI_SHADER_USER_DATA_ES_7"},
473 {0x2cd4, "SPI_SHADER_USER_DATA_ES_8"},
474 {0x2cd5, "SPI_SHADER_USER_DATA_ES_9"},
475 {0x2cd6, "SPI_SHADER_USER_DATA_ES_10"},
476 {0x2cd7, "SPI_SHADER_USER_DATA_ES_11"},
477 {0x2cd8, "SPI_SHADER_USER_DATA_ES_12"},
478 {0x2cd9, "SPI_SHADER_USER_DATA_ES_13"},
479 {0x2cda, "SPI_SHADER_USER_DATA_ES_14"},
480 {0x2cdb, "SPI_SHADER_USER_DATA_ES_15"},
481 {0x2cdc, "SPI_SHADER_USER_DATA_ES_16"},
482 {0x2cdd, "SPI_SHADER_USER_DATA_ES_17"},
483 {0x2cde, "SPI_SHADER_USER_DATA_ES_18"},
484 {0x2cdf, "SPI_SHADER_USER_DATA_ES_19"},
485 {0x2ce0, "SPI_SHADER_USER_DATA_ES_20"},
486 {0x2ce1, "SPI_SHADER_USER_DATA_ES_21"},
487 {0x2ce2, "SPI_SHADER_USER_DATA_ES_22"},
488 {0x2ce3, "SPI_SHADER_USER_DATA_ES_23"},
489 {0x2ce4, "SPI_SHADER_USER_DATA_ES_24"},
490 {0x2ce5, "SPI_SHADER_USER_DATA_ES_25"},
491 {0x2ce6, "SPI_SHADER_USER_DATA_ES_26"},
492 {0x2ce7, "SPI_SHADER_USER_DATA_ES_27"},
493 {0x2ce8, "SPI_SHADER_USER_DATA_ES_28"},
494 {0x2ce9, "SPI_SHADER_USER_DATA_ES_29"},
495 {0x2cea, "SPI_SHADER_USER_DATA_ES_30"},
496 {0x2ceb, "SPI_SHADER_USER_DATA_ES_31"},
497
498 {0x2c0c, "SPI_SHADER_USER_DATA_PS_0"},
499 {0x2c0d, "SPI_SHADER_USER_DATA_PS_1"},
500 {0x2c0e, "SPI_SHADER_USER_DATA_PS_2"},
501 {0x2c0f, "SPI_SHADER_USER_DATA_PS_3"},
502 {0x2c10, "SPI_SHADER_USER_DATA_PS_4"},
503 {0x2c11, "SPI_SHADER_USER_DATA_PS_5"},
504 {0x2c12, "SPI_SHADER_USER_DATA_PS_6"},
505 {0x2c13, "SPI_SHADER_USER_DATA_PS_7"},
506 {0x2c14, "SPI_SHADER_USER_DATA_PS_8"},
507 {0x2c15, "SPI_SHADER_USER_DATA_PS_9"},
508 {0x2c16, "SPI_SHADER_USER_DATA_PS_10"},
509 {0x2c17, "SPI_SHADER_USER_DATA_PS_11"},
510 {0x2c18, "SPI_SHADER_USER_DATA_PS_12"},
511 {0x2c19, "SPI_SHADER_USER_DATA_PS_13"},
512 {0x2c1a, "SPI_SHADER_USER_DATA_PS_14"},
513 {0x2c1b, "SPI_SHADER_USER_DATA_PS_15"},
514 {0x2c1c, "SPI_SHADER_USER_DATA_PS_16"},
515 {0x2c1d, "SPI_SHADER_USER_DATA_PS_17"},
516 {0x2c1e, "SPI_SHADER_USER_DATA_PS_18"},
517 {0x2c1f, "SPI_SHADER_USER_DATA_PS_19"},
518 {0x2c20, "SPI_SHADER_USER_DATA_PS_20"},
519 {0x2c21, "SPI_SHADER_USER_DATA_PS_21"},
520 {0x2c22, "SPI_SHADER_USER_DATA_PS_22"},
521 {0x2c23, "SPI_SHADER_USER_DATA_PS_23"},
522 {0x2c24, "SPI_SHADER_USER_DATA_PS_24"},
523 {0x2c25, "SPI_SHADER_USER_DATA_PS_25"},
524 {0x2c26, "SPI_SHADER_USER_DATA_PS_26"},
525 {0x2c27, "SPI_SHADER_USER_DATA_PS_27"},
526 {0x2c28, "SPI_SHADER_USER_DATA_PS_28"},
527 {0x2c29, "SPI_SHADER_USER_DATA_PS_29"},
528 {0x2c2a, "SPI_SHADER_USER_DATA_PS_30"},
529 {0x2c2b, "SPI_SHADER_USER_DATA_PS_31"},
530
531 {0x2e40, "COMPUTE_USER_DATA_0"},
532 {0x2e41, "COMPUTE_USER_DATA_1"},
533 {0x2e42, "COMPUTE_USER_DATA_2"},
534 {0x2e43, "COMPUTE_USER_DATA_3"},
535 {0x2e44, "COMPUTE_USER_DATA_4"},
536 {0x2e45, "COMPUTE_USER_DATA_5"},
537 {0x2e46, "COMPUTE_USER_DATA_6"},
538 {0x2e47, "COMPUTE_USER_DATA_7"},
539 {0x2e48, "COMPUTE_USER_DATA_8"},
540 {0x2e49, "COMPUTE_USER_DATA_9"},
541 {0x2e4a, "COMPUTE_USER_DATA_10"},
542 {0x2e4b, "COMPUTE_USER_DATA_11"},
543 {0x2e4c, "COMPUTE_USER_DATA_12"},
544 {0x2e4d, "COMPUTE_USER_DATA_13"},
545 {0x2e4e, "COMPUTE_USER_DATA_14"},
546 {0x2e4f, "COMPUTE_USER_DATA_15"},
547
548 {0x2e07, "COMPUTE_NUM_THREAD_X"},
549 {0x2e08, "COMPUTE_NUM_THREAD_Y"},
550 {0x2e09, "COMPUTE_NUM_THREAD_Z"},
551 {0xa2db, "VGT_TF_PARAM"},
552 {0xa2d6, "VGT_LS_HS_CONFIG"},
553 {0xa287, "VGT_HOS_MIN_TESS_LEVEL"},
554 {0xa286, "VGT_HOS_MAX_TESS_LEVEL"},
555 {0xa2f8, "PA_SC_AA_CONFIG"},
556 {0xa310, "PA_SC_SHADER_CONTROL"},
557 {0xa313, "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"},
558
559 {0x2d0c, "SPI_SHADER_USER_DATA_HS_0"},
560 {0x2d0d, "SPI_SHADER_USER_DATA_HS_1"},
561 {0x2d0e, "SPI_SHADER_USER_DATA_HS_2"},
562 {0x2d0f, "SPI_SHADER_USER_DATA_HS_3"},
563 {0x2d10, "SPI_SHADER_USER_DATA_HS_4"},
564 {0x2d11, "SPI_SHADER_USER_DATA_HS_5"},
565 {0x2d12, "SPI_SHADER_USER_DATA_HS_6"},
566 {0x2d13, "SPI_SHADER_USER_DATA_HS_7"},
567 {0x2d14, "SPI_SHADER_USER_DATA_HS_8"},
568 {0x2d15, "SPI_SHADER_USER_DATA_HS_9"},
569 {0x2d16, "SPI_SHADER_USER_DATA_HS_10"},
570 {0x2d17, "SPI_SHADER_USER_DATA_HS_11"},
571 {0x2d18, "SPI_SHADER_USER_DATA_HS_12"},
572 {0x2d19, "SPI_SHADER_USER_DATA_HS_13"},
573 {0x2d1a, "SPI_SHADER_USER_DATA_HS_14"},
574 {0x2d1b, "SPI_SHADER_USER_DATA_HS_15"},
575 {0x2d1c, "SPI_SHADER_USER_DATA_HS_16"},
576 {0x2d1d, "SPI_SHADER_USER_DATA_HS_17"},
577 {0x2d1e, "SPI_SHADER_USER_DATA_HS_18"},
578 {0x2d1f, "SPI_SHADER_USER_DATA_HS_19"},
579 {0x2d20, "SPI_SHADER_USER_DATA_HS_20"},
580 {0x2d21, "SPI_SHADER_USER_DATA_HS_21"},
581 {0x2d22, "SPI_SHADER_USER_DATA_HS_22"},
582 {0x2d23, "SPI_SHADER_USER_DATA_HS_23"},
583 {0x2d24, "SPI_SHADER_USER_DATA_HS_24"},
584 {0x2d25, "SPI_SHADER_USER_DATA_HS_25"},
585 {0x2d26, "SPI_SHADER_USER_DATA_HS_26"},
586 {0x2d27, "SPI_SHADER_USER_DATA_HS_27"},
587 {0x2d28, "SPI_SHADER_USER_DATA_HS_28"},
588 {0x2d29, "SPI_SHADER_USER_DATA_HS_29"},
589 {0x2d2a, "SPI_SHADER_USER_DATA_HS_30"},
590 {0x2d2b, "SPI_SHADER_USER_DATA_HS_31"},
591
592 {0x2d4c, "SPI_SHADER_USER_DATA_LS_0"},
593 {0x2d4d, "SPI_SHADER_USER_DATA_LS_1"},
594 {0x2d4e, "SPI_SHADER_USER_DATA_LS_2"},
595 {0x2d4f, "SPI_SHADER_USER_DATA_LS_3"},
596 {0x2d50, "SPI_SHADER_USER_DATA_LS_4"},
597 {0x2d51, "SPI_SHADER_USER_DATA_LS_5"},
598 {0x2d52, "SPI_SHADER_USER_DATA_LS_6"},
599 {0x2d53, "SPI_SHADER_USER_DATA_LS_7"},
600 {0x2d54, "SPI_SHADER_USER_DATA_LS_8"},
601 {0x2d55, "SPI_SHADER_USER_DATA_LS_9"},
602 {0x2d56, "SPI_SHADER_USER_DATA_LS_10"},
603 {0x2d57, "SPI_SHADER_USER_DATA_LS_11"},
604 {0x2d58, "SPI_SHADER_USER_DATA_LS_12"},
605 {0x2d59, "SPI_SHADER_USER_DATA_LS_13"},
606 {0x2d5a, "SPI_SHADER_USER_DATA_LS_14"},
607 {0x2d5b, "SPI_SHADER_USER_DATA_LS_15"},
608
609 {0xa2aa, "IA_MULTI_VGT_PARAM"},
610 {0xa2a5, "VGT_GS_MAX_PRIMS_PER_SUBGROUP"},
611 {0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"},
612 {0xa2e5, "VGT_STRMOUT_CONFIG"},
613 {0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"},
614 {0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"},
615 {0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"},
616 {0xa2c1, "VGT_STRMOUT_VTX_STRIDE_3"},
617 {0xa316, "VGT_VERTEX_REUSE_BLOCK_CNTL"},
618
619 {0x2e28, "COMPUTE_PGM_RSRC3"},
620 {0x2e2a, "COMPUTE_SHADER_CHKSUM"},
621 {0x2e24, "COMPUTE_USER_ACCUM_0"},
622 {0x2e25, "COMPUTE_USER_ACCUM_1"},
623 {0x2e26, "COMPUTE_USER_ACCUM_2"},
624 {0x2e27, "COMPUTE_USER_ACCUM_3"},
625 {0xa1ff, "GE_MAX_OUTPUT_PER_SUBGROUP"},
626 {0xa2d3, "GE_NGG_SUBGRP_CNTL"},
627 {0xc25f, "GE_STEREO_CNTL"},
628 {0xc262, "GE_USER_VGPR_EN"},
629 {0xc258, "IA_MULTI_VGT_PARAM_PIPED"},
630 {0xa210, "PA_STEREO_CNTL"},
631 {0xa1c2, "SPI_SHADER_IDX_FORMAT"},
632 {0x2c80, "SPI_SHADER_PGM_CHKSUM_GS"},
633 {0x2d00, "SPI_SHADER_PGM_CHKSUM_HS"},
634 {0x2c06, "SPI_SHADER_PGM_CHKSUM_PS"},
635 {0x2c45, "SPI_SHADER_PGM_CHKSUM_VS"},
636 {0x2c88, "SPI_SHADER_PGM_LO_GS"},
637 {0x2cb2, "SPI_SHADER_USER_ACCUM_ESGS_0"},
638 {0x2cb3, "SPI_SHADER_USER_ACCUM_ESGS_1"},
639 {0x2cb4, "SPI_SHADER_USER_ACCUM_ESGS_2"},
640 {0x2cb5, "SPI_SHADER_USER_ACCUM_ESGS_3"},
641 {0x2d32, "SPI_SHADER_USER_ACCUM_LSHS_0"},
642 {0x2d33, "SPI_SHADER_USER_ACCUM_LSHS_1"},
643 {0x2d34, "SPI_SHADER_USER_ACCUM_LSHS_2"},
644 {0x2d35, "SPI_SHADER_USER_ACCUM_LSHS_3"},
645 {0x2c32, "SPI_SHADER_USER_ACCUM_PS_0"},
646 {0x2c33, "SPI_SHADER_USER_ACCUM_PS_1"},
647 {0x2c34, "SPI_SHADER_USER_ACCUM_PS_2"},
648 {0x2c35, "SPI_SHADER_USER_ACCUM_PS_3"},
649 {0x2c72, "SPI_SHADER_USER_ACCUM_VS_0"},
650 {0x2c73, "SPI_SHADER_USER_ACCUM_VS_1"},
651 {0x2c74, "SPI_SHADER_USER_ACCUM_VS_2"},
652 {0x2c75, "SPI_SHADER_USER_ACCUM_VS_3"},
653
654 {0, nullptr}};
655 auto Entry = RegInfoTable;
656 for (; Entry->Num && Entry->Num != RegNum; ++Entry)
657 ;
658 return Entry->Name;
659}
660
661// Convert the accumulated PAL metadata into an asm directive.
663 String.clear();
664 if (!BlobType)
665 return;
667 if (isLegacy()) {
668 if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil)
669 return;
670 // Old linear reg=val format.
671 Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' ';
672 auto Regs = getRegisters();
673 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) {
674 if (I != Regs.begin())
675 Stream << ',';
676 unsigned Reg = I->first.getUInt();
677 unsigned Val = I->second.getUInt();
678 Stream << "0x" << Twine::utohexstr(Reg) << ",0x" << Twine::utohexstr(Val);
679 }
680 Stream << '\n';
681 return;
682 }
683
684 // New msgpack-based format -- output as YAML (with unsigned numbers in hex),
685 // but first change the registers map to use names.
686 MsgPackDoc.setHexMode();
687 auto &RegsObj = refRegisters();
688 auto OrigRegs = RegsObj.getMap();
689 RegsObj = MsgPackDoc.getMapNode();
690 for (auto I : OrigRegs) {
691 auto Key = I.first;
692 if (const char *RegName = getRegisterName(Key.getUInt())) {
693 std::string KeyName = Key.toString();
694 KeyName += " (";
695 KeyName += RegName;
696 KeyName += ')';
697 Key = MsgPackDoc.getNode(KeyName, /*Copy=*/true);
698 }
699 RegsObj.getMap()[Key] = I.second;
700 }
701
702 // Output as YAML.
703 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveBegin << '\n';
704 MsgPackDoc.toYAML(Stream);
705 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveEnd << '\n';
706
707 // Restore original registers map.
708 RegsObj = OrigRegs;
709}
710
711// Convert the accumulated PAL metadata into a binary blob for writing as
712// a .note record of the specified AMD type. Returns an empty blob if
713// there is no PAL metadata,
714void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) {
716 toLegacyBlob(Blob);
717 else if (Type)
718 toMsgPackBlob(Blob);
719}
720
721void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) {
722 Blob.clear();
723 auto Registers = getRegisters();
724 if (Registers.getMap().empty())
725 return;
728 for (auto I : Registers.getMap()) {
729 EW.write(uint32_t(I.first.getUInt()));
730 EW.write(uint32_t(I.second.getUInt()));
731 }
732}
733
734void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) {
735 Blob.clear();
736 MsgPackDoc.writeToBlob(Blob);
737}
738
739// Set PAL metadata from YAML text. Returns false if failed.
741 BlobType = ELF::NT_AMDGPU_METADATA;
742 if (!MsgPackDoc.fromYAML(S))
743 return false;
744
745 // In the registers map, some keys may be of the form "0xa191
746 // (SPI_PS_INPUT_CNTL_0)", in which case the YAML input code made it a
747 // string. We need to turn it into a number.
748 auto &RegsObj = refRegisters();
749 auto OrigRegs = RegsObj;
750 RegsObj = MsgPackDoc.getMapNode();
751 Registers = RegsObj.getMap();
752 bool Ok = true;
753 for (auto I : OrigRegs.getMap()) {
754 auto Key = I.first;
755 if (Key.getKind() == msgpack::Type::String) {
756 StringRef S = Key.getString();
757 uint64_t Val;
758 if (S.consumeInteger(0, Val)) {
759 Ok = false;
760 errs() << "Unrecognized PAL metadata register key '" << S << "'\n";
761 continue;
762 }
763 Key = MsgPackDoc.getNode(uint64_t(Val));
764 }
765 Registers.getMap()[Key] = I.second;
766 }
767 return Ok;
768}
769
770// Reference (create if necessary) the node for the registers map.
771msgpack::DocNode &AMDGPUPALMetadata::refRegisters() {
772 auto &N =
773 MsgPackDoc.getRoot()
774 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
775 .getArray(/*Convert=*/true)[0]
776 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".registers")];
777 N.getMap(/*Convert=*/true);
778 return N;
779}
780
781// Get (create if necessary) the registers map.
782msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() {
783 if (Registers.isEmpty())
784 Registers = refRegisters();
785 return Registers.getMap();
786}
787
788// Reference (create if necessary) the node for the shader functions map.
789msgpack::DocNode &AMDGPUPALMetadata::refShaderFunctions() {
790 auto &N =
791 MsgPackDoc.getRoot()
792 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
793 .getArray(/*Convert=*/true)[0]
794 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".shader_functions")];
795 N.getMap(/*Convert=*/true);
796 return N;
797}
798
799// Get (create if necessary) the shader functions map.
800msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunctions() {
801 if (ShaderFunctions.isEmpty())
802 ShaderFunctions = refShaderFunctions();
803 return ShaderFunctions.getMap();
804}
805
806// Get (create if necessary) a function in the shader functions map.
807msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunction(StringRef Name) {
808 auto Functions = getShaderFunctions();
809 return Functions[Name].getMap(/*Convert=*/true);
810}
811
812msgpack::DocNode &AMDGPUPALMetadata::refComputeRegisters() {
813 auto &N =
814 MsgPackDoc.getRoot()
815 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
816 .getArray(/*Convert=*/true)[0]
817 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".compute_registers")];
818 N.getMap(/*Convert=*/true);
819 return N;
820}
821
822msgpack::MapDocNode AMDGPUPALMetadata::getComputeRegisters() {
823 if (ComputeRegisters.isEmpty())
824 ComputeRegisters = refComputeRegisters();
825 return ComputeRegisters.getMap();
826}
827
828msgpack::DocNode &AMDGPUPALMetadata::refGraphicsRegisters() {
829 auto &N =
830 MsgPackDoc.getRoot()
831 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
832 .getArray(/*Convert=*/true)[0]
833 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".graphics_registers")];
834 N.getMap(/*Convert=*/true);
835 return N;
836}
837
838msgpack::MapDocNode AMDGPUPALMetadata::getGraphicsRegisters() {
839 if (GraphicsRegisters.isEmpty())
840 GraphicsRegisters = refGraphicsRegisters();
841 return GraphicsRegisters.getMap();
842}
843
844// Return the PAL metadata hardware shader stage name.
845static const char *getStageName(CallingConv::ID CC) {
846 switch (CC) {
848 return ".ps";
850 return ".vs";
852 return ".gs";
854 return ".es";
856 return ".hs";
858 return ".ls";
860 llvm_unreachable("Callable shader has no hardware stage");
861 default:
862 return ".cs";
863 }
864}
865
866msgpack::DocNode &AMDGPUPALMetadata::refHwStage() {
867 auto &N =
868 MsgPackDoc.getRoot()
869 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
870 .getArray(/*Convert=*/true)[0]
871 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".hardware_stages")];
872 N.getMap(/*Convert=*/true);
873 return N;
874}
875
876// Get (create if necessary) the .hardware_stages entry for the given calling
877// convention.
878msgpack::MapDocNode AMDGPUPALMetadata::getHwStage(unsigned CC) {
879 if (HwStages.isEmpty())
880 HwStages = refHwStage();
881 return HwStages.getMap()[getStageName(CC)].getMap(/*Convert=*/true);
882}
883
884// Get .note record vendor name of metadata blob to be emitted.
885const char *AMDGPUPALMetadata::getVendor() const {
886 return isLegacy() ? ElfNote::NoteNameV2 : ElfNote::NoteNameV3;
887}
888
889// Get .note record type of metadata blob to be emitted:
890// ELF::NT_AMD_PAL_METADATA (legacy key=val format), or
891// ELF::NT_AMDGPU_METADATA (MsgPack format), or
892// 0 (no PAL metadata).
894 return BlobType;
895}
896
897// Return whether the blob type is legacy PAL metadata.
898bool AMDGPUPALMetadata::isLegacy() const {
899 return BlobType == ELF::NT_AMD_PAL_METADATA;
900}
901
902// Set legacy PAL metadata format.
904 BlobType = ELF::NT_AMD_PAL_METADATA;
905}
906
907// Erase all PAL metadata.
909 MsgPackDoc.clear();
910 Registers = MsgPackDoc.getEmptyNode();
911 HwStages = MsgPackDoc.getEmptyNode();
912 ShaderFunctions = MsgPackDoc.getEmptyNode();
913}
914
915unsigned AMDGPUPALMetadata::getPALVersion(unsigned idx) {
916 assert(idx < 2 &&
917 "illegal index to PAL version - should be 0 (major) or 1 (minor)");
918 if (!VersionChecked) {
919 if (Version.isEmpty()) {
920 auto &M = MsgPackDoc.getRoot().getMap(/*Convert=*/true);
921 auto I = M.find(MsgPackDoc.getNode("amdpal.version"));
922 if (I != M.end())
923 Version = I->second;
924 }
925 VersionChecked = true;
926 }
927 if (Version.isEmpty())
928 // Default to 2.6 if there's no version info
929 return idx ? 6 : 2;
930 return Version.getArray()[idx].getUInt();
931}
932
933unsigned AMDGPUPALMetadata::getPALMajorVersion() { return getPALVersion(0); }
934
935unsigned AMDGPUPALMetadata::getPALMinorVersion() { return getPALVersion(1); }
936
937// Set the field in a given .hardware_stages entry
938void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, unsigned Val) {
939 getHwStage(CC)[field] = Val;
940}
941
942void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, bool Val) {
943 getHwStage(CC)[field] = Val;
944}
945
947 getComputeRegisters()[field] = Val;
948}
949
951 getComputeRegisters()[field] = Val;
952}
953
955 auto M = getComputeRegisters();
956 auto I = M.find(field);
957 return I == M.end() ? nullptr : &I->second;
958}
959
961 if (auto N = refComputeRegister(field))
962 return N->getUInt() == Val;
963 return false;
964}
965
967 if (auto N = refComputeRegister(field))
968 return N->getBool() == Val;
969 return false;
970}
971
973 getGraphicsRegisters()[field] = Val;
974}
975
977 getGraphicsRegisters()[field] = Val;
978}
979
981 unsigned Val) {
982 getGraphicsRegisters()[field1].getMap(true)[field2] = Val;
983}
984
986 bool Val) {
987 getGraphicsRegisters()[field1].getMap(true)[field2] = Val;
988}
AMDGPU metadata definitions and in-memory representations.
static unsigned getScratchSizeKey(CallingConv::ID CC)
static unsigned getRsrc1Reg(CallingConv::ID CC)
static const char * getStageName(CallingConv::ID CC)
PAL metadata handling.
Enums and constants for AMDGPU PT_NOTE sections.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
std::string Name
#define RegName(no)
#define I(x, y, z)
Definition: MD5.cpp:58
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)
Definition: MIParser.cpp:1422
Module.h This file contains the declarations for the Module class.
#define S_0286D8_PS_W32_EN(x)
Definition: SIDefines.h:1116
#define S_00B800_CS_W32_EN(x)
Definition: SIDefines.h:1118
#define S_028B54_GS_W32_EN(x)
Definition: SIDefines.h:1113
#define S_028B54_VS_W32_EN(x)
Definition: SIDefines.h:1114
#define S_028B54_HS_W32_EN(x)
Definition: SIDefines.h:1112
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
void setSpiPsInputAddr(unsigned Val)
void setEntryPoint(unsigned CC, StringRef Name)
const char * getVendor() const
void setFunctionScratchSize(StringRef FnName, unsigned Val)
bool setFromString(StringRef S)
void setNumUsedVgprs(unsigned CC, unsigned Val)
unsigned getRegister(unsigned Reg)
msgpack::DocNode * refComputeRegister(StringRef field)
void setFunctionNumUsedVgprs(StringRef FnName, unsigned Val)
bool setFromBlob(unsigned Type, StringRef Blob)
void setFunctionNumUsedSgprs(StringRef FnName, unsigned Val)
void setScratchSize(unsigned CC, unsigned Val)
void setRegister(unsigned Reg, unsigned Val)
void setHwStage(unsigned CC, StringRef field, unsigned Val)
void setRsrc1(unsigned CC, unsigned Val)
void setSpiPsInputEna(unsigned Val)
void setNumUsedAgprs(unsigned CC, unsigned Val)
void setGraphicsRegisters(StringRef field, unsigned Val)
bool checkComputeRegisters(StringRef field, unsigned Val)
void toBlob(unsigned Type, std::string &S)
void toString(std::string &S)
void setFunctionLdsSize(StringRef FnName, unsigned Val)
void setRsrc2(unsigned CC, unsigned Val)
void setNumUsedSgprs(unsigned CC, unsigned Val)
void setComputeRegisters(StringRef field, unsigned Val)
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool consumeInteger(unsigned Radix, T &Result)
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:503
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:131
static Twine utohexstr(const uint64_t &Val)
Definition: Twine.h:416
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
A node in a MsgPack Document.
MapDocNode & getMap(bool Convert=false)
Get a MapDocNode for a map node.
ArrayDocNode & getArray(bool Convert=false)
Get an ArrayDocNode for an array node.
MapDocNode getMapNode()
Create an empty Map node associated with this Document.
DocNode getEmptyNode()
Create an empty node associated with this Document.
DocNode & getRoot()
Get ref to the document's root element.
void clear()
Restore the Document to an empty state.
DocNode getNode()
Create a nil node associated with this Document.
void setHexMode(bool Val=true)
Set whether YAML output uses hex for UInt. Default off.
void toYAML(raw_ostream &OS)
Convert MsgPack Document to YAML text.
void writeToBlob(std::string &Blob)
Write a MsgPack document to a binary MsgPack blob.
bool readFromBlob(StringRef Blob, bool Multi, function_ref< int(DocNode *DestNode, DocNode SrcNode, DocNode MapKey)> Merger=[](DocNode *DestNode, DocNode SrcNode, DocNode MapKey) { return -1;})
Read a document from a binary msgpack blob, merging into anything already in the Document.
bool fromYAML(StringRef S)
Read YAML text into the MsgPack document. Returns false on failure.
A DocNode that is a map.
Reads MessagePack objects from memory, one at a time.
Definition: MsgPackReader.h:99
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:642
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const char NoteNameV2[]
Definition: AMDGPUPTNote.h:26
const char NoteNameV3[]
Definition: AMDGPUPTNote.h:27
constexpr char AssemblerDirective[]
PAL metadata (old linear format) assembler directive.
constexpr char AssemblerDirectiveBegin[]
PAL metadata (new MsgPack format) beginning assembler directive.
constexpr char AssemblerDirectiveEnd[]
PAL metadata (new MsgPack format) ending assembler directive.
@ AMDGPU_CS
Used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:194
@ AMDGPU_VS
Used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (vertex shader if tess...
Definition: CallingConv.h:185
@ AMDGPU_Gfx
Used for AMD graphics targets.
Definition: CallingConv.h:229
@ AMDGPU_HS
Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:203
@ AMDGPU_GS
Used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:188
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:191
@ AMDGPU_ES
Used for AMDPAL shader stage before geometry shader if geometry is in use.
Definition: CallingConv.h:215
@ AMDGPU_LS
Used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:210
@ NT_AMDGPU_METADATA
Definition: ELF.h:1780
@ NT_AMD_PAL_METADATA
Definition: ELF.h:1774
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
#define N
Adapter to write values to a stream in a particular byte order.
Definition: EndianStream.h:67