31 auto NamedMD = M.getNamedMetadata(
"amdgpu.pal.metadata.msgpack");
32 if (NamedMD && NamedMD->getNumOperands()) {
36 auto MDN = dyn_cast<MDTuple>(NamedMD->getOperand(0));
37 if (MDN && MDN->getNumOperands()) {
38 if (
auto MDS = dyn_cast<MDString>(MDN->getOperand(0)))
39 setFromMsgPackBlob(MDS->getString());
44 NamedMD = M.getNamedMetadata(
"amdgpu.pal.metadata");
45 if (!NamedMD || !NamedMD->getNumOperands()) {
54 auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
57 for (
unsigned I = 0,
E = Tuple->getNumOperands() & -2;
I !=
E;
I += 2) {
58 auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(
I));
59 auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(
I + 1));
62 setRegister(Key->getZExtValue(), Val->getZExtValue());
72 return setFromLegacyBlob(Blob);
73 return setFromMsgPackBlob(Blob);
77bool AMDGPUPALMetadata::setFromLegacyBlob(
StringRef Blob) {
85bool AMDGPUPALMetadata::setFromMsgPackBlob(
StringRef Blob) {
119 return PALMD::Key::PS_SCRATCH_SIZE;
121 return PALMD::Key::VS_SCRATCH_SIZE;
123 return PALMD::Key::GS_SCRATCH_SIZE;
125 return PALMD::Key::ES_SCRATCH_SIZE;
127 return PALMD::Key::HS_SCRATCH_SIZE;
129 return PALMD::Key::LS_SCRATCH_SIZE;
131 return PALMD::Key::CS_SCRATCH_SIZE;
161 auto Regs = getRegisters();
162 auto It = Regs.find(MsgPackDoc.
getNode(Reg));
163 if (It == Regs.end())
177 if (Reg >= 0x10000000)
180 auto &
N = getRegisters()[MsgPackDoc.
getNode(Reg)];
183 N =
N.getDocument()->getNode(Val);
191 getHwStage(
CC)[
".entry_point"] = MsgPackDoc.
getNode(
Name,
true);
202 PALMD::Key::VS_NUM_USED_VGPRS -
203 PALMD::Key::VS_SCRATCH_SIZE;
208 getHwStage(
CC)[
".vgpr_count"] = MsgPackDoc.
getNode(Val);
213 getHwStage(
CC)[
".agpr_count"] = Val;
223 PALMD::Key::VS_NUM_USED_SGPRS -
224 PALMD::Key::VS_SCRATCH_SIZE;
229 getHwStage(
CC)[
".sgpr_count"] = MsgPackDoc.
getNode(Val);
240 getHwStage(
CC)[
".scratch_memory_size"] = MsgPackDoc.
getNode(Val);
245 auto Node = getShaderFunction(FnName);
246 Node[
".stack_frame_size_in_bytes"] = MsgPackDoc.
getNode(Val);
247 Node[
".backend_stack_size"] = MsgPackDoc.
getNode(Val);
252 auto Node = getShaderFunction(FnName);
253 Node[
".lds_size"] = MsgPackDoc.
getNode(Val);
259 auto Node = getShaderFunction(FnName);
260 Node[
".vgpr_count"] = MsgPackDoc.
getNode(Val);
266 auto Node = getShaderFunction(FnName);
267 Node[
".sgpr_count"] = MsgPackDoc.
getNode(Val);
323 {0x2c07,
"SPI_SHADER_PGM_RSRC3_PS"},
324 {0x2c46,
"SPI_SHADER_PGM_RSRC3_VS"},
325 {0x2c87,
"SPI_SHADER_PGM_RSRC3_GS"},
326 {0x2cc7,
"SPI_SHADER_PGM_RSRC3_ES"},
327 {0x2d07,
"SPI_SHADER_PGM_RSRC3_HS"},
328 {0x2d47,
"SPI_SHADER_PGM_RSRC3_LS"},
330 {0xa1c3,
"SPI_SHADER_POS_FORMAT"},
331 {0xa1b1,
"SPI_VS_OUT_CONFIG"},
332 {0xa207,
"PA_CL_VS_OUT_CNTL"},
333 {0xa204,
"PA_CL_CLIP_CNTL"},
334 {0xa206,
"PA_CL_VTE_CNTL"},
335 {0xa2f9,
"PA_SU_VTX_CNTL"},
336 {0xa293,
"PA_SC_MODE_CNTL_1"},
337 {0xa2a1,
"VGT_PRIMITIVEID_EN"},
338 {0x2c81,
"SPI_SHADER_PGM_RSRC4_GS"},
339 {0x2e18,
"COMPUTE_TMPRING_SIZE"},
340 {0xa1b5,
"SPI_INTERP_CONTROL_0"},
341 {0xa1ba,
"SPI_TMPRING_SIZE"},
342 {0xa1c4,
"SPI_SHADER_Z_FORMAT"},
343 {0xa1c5,
"SPI_SHADER_COL_FORMAT"},
344 {0xa203,
"DB_SHADER_CONTROL"},
345 {0xa08f,
"CB_SHADER_MASK"},
346 {0xa191,
"SPI_PS_INPUT_CNTL_0"},
347 {0xa192,
"SPI_PS_INPUT_CNTL_1"},
348 {0xa193,
"SPI_PS_INPUT_CNTL_2"},
349 {0xa194,
"SPI_PS_INPUT_CNTL_3"},
350 {0xa195,
"SPI_PS_INPUT_CNTL_4"},
351 {0xa196,
"SPI_PS_INPUT_CNTL_5"},
352 {0xa197,
"SPI_PS_INPUT_CNTL_6"},
353 {0xa198,
"SPI_PS_INPUT_CNTL_7"},
354 {0xa199,
"SPI_PS_INPUT_CNTL_8"},
355 {0xa19a,
"SPI_PS_INPUT_CNTL_9"},
356 {0xa19b,
"SPI_PS_INPUT_CNTL_10"},
357 {0xa19c,
"SPI_PS_INPUT_CNTL_11"},
358 {0xa19d,
"SPI_PS_INPUT_CNTL_12"},
359 {0xa19e,
"SPI_PS_INPUT_CNTL_13"},
360 {0xa19f,
"SPI_PS_INPUT_CNTL_14"},
361 {0xa1a0,
"SPI_PS_INPUT_CNTL_15"},
362 {0xa1a1,
"SPI_PS_INPUT_CNTL_16"},
363 {0xa1a2,
"SPI_PS_INPUT_CNTL_17"},
364 {0xa1a3,
"SPI_PS_INPUT_CNTL_18"},
365 {0xa1a4,
"SPI_PS_INPUT_CNTL_19"},
366 {0xa1a5,
"SPI_PS_INPUT_CNTL_20"},
367 {0xa1a6,
"SPI_PS_INPUT_CNTL_21"},
368 {0xa1a7,
"SPI_PS_INPUT_CNTL_22"},
369 {0xa1a8,
"SPI_PS_INPUT_CNTL_23"},
370 {0xa1a9,
"SPI_PS_INPUT_CNTL_24"},
371 {0xa1aa,
"SPI_PS_INPUT_CNTL_25"},
372 {0xa1ab,
"SPI_PS_INPUT_CNTL_26"},
373 {0xa1ac,
"SPI_PS_INPUT_CNTL_27"},
374 {0xa1ad,
"SPI_PS_INPUT_CNTL_28"},
375 {0xa1ae,
"SPI_PS_INPUT_CNTL_29"},
376 {0xa1af,
"SPI_PS_INPUT_CNTL_30"},
377 {0xa1b0,
"SPI_PS_INPUT_CNTL_31"},
379 {0xa2ce,
"VGT_GS_MAX_VERT_OUT"},
380 {0xa2ab,
"VGT_ESGS_RING_ITEMSIZE"},
381 {0xa290,
"VGT_GS_MODE"},
382 {0xa291,
"VGT_GS_ONCHIP_CNTL"},
383 {0xa2d7,
"VGT_GS_VERT_ITEMSIZE"},
384 {0xa2d8,
"VGT_GS_VERT_ITEMSIZE_1"},
385 {0xa2d9,
"VGT_GS_VERT_ITEMSIZE_2"},
386 {0xa2da,
"VGT_GS_VERT_ITEMSIZE_3"},
387 {0xa298,
"VGT_GSVS_RING_OFFSET_1"},
388 {0xa299,
"VGT_GSVS_RING_OFFSET_2"},
389 {0xa29a,
"VGT_GSVS_RING_OFFSET_3"},
391 {0xa2e4,
"VGT_GS_INSTANCE_CNT"},
392 {0xa297,
"VGT_GS_PER_VS"},
393 {0xa29b,
"VGT_GS_OUT_PRIM_TYPE"},
394 {0xa2ac,
"VGT_GSVS_RING_ITEMSIZE"},
396 {0xa2ad,
"VGT_REUSE_OFF"},
397 {0xa1b8,
"SPI_BARYC_CNTL"},
399 {0x2c4c,
"SPI_SHADER_USER_DATA_VS_0"},
400 {0x2c4d,
"SPI_SHADER_USER_DATA_VS_1"},
401 {0x2c4e,
"SPI_SHADER_USER_DATA_VS_2"},
402 {0x2c4f,
"SPI_SHADER_USER_DATA_VS_3"},
403 {0x2c50,
"SPI_SHADER_USER_DATA_VS_4"},
404 {0x2c51,
"SPI_SHADER_USER_DATA_VS_5"},
405 {0x2c52,
"SPI_SHADER_USER_DATA_VS_6"},
406 {0x2c53,
"SPI_SHADER_USER_DATA_VS_7"},
407 {0x2c54,
"SPI_SHADER_USER_DATA_VS_8"},
408 {0x2c55,
"SPI_SHADER_USER_DATA_VS_9"},
409 {0x2c56,
"SPI_SHADER_USER_DATA_VS_10"},
410 {0x2c57,
"SPI_SHADER_USER_DATA_VS_11"},
411 {0x2c58,
"SPI_SHADER_USER_DATA_VS_12"},
412 {0x2c59,
"SPI_SHADER_USER_DATA_VS_13"},
413 {0x2c5a,
"SPI_SHADER_USER_DATA_VS_14"},
414 {0x2c5b,
"SPI_SHADER_USER_DATA_VS_15"},
415 {0x2c5c,
"SPI_SHADER_USER_DATA_VS_16"},
416 {0x2c5d,
"SPI_SHADER_USER_DATA_VS_17"},
417 {0x2c5e,
"SPI_SHADER_USER_DATA_VS_18"},
418 {0x2c5f,
"SPI_SHADER_USER_DATA_VS_19"},
419 {0x2c60,
"SPI_SHADER_USER_DATA_VS_20"},
420 {0x2c61,
"SPI_SHADER_USER_DATA_VS_21"},
421 {0x2c62,
"SPI_SHADER_USER_DATA_VS_22"},
422 {0x2c63,
"SPI_SHADER_USER_DATA_VS_23"},
423 {0x2c64,
"SPI_SHADER_USER_DATA_VS_24"},
424 {0x2c65,
"SPI_SHADER_USER_DATA_VS_25"},
425 {0x2c66,
"SPI_SHADER_USER_DATA_VS_26"},
426 {0x2c67,
"SPI_SHADER_USER_DATA_VS_27"},
427 {0x2c68,
"SPI_SHADER_USER_DATA_VS_28"},
428 {0x2c69,
"SPI_SHADER_USER_DATA_VS_29"},
429 {0x2c6a,
"SPI_SHADER_USER_DATA_VS_30"},
430 {0x2c6b,
"SPI_SHADER_USER_DATA_VS_31"},
432 {0x2c8c,
"SPI_SHADER_USER_DATA_GS_0"},
433 {0x2c8d,
"SPI_SHADER_USER_DATA_GS_1"},
434 {0x2c8e,
"SPI_SHADER_USER_DATA_GS_2"},
435 {0x2c8f,
"SPI_SHADER_USER_DATA_GS_3"},
436 {0x2c90,
"SPI_SHADER_USER_DATA_GS_4"},
437 {0x2c91,
"SPI_SHADER_USER_DATA_GS_5"},
438 {0x2c92,
"SPI_SHADER_USER_DATA_GS_6"},
439 {0x2c93,
"SPI_SHADER_USER_DATA_GS_7"},
440 {0x2c94,
"SPI_SHADER_USER_DATA_GS_8"},
441 {0x2c95,
"SPI_SHADER_USER_DATA_GS_9"},
442 {0x2c96,
"SPI_SHADER_USER_DATA_GS_10"},
443 {0x2c97,
"SPI_SHADER_USER_DATA_GS_11"},
444 {0x2c98,
"SPI_SHADER_USER_DATA_GS_12"},
445 {0x2c99,
"SPI_SHADER_USER_DATA_GS_13"},
446 {0x2c9a,
"SPI_SHADER_USER_DATA_GS_14"},
447 {0x2c9b,
"SPI_SHADER_USER_DATA_GS_15"},
448 {0x2c9c,
"SPI_SHADER_USER_DATA_GS_16"},
449 {0x2c9d,
"SPI_SHADER_USER_DATA_GS_17"},
450 {0x2c9e,
"SPI_SHADER_USER_DATA_GS_18"},
451 {0x2c9f,
"SPI_SHADER_USER_DATA_GS_19"},
452 {0x2ca0,
"SPI_SHADER_USER_DATA_GS_20"},
453 {0x2ca1,
"SPI_SHADER_USER_DATA_GS_21"},
454 {0x2ca2,
"SPI_SHADER_USER_DATA_GS_22"},
455 {0x2ca3,
"SPI_SHADER_USER_DATA_GS_23"},
456 {0x2ca4,
"SPI_SHADER_USER_DATA_GS_24"},
457 {0x2ca5,
"SPI_SHADER_USER_DATA_GS_25"},
458 {0x2ca6,
"SPI_SHADER_USER_DATA_GS_26"},
459 {0x2ca7,
"SPI_SHADER_USER_DATA_GS_27"},
460 {0x2ca8,
"SPI_SHADER_USER_DATA_GS_28"},
461 {0x2ca9,
"SPI_SHADER_USER_DATA_GS_29"},
462 {0x2caa,
"SPI_SHADER_USER_DATA_GS_30"},
463 {0x2cab,
"SPI_SHADER_USER_DATA_GS_31"},
465 {0x2ccc,
"SPI_SHADER_USER_DATA_ES_0"},
466 {0x2ccd,
"SPI_SHADER_USER_DATA_ES_1"},
467 {0x2cce,
"SPI_SHADER_USER_DATA_ES_2"},
468 {0x2ccf,
"SPI_SHADER_USER_DATA_ES_3"},
469 {0x2cd0,
"SPI_SHADER_USER_DATA_ES_4"},
470 {0x2cd1,
"SPI_SHADER_USER_DATA_ES_5"},
471 {0x2cd2,
"SPI_SHADER_USER_DATA_ES_6"},
472 {0x2cd3,
"SPI_SHADER_USER_DATA_ES_7"},
473 {0x2cd4,
"SPI_SHADER_USER_DATA_ES_8"},
474 {0x2cd5,
"SPI_SHADER_USER_DATA_ES_9"},
475 {0x2cd6,
"SPI_SHADER_USER_DATA_ES_10"},
476 {0x2cd7,
"SPI_SHADER_USER_DATA_ES_11"},
477 {0x2cd8,
"SPI_SHADER_USER_DATA_ES_12"},
478 {0x2cd9,
"SPI_SHADER_USER_DATA_ES_13"},
479 {0x2cda,
"SPI_SHADER_USER_DATA_ES_14"},
480 {0x2cdb,
"SPI_SHADER_USER_DATA_ES_15"},
481 {0x2cdc,
"SPI_SHADER_USER_DATA_ES_16"},
482 {0x2cdd,
"SPI_SHADER_USER_DATA_ES_17"},
483 {0x2cde,
"SPI_SHADER_USER_DATA_ES_18"},
484 {0x2cdf,
"SPI_SHADER_USER_DATA_ES_19"},
485 {0x2ce0,
"SPI_SHADER_USER_DATA_ES_20"},
486 {0x2ce1,
"SPI_SHADER_USER_DATA_ES_21"},
487 {0x2ce2,
"SPI_SHADER_USER_DATA_ES_22"},
488 {0x2ce3,
"SPI_SHADER_USER_DATA_ES_23"},
489 {0x2ce4,
"SPI_SHADER_USER_DATA_ES_24"},
490 {0x2ce5,
"SPI_SHADER_USER_DATA_ES_25"},
491 {0x2ce6,
"SPI_SHADER_USER_DATA_ES_26"},
492 {0x2ce7,
"SPI_SHADER_USER_DATA_ES_27"},
493 {0x2ce8,
"SPI_SHADER_USER_DATA_ES_28"},
494 {0x2ce9,
"SPI_SHADER_USER_DATA_ES_29"},
495 {0x2cea,
"SPI_SHADER_USER_DATA_ES_30"},
496 {0x2ceb,
"SPI_SHADER_USER_DATA_ES_31"},
498 {0x2c0c,
"SPI_SHADER_USER_DATA_PS_0"},
499 {0x2c0d,
"SPI_SHADER_USER_DATA_PS_1"},
500 {0x2c0e,
"SPI_SHADER_USER_DATA_PS_2"},
501 {0x2c0f,
"SPI_SHADER_USER_DATA_PS_3"},
502 {0x2c10,
"SPI_SHADER_USER_DATA_PS_4"},
503 {0x2c11,
"SPI_SHADER_USER_DATA_PS_5"},
504 {0x2c12,
"SPI_SHADER_USER_DATA_PS_6"},
505 {0x2c13,
"SPI_SHADER_USER_DATA_PS_7"},
506 {0x2c14,
"SPI_SHADER_USER_DATA_PS_8"},
507 {0x2c15,
"SPI_SHADER_USER_DATA_PS_9"},
508 {0x2c16,
"SPI_SHADER_USER_DATA_PS_10"},
509 {0x2c17,
"SPI_SHADER_USER_DATA_PS_11"},
510 {0x2c18,
"SPI_SHADER_USER_DATA_PS_12"},
511 {0x2c19,
"SPI_SHADER_USER_DATA_PS_13"},
512 {0x2c1a,
"SPI_SHADER_USER_DATA_PS_14"},
513 {0x2c1b,
"SPI_SHADER_USER_DATA_PS_15"},
514 {0x2c1c,
"SPI_SHADER_USER_DATA_PS_16"},
515 {0x2c1d,
"SPI_SHADER_USER_DATA_PS_17"},
516 {0x2c1e,
"SPI_SHADER_USER_DATA_PS_18"},
517 {0x2c1f,
"SPI_SHADER_USER_DATA_PS_19"},
518 {0x2c20,
"SPI_SHADER_USER_DATA_PS_20"},
519 {0x2c21,
"SPI_SHADER_USER_DATA_PS_21"},
520 {0x2c22,
"SPI_SHADER_USER_DATA_PS_22"},
521 {0x2c23,
"SPI_SHADER_USER_DATA_PS_23"},
522 {0x2c24,
"SPI_SHADER_USER_DATA_PS_24"},
523 {0x2c25,
"SPI_SHADER_USER_DATA_PS_25"},
524 {0x2c26,
"SPI_SHADER_USER_DATA_PS_26"},
525 {0x2c27,
"SPI_SHADER_USER_DATA_PS_27"},
526 {0x2c28,
"SPI_SHADER_USER_DATA_PS_28"},
527 {0x2c29,
"SPI_SHADER_USER_DATA_PS_29"},
528 {0x2c2a,
"SPI_SHADER_USER_DATA_PS_30"},
529 {0x2c2b,
"SPI_SHADER_USER_DATA_PS_31"},
531 {0x2e40,
"COMPUTE_USER_DATA_0"},
532 {0x2e41,
"COMPUTE_USER_DATA_1"},
533 {0x2e42,
"COMPUTE_USER_DATA_2"},
534 {0x2e43,
"COMPUTE_USER_DATA_3"},
535 {0x2e44,
"COMPUTE_USER_DATA_4"},
536 {0x2e45,
"COMPUTE_USER_DATA_5"},
537 {0x2e46,
"COMPUTE_USER_DATA_6"},
538 {0x2e47,
"COMPUTE_USER_DATA_7"},
539 {0x2e48,
"COMPUTE_USER_DATA_8"},
540 {0x2e49,
"COMPUTE_USER_DATA_9"},
541 {0x2e4a,
"COMPUTE_USER_DATA_10"},
542 {0x2e4b,
"COMPUTE_USER_DATA_11"},
543 {0x2e4c,
"COMPUTE_USER_DATA_12"},
544 {0x2e4d,
"COMPUTE_USER_DATA_13"},
545 {0x2e4e,
"COMPUTE_USER_DATA_14"},
546 {0x2e4f,
"COMPUTE_USER_DATA_15"},
548 {0x2e07,
"COMPUTE_NUM_THREAD_X"},
549 {0x2e08,
"COMPUTE_NUM_THREAD_Y"},
550 {0x2e09,
"COMPUTE_NUM_THREAD_Z"},
551 {0xa2db,
"VGT_TF_PARAM"},
552 {0xa2d6,
"VGT_LS_HS_CONFIG"},
553 {0xa287,
"VGT_HOS_MIN_TESS_LEVEL"},
554 {0xa286,
"VGT_HOS_MAX_TESS_LEVEL"},
555 {0xa2f8,
"PA_SC_AA_CONFIG"},
556 {0xa310,
"PA_SC_SHADER_CONTROL"},
557 {0xa313,
"PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"},
559 {0x2d0c,
"SPI_SHADER_USER_DATA_HS_0"},
560 {0x2d0d,
"SPI_SHADER_USER_DATA_HS_1"},
561 {0x2d0e,
"SPI_SHADER_USER_DATA_HS_2"},
562 {0x2d0f,
"SPI_SHADER_USER_DATA_HS_3"},
563 {0x2d10,
"SPI_SHADER_USER_DATA_HS_4"},
564 {0x2d11,
"SPI_SHADER_USER_DATA_HS_5"},
565 {0x2d12,
"SPI_SHADER_USER_DATA_HS_6"},
566 {0x2d13,
"SPI_SHADER_USER_DATA_HS_7"},
567 {0x2d14,
"SPI_SHADER_USER_DATA_HS_8"},
568 {0x2d15,
"SPI_SHADER_USER_DATA_HS_9"},
569 {0x2d16,
"SPI_SHADER_USER_DATA_HS_10"},
570 {0x2d17,
"SPI_SHADER_USER_DATA_HS_11"},
571 {0x2d18,
"SPI_SHADER_USER_DATA_HS_12"},
572 {0x2d19,
"SPI_SHADER_USER_DATA_HS_13"},
573 {0x2d1a,
"SPI_SHADER_USER_DATA_HS_14"},
574 {0x2d1b,
"SPI_SHADER_USER_DATA_HS_15"},
575 {0x2d1c,
"SPI_SHADER_USER_DATA_HS_16"},
576 {0x2d1d,
"SPI_SHADER_USER_DATA_HS_17"},
577 {0x2d1e,
"SPI_SHADER_USER_DATA_HS_18"},
578 {0x2d1f,
"SPI_SHADER_USER_DATA_HS_19"},
579 {0x2d20,
"SPI_SHADER_USER_DATA_HS_20"},
580 {0x2d21,
"SPI_SHADER_USER_DATA_HS_21"},
581 {0x2d22,
"SPI_SHADER_USER_DATA_HS_22"},
582 {0x2d23,
"SPI_SHADER_USER_DATA_HS_23"},
583 {0x2d24,
"SPI_SHADER_USER_DATA_HS_24"},
584 {0x2d25,
"SPI_SHADER_USER_DATA_HS_25"},
585 {0x2d26,
"SPI_SHADER_USER_DATA_HS_26"},
586 {0x2d27,
"SPI_SHADER_USER_DATA_HS_27"},
587 {0x2d28,
"SPI_SHADER_USER_DATA_HS_28"},
588 {0x2d29,
"SPI_SHADER_USER_DATA_HS_29"},
589 {0x2d2a,
"SPI_SHADER_USER_DATA_HS_30"},
590 {0x2d2b,
"SPI_SHADER_USER_DATA_HS_31"},
592 {0x2d4c,
"SPI_SHADER_USER_DATA_LS_0"},
593 {0x2d4d,
"SPI_SHADER_USER_DATA_LS_1"},
594 {0x2d4e,
"SPI_SHADER_USER_DATA_LS_2"},
595 {0x2d4f,
"SPI_SHADER_USER_DATA_LS_3"},
596 {0x2d50,
"SPI_SHADER_USER_DATA_LS_4"},
597 {0x2d51,
"SPI_SHADER_USER_DATA_LS_5"},
598 {0x2d52,
"SPI_SHADER_USER_DATA_LS_6"},
599 {0x2d53,
"SPI_SHADER_USER_DATA_LS_7"},
600 {0x2d54,
"SPI_SHADER_USER_DATA_LS_8"},
601 {0x2d55,
"SPI_SHADER_USER_DATA_LS_9"},
602 {0x2d56,
"SPI_SHADER_USER_DATA_LS_10"},
603 {0x2d57,
"SPI_SHADER_USER_DATA_LS_11"},
604 {0x2d58,
"SPI_SHADER_USER_DATA_LS_12"},
605 {0x2d59,
"SPI_SHADER_USER_DATA_LS_13"},
606 {0x2d5a,
"SPI_SHADER_USER_DATA_LS_14"},
607 {0x2d5b,
"SPI_SHADER_USER_DATA_LS_15"},
609 {0xa2aa,
"IA_MULTI_VGT_PARAM"},
610 {0xa2a5,
"VGT_GS_MAX_PRIMS_PER_SUBGROUP"},
611 {0xa2e6,
"VGT_STRMOUT_BUFFER_CONFIG"},
612 {0xa2e5,
"VGT_STRMOUT_CONFIG"},
613 {0xa2b5,
"VGT_STRMOUT_VTX_STRIDE_0"},
614 {0xa2b9,
"VGT_STRMOUT_VTX_STRIDE_1"},
615 {0xa2bd,
"VGT_STRMOUT_VTX_STRIDE_2"},
616 {0xa2c1,
"VGT_STRMOUT_VTX_STRIDE_3"},
617 {0xa316,
"VGT_VERTEX_REUSE_BLOCK_CNTL"},
619 {0x2e28,
"COMPUTE_PGM_RSRC3"},
620 {0x2e2a,
"COMPUTE_SHADER_CHKSUM"},
621 {0x2e24,
"COMPUTE_USER_ACCUM_0"},
622 {0x2e25,
"COMPUTE_USER_ACCUM_1"},
623 {0x2e26,
"COMPUTE_USER_ACCUM_2"},
624 {0x2e27,
"COMPUTE_USER_ACCUM_3"},
625 {0xa1ff,
"GE_MAX_OUTPUT_PER_SUBGROUP"},
626 {0xa2d3,
"GE_NGG_SUBGRP_CNTL"},
627 {0xc25f,
"GE_STEREO_CNTL"},
628 {0xc262,
"GE_USER_VGPR_EN"},
629 {0xc258,
"IA_MULTI_VGT_PARAM_PIPED"},
630 {0xa210,
"PA_STEREO_CNTL"},
631 {0xa1c2,
"SPI_SHADER_IDX_FORMAT"},
632 {0x2c80,
"SPI_SHADER_PGM_CHKSUM_GS"},
633 {0x2d00,
"SPI_SHADER_PGM_CHKSUM_HS"},
634 {0x2c06,
"SPI_SHADER_PGM_CHKSUM_PS"},
635 {0x2c45,
"SPI_SHADER_PGM_CHKSUM_VS"},
636 {0x2c88,
"SPI_SHADER_PGM_LO_GS"},
637 {0x2cb2,
"SPI_SHADER_USER_ACCUM_ESGS_0"},
638 {0x2cb3,
"SPI_SHADER_USER_ACCUM_ESGS_1"},
639 {0x2cb4,
"SPI_SHADER_USER_ACCUM_ESGS_2"},
640 {0x2cb5,
"SPI_SHADER_USER_ACCUM_ESGS_3"},
641 {0x2d32,
"SPI_SHADER_USER_ACCUM_LSHS_0"},
642 {0x2d33,
"SPI_SHADER_USER_ACCUM_LSHS_1"},
643 {0x2d34,
"SPI_SHADER_USER_ACCUM_LSHS_2"},
644 {0x2d35,
"SPI_SHADER_USER_ACCUM_LSHS_3"},
645 {0x2c32,
"SPI_SHADER_USER_ACCUM_PS_0"},
646 {0x2c33,
"SPI_SHADER_USER_ACCUM_PS_1"},
647 {0x2c34,
"SPI_SHADER_USER_ACCUM_PS_2"},
648 {0x2c35,
"SPI_SHADER_USER_ACCUM_PS_3"},
649 {0x2c72,
"SPI_SHADER_USER_ACCUM_VS_0"},
650 {0x2c73,
"SPI_SHADER_USER_ACCUM_VS_1"},
651 {0x2c74,
"SPI_SHADER_USER_ACCUM_VS_2"},
652 {0x2c75,
"SPI_SHADER_USER_ACCUM_VS_3"},
655 auto Entry = RegInfoTable;
656 for (; Entry->Num && Entry->Num != RegNum; ++Entry)
672 auto Regs = getRegisters();
673 for (
auto I = Regs.begin(),
E = Regs.end();
I !=
E; ++
I) {
674 if (
I != Regs.begin())
676 unsigned Reg =
I->first.getUInt();
677 unsigned Val =
I->second.getUInt();
687 auto &RegsObj = refRegisters();
688 auto OrigRegs = RegsObj.getMap();
690 for (
auto I : OrigRegs) {
693 std::string KeyName = Key.toString();
697 Key = MsgPackDoc.
getNode(KeyName,
true);
699 RegsObj.
getMap()[Key] =
I.second;
704 MsgPackDoc.
toYAML(Stream);
721void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) {
723 auto Registers = getRegisters();
728 for (
auto I : Registers.
getMap()) {
734void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) {
748 auto &RegsObj = refRegisters();
749 auto OrigRegs = RegsObj;
751 Registers = RegsObj.
getMap();
753 for (
auto I : OrigRegs.getMap()) {
760 errs() <<
"Unrecognized PAL metadata register key '" << S <<
"'\n";
765 Registers.
getMap()[Key] =
I.second;
784 Registers = refRegisters();
785 return Registers.
getMap();
802 ShaderFunctions = refShaderFunctions();
803 return ShaderFunctions.
getMap();
808 auto Functions = getShaderFunctions();
809 return Functions[
Name].getMap(
true);
823 if (ComputeRegisters.
isEmpty())
824 ComputeRegisters = refComputeRegisters();
825 return ComputeRegisters.
getMap();
839 if (GraphicsRegisters.
isEmpty())
840 GraphicsRegisters = refGraphicsRegisters();
841 return GraphicsRegisters.
getMap();
880 HwStages = refHwStage();
898bool AMDGPUPALMetadata::isLegacy()
const {
915unsigned AMDGPUPALMetadata::getPALVersion(
unsigned idx) {
917 "illegal index to PAL version - should be 0 (major) or 1 (minor)");
918 if (!VersionChecked) {
921 auto I = M.find(MsgPackDoc.
getNode(
"amdpal.version"));
925 VersionChecked =
true;
939 getHwStage(
CC)[field] = Val;
943 getHwStage(
CC)[field] = Val;
947 getComputeRegisters()[field] = Val;
951 getComputeRegisters()[field] = Val;
955 auto M = getComputeRegisters();
956 auto I = M.find(field);
957 return I == M.end() ? nullptr : &
I->second;
962 return N->getUInt() == Val;
968 return N->getBool() == Val;
973 getGraphicsRegisters()[field] = Val;
977 getGraphicsRegisters()[field] = Val;
982 getGraphicsRegisters()[field1].
getMap(
true)[field2] = Val;
987 getGraphicsRegisters()[field1].
getMap(
true)[field2] = Val;
Enums and constants for AMDGPU PT_NOTE sections.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)
Module.h This file contains the declarations for the Module class.
#define S_0286D8_PS_W32_EN(x)
#define S_00B800_CS_W32_EN(x)
#define S_028B54_GS_W32_EN(x)
#define S_028B54_VS_W32_EN(x)
#define S_028B54_HS_W32_EN(x)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A Module instance is used to store all the information related to an LLVM module.
StringRef - Represent a constant reference to a string, i.e.
bool consumeInteger(unsigned Radix, T &Result)
Parse the current string as an integer of the specified radix.
constexpr size_t size() const
size - Get the string size.
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
static Twine utohexstr(const uint64_t &Val)
The instances of the Type class are immutable: once they are created, they are never changed.
A node in a MsgPack Document.
MapDocNode & getMap(bool Convert=false)
Get a MapDocNode for a map node.
ArrayDocNode & getArray(bool Convert=false)
Get an ArrayDocNode for an array node.
MapDocNode getMapNode()
Create an empty Map node associated with this Document.
DocNode getEmptyNode()
Create an empty node associated with this Document.
DocNode & getRoot()
Get ref to the document's root element.
void clear()
Restore the Document to an empty state.
DocNode getNode()
Create a nil node associated with this Document.
void setHexMode(bool Val=true)
Set whether YAML output uses hex for UInt. Default off.
void toYAML(raw_ostream &OS)
Convert MsgPack Document to YAML text.
void writeToBlob(std::string &Blob)
Write a MsgPack document to a binary MsgPack blob.
bool readFromBlob(StringRef Blob, bool Multi, function_ref< int(DocNode *DestNode, DocNode SrcNode, DocNode MapKey)> Merger=[](DocNode *DestNode, DocNode SrcNode, DocNode MapKey) { return -1;})
Read a document from a binary msgpack blob, merging into anything already in the Document.
bool fromYAML(StringRef S)
Read YAML text into the MsgPack document. Returns false on failure.
Reads MessagePack objects from memory, one at a time.
A raw_ostream that writes to an std::string.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char AssemblerDirective[]
PAL metadata (old linear format) assembler directive.
constexpr char AssemblerDirectiveBegin[]
PAL metadata (new MsgPack format) beginning assembler directive.
constexpr char AssemblerDirectiveEnd[]
PAL metadata (new MsgPack format) ending assembler directive.
@ R_A1B6_SPI_PS_IN_CONTROL
@ R_A1B3_SPI_PS_INPUT_ENA
@ R_2D4A_SPI_SHADER_PGM_RSRC1_LS
@ R_2C4A_SPI_SHADER_PGM_RSRC1_VS
@ R_2D0A_SPI_SHADER_PGM_RSRC1_HS
@ R_2E12_COMPUTE_PGM_RSRC1
@ R_2E00_COMPUTE_DISPATCH_INITIATOR
@ R_A2D5_VGT_SHADER_STAGES_EN
@ R_A1B4_SPI_PS_INPUT_ADDR
@ R_2C0A_SPI_SHADER_PGM_RSRC1_PS
@ R_2C8A_SPI_SHADER_PGM_RSRC1_GS
@ R_2CCA_SPI_SHADER_PGM_RSRC1_ES
@ AMDGPU_CS
Used for Mesa/AMDPAL compute shaders.
@ AMDGPU_VS
Used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (vertex shader if tess...
@ AMDGPU_Gfx
Used for AMD graphics targets.
@ AMDGPU_HS
Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
@ AMDGPU_GS
Used for Mesa/AMDPAL geometry shaders.
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
@ AMDGPU_ES
Used for AMDPAL shader stage before geometry shader if geometry is in use.
@ AMDGPU_LS
Used for AMDPAL vertex shader if tessellation is in use.
This is an optimization pass for GlobalISel generic memory operations.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Adapter to write values to a stream in a particular byte order.