84 if (&Subtarget == &NewSubtarget)
87 Names2InstrOpCodes.clear();
89 Names2RegMasks.clear();
90 Names2SubRegIndices.clear();
91 Names2TargetIndices.clear();
92 Names2DirectTargetFlags.clear();
93 Names2BitmaskTargetFlags.clear();
94 Names2MMOTargetFlags.clear();
96 initNames2RegClasses();
100void PerTargetMIParsingState::initNames2Regs() {
101 if (!Names2Regs.empty())
105 Names2Regs.insert(std::make_pair(
"noreg", 0));
107 assert(
TRI &&
"Expected target register info");
109 for (
unsigned I = 0, E =
TRI->getNumRegs();
I < E; ++
I) {
114 assert(WasInserted &&
"Expected registers to be unique case-insensitively");
121 auto RegInfo = Names2Regs.find(
RegName);
122 if (RegInfo == Names2Regs.end())
124 Reg = RegInfo->getValue();
130 const auto *
TRI = Subtarget.getRegisterInfo();
131 std::optional<uint8_t> FV =
TRI->getVRegFlagValue(FlagName);
138void PerTargetMIParsingState::initNames2InstrOpCodes() {
139 if (!Names2InstrOpCodes.
empty())
142 assert(
TII &&
"Expected target instruction info");
143 for (
unsigned I = 0, E =
TII->getNumOpcodes();
I < E; ++
I)
149 initNames2InstrOpCodes();
150 auto InstrInfo = Names2InstrOpCodes.find(InstrName);
151 if (InstrInfo == Names2InstrOpCodes.end())
153 OpCode = InstrInfo->getValue();
157void PerTargetMIParsingState::initNames2RegMasks() {
158 if (!Names2RegMasks.
empty())
161 assert(
TRI &&
"Expected target register info");
165 for (
size_t I = 0, E = RegMasks.
size();
I < E; ++
I)
167 std::make_pair(
StringRef(RegMaskNames[
I]).lower(), RegMasks[
I]));
171 initNames2RegMasks();
172 auto RegMaskInfo = Names2RegMasks.find(Identifier);
173 if (RegMaskInfo == Names2RegMasks.end())
175 return RegMaskInfo->getValue();
178void PerTargetMIParsingState::initNames2SubRegIndices() {
179 if (!Names2SubRegIndices.
empty())
182 for (
unsigned I = 1, E =
TRI->getNumSubRegIndices();
I < E; ++
I)
183 Names2SubRegIndices.
insert(
184 std::make_pair(
TRI->getSubRegIndexName(
I),
I));
188 initNames2SubRegIndices();
189 auto SubRegInfo = Names2SubRegIndices.find(Name);
190 if (SubRegInfo == Names2SubRegIndices.end())
192 return SubRegInfo->getValue();
195void PerTargetMIParsingState::initNames2TargetIndices() {
196 if (!Names2TargetIndices.
empty())
199 assert(
TII &&
"Expected target instruction info");
200 auto Indices =
TII->getSerializableTargetIndices();
201 for (
const auto &
I : Indices)
206 initNames2TargetIndices();
207 auto IndexInfo = Names2TargetIndices.find(Name);
208 if (IndexInfo == Names2TargetIndices.end())
210 Index = IndexInfo->second;
214void PerTargetMIParsingState::initNames2DirectTargetFlags() {
215 if (!Names2DirectTargetFlags.
empty())
219 assert(
TII &&
"Expected target instruction info");
220 auto Flags =
TII->getSerializableDirectMachineOperandTargetFlags();
221 for (
const auto &
I : Flags)
222 Names2DirectTargetFlags.
insert(
228 initNames2DirectTargetFlags();
229 auto FlagInfo = Names2DirectTargetFlags.find(Name);
230 if (FlagInfo == Names2DirectTargetFlags.end())
232 Flag = FlagInfo->second;
236void PerTargetMIParsingState::initNames2BitmaskTargetFlags() {
237 if (!Names2BitmaskTargetFlags.
empty())
241 assert(
TII &&
"Expected target instruction info");
242 auto Flags =
TII->getSerializableBitmaskMachineOperandTargetFlags();
243 for (
const auto &
I : Flags)
244 Names2BitmaskTargetFlags.
insert(
250 initNames2BitmaskTargetFlags();
251 auto FlagInfo = Names2BitmaskTargetFlags.find(Name);
252 if (FlagInfo == Names2BitmaskTargetFlags.end())
254 Flag = FlagInfo->second;
258void PerTargetMIParsingState::initNames2MMOTargetFlags() {
259 if (!Names2MMOTargetFlags.
empty())
263 assert(
TII &&
"Expected target instruction info");
264 auto Flags =
TII->getSerializableMachineMemOperandTargetFlags();
265 for (
const auto &
I : Flags)
271 initNames2MMOTargetFlags();
272 auto FlagInfo = Names2MMOTargetFlags.find(Name);
273 if (FlagInfo == Names2MMOTargetFlags.end())
275 Flag = FlagInfo->second;
279void PerTargetMIParsingState::initNames2RegClasses() {
280 if (!Names2RegClasses.
empty())
284 for (
unsigned I = 0, E =
TRI->getNumRegClasses();
I < E; ++
I) {
285 const auto *RC =
TRI->getRegClass(
I);
291void PerTargetMIParsingState::initNames2RegBanks() {
292 if (!Names2RegBanks.empty())
295 const RegisterBankInfo *RBI = Subtarget.getRegBankInfo();
303 Names2RegBanks.insert(
304 std::make_pair(StringRef(RegBank.getName()).lower(), &RegBank));
310 auto RegClassInfo = Names2RegClasses.find(Name);
311 if (RegClassInfo == Names2RegClasses.end())
313 return RegClassInfo->getValue();
317 auto RegBankInfo = Names2RegBanks.find(Name);
318 if (RegBankInfo == Names2RegBanks.end())
320 return RegBankInfo->getValue();
333 Info->
VReg =
MRI.createIncompleteVirtualRegister();
334 I.first->second = Info;
336 return *
I.first->second;
345 Info->
VReg =
MF.getRegInfo().createIncompleteVirtualRegister(
RegName);
346 I.first->second = Info;
348 return *
I.first->second;
356 Slots2Values.
insert(std::make_pair(
unsigned(Slot), V));
364 for (
const auto &Arg :
F.args())
366 for (
const auto &BB :
F) {
368 for (
const auto &
I : BB)
383struct ParsedMachineOperand {
387 std::optional<unsigned> TiedDefIdx;
391 std::optional<unsigned> &TiedDefIdx)
392 : Operand(Operand), Begin(Begin), End(End), TiedDefIdx(TiedDefIdx) {
395 "Only used register operands can be tied");
402 StringRef
Source, CurrentSource;
405 PerFunctionMIParsingState &PFS;
407 DenseMap<unsigned, const BasicBlock *> Slots2BasicBlocks;
410 MIParser(PerFunctionMIParsingState &PFS, SMDiagnostic &
Error,
412 MIParser(PerFunctionMIParsingState &PFS, SMDiagnostic &
Error,
413 StringRef Source, SMRange SourceRange);
417 void lex(
unsigned SkipChar = 0);
422 bool error(
const Twine &Msg);
430 parseBasicBlockDefinitions(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
431 bool parseBasicBlocks();
433 bool parseStandaloneMBB(MachineBasicBlock *&
MBB);
435 bool parseStandaloneVirtualRegister(VRegInfo *&Info);
437 bool parseStandaloneStackObject(
int &FI);
438 bool parseStandaloneMDNode(MDNode *&Node);
440 bool parseMDTuple(MDNode *&MD,
bool IsDistinct);
441 bool parseMDNodeVector(SmallVectorImpl<Metadata *> &Elts);
445 parseBasicBlockDefinition(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
446 bool parseBasicBlock(MachineBasicBlock &
MBB,
447 MachineBasicBlock *&AddFalthroughFrom);
448 bool parseBasicBlockLiveins(MachineBasicBlock &
MBB);
449 bool parseBasicBlockSuccessors(MachineBasicBlock &
MBB);
452 bool parseVirtualRegister(VRegInfo *&Info);
453 bool parseNamedVirtualRegister(VRegInfo *&Info);
454 bool parseRegister(
Register &
Reg, VRegInfo *&VRegInfo);
455 bool parseRegisterFlag(
RegState &Flags);
456 bool parseRegisterClassOrBank(VRegInfo &RegInfo);
457 bool parseSubRegisterIndex(
unsigned &
SubReg);
458 bool parseRegisterTiedDefIndex(
unsigned &TiedDefIdx);
459 bool parseRegisterOperand(MachineOperand &Dest,
460 std::optional<unsigned> &TiedDefIdx,
462 bool parseImmediateOperand(MachineOperand &Dest);
467 bool parseTypedImmediateOperand(MachineOperand &Dest);
468 bool parseFPImmediateOperand(MachineOperand &Dest);
470 bool parseMBBOperand(MachineOperand &Dest);
471 bool parseStackFrameIndex(
int &FI);
472 bool parseStackObjectOperand(MachineOperand &Dest);
473 bool parseFixedStackFrameIndex(
int &FI);
474 bool parseFixedStackObjectOperand(MachineOperand &Dest);
476 bool parseGlobalAddressOperand(MachineOperand &Dest);
477 bool parseConstantPoolIndexOperand(MachineOperand &Dest);
478 bool parseSubRegisterIndexOperand(MachineOperand &Dest);
479 bool parseJumpTableIndexOperand(MachineOperand &Dest);
480 bool parseExternalSymbolOperand(MachineOperand &Dest);
481 bool parseMCSymbolOperand(MachineOperand &Dest);
483 bool parseDIExpression(MDNode *&Expr);
484 bool parseDILocation(MDNode *&Expr);
485 bool parseMetadataOperand(MachineOperand &Dest);
486 bool parseCFIOffset(
int &
Offset);
487 bool parseCFIRegister(
unsigned &
Reg);
489 bool parseCFIEscapeValues(std::string& Values);
490 bool parseCFIOperand(MachineOperand &Dest);
491 bool parseIRBlock(BasicBlock *&BB,
const Function &
F);
492 bool parseBlockAddressOperand(MachineOperand &Dest);
493 bool parseIntrinsicOperand(MachineOperand &Dest);
494 bool parsePredicateOperand(MachineOperand &Dest);
495 bool parseShuffleMaskOperand(MachineOperand &Dest);
496 bool parseTargetIndexOperand(MachineOperand &Dest);
497 bool parseDbgInstrRefOperand(MachineOperand &Dest);
498 bool parseCustomRegisterMaskOperand(MachineOperand &Dest);
499 bool parseLaneMaskOperand(MachineOperand &Dest);
500 bool parseLiveoutRegisterMaskOperand(MachineOperand &Dest);
501 bool parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
502 MachineOperand &Dest,
503 std::optional<unsigned> &TiedDefIdx);
504 bool parseMachineOperandAndTargetFlags(
const unsigned OpCode,
505 const unsigned OpIdx,
506 MachineOperand &Dest,
507 std::optional<unsigned> &TiedDefIdx);
508 bool parseOffset(int64_t &
Offset);
509 bool parseIRBlockAddressTaken(BasicBlock *&BB);
511 bool parseAddrspace(
unsigned &Addrspace);
512 bool parseSectionID(std::optional<MBBSectionID> &SID);
513 bool parseBBID(std::optional<UniqueBBID> &BBID);
514 bool parseCallFrameSize(
unsigned &CallFrameSize);
515 bool parseOperandsOffset(MachineOperand &
Op);
518 bool parseMemoryPseudoSourceValue(
const PseudoSourceValue *&PSV);
519 bool parseMachinePointerInfo(MachinePointerInfo &Dest);
522 bool parseMachineMemoryOperand(MachineMemOperand *&Dest);
523 bool parsePreOrPostInstrSymbol(MCSymbol *&Symbol);
524 bool parseHeapAllocMarker(MDNode *&Node);
525 bool parsePCSections(MDNode *&Node);
526 bool parseMMRA(MDNode *&Node);
528 bool parseTargetImmMnemonic(
const unsigned OpCode,
const unsigned OpIdx,
529 MachineOperand &Dest,
const MIRFormatter &MF);
540 bool getUint64(uint64_t &Result);
556 bool parseInstruction(
unsigned &OpCode,
unsigned &Flags);
558 bool assignRegisterTies(MachineInstr &
MI,
562 const MCInstrDesc &MCID);
565 const BasicBlock *getIRBlock(
unsigned Slot,
const Function &
F);
568 MCSymbol *getOrCreateMCSymbol(StringRef Name);
572 bool parseStringConstant(std::string &Result);
589 SourceRange(SourceRange), PFS(PFS) {}
591void MIParser::lex(
unsigned SkipChar) {
593 CurrentSource.substr(SkipChar), Token,
597bool MIParser::error(
const Twine &Msg) {
return error(Token.location(), Msg); }
617 assert(SourceRange.isValid() &&
"Invalid source range");
639 return "<unknown token>";
644 if (Token.isNot(TokenKind))
651 if (Token.isNot(TokenKind))
658bool MIParser::parseSectionID(std::optional<MBBSectionID> &SID) {
664 return error(
"Unknown Section ID");
667 const StringRef &S = Token.stringValue();
668 if (S ==
"Exception")
670 else if (S ==
"Cold")
673 return error(
"Unknown Section ID");
680bool MIParser::parseBBID(std::optional<UniqueBBID> &BBID) {
684 unsigned CloneID = 0;
686 return error(
"Unknown BB ID");
690 return error(
"Unknown Clone ID");
693 BBID = {BaseID, CloneID};
698bool MIParser::parseCallFrameSize(
unsigned &CallFrameSize) {
703 return error(
"Unknown call frame size");
704 CallFrameSize =
Value;
709bool MIParser::parseBasicBlockDefinition(
715 auto Loc = Token.location();
716 auto Name = Token.stringValue();
718 bool MachineBlockAddressTaken =
false;
720 bool IsLandingPad =
false;
721 bool IsInlineAsmBrIndirectTarget =
false;
722 bool IsEHFuncletEntry =
false;
723 bool IsEHScopeEntry =
false;
724 std::optional<MBBSectionID> SectionID;
725 uint64_t Alignment = 0;
726 std::optional<UniqueBBID> BBID;
727 unsigned CallFrameSize = 0;
732 switch (Token.kind()) {
734 MachineBlockAddressTaken =
true;
738 if (parseIRBlockAddressTaken(AddressTakenIRBlock))
746 IsInlineAsmBrIndirectTarget =
true;
750 IsEHFuncletEntry =
true;
754 IsEHScopeEntry =
true;
764 if (parseIRBlock(BB, MF.getFunction()))
769 if (parseSectionID(SectionID))
777 if (parseCallFrameSize(CallFrameSize))
792 MF.getFunction().getValueSymbolTable()->lookup(Name));
795 "' is not defined in the function '" +
798 auto *
MBB = MF.CreateMachineBasicBlock(BB, BBID);
800 bool WasInserted = MBBSlots.
insert(std::make_pair(
ID,
MBB)).second;
802 return error(
Loc,
Twine(
"redefinition of machine basic block with id #") +
806 if (MachineBlockAddressTaken)
808 if (AddressTakenIRBlock)
822bool MIParser::parseBasicBlockDefinitions(
828 if (Token.isErrorOrEOF())
829 return Token.isError();
831 return error(
"expected a basic block definition before instructions");
832 unsigned BraceDepth = 0;
834 if (parseBasicBlockDefinition(MBBSlots))
836 bool IsAfterNewline =
false;
840 Token.isErrorOrEOF())
843 return error(
"basic block definition should be located at the start of "
846 IsAfterNewline =
true;
849 IsAfterNewline =
false;
854 return error(
"extraneous closing brace ('}')");
860 if (!Token.isError() && BraceDepth)
861 return error(
"expected '}'");
862 }
while (!Token.isErrorOrEOF());
863 return Token.isError();
871 if (Token.isNewlineOrEOF())
875 return error(
"expected a named register");
877 if (parseNamedRegister(
Reg))
885 return error(
"expected a lane mask");
887 "Use correct get-function for lane mask");
890 return error(
"invalid lane mask value");
904 if (Token.isNewlineOrEOF())
908 return error(
"expected a machine basic block reference");
917 return error(
"expected an integer literal after '('");
951 bool ExplicitSuccessors =
false;
954 if (parseBasicBlockSuccessors(
MBB))
956 ExplicitSuccessors =
true;
958 if (parseBasicBlockLiveins(
MBB))
965 if (!Token.isNewlineOrEOF())
966 return error(
"expected line break at the end of a list");
971 bool IsInBundle =
false;
995 return error(
"nested instruction bundles are not allowed");
1004 assert(Token.isNewlineOrEOF() &&
"MI is not fully parsed");
1009 if (!ExplicitSuccessors) {
1016 if (IsFallthrough) {
1017 AddFalthroughFrom = &
MBB;
1026bool MIParser::parseBasicBlocks() {
1031 if (Token.isErrorOrEOF())
1032 return Token.isError();
1041 if (AddFalthroughFrom) {
1045 AddFalthroughFrom =
nullptr;
1047 if (parseBasicBlock(*
MBB, AddFalthroughFrom))
1060 while (Token.isRegister() || Token.isRegisterFlag()) {
1061 auto Loc = Token.location();
1062 std::optional<unsigned> TiedDefIdx;
1063 if (parseRegisterOperand(MO, TiedDefIdx,
true))
1066 ParsedMachineOperand(MO,
Loc, Token.location(), TiedDefIdx));
1075 if (Token.isError() || parseInstruction(OpCode, Flags))
1088 auto Loc = Token.location();
1089 std::optional<unsigned> TiedDefIdx;
1090 if (parseMachineOperandAndTargetFlags(OpCode, Operands.
size(), MO, TiedDefIdx))
1093 ParsedMachineOperand(MO,
Loc, Token.location(), TiedDefIdx));
1098 return error(
"expected ',' before the next machine operand");
1102 MCSymbol *PreInstrSymbol =
nullptr;
1104 if (parsePreOrPostInstrSymbol(PreInstrSymbol))
1106 MCSymbol *PostInstrSymbol =
nullptr;
1108 if (parsePreOrPostInstrSymbol(PostInstrSymbol))
1110 MDNode *HeapAllocMarker =
nullptr;
1112 if (parseHeapAllocMarker(HeapAllocMarker))
1114 MDNode *PCSections =
nullptr;
1116 if (parsePCSections(PCSections))
1121 unsigned CFIType = 0;
1125 return error(
"expected an integer literal after 'cfi-type'");
1143 unsigned InstrNum = 0;
1147 return error(
"expected an integer literal after 'debug-instr-number'");
1164 if (parseDILocation(Node))
1167 return error(
"expected a metadata node after 'debug-location'");
1170 return error(
"referenced metadata is not a DILocation");
1178 while (!Token.isNewlineOrEOF()) {
1180 if (parseMachineMemoryOperand(
MemOp))
1183 if (Token.isNewlineOrEOF())
1188 return error(
"expected ',' before the next machine memory operand");
1193 const auto &
MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
1194 if (!
MCID.isVariadic()) {
1196 if (verifyImplicitOperands(Operands,
MCID))
1200 MI = MF.CreateMachineInstr(
MCID, DebugLocation,
true);
1201 MI->setFlags(Flags);
1205 for (
const auto &Operand : Operands)
1206 MI->addOperand(MF, Operand.Operand);
1208 if (assignRegisterTies(*
MI, Operands))
1211 MI->setPreInstrSymbol(MF, PreInstrSymbol);
1212 if (PostInstrSymbol)
1213 MI->setPostInstrSymbol(MF, PostInstrSymbol);
1214 if (HeapAllocMarker)
1215 MI->setHeapAllocMarker(MF, HeapAllocMarker);
1217 MI->setPCSections(MF, PCSections);
1219 MI->setMMRAMetadata(MF, MMRA);
1221 MI->setCFIType(MF, CFIType);
1223 MI->setDeactivationSymbol(MF, DS);
1224 if (!MemOperands.
empty())
1225 MI->setMemRefs(MF, MemOperands);
1227 MI->setDebugInstrNum(InstrNum);
1234 return error(
"expected a machine basic block reference");
1240 "expected end of string after the machine basic block reference");
1244bool MIParser::parseStandaloneNamedRegister(
Register &
Reg) {
1247 return error(
"expected a named register");
1248 if (parseNamedRegister(
Reg))
1252 return error(
"expected end of string after the register reference");
1256bool MIParser::parseStandaloneVirtualRegister(
VRegInfo *&Info) {
1259 return error(
"expected a virtual register");
1260 if (parseVirtualRegister(Info))
1264 return error(
"expected end of string after the register reference");
1268bool MIParser::parseStandaloneRegister(
Register &
Reg) {
1272 return error(
"expected either a named or virtual register");
1275 if (parseRegister(
Reg, Info))
1280 return error(
"expected end of string after the register reference");
1284bool MIParser::parseStandaloneStackObject(
int &FI) {
1287 return error(
"expected a stack object");
1288 if (parseStackFrameIndex(FI))
1291 return error(
"expected end of string after the stack object reference");
1295bool MIParser::parseStandaloneMDNode(
MDNode *&Node) {
1301 if (parseDIExpression(Node))
1304 if (parseDILocation(Node))
1307 return error(
"expected a metadata node");
1310 return error(
"expected end of string after the metadata node");
1314bool MIParser::parseMachineMetadata() {
1317 return error(
"expected a metadata node");
1321 return error(
"expected metadata id after '!'");
1332 return error(
"expected a metadata node");
1336 if (parseMDTuple(MD, IsDistinct))
1339 auto FI = PFS.MachineForwardRefMDNodes.find(
ID);
1340 if (FI != PFS.MachineForwardRefMDNodes.end()) {
1341 FI->second.first->replaceAllUsesWith(MD);
1342 PFS.MachineForwardRefMDNodes.erase(FI);
1344 assert(PFS.MachineMetadataNodes[
ID] == MD &&
"Tracking VH didn't work");
1346 auto [It,
Inserted] = PFS.MachineMetadataNodes.try_emplace(
ID);
1348 return error(
"Metadata id is already used");
1349 It->second.reset(MD);
1355bool MIParser::parseMDTuple(
MDNode *&MD,
bool IsDistinct) {
1357 if (parseMDNodeVector(Elts))
1366 return error(
"expected '{' here");
1387 return error(
"expected end of metadata node");
1395bool MIParser::parseMetadata(
Metadata *&MD) {
1397 return error(
"expected '!' here");
1402 if (parseStringConstant(Str))
1409 return error(
"expected metadata id after '!'");
1411 SMLoc Loc = mapSMLoc(Token.location());
1418 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(
ID);
1419 if (NodeInfo != PFS.IRSlots.MetadataNodes.end()) {
1420 MD = NodeInfo->second.get();
1424 NodeInfo = PFS.MachineMetadataNodes.find(
ID);
1425 if (NodeInfo != PFS.MachineMetadataNodes.end()) {
1426 MD = NodeInfo->second.get();
1430 auto &FwdRef = PFS.MachineForwardRefMDNodes[
ID];
1431 FwdRef = std::make_pair(
1433 PFS.MachineMetadataNodes[
ID].reset(FwdRef.first.get());
1434 MD = FwdRef.first.get();
1441 return MO.
isDef() ?
"implicit-def" :
"implicit";
1446 assert(
Reg.isPhysical() &&
"expected phys reg");
1453 for (
const auto &
I : Operands) {
1474 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
1475 assert(
TRI &&
"Expected target register info");
1476 for (
const auto &
I : ImplicitOperands) {
1479 return error(Operands.
empty() ? Token.location() : Operands.
back().End,
1480 Twine(
"missing implicit register operand '") +
1487bool MIParser::parseInstruction(
unsigned &OpCode,
unsigned &Flags) {
1556 return error(
"expected a machine instruction");
1557 StringRef InstrName = Token.stringValue();
1558 if (PFS.Target.parseInstrName(InstrName, OpCode))
1559 return error(
Twine(
"unknown machine instruction name '") + InstrName +
"'");
1567 if (PFS.Target.getRegisterByName(Name,
Reg))
1568 return error(
Twine(
"unknown register name '") + Name +
"'");
1572bool MIParser::parseNamedVirtualRegister(
VRegInfo *&Info) {
1577 Info = &PFS.getVRegInfoNamed(Name);
1581bool MIParser::parseVirtualRegister(
VRegInfo *&Info) {
1583 return parseNamedVirtualRegister(Info);
1588 Info = &PFS.getVRegInfo(
ID);
1593 switch (Token.kind()) {
1598 return parseNamedRegister(
Reg);
1601 if (parseVirtualRegister(Info))
1611bool MIParser::parseRegisterClassOrBank(
VRegInfo &RegInfo) {
1613 return error(
"expected '_', register class, or register bank name");
1622 switch (RegInfo.
Kind) {
1628 return error(
Loc,
Twine(
"conflicting register classes, previously: ") +
1637 return error(
Loc,
"register class specification on generic register");
1645 RegBank = PFS.Target.getRegBank(Name);
1647 return error(
Loc,
"expected '_', register class, or register bank name");
1652 switch (RegInfo.
Kind) {
1658 return error(
Loc,
"conflicting generic register banks");
1664 return error(
Loc,
"register bank specification on normal register");
1669bool MIParser::parseRegisterFlag(
RegState &Flags) {
1671 switch (Token.kind()) {
1705 if (OldFlags == Flags)
1708 return error(
"duplicate '" + Token.stringValue() +
"' register flag");
1713bool MIParser::parseSubRegisterIndex(
unsigned &
SubReg) {
1717 return error(
"expected a subregister index after '.'");
1718 auto Name = Token.stringValue();
1719 SubReg = PFS.Target.getSubRegIndex(Name);
1721 return error(
Twine(
"use of unknown subregister index '") + Name +
"'");
1726bool MIParser::parseRegisterTiedDefIndex(
unsigned &TiedDefIdx) {
1730 return error(
"expected an integer literal after 'tied-def'");
1740 for (
unsigned I = 0,
E = Operands.
size();
I !=
E; ++
I) {
1741 if (!Operands[
I].TiedDefIdx)
1745 unsigned DefIdx = *Operands[
I].TiedDefIdx;
1747 return error(Operands[
I].Begin,
1748 Twine(
"use of invalid tied-def operand index '" +
1749 Twine(DefIdx) +
"'; instruction has only ") +
1751 const auto &DefOperand = Operands[DefIdx].Operand;
1752 if (!DefOperand.isReg() || !DefOperand.isDef())
1754 return error(Operands[
I].Begin,
1755 Twine(
"use of invalid tied-def operand index '") +
1756 Twine(DefIdx) +
"'; the operand #" +
Twine(DefIdx) +
1757 " isn't a defined register");
1759 for (
const auto &TiedPair : TiedRegisterPairs) {
1760 if (TiedPair.first == DefIdx)
1761 return error(Operands[
I].Begin,
1762 Twine(
"the tied-def operand #") +
Twine(DefIdx) +
1763 " is already tied with another register operand");
1765 TiedRegisterPairs.push_back(std::make_pair(DefIdx,
I));
1769 for (
const auto &TiedPair : TiedRegisterPairs)
1770 MI.tieOperands(TiedPair.first, TiedPair.second);
1775 std::optional<unsigned> &TiedDefIdx,
1778 while (Token.isRegisterFlag()) {
1779 if (parseRegisterFlag(Flags))
1784 if (!Token.isRegister())
1785 return error(
"expected a register after register flags");
1788 if (parseRegister(
Reg, RegInfo))
1793 if (parseSubRegisterIndex(
SubReg))
1796 return error(
"subregister index expects a virtual register");
1800 return error(
"register class specification expects a virtual register");
1802 if (parseRegisterClassOrBank(*RegInfo))
1811 return error(
"tied-def not supported for defs");
1813 if (parseRegisterTiedDefIndex(Idx))
1818 return error(
"unexpected type on physical register");
1822 if (parseLowLevelType(Token.location(), Ty))
1824 :
error(
"expected tied-def or low-level type after '('");
1830 if (
MRI.getType(
Reg).isValid() &&
MRI.getType(
Reg) != Ty)
1831 return error(
"inconsistent type for generic virtual register");
1835 MRI.noteNewVirtualRegister(
Reg);
1841 return error(
"generic virtual registers must have a type");
1846 return error(
"cannot have a killed def operand");
1849 return error(
"cannot have a dead use operand");
1866 const APSInt &
Int = Token.integerValue();
1867 if (
auto SImm =
Int.trySExtValue();
Int.isSigned() && SImm.has_value())
1869 else if (
auto UImm =
Int.tryZExtValue(); !
Int.isSigned() && UImm.has_value())
1872 return error(
"integer literal is too large to be an immediate operand");
1877bool MIParser::parseTargetImmMnemonic(
const unsigned OpCode,
1878 const unsigned OpIdx,
1882 auto Loc = Token.location();
1888 Len += Token.range().size();
1897 Src =
StringRef(
Loc, Len + Token.stringValue().size());
1902 ->
bool { return error(Loc, Msg); }))
1914 auto Source = StringValue.
str();
1919 return ErrCB(
Loc + Err.getColumnNo(), Err.getMessage());
1925 return ::parseIRConstant(
1926 Loc, StringValue, PFS,
C,
1953 if (Token.range().front() ==
's' || Token.range().front() ==
'p') {
1956 return error(
"expected integers after 's'/'p' type character");
1959 if (Token.range().front() ==
's') {
1963 return error(
"invalid size for scalar type");
1970 }
else if (Token.range().front() ==
'p') {
1974 return error(
"invalid address space number");
1983 return error(
Loc,
"expected sN, pA, <M x sN>, <M x pA>, <vscale x M x sN>, "
1984 "or <vscale x M x pA> for GlobalISel type");
1992 return error(
"expected <vscale x M x sN> or <vscale x M x pA>");
1996 auto GetError = [
this, &HasVScale,
Loc]() {
1999 Loc,
"expected <vscale x M x sN> or <vscale M x pA> for vector type");
2000 return error(
Loc,
"expected <M x sN> or <M x pA> for vector type");
2005 uint64_t NumElements = Token.integerValue().getZExtValue();
2007 return error(
"invalid number of vector elements");
2015 if (Token.range().front() !=
's' && Token.range().front() !=
'p')
2020 return error(
"expected integers after 's'/'p' type character");
2022 if (Token.range().front() ==
's') {
2025 return error(
"invalid size for scalar element in vector");
2027 }
else if (Token.range().front() ==
'p') {
2031 return error(
"invalid address space number");
2051 if (TypeStr.
front() !=
'i' && TypeStr.
front() !=
's' &&
2052 TypeStr.
front() !=
'p')
2054 "a typed immediate operand should start with one of 'i', 's', or 'p'");
2057 return error(
"expected integers after 'i'/'s'/'p' type character");
2059 auto Loc = Token.location();
2063 !(Token.range() ==
"true" || Token.range() ==
"false"))
2064 return error(
"expected an integer literal");
2074 auto Loc = Token.location();
2078 return error(
"expected a floating point literal");
2089 assert(S[0] ==
'0' && tolower(S[1]) ==
'x');
2091 if (!isxdigit(S[2]))
2094 APInt A(V.size()*4, V, 16);
2098 unsigned NumBits = (
A == 0) ? 32 :
A.getActiveBits();
2109 return ErrCB(Token.
location(),
"expected unsigned integer");
2112 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2120 if (
A.getBitWidth() > 32)
2121 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2122 Result =
A.getZExtValue();
2128bool MIParser::getUnsigned(
unsigned &Result) {
2129 return ::getUnsigned(
2141 auto MBBInfo = PFS.MBBSlots.find(
Number);
2142 if (MBBInfo == PFS.MBBSlots.end())
2143 return error(
Twine(
"use of undefined machine basic block #") +
2145 MBB = MBBInfo->second;
2148 if (!Token.stringValue().empty() && Token.stringValue() !=
MBB->
getName())
2150 " isn't '" + Token.stringValue() +
"'");
2163bool MIParser::parseStackFrameIndex(
int &FI) {
2168 auto ObjectInfo = PFS.StackObjectSlots.find(
ID);
2169 if (ObjectInfo == PFS.StackObjectSlots.end())
2173 if (
const auto *Alloca =
2174 MF.getFrameInfo().getObjectAllocation(ObjectInfo->second))
2175 Name = Alloca->getName();
2176 if (!Token.stringValue().empty() && Token.stringValue() != Name)
2178 "' isn't '" + Token.stringValue() +
"'");
2180 FI = ObjectInfo->second;
2186 if (parseStackFrameIndex(FI))
2192bool MIParser::parseFixedStackFrameIndex(
int &FI) {
2197 auto ObjectInfo = PFS.FixedStackObjectSlots.find(
ID);
2198 if (ObjectInfo == PFS.FixedStackObjectSlots.end())
2199 return error(
Twine(
"use of undefined fixed stack object '%fixed-stack.") +
2202 FI = ObjectInfo->second;
2206bool MIParser::parseFixedStackObjectOperand(
MachineOperand &Dest) {
2208 if (parseFixedStackFrameIndex(FI))
2217 switch (Token.
kind()) {
2222 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '") +
2223 Token.
range() +
"'");
2232 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '@") +
2233 Twine(GVIdx) +
"'");
2242bool MIParser::parseGlobalValue(
GlobalValue *&GV) {
2243 return ::parseGlobalValue(
2256 if (parseOperandsOffset(Dest))
2261bool MIParser::parseConstantPoolIndexOperand(
MachineOperand &Dest) {
2268 return error(
"use of undefined constant '%const." +
Twine(
ID) +
"'");
2271 if (parseOperandsOffset(Dest))
2281 auto JumpTableEntryInfo = PFS.JumpTableSlots.find(
ID);
2282 if (JumpTableEntryInfo == PFS.JumpTableSlots.end())
2283 return error(
"use of undefined jump table '%jump-table." +
Twine(
ID) +
"'");
2291 const char *
Symbol = MF.createExternalSymbolName(Token.stringValue());
2294 if (parseOperandsOffset(Dest))
2304 if (parseOperandsOffset(Dest))
2309bool MIParser::parseSubRegisterIndexOperand(
MachineOperand &Dest) {
2312 unsigned SubRegIndex = PFS.Target.getSubRegIndex(Token.stringValue());
2313 if (SubRegIndex == 0)
2314 return error(
Twine(
"unknown subregister index '") + Name +
"'");
2320bool MIParser::parseMDNode(
MDNode *&Node) {
2323 auto Loc = Token.location();
2326 return error(
"expected metadata id after '!'");
2330 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(
ID);
2331 if (NodeInfo == PFS.IRSlots.MetadataNodes.end()) {
2332 NodeInfo = PFS.MachineMetadataNodes.find(
ID);
2333 if (NodeInfo == PFS.MachineMetadataNodes.end())
2337 Node = NodeInfo->second.get();
2341bool MIParser::parseDIExpression(
MDNode *&Expr) {
2344 CurrentSource,
Read,
Error, *PFS.MF.getFunction().getParent(),
2346 CurrentSource = CurrentSource.substr(
Read);
2353bool MIParser::parseDILocation(
MDNode *&
Loc) {
2357 bool HaveLine =
false;
2359 unsigned Column = 0;
2361 MDNode *InlinedAt =
nullptr;
2362 bool ImplicitCode =
false;
2363 uint64_t AtomGroup = 0;
2364 uint64_t AtomRank = 0;
2372 if (Token.stringValue() ==
"line") {
2377 Token.integerValue().isSigned())
2378 return error(
"expected unsigned integer");
2379 Line = Token.integerValue().getZExtValue();
2384 if (Token.stringValue() ==
"column") {
2389 Token.integerValue().isSigned())
2390 return error(
"expected unsigned integer");
2391 Column = Token.integerValue().getZExtValue();
2395 if (Token.stringValue() ==
"scope") {
2400 return error(
"expected metadata node");
2402 return error(
"expected DIScope node");
2405 if (Token.stringValue() ==
"inlinedAt") {
2413 if (parseDILocation(InlinedAt))
2416 return error(
"expected metadata node");
2419 return error(
"expected DILocation node");
2422 if (Token.stringValue() ==
"isImplicitCode") {
2427 return error(
"expected true/false");
2431 if (Token.stringValue() ==
"true")
2432 ImplicitCode =
true;
2433 else if (Token.stringValue() ==
"false")
2434 ImplicitCode =
false;
2436 return error(
"expected true/false");
2440 if (Token.stringValue() ==
"atomGroup") {
2445 Token.integerValue().isSigned())
2446 return error(
"expected unsigned integer");
2447 AtomGroup = Token.integerValue().getZExtValue();
2451 if (Token.stringValue() ==
"atomRank") {
2456 Token.integerValue().isSigned())
2457 return error(
"expected unsigned integer");
2458 AtomRank = Token.integerValue().getZExtValue();
2463 return error(
Twine(
"invalid DILocation argument '") +
2464 Token.stringValue() +
"'");
2472 return error(
"DILocation requires line number");
2474 return error(
"DILocation requires a scope");
2477 InlinedAt, ImplicitCode, AtomGroup, AtomRank);
2487 if (parseDIExpression(Node))
2494bool MIParser::parseCFIOffset(
int &
Offset) {
2496 return error(
"expected a cfi offset");
2497 if (Token.integerValue().getSignificantBits() > 32)
2498 return error(
"expected a 32 bit integer (the cfi offset is too large)");
2499 Offset = (int)Token.integerValue().getExtValue();
2504bool MIParser::parseCFIRegister(
unsigned &
Reg) {
2506 return error(
"expected a cfi register");
2508 if (parseNamedRegister(LLVMReg))
2510 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
2511 assert(
TRI &&
"Expected target register info");
2512 int DwarfReg =
TRI->getDwarfRegNum(LLVMReg,
true);
2514 return error(
"invalid DWARF register");
2515 Reg = (unsigned)DwarfReg;
2520bool MIParser::parseCFIAddressSpace(
unsigned &
AddressSpace) {
2522 return error(
"expected a cfi address space literal");
2523 if (Token.integerValue().isSigned())
2524 return error(
"expected an unsigned integer (cfi address space)");
2530bool MIParser::parseCFIEscapeValues(std::string &Values) {
2533 return error(
"expected a hexadecimal literal");
2537 if (
Value > UINT8_MAX)
2538 return error(
"expected a 8-bit integer (too large)");
2539 Values.push_back(
static_cast<uint8_t
>(
Value));
2546 auto Kind = Token.kind();
2554 if (parseCFIRegister(
Reg))
2569 CFIIndex = MF.addFrameInst(
2573 if (parseCFIRegister(
Reg))
2579 if (parseCFIOffset(
Offset))
2585 if (parseCFIOffset(
Offset))
2587 CFIIndex = MF.addFrameInst(
2609 if (parseCFIRegister(
Reg))
2617 if (parseCFIRegister(
Reg))
2624 parseCFIRegister(Reg2))
2643 if (parseCFIEscapeValues(Values))
2657 switch (Token.kind()) {
2660 F.getValueSymbolTable()->lookup(Token.stringValue()));
2662 return error(
Twine(
"use of undefined IR block '") + Token.range() +
"'");
2666 unsigned SlotNumber = 0;
2669 BB =
const_cast<BasicBlock *
>(getIRBlock(SlotNumber,
F));
2671 return error(
Twine(
"use of undefined IR block '%ir-block.") +
2672 Twine(SlotNumber) +
"'");
2688 return error(
"expected a global value");
2694 return error(
"expected an IR function reference");
2700 return error(
"expected an IR block reference");
2701 if (parseIRBlock(BB, *
F))
2707 if (parseOperandsOffset(Dest))
2716 return error(
"expected syntax intrinsic(@llvm.whatever)");
2719 return error(
"expected syntax intrinsic(@llvm.whatever)");
2721 std::string
Name = std::string(Token.stringValue());
2725 return error(
"expected ')' to terminate intrinsic name");
2730 return error(
"unknown intrinsic name");
2742 return error(
"expected syntax intpred(whatever) or floatpred(whatever");
2745 return error(
"whatever");
2768 return error(
"invalid floating-point predicate");
2783 return error(
"invalid integer predicate");
2789 return error(
"predicate should be terminated by ')'.");
2799 return error(
"expected syntax shufflemask(<integer or undef>, ...)");
2806 const APSInt &
Int = Token.integerValue();
2809 return error(
"expected integer constant");
2816 return error(
"shufflemask should be terminated by ')'.");
2818 if (ShufMask.
size() < 2)
2819 return error(
"shufflemask should have > 1 element");
2831 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2834 return error(
"expected unsigned integer for instruction index");
2835 uint64_t InstrIdx = Token.integerValue().getZExtValue();
2836 assert(InstrIdx <= std::numeric_limits<unsigned>::max() &&
2837 "Instruction reference's instruction index is too large");
2841 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2844 return error(
"expected unsigned integer for operand index");
2845 uint64_t
OpIdx = Token.integerValue().getZExtValue();
2846 assert(
OpIdx <= std::numeric_limits<unsigned>::max() &&
2847 "Instruction reference's operand index is too large");
2851 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2863 return error(
"expected the name of the target index");
2865 if (PFS.Target.getTargetIndex(Token.stringValue(), Index))
2866 return error(
"use of undefined target index '" + Token.stringValue() +
"'");
2871 if (parseOperandsOffset(Dest))
2876bool MIParser::parseCustomRegisterMaskOperand(
MachineOperand &Dest) {
2877 assert(Token.stringValue() ==
"CustomRegMask" &&
"Expected a custom RegMask");
2882 uint32_t *
Mask = MF.allocateRegMask();
2886 return error(
"expected a named register");
2888 if (parseNamedRegister(
Reg))
2912 return error(
"expected a valid lane mask value");
2914 "Use correct get-function for lane mask.");
2928bool MIParser::parseLiveoutRegisterMaskOperand(
MachineOperand &Dest) {
2930 uint32_t *
Mask = MF.allocateRegMask();
2936 return error(
"expected a named register");
2938 if (parseNamedRegister(
Reg))
2953bool MIParser::parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
2955 std::optional<unsigned> &TiedDefIdx) {
2956 switch (Token.kind()) {
2971 return parseRegisterOperand(Dest, TiedDefIdx);
2973 return parseImmediateOperand(Dest);
2981 return parseFPImmediateOperand(Dest);
2983 return parseMBBOperand(Dest);
2985 return parseStackObjectOperand(Dest);
2987 return parseFixedStackObjectOperand(Dest);
2990 return parseGlobalAddressOperand(Dest);
2992 return parseConstantPoolIndexOperand(Dest);
2994 return parseJumpTableIndexOperand(Dest);
2996 return parseExternalSymbolOperand(Dest);
2998 return parseMCSymbolOperand(Dest);
3000 return parseSubRegisterIndexOperand(Dest);
3003 return parseMetadataOperand(Dest);
3021 return parseCFIOperand(Dest);
3023 return parseBlockAddressOperand(Dest);
3025 return parseIntrinsicOperand(Dest);
3027 return parseTargetIndexOperand(Dest);
3029 return parseLaneMaskOperand(Dest);
3031 return parseLiveoutRegisterMaskOperand(Dest);
3034 return parsePredicateOperand(Dest);
3036 return parseShuffleMaskOperand(Dest);
3038 return parseDbgInstrRefOperand(Dest);
3042 if (
const auto *RegMask = PFS.Target.getRegMask(Token.stringValue())) {
3046 }
else if (Token.stringValue() ==
"CustomRegMask") {
3047 return parseCustomRegisterMaskOperand(Dest);
3049 return parseTypedImmediateOperand(Dest);
3052 const auto *
TII = MF.getSubtarget().getInstrInfo();
3053 if (
const auto *Formatter =
TII->getMIRFormatter()) {
3054 return parseTargetImmMnemonic(OpCode,
OpIdx, Dest, *Formatter);
3060 return error(
"expected a machine operand");
3065bool MIParser::parseMachineOperandAndTargetFlags(
3067 std::optional<unsigned> &TiedDefIdx) {
3069 bool HasTargetFlags =
false;
3071 HasTargetFlags =
true;
3076 return error(
"expected the name of the target flag");
3077 if (PFS.Target.getDirectTargetFlag(Token.stringValue(), TF)) {
3078 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), TF))
3079 return error(
"use of undefined target flag '" + Token.stringValue() +
3086 return error(
"expected the name of the target flag");
3087 unsigned BitFlag = 0;
3088 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), BitFlag))
3089 return error(
"use of undefined target flag '" + Token.stringValue() +
3098 auto Loc = Token.location();
3099 if (parseMachineOperand(OpCode,
OpIdx, Dest, TiedDefIdx))
3101 if (!HasTargetFlags)
3104 return error(
Loc,
"register operands can't have target flags");
3109bool MIParser::parseOffset(int64_t &
Offset) {
3116 return error(
"expected an integer literal after '" + Sign +
"'");
3117 if (Token.integerValue().getSignificantBits() > 64)
3118 return error(
"expected 64-bit integer (too large)");
3119 Offset = Token.integerValue().getExtValue();
3126bool MIParser::parseIRBlockAddressTaken(
BasicBlock *&BB) {
3130 return error(
"expected basic block after 'ir_block_address_taken'");
3132 if (parseIRBlock(BB, MF.getFunction()))
3139bool MIParser::parseAlignment(uint64_t &Alignment) {
3143 return error(
"expected an integer literal after 'align'");
3144 if (getUint64(Alignment))
3149 return error(
"expected a power-of-2 literal after 'align'");
3154bool MIParser::parseAddrspace(
unsigned &Addrspace) {
3158 return error(
"expected an integer literal after 'addrspace'");
3175 switch (Token.
kind()) {
3181 unsigned SlotNumber = 0;
3209 return ErrCB(Token.
location(),
Twine(
"use of undefined IR value '") + Token.
range() +
"'");
3213bool MIParser::parseIRValue(
const Value *&V) {
3214 return ::parseIRValue(
3220bool MIParser::getUint64(uint64_t &Result) {
3221 if (Token.hasIntegerValue()) {
3222 if (Token.integerValue().getActiveBits() > 64)
3223 return error(
"expected 64-bit integer (too large)");
3224 Result = Token.integerValue().getZExtValue();
3231 if (
A.getBitWidth() > 64)
3232 return error(
"expected 64-bit integer (too large)");
3239bool MIParser::getHexUint(
APInt &Result) {
3240 return ::getHexUint(Token, Result);
3244 const auto OldFlags =
Flags;
3245 switch (Token.kind()) {
3260 if (PFS.Target.getMMOTargetFlag(Token.stringValue(), TF))
3261 return error(
"use of undefined target MMO flag '" + Token.stringValue() +
3269 if (OldFlags == Flags)
3272 return error(
"duplicate '" + Token.stringValue() +
"' memory operand flag");
3278 switch (Token.kind()) {
3280 PSV = MF.getPSVManager().getStack();
3283 PSV = MF.getPSVManager().getGOT();
3286 PSV = MF.getPSVManager().getJumpTable();
3289 PSV = MF.getPSVManager().getConstantPool();
3293 if (parseFixedStackFrameIndex(FI))
3295 PSV = MF.getPSVManager().getFixedStack(FI);
3301 if (parseStackFrameIndex(FI))
3303 PSV = MF.getPSVManager().getFixedStack(FI);
3309 switch (Token.kind()) {
3315 PSV = MF.getPSVManager().getGlobalValueCallEntry(GV);
3319 PSV = MF.getPSVManager().getExternalSymbolCallEntry(
3320 MF.createExternalSymbolName(Token.stringValue()));
3324 "expected a global value or an external symbol after 'call-entry'");
3329 const auto *
TII = MF.getSubtarget().getInstrInfo();
3330 if (
const auto *Formatter =
TII->getMIRFormatter()) {
3331 if (Formatter->parseCustomPseudoSourceValue(
3332 Token.stringValue(), MF, PFS, PSV,
3334 return error(Loc, Msg);
3338 return error(
"unable to parse target custom pseudo source value");
3355 if (parseMemoryPseudoSourceValue(PSV))
3368 return error(
"expected an IR value reference");
3369 const Value *
V =
nullptr;
3372 if (V && !
V->getType()->isPointerTy())
3373 return error(
"expected a pointer IR value");
3388 return error(
"expected '(' in syncscope");
3391 if (parseStringConstant(SSN))
3394 SSID =
Context.getOrInsertSyncScopeID(SSN);
3396 return error(
"expected ')' in syncscope");
3402bool MIParser::parseOptionalAtomicOrdering(
AtomicOrdering &Order) {
3421 return error(
"expected an atomic scope, ordering or a size specification");
3428 while (Token.isMemoryOperandFlag()) {
3429 if (parseMemoryOperandFlag(Flags))
3433 (Token.stringValue() !=
"load" && Token.stringValue() !=
"store"))
3434 return error(
"expected 'load' or 'store' memory operation");
3435 if (Token.stringValue() ==
"load")
3449 if (parseOptionalScope(MF.getFunction().getContext(), SSID))
3454 if (parseOptionalAtomicOrdering(Order))
3457 if (parseOptionalAtomicOrdering(FailureOrder))
3463 return error(
"expected memory LLT, the size integer literal or 'unknown-size' after "
3464 "memory operation");
3469 if (getUint64(
Size))
3480 if (parseLowLevelType(Token.location(), MemoryType))
3493 if (Token.stringValue() != Word)
3494 return error(
Twine(
"expected '") + Word +
"'");
3497 if (parseMachinePointerInfo(Ptr))
3500 uint64_t BaseAlignment =
3507 switch (Token.kind()) {
3513 if (Ptr.
Offset & (Alignment - 1)) {
3518 return error(
"specified alignment is more aligned than offset");
3520 BaseAlignment = Alignment;
3559 return error(
"expected 'align' or '!tbaa' or '!alias.scope' or "
3560 "'!noalias' or '!range' or '!noalias.addrspace'");
3565 Dest = MF.getMachineMemOperand(Ptr, Flags, MemoryType,
Align(BaseAlignment),
3566 AAInfo,
Range, SSID, Order, FailureOrder);
3570bool MIParser::parsePreOrPostInstrSymbol(
MCSymbol *&Symbol) {
3573 "Invalid token for a pre- post-instruction symbol!");
3576 return error(
"expected a symbol after 'pre-instr-symbol'");
3577 Symbol = getOrCreateMCSymbol(Token.stringValue());
3583 return error(
"expected ',' before the next machine operand");
3588bool MIParser::parseHeapAllocMarker(
MDNode *&Node) {
3590 "Invalid token for a heap alloc marker!");
3595 return error(
"expected a MDNode after 'heap-alloc-marker'");
3600 return error(
"expected ',' before the next machine operand");
3605bool MIParser::parsePCSections(
MDNode *&Node) {
3607 "Invalid token for a PC sections!");
3612 return error(
"expected a MDNode after 'pcsections'");
3617 return error(
"expected ',' before the next machine operand");
3622bool MIParser::parseMMRA(
MDNode *&Node) {
3631 return error(
"expected ',' before the next machine operand");
3641 for (
const auto &BB :
F) {
3647 Slots2BasicBlocks.
insert(std::make_pair(
unsigned(Slot), &BB));
3654 return Slots2BasicBlocks.
lookup(Slot);
3657const BasicBlock *MIParser::getIRBlock(
unsigned Slot) {
3658 if (Slots2BasicBlocks.empty())
3664 if (&
F == &MF.getFunction())
3665 return getIRBlock(Slot);
3677 return MF.getContext().getOrCreateSymbol(Name);
3680bool MIParser::parseStringConstant(std::string &Result) {
3682 return error(
"expected string constant");
3683 Result = std::string(Token.stringValue());
3691 return MIParser(PFS,
Error, Src).parseBasicBlockDefinitions(PFS.
MBBSlots);
3696 return MIParser(PFS,
Error, Src).parseBasicBlocks();
3702 return MIParser(PFS,
Error, Src).parseStandaloneMBB(
MBB);
3708 return MIParser(PFS,
Error, Src).parseStandaloneRegister(Reg);
3714 return MIParser(PFS,
Error, Src).parseStandaloneNamedRegister(Reg);
3720 return MIParser(PFS,
Error, Src).parseStandaloneVirtualRegister(Info);
3726 return MIParser(PFS,
Error, Src).parseStandaloneStackObject(FI);
3731 return MIParser(PFS,
Error, Src).parseStandaloneMDNode(
Node);
3736 return MIParser(PFS,
Error, Src, SrcRange).parseMachineMetadata();
3744 ErrorCallback(
Loc, Msg);
3748 return ::parseIRValue(Token, PFS, V, ErrorCallback);
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file defines the StringMap class.
This file implements a class to represent arbitrary precision integral constant values and operations...
This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Atomic ordering constants.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
static Error parseAlignment(StringRef Str, Align &Alignment, StringRef Name, bool AllowZero=false)
Attempts to parse an alignment component of a specification.
This file defines the DenseMap class.
const HexagonInstrInfo * TII
Module.h This file contains the declarations for the Module class.
A common definition of LaneBitmask for use in TableGen and CodeGen.
static llvm::Error parse(DataExtractor &Data, uint64_t BaseAddr, LineEntryCallback const &Callback)
Implement a low-level type suitable for MachineInstr level instruction selection.
static const char * printImplicitRegisterFlag(const MachineOperand &MO)
static const BasicBlock * getIRBlockFromSlot(unsigned Slot, const DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)
static bool parseIRConstant(StringRef::iterator Loc, StringRef StringValue, PerFunctionMIParsingState &PFS, const Constant *&C, ErrorCallbackType ErrCB)
static void initSlots2Values(const Function &F, DenseMap< unsigned, const Value * > &Slots2Values)
Creates the mapping from slot numbers to function's unnamed IR values.
static bool parseIRValue(const MIToken &Token, PerFunctionMIParsingState &PFS, const Value *&V, ErrorCallbackType ErrCB)
static bool verifyScalarSize(uint64_t Size)
static bool getUnsigned(const MIToken &Token, unsigned &Result, ErrorCallbackType ErrCB)
static bool getHexUint(const MIToken &Token, APInt &Result)
static bool verifyVectorElementCount(uint64_t NumElts)
static void mapValueToSlot(const Value *V, ModuleSlotTracker &MST, DenseMap< unsigned, const Value * > &Slots2Values)
static void initSlots2BasicBlocks(const Function &F, DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
function_ref< bool(StringRef::iterator Loc, const Twine &)> ErrorCallbackType
static bool isImplicitOperandIn(const MachineOperand &ImplicitOperand, ArrayRef< ParsedMachineOperand > Operands)
Return true if the parsed machine operands contain a given machine operand.
static bool parseGlobalValue(const MIToken &Token, PerFunctionMIParsingState &PFS, GlobalValue *&GV, ErrorCallbackType ErrCB)
static bool verifyAddrSpace(uint64_t AddrSpace)
Register const TargetRegisterInfo * TRI
Promote Memory to Register
MachineInstr unsigned OpIdx
static constexpr unsigned SM(unsigned Version)
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
static bool parseMetadata(const StringRef &Input, uint64_t &FunctionHash, uint32_t &Attributes)
Parse Input that contains metadata.
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Class for arbitrary precision integers.
uint64_t getZExtValue() const
Get zero extended value.
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value.
An arbitrary precision integer that knows its signedness.
bool isNegative() const
Determine sign of this APSInt.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
const T & back() const
back - Get the last element.
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
LLVM Basic Block Representation.
static LLVM_ABI BlockAddress * get(Function *F, BasicBlock *BB)
Return a BlockAddress for the specified function and basic block.
static BranchProbability getRaw(uint32_t N)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
@ ICMP_SLT
signed less than
@ ICMP_SLE
signed less or equal
@ FCMP_OLT
0 1 0 0 True if ordered and less than
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
@ ICMP_UGE
unsigned greater or equal
@ ICMP_UGT
unsigned greater than
@ ICMP_SGT
signed greater than
@ FCMP_ULT
1 1 0 0 True if unordered or less than
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
@ ICMP_ULT
unsigned less than
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
@ ICMP_SGE
signed greater or equal
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
@ ICMP_ULE
unsigned less or equal
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
static bool isFPPredicate(Predicate P)
static bool isIntPredicate(Predicate P)
This is an important base class in LLVM.
A parsed version of the target data layout string in and methods for querying it.
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
Lightweight error class with error context and mandatory checking.
ValueSymbolTable * getValueSymbolTable()
getSymbolTable() - Return the symbol table if any, otherwise nullptr.
Module * getParent()
Get the module that this global value is contained inside of...
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT token()
Get a low-level token; just a scalar with zero bits (or no size).
This is an important class for using LLVM in a threaded context.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_def_cfa_register modifies a rule for computing CFA.
static MCCFIInstruction createUndefined(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_undefined From now on the previous value of Register can't be restored anymore.
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
static MCCFIInstruction createLLVMDefAspaceCfa(MCSymbol *L, unsigned Register, int64_t Offset, unsigned AddressSpace, SMLoc Loc)
.cfi_llvm_def_aspace_cfa defines the rule for computing the CFA to be the result of evaluating the DW...
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2, SMLoc Loc={})
.cfi_register Previous value of Register1 is saved in register Register2.
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction createNegateRAStateWithPC(MCSymbol *L, SMLoc Loc={})
.cfi_negate_ra_state_with_pc AArch64 negate RA state with PC.
static MCCFIInstruction createNegateRAState(MCSymbol *L, SMLoc Loc={})
.cfi_negate_ra_state AArch64 negate RA state.
static MCCFIInstruction createRememberState(MCSymbol *L, SMLoc Loc={})
.cfi_remember_state Save all current rules for all registers.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals, SMLoc Loc={}, StringRef Comment="")
.cfi_escape Allows the user to add arbitrary bytes to the unwind info.
static MCCFIInstruction createWindowSave(MCSymbol *L, SMLoc Loc={})
.cfi_window_save SPARC register window is saved.
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int64_t Adjustment, SMLoc Loc={})
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
static MCCFIInstruction createRestoreState(MCSymbol *L, SMLoc Loc={})
.cfi_restore_state Restore the previously saved state.
static MCCFIInstruction createSameValue(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_same_value Current value of Register is the same as in the previous frame.
static MCCFIInstruction createRelOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_rel_offset Previous value of Register is saved at offset Offset from the current CFA register.
Describe properties that are true of each instruction in the target description file.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
static LLVM_ABI MDString * get(LLVMContext &Context, StringRef Str)
static MDTuple * getDistinct(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Return a distinct node.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
static TempMDTuple getTemporary(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Return a temporary node.
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
void setAddressTakenIRBlock(BasicBlock *BB)
Set this block to reflect that it corresponds to an IR-level basic block with a BlockAddress.
LLVM_ABI instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
void setCallFrameSize(unsigned N)
Set the call frame size on entry to this basic block.
void setAlignment(Align A)
Set alignment of the basic block.
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void setSectionID(MBBSectionID V)
Sets the section ID for this basic block.
void setIsInlineAsmBrIndirectTarget(bool V=true)
Indicates if this is the indirect dest of an INLINEASM_BR.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
void setIsEHFuncletEntry(bool V=true)
Indicates if this is the entry block of an EH funclet.
LLVM_ABI bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
LLVM_ABI StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
void setIsEHScopeEntry(bool V=true)
Indicates if this is the entry block of an EH scope, i.e., the block that that used to have a catchpa...
void setMachineBlockAddressTaken()
Set this block to indicate that its address is used as something other than the target of a terminato...
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
void setFlag(MIFlag Flag)
Set a MI flag.
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
static MachineOperand CreateFPImm(const ConstantFP *CFP)
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static MachineOperand CreateCImm(const ConstantInt *CI)
static MachineOperand CreateMetadata(const MDNode *Meta)
static MachineOperand CreatePredicate(unsigned Pred)
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx)
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
void setTargetFlags(unsigned F)
static MachineOperand CreateLaneMask(LaneBitmask LaneMask)
LLVM_ABI bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
static MachineOperand CreateFI(int Idx)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This interface provides simple read-only access to a block of memory, and provides simple methods for...
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
const char * getBufferEnd() const
const char * getBufferStart() const
Manage lifetime of a slot tracker for printing IR.
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
void incorporateFunction(const Function &F)
Incorporate the given function.
A Module instance is used to store all the information related to an LLVM module.
Special value supplied for machine level alias analysis.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getNumRegBanks() const
Get the total number of register banks.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr unsigned id() const
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a location in source code.
static SMLoc getFromPointer(const char *Ptr)
Represents a range in source code.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This owns the files read by a parser, handles include stacks, and handles diagnostic wrangling.
bool insert(MapEntryTy *KeyValue)
insert - Insert the specified key/value pair into the map.
StringRef - Represent a constant reference to a string, i.e.
std::string str() const
str - Get the contents as an std::string.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
StringRef drop_front(size_t N=1) const
Return a StringRef equal to 'this' but with the first N elements dropped.
constexpr size_t size() const
size - Get the string size.
char front() const
front - Get the first character in the string.
LLVM_ABI std::string lower() const
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const =0
Return the target's register information.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM_ABI std::string str() const
Return the twine contents as a std::string.
Value * lookup(StringRef Name) const
This method finds the value with the given Name in the the symbol table.
LLVM Value Representation.
An efficient, type-erasing, non-owning reference to a callable.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
@ BasicBlock
Various leaf nodes.
LLVM_ABI ID lookupIntrinsicID(StringRef Name)
This does the actual lookup of an intrinsic ID which matches the given function name.
@ System
Synchronized with respect to all concurrently executing threads.
support::ulittle32_t Word
Scope
Defines the scope in which this symbol should be visible: Default – Visible in the public interface o...
NodeAddr< NodeBase * > Node
This is an optimization pass for GlobalISel generic memory operations.
FunctionAddr VTableAddr Value
bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI, StringRef Src, SMDiagnostic &Error)
bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src, SMDiagnostic &Error)
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
RegState
Flags to represent properties of register accesses.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Kill
The last use of a register.
@ InternalRead
Register reads a value that is defined inside the same instruction or bundle.
@ Undef
Value of the register doesn't matter.
@ EarlyClobber
Register definition happens before uses.
@ Define
Register definition.
@ Renamable
Register that may be renamed.
@ Debug
Register 'use' is for debugging purpose.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
StringRef lexMIToken(StringRef Source, MIToken &Token, function_ref< void(StringRef::iterator, const Twine &)> ErrorCallback)
Consume a single machine instruction token in the given source and return the remaining source string...
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine basic block definitions, and skip the machine instructions.
LLVM_ABI void guessSuccessors(const MachineBasicBlock &MBB, SmallVectorImpl< MachineBasicBlock * > &Result, bool &IsFallthrough)
Determine a possible list of successors of a basic block based on the basic block machine operand bei...
bool parseMBBReference(PerFunctionMIParsingState &PFS, MachineBasicBlock *&MBB, StringRef Src, SMDiagnostic &Error)
uint64_t PowerOf2Ceil(uint64_t A)
Returns the power of two which is greater than or equal to the given value.
auto dyn_cast_or_null(const Y &Val)
LLVM_ABI DIExpression * parseDIExpressionBodyAtBeginning(StringRef Asm, unsigned &Read, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots)
constexpr RegState getDefRegState(bool B)
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
constexpr bool hasRegState(RegState Value, RegState Test)
AtomicOrdering
Atomic ordering for LLVM's memory model.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
DWARFExpression::Operation Op
ArrayRef(const T &OneElt) -> ArrayRef< T >
std::string toString(const APInt &I, unsigned Radix, bool Signed, bool formatAsCLiteral=false, bool UpperCase=true, bool InsertSeparators=false)
bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine instructions.
bool parseRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
LLVM_ABI Constant * parseConstantValue(StringRef Asm, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots=nullptr)
Parse a type and a constant value in the given string.
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
bool parseMachineMetadata(PerFunctionMIParsingState &PFS, StringRef Src, SMRange SourceRange, SMDiagnostic &Error)
bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS, VRegInfo *&Info, StringRef Src, SMDiagnostic &Error)
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
MDNode * NoAliasAddrSpace
The tag specifying the noalias address spaces.
MDNode * Scope
The tag for alias scope specification (used with noalias).
MDNode * TBAA
The tag for type-based alias analysis.
MDNode * NoAlias
The tag specifying the noalias scope.
This struct is a compact representation of a valid (non-zero power of two) alignment.
static constexpr LaneBitmask getAll()
LLVM_ABI static const MBBSectionID ExceptionSectionID
LLVM_ABI static const MBBSectionID ColdSectionID
A token produced by the machine instruction lexer.
bool hasIntegerValue() const
bool is(TokenKind K) const
StringRef stringValue() const
Return the token's string value.
@ kw_cfi_aarch64_negate_ra_sign_state
@ kw_cfi_llvm_def_aspace_cfa
@ kw_inlineasm_br_indirect_target
@ kw_cfi_aarch64_negate_ra_sign_state_with_pc
@ kw_cfi_def_cfa_register
@ kw_cfi_adjust_cfa_offset
@ kw_machine_block_address_taken
@ kw_ir_block_address_taken
StringRef::iterator location() const
const APSInt & integerValue() const
This class contains a discriminated union of information about pointers in memory operands,...
int64_t Offset
Offset - This is an offset from the base Value*.
VRegInfo & getVRegInfo(Register Num)
const SlotMapping & IRSlots
const Value * getIRValue(unsigned Slot)
DenseMap< unsigned, MachineBasicBlock * > MBBSlots
StringMap< VRegInfo * > VRegInfosNamed
DenseMap< unsigned, const Value * > Slots2Values
Maps from slot numbers to function's unnamed values.
PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM, const SlotMapping &IRSlots, PerTargetMIParsingState &Target)
PerTargetMIParsingState & Target
DenseMap< Register, VRegInfo * > VRegInfos
VRegInfo & getVRegInfoNamed(StringRef RegName)
BumpPtrAllocator Allocator
bool getVRegFlagValue(StringRef FlagName, uint8_t &FlagValue) const
bool getDirectTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a direct target flag to the corresponding target flag.
const RegisterBank * getRegBank(StringRef Name)
Check if the given identifier is a name of a register bank.
bool parseInstrName(StringRef InstrName, unsigned &OpCode)
Try to convert an instruction name to an opcode.
unsigned getSubRegIndex(StringRef Name)
Check if the given identifier is a name of a subregister index.
bool getTargetIndex(StringRef Name, int &Index)
Try to convert a name of target index to the corresponding target index.
void setTarget(const TargetSubtargetInfo &NewSubtarget)
bool getRegisterByName(StringRef RegName, Register &Reg)
Try to convert a register name to a register number.
bool getMMOTargetFlag(StringRef Name, MachineMemOperand::Flags &Flag)
Try to convert a name of a MachineMemOperand target flag to the corresponding target flag.
bool getBitmaskTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a bitmask target flag to the corresponding target flag.
const TargetRegisterClass * getRegClass(StringRef Name)
Check if the given identifier is a name of a register class.
const uint32_t * getRegMask(StringRef Identifier)
Check if the given identifier is a name of a register mask.
This struct contains the mappings from the slot numbers to unnamed metadata nodes,...
NumberedValues< GlobalValue * > GlobalValues
const RegisterBank * RegBank
union llvm::VRegInfo::@127225073067155374133234315364317264041071000132 D
const TargetRegisterClass * RC
enum llvm::VRegInfo::@374354327266250320012227113300214031244227062232 Kind
bool Explicit
VReg was explicitly specified in the .mir file.