LLVM  14.0.0git
AMDGPUTargetTransformInfo.h
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1 //===- AMDGPUTargetTransformInfo.h - AMDGPU specific TTI --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// AMDGPU target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
19 
20 #include "AMDGPU.h"
22 
23 namespace llvm {
24 
25 class AMDGPUTargetMachine;
26 class GCNSubtarget;
27 class InstCombiner;
28 class Loop;
29 class ScalarEvolution;
30 class SITargetLowering;
31 class Type;
32 class Value;
33 
34 class AMDGPUTTIImpl final : public BasicTTIImplBase<AMDGPUTTIImpl> {
36  using TTI = TargetTransformInfo;
37 
38  friend BaseT;
39 
40  Triple TargetTriple;
41 
42  const TargetSubtargetInfo *ST;
43  const TargetLoweringBase *TLI;
44 
45  const TargetSubtargetInfo *getST() const { return ST; }
46  const TargetLoweringBase *getTLI() const { return TLI; }
47 
48 public:
49  explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
50 
54 
57 };
58 
59 class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
61  using TTI = TargetTransformInfo;
62 
63  friend BaseT;
64 
65  const GCNSubtarget *ST;
66  const SITargetLowering *TLI;
67  AMDGPUTTIImpl CommonTTI;
68  bool IsGraphics;
69  bool HasFP32Denormals;
70  bool HasFP64FP16Denormals;
71  unsigned MaxVGPRs;
72 
73  static const FeatureBitset InlineFeatureIgnoreList;
74 
75  const GCNSubtarget *getST() const { return ST; }
76  const SITargetLowering *getTLI() const { return TLI; }
77 
78  static inline int getFullRateInstrCost() {
80  }
81 
82  static inline int getHalfRateInstrCost(TTI::TargetCostKind CostKind) {
83  return CostKind == TTI::TCK_CodeSize ? 2
85  }
86 
87  // TODO: The size is usually 8 bytes, but takes 4x as many cycles. Maybe
88  // should be 2 or 4.
89  static inline int getQuarterRateInstrCost(TTI::TargetCostKind CostKind) {
90  return CostKind == TTI::TCK_CodeSize ? 2
92  }
93 
94  // On some parts, normal fp64 operations are half rate, and others
95  // quarter. This also applies to some integer operations.
96  int get64BitInstrCost(TTI::TargetCostKind CostKind) const;
97 
98 public:
99  explicit GCNTTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
100 
101  bool hasBranchDivergence() { return true; }
102  bool useGPUDivergenceAnalysis() const;
103 
107 
110 
112  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
113  return TTI::PSK_FastHardware;
114  }
115 
116  unsigned getHardwareNumberOfRegisters(bool Vector) const;
117  unsigned getNumberOfRegisters(bool Vector) const;
118  unsigned getNumberOfRegisters(unsigned RCID) const;
120  unsigned getMinVectorRegisterBitWidth() const;
121  unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const;
122  unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
123  unsigned ChainSizeInBytes,
124  VectorType *VecTy) const;
125  unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
126  unsigned ChainSizeInBytes,
127  VectorType *VecTy) const;
128  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
129 
130  bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
131  unsigned AddrSpace) const;
132  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
133  unsigned AddrSpace) const;
134  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
135  unsigned AddrSpace) const;
137  unsigned SrcAddrSpace, unsigned DestAddrSpace,
138  unsigned SrcAlign, unsigned DestAlign) const;
139 
142  unsigned RemainingBytes,
143  unsigned SrcAddrSpace,
144  unsigned DestAddrSpace,
145  unsigned SrcAlign,
146  unsigned DestAlign) const;
147  unsigned getMaxInterleaveFactor(unsigned VF);
148 
150 
152  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
158  const Instruction *CxtI = nullptr);
159 
161  const Instruction *I = nullptr);
162 
164  ArrayRef<unsigned> Indices = {}) const;
165 
166  InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy,
167  unsigned Index);
168  bool isSourceOfDivergence(const Value *V) const;
169  bool isAlwaysUniform(const Value *V) const;
170 
171  unsigned getFlatAddressSpace() const {
172  // Don't bother running InferAddressSpaces pass on graphics shaders which
173  // don't use flat addressing.
174  if (IsGraphics)
175  return -1;
176  return AMDGPUAS::FLAT_ADDRESS;
177  }
178 
180  Intrinsic::ID IID) const;
181 
183  return AS != AMDGPUAS::LOCAL_ADDRESS && AS != AMDGPUAS::REGION_ADDRESS &&
185  }
186 
188  Value *NewV) const;
189 
190  bool canSimplifyLegacyMulToMul(const Value *Op0, const Value *Op1,
191  InstCombiner &IC) const;
193  IntrinsicInst &II) const;
195  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
196  APInt &UndefElts2, APInt &UndefElts3,
197  std::function<void(Instruction *, unsigned, APInt, APInt &)>
198  SimplifyAndSetOp) const;
199 
201 
203  ArrayRef<int> Mask, int Index,
204  VectorType *SubTp);
205 
206  bool areInlineCompatible(const Function *Caller,
207  const Function *Callee) const;
208 
209  unsigned getInliningThresholdMultiplier() { return 11; }
210  unsigned adjustInliningThreshold(const CallBase *CB) const;
211 
212  int getInlinerVectorBonusPercent() { return 0; }
213 
215  unsigned Opcode, VectorType *Ty, Optional<FastMathFlags> FMF,
217 
221  VectorType *Ty, VectorType *CondTy, bool IsUnsigned,
223 };
224 
225 } // end namespace llvm
226 
227 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::PSK_FastHardware
@ PSK_FastHardware
Definition: TargetTransformInfo.h:592
llvm::GCNTTIImpl::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
Definition: AMDGPUTargetTransformInfo.cpp:865
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::TargetLoweringBase
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
Definition: TargetLowering.h:192
llvm::GCNTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: AMDGPUTargetTransformInfo.cpp:1228
llvm::AMDGPUAS::PRIVATE_ADDRESS
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:364
llvm::Function
Definition: Function.h:62
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:592
llvm::GCNTTIImpl::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Definition: AMDGPUTargetTransformInfo.cpp:958
InstCombiner
Machine InstCombiner
Definition: MachineCombiner.cpp:136
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:460
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::TargetTransformInfo::TCK_CodeSize
@ TCK_CodeSize
Instruction code size.
Definition: TargetTransformInfo.h:214
llvm::GCNTTIImpl::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: AMDGPUTargetTransformInfo.cpp:413
llvm::GCNTTIImpl::isLegalToVectorizeMemChain
bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: AMDGPUTargetTransformInfo.cpp:381
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::GCNTTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: AMDGPUTargetTransformInfo.cpp:476
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:535
llvm::AMDGPUTTIImpl
Definition: AMDGPUTargetTransformInfo.h:34
llvm::Optional
Definition: APInt.h:33
llvm::GCNTTIImpl::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: AMDGPUTargetTransformInfo.cpp:1159
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::GCNTTIImpl::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Definition: AMDGPUTargetTransformInfo.cpp:847
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
F
#define F(x, y, z)
Definition: MD5.cpp:56
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::GCNTTIImpl::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: AMDGPUInstCombineIntrinsic.cpp:191
llvm::AMDGPUTargetMachine
Definition: AMDGPUTargetMachine.h:29
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:886
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:859
llvm::GCNTTIImpl::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: AMDGPUTargetTransformInfo.cpp:400
llvm::GCNTTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: AMDGPUTargetTransformInfo.cpp:333
llvm::AMDGPUAS::LOCAL_ADDRESS
@ LOCAL_ADDRESS
Address space for local memory.
Definition: AMDGPU.h:363
llvm::GCNTTIImpl::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: AMDGPUTargetTransformInfo.cpp:441
llvm::GCNTTIImpl::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: AMDGPUTargetTransformInfo.cpp:345
llvm::Instruction
Definition: Instruction.h:45
llvm::GCNTTIImpl::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier()
Definition: AMDGPUTargetTransformInfo.h:209
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::GCNTTIImpl::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: AMDGPUTargetTransformInfo.cpp:996
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AMDGPUTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: AMDGPUTargetTransformInfo.cpp:262
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:118
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::GCNTTIImpl::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: AMDGPUTargetTransformInfo.cpp:485
llvm::GCNTTIImpl::hasBranchDivergence
bool hasBranchDivergence()
Definition: AMDGPUTargetTransformInfo.h:101
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::AMDGPUTTIImpl::AMDGPUTTIImpl
AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
Definition: AMDGPUTargetTransformInfo.cpp:98
llvm::GCNTTIImpl
Definition: AMDGPUTargetTransformInfo.h:59
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:428
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:886
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:77
TemplateParamKind::Type
@ Type
llvm::AMDGPUAS::REGION_ADDRESS
@ REGION_ADDRESS
Address space for region memory. (GDS)
Definition: AMDGPU.h:360
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::AMDGPUAS::FLAT_ADDRESS
@ FLAT_ADDRESS
Address space for flat memory.
Definition: AMDGPU.h:358
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:878
llvm::GCNTTIImpl::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent()
Definition: AMDGPUTargetTransformInfo.h:212
llvm::GCNTTIImpl::getVectorSplitCost
InstructionCost getVectorSplitCost()
Definition: AMDGPUTargetTransformInfo.h:200
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::GCNTTIImpl::canHaveNonUndefGlobalInitializerInAddressSpace
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Definition: AMDGPUTargetTransformInfo.h:182
llvm::GCNTTIImpl::getHardwareNumberOfRegisters
unsigned getHardwareNumberOfRegisters(bool Vector) const
Definition: AMDGPUTargetTransformInfo.cpp:301
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
llvm::AMDGPUTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: AMDGPUTargetTransformInfo.cpp:104
AMDGPU.h
llvm::GCNTTIImpl::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: AMDGPUTargetTransformInfo.cpp:394
llvm::GCNTTIImpl::isInlineAsmSourceOfDivergence
bool isInlineAsmSourceOfDivergence(const CallInst *CI, ArrayRef< unsigned > Indices={}) const
Analyze if the results of inline asm are divergent.
Definition: AMDGPUTargetTransformInfo.cpp:908
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::GCNTTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const
Definition: AMDGPUTargetTransformInfo.cpp:321
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:879
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:59
llvm::GCNTTIImpl::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: AMDGPUTargetTransformInfo.cpp:337
llvm::GCNTTIImpl::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: AMDGPUTargetTransformInfo.cpp:816
llvm::GCNTTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(bool Vector) const
Definition: AMDGPUTargetTransformInfo.cpp:307
llvm::GCNTTIImpl::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Definition: AMDGPUTargetTransformInfo.cpp:1046
llvm::GCNTTIImpl::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: AMDGPUTargetTransformInfo.cpp:366
llvm::GCNTTIImpl::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: AMDGPUTargetTransformInfo.cpp:356
llvm::TypeSize
Definition: TypeSize.h:417
llvm::GCNTTIImpl::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Definition: AMDGPUTargetTransformInfo.h:111
llvm::SITargetLowering
Definition: SIISelLowering.h:31
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::GCNTTIImpl::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: AMDGPUTargetTransformInfo.cpp:1198
llvm::GCNTTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: AMDGPUTargetTransformInfo.cpp:516
llvm::GCNTTIImpl::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Definition: AMDGPUTargetTransformInfo.h:171
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::GCNTTIImpl::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Definition: AMDGPUTargetTransformInfo.cpp:1063
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:907
llvm::GCNTTIImpl::GCNTTIImpl
GCNTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
Definition: AMDGPUTargetTransformInfo.cpp:287
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:70
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1161
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1475
llvm::GCNTTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp)
Definition: AMDGPUTargetTransformInfo.cpp:1135
llvm::TargetTransformInfo::TCC_Basic
@ TCC_Basic
The cost of a typical 'add' instruction.
Definition: TargetTransformInfo.h:263
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::GCNTTIImpl::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Definition: AMDGPUTargetTransformInfo.cpp:952
llvm::GCNTTIImpl::canSimplifyLegacyMulToMul
bool canSimplifyLegacyMulToMul(const Value *Op0, const Value *Op1, InstCombiner &IC) const
Definition: AMDGPUInstCombineIntrinsic.cpp:169
BasicTTIImpl.h
llvm::GCNTTIImpl::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: AMDGPUInstCombineIntrinsic.cpp:1047
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::GCNTTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: AMDGPUTargetTransformInfo.cpp:736
llvm::GCNTTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index)
Definition: AMDGPUTargetTransformInfo.cpp:879
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::GCNTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: AMDGPUTargetTransformInfo.cpp:1234