LLVM 17.0.0git
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#include "Target/AMDGPU/AMDGPUTargetTransformInfo.h"
Definition at line 60 of file AMDGPUTargetTransformInfo.h.
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explicit |
Definition at line 290 of file AMDGPUTargetTransformInfo.cpp.
References F.
Definition at line 1216 of file AMDGPUTargetTransformInfo.cpp.
References adjustInliningThresholdUsingCallee(), ArgAllocaCost, ArgAllocaCutoff, llvm::CallBase::args(), llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::AMDGPUAS::FLAT_ADDRESS, llvm::PointerType::getAddressSpace(), llvm::DataLayout::getTypeAllocSize(), llvm::getUnderlyingObject(), llvm::SmallPtrSetImpl< PtrType >::insert(), and llvm::AMDGPUAS::PRIVATE_ADDRESS.
Definition at line 1131 of file AMDGPUTargetTransformInfo.cpp.
References Callee, llvm::TargetLoweringBase::getTargetMachine(), InlineMaxBB, llvm::SIModeRegisterDefaults::isInlineCompatible(), and TM.
Definition at line 204 of file AMDGPUTargetTransformInfo.h.
References llvm::AMDGPUAS::LOCAL_ADDRESS, llvm::AMDGPUAS::PRIVATE_ADDRESS, and llvm::AMDGPUAS::REGION_ADDRESS.
bool GCNTTIImpl::canSimplifyLegacyMulToMul | ( | const Instruction & | I, |
const Value * | Op0, | ||
const Value * | Op1, | ||
InstCombiner & | IC | ||
) | const |
Definition at line 332 of file AMDGPUInstCombineIntrinsic.cpp.
References llvm::InstCombiner::getAssumptionCache(), llvm::InstCombiner::getDataLayout(), llvm::InstCombiner::getDominatorTree(), llvm::InstCombiner::getOptimizationRemarkEmitter(), llvm::InstCombiner::getTargetLibraryInfo(), I, llvm::isKnownNeverInfOrNaN(), llvm::PatternMatch::m_FiniteNonZero(), and llvm::PatternMatch::match().
Referenced by instCombineIntrinsic().
bool GCNTTIImpl::collectFlatAddressOperands | ( | SmallVectorImpl< int > & | OpIndexes, |
Intrinsic::ID | IID | ||
) | const |
Definition at line 998 of file AMDGPUTargetTransformInfo.cpp.
References llvm::SmallVectorTemplateBase< T, bool >::push_back().
InstructionCost GCNTTIImpl::getArithmeticInstrCost | ( | unsigned | Opcode, |
Type * | Ty, | ||
TTI::TargetCostKind | CostKind, | ||
TTI::OperandValueInfo | Op1Info = {TTI::OK_AnyValue, TTI::OP_None} , |
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TTI::OperandValueInfo | Op2Info = {TTI::OK_AnyValue, TTI::OP_None} , |
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ArrayRef< const Value * > | Args = ArrayRef<const Value *>() , |
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const Instruction * | CxtI = nullptr |
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) |
Definition at line 517 of file AMDGPUTargetTransformInfo.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, CostKind, llvm::FAdd, llvm::ISD::FADD, llvm::FPOpFusion::Fast, llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FREM, llvm::ISD::FSUB, llvm::BasicTTIImplBase< GCNTTIImpl >::getArithmeticInstrCost(), llvm::TargetLoweringBase::getTargetMachine(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::Instruction::hasAllowContract(), llvm::AMDGPUSubtarget::hasMadMacF32Insts(), llvm::Value::hasOneUse(), llvm::GCNSubtarget::hasPackedFP32Ops(), llvm::GCNSubtarget::hasUsableDivScaleConditionOutput(), llvm::TargetLoweringBase::InstructionOpcodeToISD(), llvm::AMDGPUTargetLowering::isFNegFree(), llvm::PatternMatch::m_FPOne(), llvm::PatternMatch::match(), llvm::ISD::MUL, llvm::TargetMachine::Options, Options, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::TargetTransformInfo::TCC_Free, llvm::Value::user_begin(), and llvm::ISD::XOR.
InstructionCost GCNTTIImpl::getArithmeticReductionCost | ( | unsigned | Opcode, |
VectorType * | Ty, | ||
std::optional< FastMathFlags > | FMF, | ||
TTI::TargetCostKind | CostKind | ||
) |
Definition at line 762 of file AMDGPUTargetTransformInfo.cpp.
References CostKind, llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::BasicTTIImplBase< GCNTTIImpl >::getArithmeticReductionCost(), llvm::EVT::getScalarSizeInBits(), llvm::TargetLoweringBase::getValueType(), llvm::AMDGPUSubtarget::hasVOP3PInsts(), and llvm::TargetTransformInfo::requiresOrderedReduction().
InstructionCost GCNTTIImpl::getCFInstrCost | ( | unsigned | Opcode, |
TTI::TargetCostKind | CostKind, | ||
const Instruction * | I = nullptr |
||
) |
Definition at line 731 of file AMDGPUTargetTransformInfo.cpp.
References assert(), CostKind, llvm::BasicTTIImplBase< GCNTTIImpl >::getCFInstrCost(), I, SI, llvm::TargetTransformInfo::TCK_CodeSize, and llvm::TargetTransformInfo::TCK_SizeAndLatency.
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inline |
Definition at line 193 of file AMDGPUTargetTransformInfo.h.
References llvm::AMDGPUAS::FLAT_ADDRESS.
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inline |
Definition at line 236 of file AMDGPUTargetTransformInfo.h.
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inline |
Definition at line 233 of file AMDGPUTargetTransformInfo.h.
InstructionCost GCNTTIImpl::getIntrinsicInstrCost | ( | const IntrinsicCostAttributes & | ICA, |
TTI::TargetCostKind | CostKind | ||
) |
Definition at line 685 of file AMDGPUTargetTransformInfo.cpp.
References llvm::any_of(), CostKind, llvm::IntrinsicCostAttributes::getID(), llvm::BasicTTIImplBase< GCNTTIImpl >::getIntrinsicInstrCost(), llvm::IntrinsicCostAttributes::getReturnType(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::GCNSubtarget::hasFastFMAF32(), llvm::GCNSubtarget::hasPackedFP32Ops(), intrinsicHasPackedVectorBenefit(), and RetTy.
Definition at line 357 of file AMDGPUTargetTransformInfo.cpp.
References llvm::AMDGPUAS::BUFFER_FAT_POINTER, llvm::AMDGPUAS::BUFFER_RESOURCE, llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::GCNSubtarget::getMaxPrivateElementSize(), llvm::AMDGPUAS::GLOBAL_ADDRESS, and llvm::AMDGPUAS::PRIVATE_ADDRESS.
unsigned GCNTTIImpl::getLoadVectorFactor | ( | unsigned | VF, |
unsigned | LoadSize, | ||
unsigned | ChainSizeInBytes, | ||
VectorType * | VecTy | ||
) | const |
Definition at line 336 of file AMDGPUTargetTransformInfo.cpp.
References llvm::Type::getScalarSizeInBits().
Definition at line 328 of file AMDGPUTargetTransformInfo.cpp.
References llvm::AMDGPUSubtarget::has16BitInsts(), and llvm::GCNSubtarget::hasPackedFP32Ops().
unsigned GCNTTIImpl::getMaxInterleaveFactor | ( | ElementCount | VF | ) |
Definition at line 477 of file AMDGPUTargetTransformInfo.cpp.
References llvm::ElementCount::isScalar().
Type * GCNTTIImpl::getMemcpyLoopLoweringType | ( | LLVMContext & | Context, |
Value * | Length, | ||
unsigned | SrcAddrSpace, | ||
unsigned | DestAddrSpace, | ||
unsigned | SrcAlign, | ||
unsigned | DestAlign, | ||
std::optional< uint32_t > | AtomicElementSize | ||
) | const |
Definition at line 405 of file AMDGPUTargetTransformInfo.cpp.
References Context, llvm::FixedVectorType::get(), llvm::Type::getInt16Ty(), llvm::Type::getInt32Ty(), llvm::Type::getIntNTy(), llvm::AMDGPUAS::LOCAL_ADDRESS, llvm::MinAlign(), and llvm::AMDGPUAS::REGION_ADDRESS.
void GCNTTIImpl::getMemcpyLoopResidualLoweringType | ( | SmallVectorImpl< Type * > & | OpsOut, |
LLVMContext & | Context, | ||
unsigned | RemainingBytes, | ||
unsigned | SrcAddrSpace, | ||
unsigned | DestAddrSpace, | ||
unsigned | SrcAlign, | ||
unsigned | DestAlign, | ||
std::optional< uint32_t > | AtomicCpySize | ||
) | const |
Definition at line 436 of file AMDGPUTargetTransformInfo.cpp.
References assert(), Context, llvm::Type::getInt16Ty(), llvm::Type::getInt32Ty(), llvm::Type::getInt64Ty(), llvm::Type::getInt8Ty(), llvm::TargetTransformInfoImplBase::getMemcpyLoopResidualLoweringType(), llvm::MinAlign(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().
InstructionCost GCNTTIImpl::getMinMaxReductionCost | ( | VectorType * | Ty, |
VectorType * | CondTy, | ||
bool | IsUnsigned, | ||
FastMathFlags | FMF, | ||
TTI::TargetCostKind | CostKind | ||
) |
Definition at line 780 of file AMDGPUTargetTransformInfo.cpp.
References CostKind, llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::BasicTTIImplBase< GCNTTIImpl >::getMinMaxReductionCost(), llvm::EVT::getScalarSizeInBits(), llvm::TargetLoweringBase::getValueType(), and llvm::AMDGPUSubtarget::hasVOP3PInsts().
unsigned GCNTTIImpl::getMinVectorRegisterBitWidth | ( | ) | const |
Definition at line 324 of file AMDGPUTargetTransformInfo.cpp.
Definition at line 300 of file AMDGPUTargetTransformInfo.cpp.
void GCNTTIImpl::getPeelingPreferences | ( | Loop * | L, |
ScalarEvolution & | SE, | ||
TTI::PeelingPreferences & | PP | ||
) |
Definition at line 1254 of file AMDGPUTargetTransformInfo.cpp.
References llvm::AMDGPUTTIImpl::getPeelingPreferences().
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inline |
Definition at line 112 of file AMDGPUTargetTransformInfo.h.
References assert(), llvm::isPowerOf2_32(), and llvm::TargetTransformInfo::PSK_FastHardware.
TypeSize GCNTTIImpl::getRegisterBitWidth | ( | TargetTransformInfo::RegisterKind | Vector | ) | const |
Definition at line 312 of file AMDGPUTargetTransformInfo.cpp.
References llvm::TypeSize::getFixed(), llvm::TypeSize::getScalable(), llvm::GCNSubtarget::hasPackedFP32Ops(), llvm_unreachable, llvm::TargetTransformInfo::RGK_FixedWidthVector, llvm::TargetTransformInfo::RGK_ScalableVector, and llvm::TargetTransformInfo::RGK_Scalar.
InstructionCost GCNTTIImpl::getShuffleCost | ( | TTI::ShuffleKind | Kind, |
VectorType * | Tp, | ||
ArrayRef< int > | Mask, | ||
TTI::TargetCostKind | CostKind, | ||
int | Index, | ||
VectorType * | SubTp, | ||
ArrayRef< const Value * > | Args = std::nullopt |
||
) |
Definition at line 1105 of file AMDGPUTargetTransformInfo.cpp.
References CostKind, llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::VectorType::getElementType(), llvm::BasicTTIImplBase< GCNTTIImpl >::getShuffleCost(), llvm::DataLayout::getTypeSizeInBits(), llvm::AMDGPUSubtarget::hasVOP3PInsts(), llvm::BasicTTIImplBase< GCNTTIImpl >::improveShuffleKindFromMask(), llvm::TargetTransformInfo::SK_Broadcast, llvm::TargetTransformInfo::SK_PermuteSingleSrc, and llvm::TargetTransformInfo::SK_Reverse.
unsigned GCNTTIImpl::getStoreVectorFactor | ( | unsigned | VF, |
unsigned | StoreSize, | ||
unsigned | ChainSizeInBytes, | ||
VectorType * | VecTy | ||
) | const |
Definition at line 347 of file AMDGPUTargetTransformInfo.cpp.
bool GCNTTIImpl::getTgtMemIntrinsic | ( | IntrinsicInst * | Inst, |
MemIntrinsicInfo & | Info | ||
) | const |
Definition at line 486 of file AMDGPUTargetTransformInfo.cpp.
References llvm::CallBase::getArgOperand(), llvm::IntrinsicInst::getIntrinsicID(), Info, and llvm::SequentiallyConsistent.
void GCNTTIImpl::getUnrollingPreferences | ( | Loop * | L, |
ScalarEvolution & | SE, | ||
TTI::UnrollingPreferences & | UP, | ||
OptimizationRemarkEmitter * | ORE | ||
) |
Definition at line 1248 of file AMDGPUTargetTransformInfo.cpp.
References llvm::AMDGPUTTIImpl::getUnrollingPreferences().
InstructionCost GCNTTIImpl::getVectorInstrCost | ( | unsigned | Opcode, |
Type * | ValTy, | ||
TTI::TargetCostKind | CostKind, | ||
unsigned | Index, | ||
Value * | Op0, | ||
Value * | Op1 | ||
) |
Definition at line 794 of file AMDGPUTargetTransformInfo.cpp.
References CostKind, llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::DataLayout::getTypeSizeInBits(), llvm::BasicTTIImplBase< GCNTTIImpl >::getVectorInstrCost(), and llvm::AMDGPUSubtarget::has16BitInsts().
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Definition at line 222 of file AMDGPUTargetTransformInfo.h.
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inline |
Definition at line 103 of file AMDGPUTargetTransformInfo.h.
std::optional< Instruction * > GCNTTIImpl::instCombineIntrinsic | ( | InstCombiner & | IC, |
IntrinsicInst & | II | ||
) | const |
Definition at line 380 of file AMDGPUInstCombineIntrinsic.cpp.
References llvm::CallBase::addFnAttr(), assert(), llvm::InstCombiner::Builder, llvm::CallingConv::C, canSimplifyLegacyMulToMul(), CC, llvm::APFloat::convert(), llvm::Instruction::copyFastMathFlags(), llvm::IRBuilderBase::CreateAShr(), llvm::IRBuilderBase::CreateCall(), llvm::IRBuilderBase::CreateFAddFMF(), llvm::IRBuilderBase::CreateFMulFMF(), llvm::IRBuilderBase::CreateIntrinsic(), llvm::IRBuilderBase::CreateLShr(), llvm::IRBuilderBase::CreateMaxNum(), llvm::IRBuilderBase::CreateMinNum(), llvm::IRBuilderBase::CreateSExt(), llvm::IRBuilderBase::CreateShl(), llvm::IRBuilderBase::CreateZExt(), llvm::APFloat::divide(), llvm::InstCombiner::eraseInstFromFunction(), llvm::FAdd, llvm::fcAllFlags, llvm::CmpInst::FIRST_FCMP_PREDICATE, llvm::CmpInst::FIRST_ICMP_PREDICATE, fmed3AMDGCN(), llvm::FMul, llvm::frexp(), llvm::ConstantVector::get(), llvm::MDNode::get(), llvm::MetadataAsValue::get(), llvm::MDString::get(), llvm::UndefValue::get(), llvm::ConstantFP::get(), llvm::ConstantInt::get(), llvm::CallBase::getArgOperand(), llvm::ConstantExpr::getCompare(), llvm::IRBuilderBase::getContext(), llvm::Value::getContext(), llvm::Intrinsic::getDeclaration(), llvm::ConstantInt::getFalse(), llvm::Type::getFltSemantics(), llvm::AMDGPU::getImageDimIntrinsicInfo(), llvm::Type::getIntegerBitWidth(), llvm::IRBuilderBase::getIntNTy(), llvm::IntrinsicInst::getIntrinsicID(), llvm::CmpInst::getInversePredicate(), llvm::Instruction::getModule(), llvm::Value::getName(), llvm::Constant::getNullValue(), llvm::Instruction::getParent(), llvm::APFloat::getQNaN(), llvm::Type::getScalarType(), llvm::APFloat::getSemantics(), llvm::ConstantExpr::getSExt(), llvm::CmpInst::getSwappedPredicate(), llvm::ConstantInt::getType(), llvm::Value::getType(), llvm::ConstantFP::getZero(), llvm::ConstantInt::getZExtValue(), llvm::GCNSubtarget::hasMed3_16(), I, llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, llvm::APFloatBase::IEK_Inf, llvm::APFloatBase::IEK_NaN, llvm::Type::isDoubleTy(), llvm::Type::isFloatTy(), llvm::CmpInst::isFPPredicate(), llvm::Type::isHalfTy(), llvm::Type::isIntegerTy(), llvm::Constant::isNullValue(), llvm::CmpInst::isSigned(), llvm::CallBase::isStrictFP(), llvm::CmpInst::LAST_FCMP_PREDICATE, llvm::CmpInst::LAST_ICMP_PREDICATE, llvm::PatternMatch::m_AllOnes(), llvm::PatternMatch::m_AnyZeroFP(), llvm::PatternMatch::m_APFloat(), llvm::PatternMatch::m_Cmp(), llvm::PatternMatch::m_NaN(), llvm::PatternMatch::m_One(), llvm::PatternMatch::m_SExt(), llvm::PatternMatch::m_Specific(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Zero(), llvm::PatternMatch::m_ZeroInt(), llvm::PatternMatch::m_ZExt(), llvm::PatternMatch::m_ZExtOrSExt(), llvm::PatternMatch::match(), matchFPExtFromF16(), llvm::Offset, RegName, llvm::InstCombiner::replaceInstUsesWith(), llvm::InstCombiner::replaceOperand(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::rmTowardZero, llvm::CallBase::setArgOperand(), llvm::CallBase::setCalledOperand(), Signed, simplifyAMDGCNImageIntrinsic(), std::swap(), llvm::Value::takeName(), X, and Y.
Definition at line 927 of file AMDGPUTargetTransformInfo.cpp.
References llvm::CallingConv::C, llvm::computeKnownBits(), llvm::BasicTTIImplBase< GCNTTIImpl >::DL, F, llvm::ExtractValueInst::getIndices(), llvm::AMDGPUSubtarget::getMaxWorkitemID(), llvm::User::getOperand(), llvm::AMDGPUSubtarget::getWavefrontSizeLog2(), llvm::CallBase::isInlineAsm(), isInlineAsmSourceOfDivergence(), llvm::AMDGPU::isIntrinsicAlwaysUniform(), llvm::PatternMatch::m_AShr(), llvm::PatternMatch::m_c_And(), llvm::PatternMatch::m_ConstantInt(), llvm::PatternMatch::m_LShr(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::match(), and llvm::ArrayRef< T >::size().
bool GCNTTIImpl::isInlineAsmSourceOfDivergence | ( | const CallInst * | CI, |
ArrayRef< unsigned > | Indices = {} |
||
) | const |
Analyze if the results of inline asm are divergent.
If Indices
is empty, this is analyzing the collective result of all output registers. Otherwise, this is only querying a specific result index if this returns multiple registers in a struct.
Definition at line 826 of file AMDGPUTargetTransformInfo.cpp.
References llvm::TargetLowering::ComputeConstraintToUse(), llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::ArrayRef< T >::empty(), llvm::Module::getDataLayout(), llvm::Instruction::getModule(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::GCNSubtarget::getRegisterInfo(), llvm::InlineAsm::isOutput, llvm::TargetLowering::ParseConstraints(), llvm::ArrayRef< T >::size(), and TRI.
Referenced by isAlwaysUniform(), and isSourceOfDivergence().
bool GCNTTIImpl::isLegalToVectorizeLoadChain | ( | unsigned | ChainSizeInBytes, |
Align | Alignment, | ||
unsigned | AddrSpace | ||
) | const |
Definition at line 386 of file AMDGPUTargetTransformInfo.cpp.
References isLegalToVectorizeMemChain().
bool GCNTTIImpl::isLegalToVectorizeMemChain | ( | unsigned | ChainSizeInBytes, |
Align | Alignment, | ||
unsigned | AddrSpace | ||
) | const |
Definition at line 373 of file AMDGPUTargetTransformInfo.cpp.
References llvm::GCNSubtarget::getMaxPrivateElementSize(), llvm::GCNSubtarget::hasUnalignedScratchAccess(), and llvm::AMDGPUAS::PRIVATE_ADDRESS.
Referenced by isLegalToVectorizeLoadChain(), and isLegalToVectorizeStoreChain().
bool GCNTTIImpl::isLegalToVectorizeStoreChain | ( | unsigned | ChainSizeInBytes, |
Align | Alignment, | ||
unsigned | AddrSpace | ||
) | const |
Definition at line 392 of file AMDGPUTargetTransformInfo.cpp.
References isLegalToVectorizeMemChain().
bool GCNTTIImpl::isReadRegisterSourceOfDivergence | ( | const IntrinsicInst * | ReadReg | ) | const |
Definition at line 862 of file AMDGPUTargetTransformInfo.cpp.
References llvm::CallBase::getArgOperand(), llvm::Value::getType(), llvm::MVT::getVT(), and RegName.
Referenced by isSourceOfDivergence().
Definition at line 885 of file AMDGPUTargetTransformInfo.cpp.
References A, llvm::AMDGPUAS::FLAT_ADDRESS, llvm::AMDGPU::isArgPassedInSGPR(), isInlineAsmSourceOfDivergence(), llvm::AMDGPU::isIntrinsicSourceOfDivergence(), isReadRegisterSourceOfDivergence(), and llvm::AMDGPUAS::PRIVATE_ADDRESS.
Definition at line 171 of file AMDGPUTargetTransformInfo.h.
References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::AMDGPUAS::FLAT_ADDRESS, llvm::AMDGPUAS::GLOBAL_ADDRESS, llvm::AMDGPUAS::LOCAL_ADDRESS, and llvm::AMDGPUAS::PRIVATE_ADDRESS.
Value * GCNTTIImpl::rewriteIntrinsicWithAddressSpace | ( | IntrinsicInst * | II, |
Value * | OldV, | ||
Value * | NewV | ||
) | const |
Definition at line 1018 of file AMDGPUTargetTransformInfo.cpp.
References B, llvm::computeKnownBits(), llvm::KnownBits::countMinLeadingOnes(), llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::CallBase::getArgOperand(), llvm::Type::getContext(), llvm::Intrinsic::getDeclaration(), llvm::ConstantInt::getFalse(), llvm::IntrinsicInst::getIntrinsicID(), llvm::Instruction::getModule(), llvm::GlobalValue::getParent(), llvm::BasicBlock::getParent(), llvm::Instruction::getParent(), llvm::Type::getPointerAddressSpace(), llvm::DataLayout::getPointerSizeInBits(), llvm::TargetLoweringBase::getTargetMachine(), llvm::ConstantInt::getTrue(), llvm::Value::getType(), llvm::AMDGPU::isExtendedGlobalAddrSpace(), llvm::AMDGPUAS::LOCAL_ADDRESS, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::CallBase::setArgOperand(), llvm::CallBase::setCalledFunction(), and TM.
std::optional< Value * > GCNTTIImpl::simplifyDemandedVectorEltsIntrinsic | ( | InstCombiner & | IC, |
IntrinsicInst & | II, | ||
APInt | DemandedElts, | ||
APInt & | UndefElts, | ||
APInt & | UndefElts2, | ||
APInt & | UndefElts3, | ||
std::function< void(Instruction *, unsigned, APInt, APInt &)> | SimplifyAndSetOp | ||
) | const |
Definition at line 1181 of file AMDGPUInstCombineIntrinsic.cpp.
References llvm::IntrinsicInst::getIntrinsicID(), and simplifyAMDGCNMemoryIntrinsicDemanded().