LLVM 20.0.0git
Public Member Functions | List of all members
llvm::GCNTTIImpl Class Referencefinal

#include "Target/AMDGPU/AMDGPUTargetTransformInfo.h"

Inheritance diagram for llvm::GCNTTIImpl:
Inheritance graph
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Public Member Functions

 GCNTTIImpl (const AMDGPUTargetMachine *TM, const Function &F)
 
bool hasBranchDivergence (const Function *F=nullptr) const
 
void getUnrollingPreferences (Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
 
void getPeelingPreferences (Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
 
TTI::PopcntSupportKind getPopcntSupport (unsigned TyWidth)
 
unsigned getNumberOfRegisters (unsigned RCID) const
 
TypeSize getRegisterBitWidth (TargetTransformInfo::RegisterKind Vector) const
 
unsigned getMinVectorRegisterBitWidth () const
 
unsigned getMaximumVF (unsigned ElemWidth, unsigned Opcode) const
 
unsigned getLoadVectorFactor (unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
 
unsigned getStoreVectorFactor (unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
 
unsigned getLoadStoreVecRegBitWidth (unsigned AddrSpace) const
 
bool isLegalToVectorizeMemChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
 
bool isLegalToVectorizeLoadChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
 
bool isLegalToVectorizeStoreChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
 
int64_t getMaxMemIntrinsicInlineSizeThreshold () const
 
Type * getMemcpyLoopLoweringType (LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicElementSize) const
 
void getMemcpyLoopResidualLoweringType (SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicCpySize) const
 
unsigned getMaxInterleaveFactor (ElementCount VF)
 
bool getTgtMemIntrinsic (IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
 
InstructionCost getArithmeticInstrCost (unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr)
 
InstructionCost getCFInstrCost (unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
bool isInlineAsmSourceOfDivergence (const CallInst *CI, ArrayRef< unsigned > Indices={}) const
 Analyze if the results of inline asm are divergent.
 
InstructionCost getVectorInstrCost (unsigned Opcode, Type *ValTy, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
 
bool isReadRegisterSourceOfDivergence (const IntrinsicInst *ReadReg) const
 
bool isSourceOfDivergence (const Value *V) const
 
bool isAlwaysUniform (const Value *V) const
 
bool isValidAddrSpaceCast (unsigned FromAS, unsigned ToAS) const
 
bool addrspacesMayAlias (unsigned AS0, unsigned AS1) const
 
unsigned getFlatAddressSpace () const
 
bool collectFlatAddressOperands (SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
 
bool canHaveNonUndefGlobalInitializerInAddressSpace (unsigned AS) const
 
Value * rewriteIntrinsicWithAddressSpace (IntrinsicInst *II, Value *OldV, Value *NewV) const
 
bool canSimplifyLegacyMulToMul (const Instruction &I, const Value *Op0, const Value *Op1, InstCombiner &IC) const
 
bool simplifyDemandedLaneMaskArg (InstCombiner &IC, IntrinsicInst &II, unsigned LaneAgIdx) const
 Simplify a lane index operand (e.g.
 
std::optional< Instruction * > instCombineIntrinsic (InstCombiner &IC, IntrinsicInst &II) const
 
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
 
InstructionCost getVectorSplitCost ()
 
InstructionCost getShuffleCost (TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr)
 
bool isProfitableToSinkOperands (Instruction *I, SmallVectorImpl< Use * > &Ops) const
 Whether it is profitable to sink the operands of an Instruction I to the basic block of I.
 
bool areInlineCompatible (const Function *Caller, const Function *Callee) const
 
int getInliningLastCallToStaticBonus () const
 
unsigned getInliningThresholdMultiplier () const
 
unsigned adjustInliningThreshold (const CallBase *CB) const
 
unsigned getCallerAllocaCost (const CallBase *CB, const AllocaInst *AI) const
 
int getInlinerVectorBonusPercent () const
 
InstructionCost getArithmeticReductionCost (unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
 
InstructionCost getIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
 
InstructionCost getMinMaxReductionCost (Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind)
 
unsigned getCacheLineSize () const override
 Data cache line size for LoopDataPrefetch pass. Has no use before GFX12.
 
unsigned getPrefetchDistance () const override
 How much before a load we should place the prefetch instruction.
 
bool shouldPrefetchAddressSpace (unsigned AS) const override
 
- Public Member Functions inherited from llvm::BasicTTIImplBase< GCNTTIImpl >
bool allowsMisalignedMemoryAccesses (LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, unsigned *Fast) const
 
bool areInlineCompatible (const Function *Caller, const Function *Callee) const
 
bool hasBranchDivergence (const Function *F=nullptr)
 
bool isSourceOfDivergence (const Value *V)
 
bool isAlwaysUniform (const Value *V)
 
bool isValidAddrSpaceCast (unsigned FromAS, unsigned ToAS) const
 
bool addrspacesMayAlias (unsigned AS0, unsigned AS1) const
 
unsigned getFlatAddressSpace ()
 
bool collectFlatAddressOperands (SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
 
bool isNoopAddrSpaceCast (unsigned FromAS, unsigned ToAS) const
 
unsigned getAssumedAddrSpace (const Value *V) const
 
bool isSingleThreaded () const
 
std::pair< const Value *, unsigned > getPredicatedAddrSpace (const Value *V) const
 
Value * rewriteIntrinsicWithAddressSpace (IntrinsicInst *II, Value *OldV, Value *NewV) const
 
bool isLegalAddImmediate (int64_t imm)
 
bool isLegalAddScalableImmediate (int64_t Imm)
 
bool isLegalICmpImmediate (int64_t imm)
 
bool isLegalAddressingMode (Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr, int64_t ScalableOffset=0)
 
int64_t getPreferredLargeGEPBaseOffset (int64_t MinOffset, int64_t MaxOffset)
 
unsigned getStoreMinimumVF (unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const
 
bool isIndexedLoadLegal (TTI::MemIndexedMode M, Type *Ty, const DataLayout &DL) const
 
bool isIndexedStoreLegal (TTI::MemIndexedMode M, Type *Ty, const DataLayout &DL) const
 
bool isLSRCostLess (TTI::LSRCost C1, TTI::LSRCost C2)
 
bool isNumRegsMajorCostOfLSR ()
 
bool shouldDropLSRSolutionIfLessProfitable () const
 
bool isProfitableLSRChainElement (Instruction *I)
 
InstructionCost getScalingFactorCost (Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace)
 
bool isTruncateFree (Type *Ty1, Type *Ty2)
 
bool isProfitableToHoist (Instruction *I)
 
bool useAA () const
 
bool isTypeLegal (Type *Ty)
 
unsigned getRegUsageForType (Type *Ty)
 
InstructionCost getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType, TTI::TargetCostKind CostKind)
 
unsigned getEstimatedNumberOfCaseClusters (const SwitchInst &SI, unsigned &JumpTableSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
 
bool shouldBuildLookupTables ()
 
bool shouldBuildRelLookupTables () const
 
bool haveFastSqrt (Type *Ty)
 
bool isFCmpOrdCheaperThanFCmpZero (Type *Ty)
 
InstructionCost getFPOpCost (Type *Ty)
 
bool preferToKeepConstantsAttached (const Instruction &Inst, const Function &Fn) const
 
unsigned getInliningThresholdMultiplier () const
 
unsigned adjustInliningThreshold (const CallBase *CB)
 
unsigned getCallerAllocaCost (const CallBase *CB, const AllocaInst *AI) const
 
int getInlinerVectorBonusPercent () const
 
void getUnrollingPreferences (Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
 
void getPeelingPreferences (Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
 
bool isHardwareLoopProfitable (Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo)
 
unsigned getEpilogueVectorizationMinVF ()
 
bool preferPredicateOverEpilogue (TailFoldingInfo *TFI)
 
TailFoldingStyle getPreferredTailFoldingStyle (bool IVUpdateMayOverflow=true)
 
std::optional< Instruction * > instCombineIntrinsic (InstCombiner &IC, IntrinsicInst &II)
 
std::optional< Value * > simplifyDemandedUseBitsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed)
 
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp)
 
virtual std::optional< unsigned > getCacheSize (TargetTransformInfo::CacheLevel Level) const
 
virtual std::optional< unsigned > getCacheAssociativity (TargetTransformInfo::CacheLevel Level) const
 
virtual unsigned getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
 
virtual unsigned getMaxPrefetchIterationsAhead () const
 
virtual bool enableWritePrefetching () const
 
TypeSize getRegisterBitWidth (TargetTransformInfo::RegisterKind K) const
 
std::optional< unsigned > getMaxVScale () const
 
std::optional< unsigned > getVScaleForTuning () const
 
bool isVScaleKnownToBeAPowerOfTwo () const
 
InstructionCost getScalarizationOverhead (VectorType *InTy, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind, ArrayRef< Value * > VL={})
 Estimate the overhead of scalarizing an instruction.
 
InstructionCost getScalarizationOverhead (VectorType *InTy, bool Insert, bool Extract, TTI::TargetCostKind CostKind)
 Helper wrapper for the DemandedElts variant of getScalarizationOverhead.
 
InstructionCost getScalarizationOverhead (VectorType *RetTy, ArrayRef< const Value * > Args, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind)
 Estimate the overhead of scalarizing the inputs and outputs of an instruction, with return type RetTy and arguments Args of type Tys.
 
bool isTargetIntrinsicTriviallyScalarizable (Intrinsic::ID ID) const
 
bool isTargetIntrinsicWithScalarOpAtArg (Intrinsic::ID ID, unsigned ScalarOpdIdx) const
 
bool isTargetIntrinsicWithOverloadTypeAtArg (Intrinsic::ID ID, int OpdIdx) const
 
bool isTargetIntrinsicWithStructReturnOverloadAtField (Intrinsic::ID ID, int RetIdx) const
 
InstructionCost getOperandsScalarizationOverhead (ArrayRef< const Value * > Args, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind)
 Estimate the overhead of scalarizing an instructions unique non-constant operands.
 
std::pair< InstructionCost, MVT > getTypeLegalizationCost (Type *Ty) const
 Estimate the cost of type-legalization and the legalized type.
 
unsigned getMaxInterleaveFactor (ElementCount VF)
 
InstructionCost getArithmeticInstrCost (unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr)
 
TTI::ShuffleKind improveShuffleKindFromMask (TTI::ShuffleKind Kind, ArrayRef< int > Mask, VectorType *Ty, int &Index, VectorType *&SubTy) const
 
InstructionCost getShuffleCost (TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr)
 
InstructionCost getCastInstrCost (unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getExtractWithExtendCost (unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index)
 
InstructionCost getCFInstrCost (unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getCmpSelInstrCost (unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
 
InstructionCost getVectorInstrCost (unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
 
InstructionCost getVectorInstrCost (unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Scalar, ArrayRef< std::tuple< Value *, User *, int > > ScalarUserAndIdx)
 
InstructionCost getVectorInstrCost (const Instruction &I, Type *Val, TTI::TargetCostKind CostKind, unsigned Index)
 
InstructionCost getReplicationShuffleCost (Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
 
InstructionCost getMemoryOpCost (unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
 
InstructionCost getMaskedMemoryOpCost (unsigned Opcode, Type *DataTy, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
 
InstructionCost getGatherScatterOpCost (unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getStridedMemoryOpCost (unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
 
InstructionCost getInterleavedMemoryOpCost (unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
 
InstructionCost getIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
 Get intrinsic cost based on arguments.
 
InstructionCost getTypeBasedIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
 Get intrinsic cost based on argument types.
 
InstructionCost getCallInstrCost (Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind)
 Compute a cost of the given call instruction.
 
unsigned getNumberOfParts (Type *Tp)
 
InstructionCost getAddressComputationCost (Type *Ty, ScalarEvolution *, const SCEV *)
 
InstructionCost getTreeReductionCost (unsigned Opcode, VectorType *Ty, TTI::TargetCostKind CostKind)
 Try to calculate arithmetic and shuffle op costs for reduction intrinsics.
 
InstructionCost getOrderedReductionCost (unsigned Opcode, VectorType *Ty, TTI::TargetCostKind CostKind)
 Try to calculate the cost of performing strict (in-order) reductions, which involves doing a sequence of floating point additions in lane order, starting with an initial value.
 
InstructionCost getArithmeticReductionCost (unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
 
InstructionCost getMinMaxReductionCost (Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind)
 Try to calculate op costs for min/max reduction operations.
 
InstructionCost getExtendedReductionCost (unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind)
 
InstructionCost getMulAccReductionCost (bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind)
 
InstructionCost getVectorSplitCost ()
 
- Public Member Functions inherited from llvm::TargetTransformInfoImplCRTPBase< T >
InstructionCost getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType, TTI::TargetCostKind CostKind)
 
InstructionCost getPointersChainCost (ArrayRef< const Value * > Ptrs, const Value *Base, const TTI::PointersChainInfo &Info, Type *AccessTy, TTI::TargetCostKind CostKind)
 
InstructionCost getInstructionCost (const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
 
bool isExpensiveToSpeculativelyExecute (const Instruction *I)
 
bool supportsTailCallFor (const CallBase *CB) const
 
InstructionCost getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType, TTI::TargetCostKind CostKind) const
 
- Public Member Functions inherited from llvm::TargetTransformInfoImplBase
 TargetTransformInfoImplBase (const TargetTransformInfoImplBase &Arg)=default
 
 TargetTransformInfoImplBase (TargetTransformInfoImplBase &&Arg)
 
const DataLayout & getDataLayout () const
 
InstructionCost getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType, TTI::TargetCostKind CostKind) const
 
unsigned getEstimatedNumberOfCaseClusters (const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
 
unsigned getInliningThresholdMultiplier () const
 
unsigned getInliningCostBenefitAnalysisSavingsMultiplier () const
 
unsigned getInliningCostBenefitAnalysisProfitableMultiplier () const
 
int getInliningLastCallToStaticBonus () const
 
unsigned adjustInliningThreshold (const CallBase *CB) const
 
unsigned getCallerAllocaCost (const CallBase *CB, const AllocaInst *AI) const
 
int getInlinerVectorBonusPercent () const
 
InstructionCost getMemcpyCost (const Instruction *I) const
 
uint64_t getMaxMemIntrinsicInlineSizeThreshold () const
 
BranchProbability getPredictableBranchThreshold () const
 
InstructionCost getBranchMispredictPenalty () const
 
bool hasBranchDivergence (const Function *F=nullptr) const
 
bool isSourceOfDivergence (const Value *V) const
 
bool isAlwaysUniform (const Value *V) const
 
bool isValidAddrSpaceCast (unsigned FromAS, unsigned ToAS) const
 
bool addrspacesMayAlias (unsigned AS0, unsigned AS1) const
 
unsigned getFlatAddressSpace () const
 
bool collectFlatAddressOperands (SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
 
bool isNoopAddrSpaceCast (unsigned, unsigned) const
 
bool canHaveNonUndefGlobalInitializerInAddressSpace (unsigned AS) const
 
unsigned getAssumedAddrSpace (const Value *V) const
 
bool isSingleThreaded () const
 
std::pair< const Value *, unsigned > getPredicatedAddrSpace (const Value *V) const
 
Value * rewriteIntrinsicWithAddressSpace (IntrinsicInst *II, Value *OldV, Value *NewV) const
 
bool isLoweredToCall (const Function *F) const
 
bool isHardwareLoopProfitable (Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
 
unsigned getEpilogueVectorizationMinVF () const
 
bool preferPredicateOverEpilogue (TailFoldingInfo *TFI) const
 
TailFoldingStyle getPreferredTailFoldingStyle (bool IVUpdateMayOverflow=true) const
 
std::optional< Instruction * > instCombineIntrinsic (InstCombiner &IC, IntrinsicInst &II) const
 
std::optional< Value * > simplifyDemandedUseBitsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
 
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
 
void getUnrollingPreferences (Loop *, ScalarEvolution &, TTI::UnrollingPreferences &, OptimizationRemarkEmitter *) const
 
void getPeelingPreferences (Loop *, ScalarEvolution &, TTI::PeelingPreferences &) const
 
bool isLegalAddImmediate (int64_t Imm) const
 
bool isLegalAddScalableImmediate (int64_t Imm) const
 
bool isLegalICmpImmediate (int64_t Imm) const
 
bool isLegalAddressingMode (Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr, int64_t ScalableOffset=0) const
 
bool isLSRCostLess (const TTI::LSRCost &C1, const TTI::LSRCost &C2) const
 
bool isNumRegsMajorCostOfLSR () const
 
bool shouldDropLSRSolutionIfLessProfitable () const
 
bool isProfitableLSRChainElement (Instruction *I) const
 
bool canMacroFuseCmp () const
 
bool canSaveCmp (Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
 
TTI::AddressingModeKind getPreferredAddressingMode (const Loop *L, ScalarEvolution *SE) const
 
bool isLegalMaskedStore (Type *DataType, Align Alignment) const
 
bool isLegalMaskedLoad (Type *DataType, Align Alignment) const
 
bool isLegalNTStore (Type *DataType, Align Alignment) const
 
bool isLegalNTLoad (Type *DataType, Align Alignment) const
 
bool isLegalBroadcastLoad (Type *ElementTy, ElementCount NumElements) const
 
bool isLegalMaskedScatter (Type *DataType, Align Alignment) const
 
bool isLegalMaskedGather (Type *DataType, Align Alignment) const
 
bool forceScalarizeMaskedGather (VectorType *DataType, Align Alignment) const
 
bool forceScalarizeMaskedScatter (VectorType *DataType, Align Alignment) const
 
bool isLegalMaskedCompressStore (Type *DataType, Align Alignment) const
 
bool isLegalAltInstr (VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
 
bool isLegalMaskedExpandLoad (Type *DataType, Align Alignment) const
 
bool isLegalStridedLoadStore (Type *DataType, Align Alignment) const
 
bool isLegalInterleavedAccessType (VectorType *VTy, unsigned Factor, Align Alignment, unsigned AddrSpace)
 
bool isLegalMaskedVectorHistogram (Type *AddrType, Type *DataType) const
 
bool enableOrderedReductions () const
 
bool hasDivRemOp (Type *DataType, bool IsSigned) const
 
bool hasVolatileVariant (Instruction *I, unsigned AddrSpace) const
 
bool prefersVectorizedAddressing () const
 
InstructionCost getScalingFactorCost (Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
 
bool LSRWithInstrQueries () const
 
bool isTruncateFree (Type *Ty1, Type *Ty2) const
 
bool isProfitableToHoist (Instruction *I) const
 
bool useAA () const
 
bool isTypeLegal (Type *Ty) const
 
unsigned getRegUsageForType (Type *Ty) const
 
bool shouldBuildLookupTables () const
 
bool shouldBuildLookupTablesForConstant (Constant *C) const
 
bool shouldBuildRelLookupTables () const
 
bool useColdCCForColdCall (Function &F) const
 
bool isTargetIntrinsicTriviallyScalarizable (Intrinsic::ID ID) const
 
bool isTargetIntrinsicWithScalarOpAtArg (Intrinsic::ID ID, unsigned ScalarOpdIdx) const
 
bool isTargetIntrinsicWithOverloadTypeAtArg (Intrinsic::ID ID, int OpdIdx) const
 
bool isTargetIntrinsicWithStructReturnOverloadAtField (Intrinsic::ID ID, int RetIdx) const
 
InstructionCost getScalarizationOverhead (VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind, ArrayRef< Value * > VL={}) const
 
InstructionCost getOperandsScalarizationOverhead (ArrayRef< const Value * > Args, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
 
bool supportsEfficientVectorElementLoadStore () const
 
bool supportsTailCalls () const
 
bool enableAggressiveInterleaving (bool LoopHasReductions) const
 
TTI::MemCmpExpansionOptions enableMemCmpExpansion (bool OptSize, bool IsZeroCmp) const
 
bool enableSelectOptimize () const
 
bool shouldTreatInstructionLikeSelect (const Instruction *I)
 
bool enableInterleavedAccessVectorization () const
 
bool enableMaskedInterleavedAccessVectorization () const
 
bool isFPVectorizationPotentiallyUnsafe () const
 
bool allowsMisalignedMemoryAccesses (LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, unsigned *Fast) const
 
TTI::PopcntSupportKind getPopcntSupport (unsigned IntTyWidthInBit) const
 
bool haveFastSqrt (Type *Ty) const
 
bool isExpensiveToSpeculativelyExecute (const Instruction *I)
 
bool isFCmpOrdCheaperThanFCmpZero (Type *Ty) const
 
InstructionCost getFPOpCost (Type *Ty) const
 
InstructionCost getIntImmCodeSizeCost (unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const
 
InstructionCost getIntImmCost (const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
 
InstructionCost getIntImmCostInst (unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const
 
InstructionCost getIntImmCostIntrin (Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
 
bool preferToKeepConstantsAttached (const Instruction &Inst, const Function &Fn) const
 
unsigned getNumberOfRegisters (unsigned ClassID) const
 
bool hasConditionalLoadStoreForType (Type *Ty) const
 
unsigned getRegisterClassForType (bool Vector, Type *Ty=nullptr) const
 
const char * getRegisterClassName (unsigned ClassID) const
 
TypeSize getRegisterBitWidth (TargetTransformInfo::RegisterKind K) const
 
unsigned getMinVectorRegisterBitWidth () const
 
std::optional< unsigned > getMaxVScale () const
 
std::optional< unsigned > getVScaleForTuning () const
 
bool isVScaleKnownToBeAPowerOfTwo () const
 
bool shouldMaximizeVectorBandwidth (TargetTransformInfo::RegisterKind K) const
 
ElementCount getMinimumVF (unsigned ElemWidth, bool IsScalable) const
 
unsigned getMaximumVF (unsigned ElemWidth, unsigned Opcode) const
 
unsigned getStoreMinimumVF (unsigned VF, Type *, Type *) const
 
bool shouldConsiderAddressTypePromotion (const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
 
unsigned getCacheLineSize () const
 
std::optional< unsigned > getCacheSize (TargetTransformInfo::CacheLevel Level) const
 
std::optional< unsigned > getCacheAssociativity (TargetTransformInfo::CacheLevel Level) const
 
std::optional< unsigned > getMinPageSize () const
 
unsigned getPrefetchDistance () const
 
unsigned getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
 
unsigned getMaxPrefetchIterationsAhead () const
 
bool enableWritePrefetching () const
 
bool shouldPrefetchAddressSpace (unsigned AS) const
 
unsigned getMaxInterleaveFactor (ElementCount VF) const
 
InstructionCost getArithmeticInstrCost (unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info, TTI::OperandValueInfo Opd2Info, ArrayRef< const Value * > Args, const Instruction *CxtI=nullptr) const
 
InstructionCost getAltInstrCost (VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind) const
 
InstructionCost getShuffleCost (TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr) const
 
InstructionCost getCastInstrCost (unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I) const
 
InstructionCost getExtractWithExtendCost (unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
 
InstructionCost getCFInstrCost (unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
 
InstructionCost getCmpSelInstrCost (unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info, TTI::OperandValueInfo Op2Info, const Instruction *I) const
 
InstructionCost getVectorInstrCost (unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1) const
 
InstructionCost getVectorInstrCost (unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Scalar, ArrayRef< std::tuple< Value *, User *, int > > ScalarUserAndIdx) const
 
InstructionCost getVectorInstrCost (const Instruction &I, Type *Val, TTI::TargetCostKind CostKind, unsigned Index) const
 
unsigned getReplicationShuffleCost (Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
 
InstructionCost getMemoryOpCost (unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo, const Instruction *I) const
 
InstructionCost getVPMemoryOpCost (unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
 
InstructionCost getMaskedMemoryOpCost (unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind) const
 
InstructionCost getGatherScatterOpCost (unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
 
InstructionCost getStridedMemoryOpCost (unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
 
unsigned getInterleavedMemoryOpCost (unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) const
 
InstructionCost getIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
 
InstructionCost getCallInstrCost (Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
 
unsigned getNumberOfParts (Type *Tp) const
 
InstructionCost getAddressComputationCost (Type *Tp, ScalarEvolution *, const SCEV *) const
 
InstructionCost getArithmeticReductionCost (unsigned, VectorType *, std::optional< FastMathFlags > FMF, TTI::TargetCostKind) const
 
InstructionCost getMinMaxReductionCost (Intrinsic::ID IID, VectorType *, FastMathFlags, TTI::TargetCostKind) const
 
InstructionCost getExtendedReductionCost (unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind) const
 
InstructionCost getMulAccReductionCost (bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind) const
 
InstructionCost getCostOfKeepingLiveOverCall (ArrayRef< Type * > Tys) const
 
bool getTgtMemIntrinsic (IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
 
unsigned getAtomicMemIntrinsicMaxElementSize () const
 
Value * getOrCreateResultFromMemIntrinsic (IntrinsicInst *Inst, Type *ExpectedType) const
 
Type * getMemcpyLoopLoweringType (LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicElementSize) const
 
void getMemcpyLoopResidualLoweringType (SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicCpySize) const
 
bool areInlineCompatible (const Function *Caller, const Function *Callee) const
 
unsigned getInlineCallPenalty (const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const
 
bool areTypesABICompatible (const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
 
bool isIndexedLoadLegal (TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
 
bool isIndexedStoreLegal (TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
 
unsigned getLoadStoreVecRegBitWidth (unsigned AddrSpace) const
 
bool isLegalToVectorizeLoad (LoadInst *LI) const
 
bool isLegalToVectorizeStore (StoreInst *SI) const
 
bool isLegalToVectorizeLoadChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
 
bool isLegalToVectorizeStoreChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
 
bool isLegalToVectorizeReduction (const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
 
bool isElementTypeLegalForScalableVector (Type *Ty) const
 
unsigned getLoadVectorFactor (unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
 
unsigned getStoreVectorFactor (unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
 
bool preferFixedOverScalableIfEqualCost () const
 
bool preferInLoopReduction (unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
 
bool preferPredicatedReductionSelect (unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
 
bool preferEpilogueVectorization () const
 
bool shouldExpandReduction (const IntrinsicInst *II) const
 
TTI::ReductionShuffle getPreferredExpandedReductionShuffle (const IntrinsicInst *II) const
 
unsigned getGISelRematGlobalCost () const
 
unsigned getMinTripCountTailFoldingThreshold () const
 
bool supportsScalableVectors () const
 
bool enableScalableVectorization () const
 
bool hasActiveVectorLength (unsigned Opcode, Type *DataType, Align Alignment) const
 
bool isProfitableToSinkOperands (Instruction *I, SmallVectorImpl< Use * > &Ops) const
 
bool isVectorShiftByScalarCheap (Type *Ty) const
 
TargetTransformInfo::VPLegalization getVPLegalizationStrategy (const VPIntrinsic &PI) const
 
bool hasArmWideBranch (bool) const
 
unsigned getMaxNumArgs () const
 
unsigned getNumBytesToPadGlobalArray (unsigned Size, Type *ArrayType) const
 

Additional Inherited Members

- Protected Types inherited from llvm::TargetTransformInfoImplBase
typedef TargetTransformInfo TTI
 
- Protected Member Functions inherited from llvm::BasicTTIImplBase< GCNTTIImpl >
 BasicTTIImplBase (const TargetMachine *TM, const DataLayout &DL)
 
virtual ~BasicTTIImplBase ()=default
 
- Protected Member Functions inherited from llvm::TargetTransformInfoImplCRTPBase< T >
 TargetTransformInfoImplCRTPBase (const DataLayout &DL)
 
- Protected Member Functions inherited from llvm::TargetTransformInfoImplBase
 TargetTransformInfoImplBase (const DataLayout &DL)
 
unsigned minRequiredElementSize (const Value *Val, bool &isSigned) const
 
bool isStridedAccess (const SCEV *Ptr) const
 
const SCEVConstant * getConstantStrideStep (ScalarEvolution *SE, const SCEV *Ptr) const
 
bool isConstantStridedAccessLessThan (ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance) const
 
- Protected Attributes inherited from llvm::BasicTTIImplBase< GCNTTIImpl >
const DataLayout & DL
 
- Protected Attributes inherited from llvm::TargetTransformInfoImplBase
const DataLayout & DL
 

Detailed Description

Definition at line 63 of file AMDGPUTargetTransformInfo.h.

Constructor & Destructor Documentation

◆ GCNTTIImpl()

GCNTTIImpl::GCNTTIImpl ( const AMDGPUTargetMachine *  TM,
const Function &  F 
)
explicit

Definition at line 301 of file AMDGPUTargetTransformInfo.cpp.

References F, and llvm::DenormalMode::getPreserveSign().

Member Function Documentation

◆ addrspacesMayAlias()

bool llvm::GCNTTIImpl::addrspacesMayAlias ( unsigned  AS0,
unsigned  AS1 
) const
inline

Definition at line 198 of file AMDGPUTargetTransformInfo.h.

References llvm::AMDGPU::addrspacesMayAlias().

◆ adjustInliningThreshold()

unsigned GCNTTIImpl::adjustInliningThreshold ( const CallBase *  CB) const

Definition at line 1342 of file AMDGPUTargetTransformInfo.cpp.

References adjustInliningThresholdUsingCallee(), ArgAllocaCost, llvm::BasicTTIImplBase< GCNTTIImpl >::DL, and getCallArgsTotalAllocaSize().

◆ areInlineCompatible()

bool GCNTTIImpl::areInlineCompatible ( const Function *  Caller,
const Function *  Callee 
) const

Definition at line 1225 of file AMDGPUTargetTransformInfo.cpp.

References llvm::TargetLoweringBase::getTargetMachine(), InlineMaxBB, and llvm::SIModeRegisterDefaults::isInlineCompatible().

◆ canHaveNonUndefGlobalInitializerInAddressSpace()

bool llvm::GCNTTIImpl::canHaveNonUndefGlobalInitializerInAddressSpace ( unsigned  AS) const
inline

Definition at line 213 of file AMDGPUTargetTransformInfo.h.

References llvm::AMDGPUAS::LOCAL_ADDRESS, llvm::AMDGPUAS::PRIVATE_ADDRESS, and llvm::AMDGPUAS::REGION_ADDRESS.

◆ canSimplifyLegacyMulToMul()

bool GCNTTIImpl::canSimplifyLegacyMulToMul ( const Instruction &  I,
const Value *  Op0,
const Value *  Op1,
InstCombiner &  IC 
) const

Definition at line 330 of file AMDGPUInstCombineIntrinsic.cpp.

References llvm::InstCombiner::getSimplifyQuery(), llvm::SimplifyQuery::getWithInstruction(), I, llvm::isKnownNeverInfOrNaN(), llvm::PatternMatch::m_FiniteNonZero(), and llvm::PatternMatch::match().

Referenced by instCombineIntrinsic().

◆ collectFlatAddressOperands()

bool GCNTTIImpl::collectFlatAddressOperands ( SmallVectorImpl< int > &  OpIndexes,
Intrinsic::ID  IID 
) const

Definition at line 1063 of file AMDGPUTargetTransformInfo.cpp.

References llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getArithmeticInstrCost()

InstructionCost GCNTTIImpl::getArithmeticInstrCost ( unsigned  Opcode,
Type *  Ty,
TTI::TargetCostKind  CostKind,
TTI::OperandValueInfo  Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
TTI::OperandValueInfo  Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
ArrayRef< const Value * >  Args = {},
const Instruction *  CxtI = nullptr 
)

Definition at line 546 of file AMDGPUTargetTransformInfo.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, CostKind, llvm::FAdd, llvm::ISD::FADD, llvm::FPOpFusion::Fast, llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FREM, llvm::ISD::FSUB, llvm::BasicTTIImplBase< GCNTTIImpl >::getArithmeticInstrCost(), llvm::TargetLoweringBase::getTargetMachine(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::Instruction::hasAllowContract(), llvm::Instruction::hasApproxFunc(), llvm::AMDGPUSubtarget::hasMadMacF32Insts(), llvm::Value::hasOneUse(), llvm::GCNSubtarget::hasPackedFP32Ops(), llvm::GCNSubtarget::hasUsableDivScaleConditionOutput(), llvm::TargetLoweringBase::InstructionOpcodeToISD(), llvm::AMDGPUTargetLowering::isFNegFree(), llvm::PatternMatch::m_FPOne(), llvm::PatternMatch::match(), llvm::ISD::MUL, llvm::TargetMachine::Options, Options, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::TargetTransformInfo::TCC_Free, llvm::TargetOptions::UnsafeFPMath, llvm::Value::user_begin(), and llvm::ISD::XOR.

◆ getArithmeticReductionCost()

InstructionCost GCNTTIImpl::getArithmeticReductionCost ( unsigned  Opcode,
VectorType *  Ty,
std::optional< FastMathFlags >  FMF,
TTI::TargetCostKind  CostKind 
)

Definition at line 827 of file AMDGPUTargetTransformInfo.cpp.

References CostKind, llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::BasicTTIImplBase< GCNTTIImpl >::getArithmeticReductionCost(), llvm::EVT::getScalarSizeInBits(), llvm::TargetLoweringBase::getValueType(), llvm::AMDGPUSubtarget::hasVOP3PInsts(), and llvm::TargetTransformInfo::requiresOrderedReduction().

◆ getCacheLineSize()

unsigned llvm::GCNTTIImpl::getCacheLineSize ( ) const
inlineoverridevirtual

Data cache line size for LoopDataPrefetch pass. Has no use before GFX12.

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 268 of file AMDGPUTargetTransformInfo.h.

◆ getCallerAllocaCost()

unsigned GCNTTIImpl::getCallerAllocaCost ( const CallBase *  CB,
const AllocaInst *  AI 
) const

Definition at line 1353 of file AMDGPUTargetTransformInfo.cpp.

References ArgAllocaCost, ArgAllocaCutoff, llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::AllocaInst::getAllocatedType(), getCallArgsTotalAllocaSize(), llvm::CallBase::getCalledFunction(), getInliningThresholdMultiplier(), llvm::DataLayout::getTypeAllocSize(), and llvm::none_of().

◆ getCFInstrCost()

InstructionCost GCNTTIImpl::getCFInstrCost ( unsigned  Opcode,
TTI::TargetCostKind  CostKind,
const Instruction *  I = nullptr 
)

Definition at line 796 of file AMDGPUTargetTransformInfo.cpp.

References assert(), CostKind, llvm::BasicTTIImplBase< GCNTTIImpl >::getCFInstrCost(), I, llvm::TargetTransformInfo::TCK_CodeSize, and llvm::TargetTransformInfo::TCK_SizeAndLatency.

◆ getFlatAddressSpace()

unsigned llvm::GCNTTIImpl::getFlatAddressSpace ( ) const
inline

Definition at line 202 of file AMDGPUTargetTransformInfo.h.

References llvm::AMDGPUAS::FLAT_ADDRESS.

◆ getInlinerVectorBonusPercent()

int llvm::GCNTTIImpl::getInlinerVectorBonusPercent ( ) const
inline

Definition at line 255 of file AMDGPUTargetTransformInfo.h.

◆ getInliningLastCallToStaticBonus()

int GCNTTIImpl::getInliningLastCallToStaticBonus ( ) const

Definition at line 1337 of file AMDGPUTargetTransformInfo.cpp.

References llvm::TargetTransformInfoImplBase::getInliningLastCallToStaticBonus(), and getInliningThresholdMultiplier().

◆ getInliningThresholdMultiplier()

unsigned llvm::GCNTTIImpl::getInliningThresholdMultiplier ( ) const
inline

Definition at line 251 of file AMDGPUTargetTransformInfo.h.

Referenced by getCallerAllocaCost(), and getInliningLastCallToStaticBonus().

◆ getIntrinsicInstrCost()

InstructionCost GCNTTIImpl::getIntrinsicInstrCost ( const IntrinsicCostAttributes &  ICA,
TTI::TargetCostKind  CostKind 
)

Definition at line 727 of file AMDGPUTargetTransformInfo.cpp.

References llvm::any_of(), assert(), CostKind, llvm::IntrinsicCostAttributes::getID(), llvm::BasicTTIImplBase< GCNTTIImpl >::getIntrinsicInstrCost(), llvm::IntrinsicCostAttributes::getReturnType(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::AMDGPUSubtarget::hasFastFMAF32(), llvm::GCNSubtarget::hasPackedFP32Ops(), intrinsicHasPackedVectorBenefit(), and RetTy.

◆ getLoadStoreVecRegBitWidth()

unsigned GCNTTIImpl::getLoadStoreVecRegBitWidth ( unsigned  AddrSpace) const

Definition at line 373 of file AMDGPUTargetTransformInfo.cpp.

References llvm::AMDGPUAS::BUFFER_FAT_POINTER, llvm::AMDGPUAS::BUFFER_RESOURCE, llvm::AMDGPUAS::BUFFER_STRIDED_POINTER, llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::GCNSubtarget::getMaxPrivateElementSize(), llvm::AMDGPUAS::GLOBAL_ADDRESS, and llvm::AMDGPUAS::PRIVATE_ADDRESS.

◆ getLoadVectorFactor()

unsigned GCNTTIImpl::getLoadVectorFactor ( unsigned  VF,
unsigned  LoadSize,
unsigned  ChainSizeInBytes,
VectorType *  VecTy 
) const

Definition at line 352 of file AMDGPUTargetTransformInfo.cpp.

References llvm::Type::getScalarSizeInBits().

◆ getMaximumVF()

unsigned GCNTTIImpl::getMaximumVF ( unsigned  ElemWidth,
unsigned  Opcode 
) const

Definition at line 344 of file AMDGPUTargetTransformInfo.cpp.

References llvm::AMDGPUSubtarget::has16BitInsts(), and llvm::GCNSubtarget::hasPackedFP32Ops().

◆ getMaxInterleaveFactor()

unsigned GCNTTIImpl::getMaxInterleaveFactor ( ElementCount  VF)

Definition at line 511 of file AMDGPUTargetTransformInfo.cpp.

References llvm::ElementCount::isScalar().

◆ getMaxMemIntrinsicInlineSizeThreshold()

int64_t GCNTTIImpl::getMaxMemIntrinsicInlineSizeThreshold ( ) const

Definition at line 415 of file AMDGPUTargetTransformInfo.cpp.

◆ getMemcpyLoopLoweringType()

Type * GCNTTIImpl::getMemcpyLoopLoweringType ( LLVMContext &  Context,
Value *  Length,
unsigned  SrcAddrSpace,
unsigned  DestAddrSpace,
Align  SrcAlign,
Align  DestAlign,
std::optional< uint32_t >  AtomicElementSize 
) const

Definition at line 421 of file AMDGPUTargetTransformInfo.cpp.

References llvm::FixedVectorType::get(), llvm::Type::getInt16Ty(), llvm::Type::getInt32Ty(), llvm::Type::getIntNTy(), llvm::Length, llvm::AMDGPUAS::LOCAL_ADDRESS, MemcpyLoopUnroll, llvm::MinAlign(), and llvm::AMDGPUAS::REGION_ADDRESS.

◆ getMemcpyLoopResidualLoweringType()

void GCNTTIImpl::getMemcpyLoopResidualLoweringType ( SmallVectorImpl< Type * > &  OpsOut,
LLVMContext &  Context,
unsigned  RemainingBytes,
unsigned  SrcAddrSpace,
unsigned  DestAddrSpace,
Align  SrcAlign,
Align  DestAlign,
std::optional< uint32_t >  AtomicCpySize 
) const

Definition at line 465 of file AMDGPUTargetTransformInfo.cpp.

References llvm::FixedVectorType::get(), llvm::Type::getInt16Ty(), llvm::Type::getInt32Ty(), llvm::Type::getInt64Ty(), llvm::Type::getInt8Ty(), llvm::TargetTransformInfoImplBase::getMemcpyLoopResidualLoweringType(), llvm::MinAlign(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getMinMaxReductionCost()

InstructionCost GCNTTIImpl::getMinMaxReductionCost ( Intrinsic::ID  IID,
VectorType *  Ty,
FastMathFlags  FMF,
TTI::TargetCostKind  CostKind 
)

Definition at line 845 of file AMDGPUTargetTransformInfo.cpp.

References CostKind, llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::BasicTTIImplBase< GCNTTIImpl >::getMinMaxReductionCost(), llvm::EVT::getScalarSizeInBits(), llvm::TargetLoweringBase::getValueType(), and llvm::AMDGPUSubtarget::hasVOP3PInsts().

◆ getMinVectorRegisterBitWidth()

unsigned GCNTTIImpl::getMinVectorRegisterBitWidth ( ) const

Definition at line 340 of file AMDGPUTargetTransformInfo.cpp.

◆ getNumberOfRegisters()

unsigned GCNTTIImpl::getNumberOfRegisters ( unsigned  RCID) const

Definition at line 316 of file AMDGPUTargetTransformInfo.cpp.

◆ getPeelingPreferences()

void GCNTTIImpl::getPeelingPreferences ( Loop *  L,
ScalarEvolution &  SE,
TTI::PeelingPreferences &  PP 
)

Definition at line 1400 of file AMDGPUTargetTransformInfo.cpp.

References llvm::AMDGPUTTIImpl::getPeelingPreferences().

◆ getPopcntSupport()

TTI::PopcntSupportKind llvm::GCNTTIImpl::getPopcntSupport ( unsigned  TyWidth)
inline

Definition at line 116 of file AMDGPUTargetTransformInfo.h.

References assert(), llvm::isPowerOf2_32(), and llvm::TargetTransformInfo::PSK_FastHardware.

◆ getPrefetchDistance()

unsigned GCNTTIImpl::getPrefetchDistance ( ) const
overridevirtual

How much before a load we should place the prefetch instruction.

This is currently measured in number of IR instructions.

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1426 of file AMDGPUTargetTransformInfo.cpp.

References llvm::GCNSubtarget::hasPrefetch().

◆ getRegisterBitWidth()

TypeSize GCNTTIImpl::getRegisterBitWidth ( TargetTransformInfo::RegisterKind  Vector) const

Definition at line 328 of file AMDGPUTargetTransformInfo.cpp.

References llvm::TypeSize::getFixed(), llvm::TypeSize::getScalable(), llvm::GCNSubtarget::hasPackedFP32Ops(), llvm_unreachable, llvm::TargetTransformInfo::RGK_FixedWidthVector, llvm::TargetTransformInfo::RGK_ScalableVector, and llvm::TargetTransformInfo::RGK_Scalar.

◆ getShuffleCost()

InstructionCost GCNTTIImpl::getShuffleCost ( TTI::ShuffleKind  Kind,
VectorType *  Tp,
ArrayRef< int >  Mask,
TTI::TargetCostKind  CostKind,
int  Index,
VectorType *  SubTp,
ArrayRef< const Value * >  Args = {},
const Instruction *  CxtI = nullptr 
)

Definition at line 1146 of file AMDGPUTargetTransformInfo.cpp.

References llvm::alignTo(), CostKind, llvm::count_if(), llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::VectorType::getElementType(), llvm::GCNSubtarget::getGeneration(), llvm::BasicTTIImplBase< GCNTTIImpl >::getShuffleCost(), llvm::DataLayout::getTypeSizeInBits(), llvm::AMDGPUSubtarget::hasVOP3PInsts(), llvm::BasicTTIImplBase< GCNTTIImpl >::improveShuffleKindFromMask(), llvm::TargetTransformInfo::SK_Broadcast, llvm::TargetTransformInfo::SK_ExtractSubvector, llvm::TargetTransformInfo::SK_InsertSubvector, llvm::TargetTransformInfo::SK_PermuteSingleSrc, llvm::TargetTransformInfo::SK_PermuteTwoSrc, llvm::TargetTransformInfo::SK_Reverse, llvm::TargetTransformInfo::SK_Select, llvm::TargetTransformInfo::SK_Splice, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

◆ getStoreVectorFactor()

unsigned GCNTTIImpl::getStoreVectorFactor ( unsigned  VF,
unsigned  StoreSize,
unsigned  ChainSizeInBytes,
VectorType *  VecTy 
) const

Definition at line 363 of file AMDGPUTargetTransformInfo.cpp.

◆ getTgtMemIntrinsic()

bool GCNTTIImpl::getTgtMemIntrinsic ( IntrinsicInst *  Inst,
MemIntrinsicInfo &  Info 
) const

Definition at line 520 of file AMDGPUTargetTransformInfo.cpp.

References llvm::CallBase::getArgOperand(), llvm::IntrinsicInst::getIntrinsicID(), Info, and llvm::SequentiallyConsistent.

◆ getUnrollingPreferences()

void GCNTTIImpl::getUnrollingPreferences ( Loop *  L,
ScalarEvolution &  SE,
TTI::UnrollingPreferences &  UP,
OptimizationRemarkEmitter *  ORE 
)

Definition at line 1394 of file AMDGPUTargetTransformInfo.cpp.

References llvm::AMDGPUTTIImpl::getUnrollingPreferences().

◆ getVectorInstrCost()

InstructionCost GCNTTIImpl::getVectorInstrCost ( unsigned  Opcode,
Type *  ValTy,
TTI::TargetCostKind  CostKind,
unsigned  Index,
Value *  Op0,
Value *  Op1 
)

Definition at line 859 of file AMDGPUTargetTransformInfo.cpp.

References CostKind, llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::DataLayout::getTypeSizeInBits(), llvm::BasicTTIImplBase< GCNTTIImpl >::getVectorInstrCost(), and llvm::AMDGPUSubtarget::has16BitInsts().

◆ getVectorSplitCost()

InstructionCost llvm::GCNTTIImpl::getVectorSplitCost ( )
inline

Definition at line 235 of file AMDGPUTargetTransformInfo.h.

◆ hasBranchDivergence()

bool GCNTTIImpl::hasBranchDivergence ( const Function *  F = nullptr) const

Definition at line 312 of file AMDGPUTargetTransformInfo.cpp.

References F, and llvm::AMDGPUSubtarget::isSingleLaneExecution().

◆ instCombineIntrinsic()

std::optional< Instruction * > GCNTTIImpl::instCombineIntrinsic ( InstCombiner &  IC,
IntrinsicInst &  II 
) const

Definition at line 485 of file AMDGPUInstCombineIntrinsic.cpp.

References llvm::CallBase::addFnAttr(), llvm::FastMathFlags::allowContract(), assert(), llvm::APFloat::bitcastToAPInt(), llvm::InstCombiner::Builder, llvm::CallingConv::C, canContractSqrtToRsq(), canSimplifyLegacyMulToMul(), CC, llvm::ConstantFoldCompareInstOperands(), llvm::APFloat::convert(), llvm::IRBuilderBase::CreateAShr(), llvm::IRBuilderBase::CreateExtractVector(), llvm::IRBuilderBase::CreateFAddFMF(), llvm::IRBuilderBase::CreateFMulFMF(), llvm::IRBuilderBase::CreateICmpNE(), llvm::IRBuilderBase::CreateInsertElement(), llvm::IRBuilderBase::CreateIntrinsic(), llvm::IRBuilderBase::CreateLShr(), llvm::IRBuilderBase::CreateMaxNum(), llvm::IRBuilderBase::CreateMinNum(), llvm::IRBuilderBase::CreateSExt(), llvm::IRBuilderBase::CreateShl(), llvm::IRBuilderBase::CreateZExt(), defaultComponentBroadcast(), llvm::APFloat::divide(), llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::InstCombiner::eraseInstFromFunction(), llvm::Exponent, llvm::FAdd, llvm::fcAllFlags, llvm::CmpInst::FIRST_FCMP_PREDICATE, llvm::CmpInst::FIRST_ICMP_PREDICATE, fmed3AMDGCN(), llvm::FMul, llvm::AMDGPU::MFMAScaleFormats::FP4_E2M1, llvm::AMDGPU::MFMAScaleFormats::FP6_E2M3, llvm::AMDGPU::MFMAScaleFormats::FP6_E3M2, llvm::AMDGPU::MFMAScaleFormats::FP8_E4M3, llvm::AMDGPU::MFMAScaleFormats::FP8_E5M2, llvm::frexp(), llvm::MDNode::get(), llvm::MetadataAsValue::get(), llvm::MDString::get(), llvm::FixedVectorType::get(), llvm::UndefValue::get(), llvm::PoisonValue::get(), llvm::IRBuilderBase::getContext(), llvm::ConstantInt::getFalse(), llvm::FPMathOperator::getFastMathFlags(), llvm::Type::getFltSemantics(), llvm::Type::getHalfTy(), llvm::AMDGPU::getImageDimIntrinsicInfo(), llvm::ConstantFP::getInfinity(), llvm::IRBuilderBase::getInt64(), llvm::Type::getIntegerBitWidth(), llvm::IRBuilderBase::getIntNTy(), llvm::CmpInst::getInversePredicate(), llvm::ConstantFP::getNaN(), llvm::Constant::getNullValue(), llvm::Intrinsic::getOrInsertDeclaration(), llvm::APFloat::getQNaN(), llvm::APFloat::getSemantics(), llvm::InstCombiner::getSimplifyQuery(), llvm::CmpInst::getSwappedPredicate(), llvm::Value::getType(), llvm::ConstantInt::getValue(), llvm::ConstantFP::getValueAPF(), llvm::AMDGPUSubtarget::getWavefrontSize(), llvm::APFloat::getZero(), llvm::ConstantFP::getZero(), llvm::APInt::getZExtValue(), llvm::ConstantInt::getZExtValue(), llvm::GCNSubtarget::hasDefaultComponentBroadcast(), llvm::GCNSubtarget::hasDefaultComponentZero(), llvm::GCNSubtarget::hasMed3_16(), I, llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, Idx, llvm::APFloatBase::IEEEhalf(), llvm::APFloatBase::IEK_Inf, llvm::APFloatBase::IEK_NaN, II, llvm::Type::isDoubleTy(), llvm::Type::isFloatTy(), llvm::CmpInst::isFPPredicate(), llvm::Type::isHalfTy(), llvm::Type::isIntegerTy(), llvm::APFloat::isNaN(), llvm::Constant::isNullValue(), llvm::CmpInst::isSigned(), isTriviallyUniform(), llvm::SimplifyQuery::isUndefValue(), llvm::GCNSubtarget::isWave32(), llvm::GCNSubtarget::isWaveSizeKnown(), llvm::CmpInst::LAST_FCMP_PREDICATE, llvm::CmpInst::LAST_ICMP_PREDICATE, llvm_unreachable, llvm::PatternMatch::m_AllOnes(), llvm::PatternMatch::m_AnyZeroFP(), llvm::PatternMatch::m_Cmp(), llvm::PatternMatch::m_ConstantFP(), llvm::PatternMatch::m_FPExt(), llvm::PatternMatch::m_NaN(), llvm::PatternMatch::m_One(), llvm::PatternMatch::m_SExt(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Zero(), llvm::PatternMatch::m_ZExt(), llvm::PatternMatch::m_ZExtOrSExt(), llvm::Make_64(), llvm::APFloat::makeQuiet(), llvm::PatternMatch::match(), matchFPExtFromF16(), llvm::NearestTiesToEven, llvm::Offset, llvm::InstCombiner::replaceInstUsesWith(), llvm::InstCombiner::replaceOperand(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::rmTowardZero, llvm::scalbn(), Signed, simplifyAMDGCNImageIntrinsic(), simplifyAMDGCNMemoryIntrinsicDemanded(), simplifyDemandedLaneMaskArg(), std::swap(), llvm::Value::takeName(), trimTrailingZerosInVector(), llvm::APInt::trunc(), X, and Y.

◆ isAlwaysUniform()

bool GCNTTIImpl::isAlwaysUniform ( const Value *  V) const

Definition at line 992 of file AMDGPUTargetTransformInfo.cpp.

References llvm::CallingConv::C, llvm::computeKnownBits(), llvm::BasicTTIImplBase< GCNTTIImpl >::DL, F, llvm::ExtractValueInst::getIndices(), llvm::AMDGPUSubtarget::getMaxWorkitemID(), llvm::User::getOperand(), llvm::AMDGPUSubtarget::getWavefrontSizeLog2(), llvm::CallBase::isInlineAsm(), isInlineAsmSourceOfDivergence(), llvm::AMDGPU::isIntrinsicAlwaysUniform(), llvm::PatternMatch::m_AShr(), llvm::PatternMatch::m_c_And(), llvm::PatternMatch::m_ConstantInt(), llvm::PatternMatch::m_LShr(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::match(), and llvm::ArrayRef< T >::size().

◆ isInlineAsmSourceOfDivergence()

bool GCNTTIImpl::isInlineAsmSourceOfDivergence ( const CallInst *  CI,
ArrayRef< unsigned >  Indices = {} 
) const

Analyze if the results of inline asm are divergent.

If Indices is empty, this is analyzing the collective result of all output registers. Otherwise, this is only querying a specific result index if this returns multiple registers in a struct.

Definition at line 891 of file AMDGPUTargetTransformInfo.cpp.

References llvm::TargetLowering::ComputeConstraintToUse(), llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::ArrayRef< T >::empty(), llvm::Instruction::getDataLayout(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::GCNSubtarget::getRegisterInfo(), llvm::InlineAsm::isOutput, llvm::TargetLowering::ParseConstraints(), llvm::ArrayRef< T >::size(), and TRI.

Referenced by isAlwaysUniform(), and isSourceOfDivergence().

◆ isLegalToVectorizeLoadChain()

bool GCNTTIImpl::isLegalToVectorizeLoadChain ( unsigned  ChainSizeInBytes,
Align  Alignment,
unsigned  AddrSpace 
) const

Definition at line 403 of file AMDGPUTargetTransformInfo.cpp.

References isLegalToVectorizeMemChain().

◆ isLegalToVectorizeMemChain()

bool GCNTTIImpl::isLegalToVectorizeMemChain ( unsigned  ChainSizeInBytes,
Align  Alignment,
unsigned  AddrSpace 
) const

Definition at line 390 of file AMDGPUTargetTransformInfo.cpp.

References llvm::GCNSubtarget::getMaxPrivateElementSize(), llvm::GCNSubtarget::hasUnalignedScratchAccessEnabled(), and llvm::AMDGPUAS::PRIVATE_ADDRESS.

Referenced by isLegalToVectorizeLoadChain(), and isLegalToVectorizeStoreChain().

◆ isLegalToVectorizeStoreChain()

bool GCNTTIImpl::isLegalToVectorizeStoreChain ( unsigned  ChainSizeInBytes,
Align  Alignment,
unsigned  AddrSpace 
) const

Definition at line 409 of file AMDGPUTargetTransformInfo.cpp.

References isLegalToVectorizeMemChain().

◆ isProfitableToSinkOperands()

bool GCNTTIImpl::isProfitableToSinkOperands ( Instruction *  I,
SmallVectorImpl< Use * > &  Ops 
) const

Whether it is profitable to sink the operands of an Instruction I to the basic block of I.

This helps using several modifiers (like abs and neg) more often.

Definition at line 1209 of file AMDGPUTargetTransformInfo.cpp.

References llvm::any_of(), llvm::SmallVectorBase< Size_T >::empty(), I, llvm::PatternMatch::m_FAbs(), llvm::PatternMatch::m_FNeg(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::match(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ isReadRegisterSourceOfDivergence()

bool GCNTTIImpl::isReadRegisterSourceOfDivergence ( const IntrinsicInst *  ReadReg) const

Definition at line 927 of file AMDGPUTargetTransformInfo.cpp.

References llvm::CallBase::getArgOperand(), llvm::Value::getType(), llvm::MVT::getVT(), and RegName.

Referenced by isSourceOfDivergence().

◆ isSourceOfDivergence()

bool GCNTTIImpl::isSourceOfDivergence ( const Value *  V) const
Returns
true if the result of the value could potentially be different across workitems in a wavefront.

Definition at line 950 of file AMDGPUTargetTransformInfo.cpp.

References A, llvm::AMDGPUAS::FLAT_ADDRESS, llvm::AMDGPU::isArgPassedInSGPR(), isInlineAsmSourceOfDivergence(), llvm::AMDGPU::isIntrinsicSourceOfDivergence(), isReadRegisterSourceOfDivergence(), and llvm::AMDGPUAS::PRIVATE_ADDRESS.

◆ isValidAddrSpaceCast()

bool llvm::GCNTTIImpl::isValidAddrSpaceCast ( unsigned  FromAS,
unsigned  ToAS 
) const
inline

Definition at line 177 of file AMDGPUTargetTransformInfo.h.

References llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::AMDGPUAS::FLAT_ADDRESS, llvm::AMDGPU::isExtendedGlobalAddrSpace(), llvm::AMDGPU::isFlatGlobalAddrSpace(), llvm::AMDGPUAS::LOCAL_ADDRESS, and llvm::AMDGPUAS::PRIVATE_ADDRESS.

◆ rewriteIntrinsicWithAddressSpace()

Value * GCNTTIImpl::rewriteIntrinsicWithAddressSpace ( IntrinsicInst *  II,
Value *  OldV,
Value *  NewV 
) const

Definition at line 1077 of file AMDGPUTargetTransformInfo.cpp.

References B, llvm::computeKnownBits(), llvm::KnownBits::countMinLeadingOnes(), llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::Type::getContext(), llvm::ConstantInt::getFalse(), llvm::Intrinsic::getOrInsertDeclaration(), llvm::Type::getPointerAddressSpace(), llvm::DataLayout::getPointerSizeInBits(), llvm::TargetLoweringBase::getTargetMachine(), llvm::ConstantInt::getTrue(), llvm::Value::getType(), II, llvm::AMDGPU::isExtendedGlobalAddrSpace(), llvm::AMDGPUAS::LOCAL_ADDRESS, and llvm::AMDGPUAS::PRIVATE_ADDRESS.

◆ shouldPrefetchAddressSpace()

bool GCNTTIImpl::shouldPrefetchAddressSpace ( unsigned  AS) const
overridevirtual
Returns
if target want to issue a prefetch in address space AS.

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1430 of file AMDGPUTargetTransformInfo.cpp.

References llvm::AMDGPU::isFlatGlobalAddrSpace().

◆ simplifyDemandedLaneMaskArg()

bool GCNTTIImpl::simplifyDemandedLaneMaskArg ( InstCombiner &  IC,
IntrinsicInst &  II,
unsigned  LaneArgIdx 
) const

Simplify a lane index operand (e.g.

llvm.amdgcn.readlane src1).

The instruction only reads the low 5 bits for wave32, and 6 bits for wave64.

Definition at line 456 of file AMDGPUInstCombineIntrinsic.cpp.

References llvm::KnownBits::getConstant(), llvm::Value::getType(), llvm::AMDGPUSubtarget::getWavefrontSizeLog2(), II, llvm::KnownBits::isConstant(), and llvm::InstCombiner::SimplifyDemandedBits().

Referenced by instCombineIntrinsic().

◆ simplifyDemandedVectorEltsIntrinsic()

std::optional< Value * > GCNTTIImpl::simplifyDemandedVectorEltsIntrinsic ( InstCombiner &  IC,
IntrinsicInst &  II,
APInt  DemandedElts,
APInt &  UndefElts,
APInt &  UndefElts2,
APInt &  UndefElts3,
std::function< void(Instruction *, unsigned, APInt, APInt &)>  SimplifyAndSetOp 
) const

Definition at line 1538 of file AMDGPUInstCombineIntrinsic.cpp.

References II, and simplifyAMDGCNMemoryIntrinsicDemanded().

The documentation for this class was generated from the following files:
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