LLVM 19.0.0git
AMDGPUAsmPrinter.cpp
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1//===-- AMDGPUAsmPrinter.cpp - AMDGPU assembly printer --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10///
11/// The AMDGPUAsmPrinter is used to print both assembly string and also binary
12/// code. When passed an MCAsmStreamer it prints assembly and when passed
13/// an MCObjectStreamer it outputs binary code.
14//
15//===----------------------------------------------------------------------===//
16//
17
18#include "AMDGPUAsmPrinter.h"
19#include "AMDGPU.h"
22#include "AMDKernelCodeT.h"
23#include "GCNSubtarget.h"
28#include "R600AsmPrinter.h"
37#include "llvm/MC/MCAssembler.h"
38#include "llvm/MC/MCContext.h"
40#include "llvm/MC/MCStreamer.h"
46
47using namespace llvm;
48using namespace llvm::AMDGPU;
49
50// This should get the default rounding mode from the kernel. We just set the
51// default here, but this could change if the OpenCL rounding mode pragmas are
52// used.
53//
54// The denormal mode here should match what is reported by the OpenCL runtime
55// for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
56// can also be override to flush with the -cl-denorms-are-zero compiler flag.
57//
58// AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
59// precision, and leaves single precision to flush all and does not report
60// CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
61// CL_FP_DENORM for both.
62//
63// FIXME: It seems some instructions do not support single precision denormals
64// regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
65// and sin_f32, cos_f32 on most parts).
66
67// We want to use these instructions, and using fp32 denormals also causes
68// instructions to run at the double precision rate for the device so it's
69// probably best to just report no single precision denormals.
73 FP_DENORM_MODE_SP(Mode.fpDenormModeSPValue()) |
74 FP_DENORM_MODE_DP(Mode.fpDenormModeDPValue());
75}
76
77static AsmPrinter *
79 std::unique_ptr<MCStreamer> &&Streamer) {
80 return new AMDGPUAsmPrinter(tm, std::move(Streamer));
81}
82
88}
89
91 std::unique_ptr<MCStreamer> Streamer)
92 : AsmPrinter(TM, std::move(Streamer)) {
93 assert(OutStreamer && "AsmPrinter constructed without streamer");
94}
95
97 return "AMDGPU Assembly Printer";
98}
99
101 return TM.getMCSubtargetInfo();
102}
103
105 if (!OutStreamer)
106 return nullptr;
107 return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
108}
109
112}
113
114void AMDGPUAsmPrinter::initTargetStreamer(Module &M) {
116
117 // TODO: Which one is called first, emitStartOfAsmFile or
118 // emitFunctionBodyStart?
119 if (getTargetStreamer() && !getTargetStreamer()->getTargetID())
120 initializeTargetID(M);
121
124 return;
125
127
130 CodeObjectVersion);
131 HSAMetadataStream->begin(M, *getTargetStreamer()->getTargetID());
132 }
133
136}
137
138uint64_t AMDGPUAsmPrinter::getMCExprValue(const MCExpr *Value, MCContext &Ctx) {
139 int64_t Val;
140 if (!Value->evaluateAsAbsolute(Val)) {
141 Ctx.reportError(SMLoc(), "could not resolve expression when required.");
142 return 0;
143 }
144 return static_cast<uint64_t>(Val);
145}
146
148 // Init target streamer if it has not yet happened
150 initTargetStreamer(M);
151
154
155 // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
156 // Emit HSA Metadata (NT_AMD_HSA_METADATA).
158 HSAMetadataStream->end();
159 bool Success = HSAMetadataStream->emitTo(*getTargetStreamer());
160 (void)Success;
161 assert(Success && "Malformed HSA Metadata");
162 }
163}
164
167 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
168 const Function &F = MF->getFunction();
169
170 // TODO: We're checking this late, would be nice to check it earlier.
171 if (STM.requiresCodeObjectV6() && CodeObjectVersion < AMDGPU::AMDHSA_COV6) {
173 STM.getCPU() + " is only available on code object version 6 or better",
174 /*gen_crash_diag*/ false);
175 }
176
177 // TODO: Which one is called first, emitStartOfAsmFile or
178 // emitFunctionBodyStart?
179 if (!getTargetStreamer()->getTargetID())
180 initializeTargetID(*F.getParent());
181
182 const auto &FunctionTargetID = STM.getTargetID();
183 // Make sure function's xnack settings are compatible with module's
184 // xnack settings.
185 if (FunctionTargetID.isXnackSupported() &&
186 FunctionTargetID.getXnackSetting() != IsaInfo::TargetIDSetting::Any &&
187 FunctionTargetID.getXnackSetting() != getTargetStreamer()->getTargetID()->getXnackSetting()) {
188 OutContext.reportError({}, "xnack setting of '" + Twine(MF->getName()) +
189 "' function does not match module xnack setting");
190 return;
191 }
192 // Make sure function's sramecc settings are compatible with module's
193 // sramecc settings.
194 if (FunctionTargetID.isSramEccSupported() &&
195 FunctionTargetID.getSramEccSetting() != IsaInfo::TargetIDSetting::Any &&
196 FunctionTargetID.getSramEccSetting() != getTargetStreamer()->getTargetID()->getSramEccSetting()) {
197 OutContext.reportError({}, "sramecc setting of '" + Twine(MF->getName()) +
198 "' function does not match module sramecc setting");
199 return;
200 }
201
202 if (!MFI.isEntryFunction())
203 return;
204
205 if (STM.isMesaKernel(F) &&
206 (F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
207 F.getCallingConv() == CallingConv::SPIR_KERNEL)) {
208 amd_kernel_code_t KernelCode;
209 getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
211 }
212
213 if (STM.isAmdHsaOS())
214 HSAMetadataStream->emitKernel(*MF, CurrentProgramInfo);
215
216 if (MFI.getNumKernargPreloadedSGPRs() > 0) {
219 STM.isAmdHsaOS());
220 }
221}
222
225 if (!MFI.isEntryFunction())
226 return;
227
229 return;
230
231 auto &Streamer = getTargetStreamer()->getStreamer();
232 auto &Context = Streamer.getContext();
233 auto &ObjectFileInfo = *Context.getObjectFileInfo();
234 auto &ReadOnlySection = *ObjectFileInfo.getReadOnlySection();
235
236 Streamer.pushSection();
237 Streamer.switchSection(&ReadOnlySection);
238
239 // CP microcode requires the kernel descriptor to be allocated on 64 byte
240 // alignment.
241 Streamer.emitValueToAlignment(Align(64), 0, 1, 0);
242 ReadOnlySection.ensureMinAlignment(Align(64));
243
244 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
245
246 SmallString<128> KernelName;
247 getNameWithPrefix(KernelName, &MF->getFunction());
249 STM, KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo),
250 getMCExprValue(CurrentProgramInfo.NumVGPRsForWavesPerEU, Context),
251 getMCExprValue(CurrentProgramInfo.NumSGPRsForWavesPerEU, Context) -
253 &STM, getMCExprValue(CurrentProgramInfo.VCCUsed, Context),
254 getMCExprValue(CurrentProgramInfo.FlatUsed, Context),
255 getTargetStreamer()->getTargetID()->isXnackOnOrAny()),
256 getMCExprValue(CurrentProgramInfo.VCCUsed, Context),
257 getMCExprValue(CurrentProgramInfo.FlatUsed, Context));
258
259 Streamer.popSection();
260}
261
263 Register RegNo = MI->getOperand(0).getReg();
264
267 OS << "implicit-def: "
268 << printReg(RegNo, MF->getSubtarget().getRegisterInfo());
269
270 if (MI->getAsmPrinterFlags() & AMDGPU::SGPR_SPILL)
271 OS << " : SGPR spill to VGPR lane";
272
273 OutStreamer->AddComment(OS.str());
274 OutStreamer->addBlankLine();
275}
276
280 return;
281 }
282
284 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
285 if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) {
286 SmallString<128> SymbolName;
287 getNameWithPrefix(SymbolName, &MF->getFunction()),
289 SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
290 }
291 if (DumpCodeInstEmitter) {
292 // Disassemble function name label to text.
293 DisasmLines.push_back(MF->getName().str() + ":");
294 DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
295 HexLines.push_back("");
296 }
297
299}
300
302 if (DumpCodeInstEmitter && !isBlockOnlyReachableByFallthrough(&MBB)) {
303 // Write a line for the basic block label if it is not only fallthrough.
304 DisasmLines.push_back(
305 (Twine("BB") + Twine(getFunctionNumber())
306 + "_" + Twine(MBB.getNumber()) + ":").str());
307 DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
308 HexLines.push_back("");
309 }
311}
312
315 if (GV->hasInitializer() && !isa<UndefValue>(GV->getInitializer())) {
317 Twine(GV->getName()) +
318 ": unsupported initializer for address space");
319 return;
320 }
321
322 // LDS variables aren't emitted in HSA or PAL yet.
324 if (OS == Triple::AMDHSA || OS == Triple::AMDPAL)
325 return;
326
327 MCSymbol *GVSym = getSymbol(GV);
328
329 GVSym->redefineIfPossible();
330 if (GVSym->isDefined() || GVSym->isVariable())
331 report_fatal_error("symbol '" + Twine(GVSym->getName()) +
332 "' is already defined");
333
334 const DataLayout &DL = GV->getParent()->getDataLayout();
335 uint64_t Size = DL.getTypeAllocSize(GV->getValueType());
336 Align Alignment = GV->getAlign().value_or(Align(4));
337
338 emitVisibility(GVSym, GV->getVisibility(), !GV->isDeclaration());
339 emitLinkage(GV, GVSym);
340 auto TS = getTargetStreamer();
341 TS->emitAMDGPULDS(GVSym, Size, Alignment);
342 return;
343 }
344
346}
347
349 CodeObjectVersion = AMDGPU::getAMDHSACodeObjectVersion(M);
350
352 switch (CodeObjectVersion) {
354 HSAMetadataStream.reset(new HSAMD::MetadataStreamerMsgPackV4());
355 break;
357 HSAMetadataStream.reset(new HSAMD::MetadataStreamerMsgPackV5());
358 break;
360 HSAMetadataStream.reset(new HSAMD::MetadataStreamerMsgPackV6());
361 break;
362 default:
363 report_fatal_error("Unexpected code object version");
364 }
365 }
367}
368
370 // Pad with s_code_end to help tools and guard against instruction prefetch
371 // causing stale data in caches. Arguably this should be done by the linker,
372 // which is why this isn't done for Mesa.
373 const MCSubtargetInfo &STI = *getGlobalSTI();
374 if ((AMDGPU::isGFX10Plus(STI) || AMDGPU::isGFX90A(STI)) &&
377 OutStreamer->switchSection(getObjFileLowering().getTextSection());
379 }
380
382}
383
384// Print comments that apply to both callable functions and entry points.
385void AMDGPUAsmPrinter::emitCommonFunctionComments(
386 uint32_t NumVGPR, std::optional<uint32_t> NumAGPR, uint32_t TotalNumVGPR,
387 uint32_t NumSGPR, uint64_t ScratchSize, uint64_t CodeSize,
388 const AMDGPUMachineFunction *MFI) {
389 OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
390 OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
391 OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
392 if (NumAGPR) {
393 OutStreamer->emitRawComment(" NumAgprs: " + Twine(*NumAGPR), false);
394 OutStreamer->emitRawComment(" TotalNumVgprs: " + Twine(TotalNumVGPR),
395 false);
396 }
397 OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
398 OutStreamer->emitRawComment(" MemoryBound: " + Twine(MFI->isMemoryBound()),
399 false);
400}
401
402uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties(
403 const MachineFunction &MF) const {
405 uint16_t KernelCodeProperties = 0;
406 const GCNUserSGPRUsageInfo &UserSGPRInfo = MFI.getUserSGPRInfo();
407
408 if (UserSGPRInfo.hasPrivateSegmentBuffer()) {
409 KernelCodeProperties |=
410 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
411 }
412 if (UserSGPRInfo.hasDispatchPtr()) {
413 KernelCodeProperties |=
414 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
415 }
416 if (UserSGPRInfo.hasQueuePtr() && CodeObjectVersion < AMDGPU::AMDHSA_COV5) {
417 KernelCodeProperties |=
418 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
419 }
420 if (UserSGPRInfo.hasKernargSegmentPtr()) {
421 KernelCodeProperties |=
422 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
423 }
424 if (UserSGPRInfo.hasDispatchID()) {
425 KernelCodeProperties |=
426 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
427 }
428 if (UserSGPRInfo.hasFlatScratchInit()) {
429 KernelCodeProperties |=
430 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
431 }
433 KernelCodeProperties |=
434 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32;
435 }
436
437 if (getMCExprValue(CurrentProgramInfo.DynamicCallStack, MF.getContext()) &&
438 CodeObjectVersion >= AMDGPU::AMDHSA_COV5)
439 KernelCodeProperties |= amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK;
440
441 return KernelCodeProperties;
442}
443
445AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(const MachineFunction &MF,
446 const SIProgramInfo &PI) const {
448 const Function &F = MF.getFunction();
450 MCContext &Ctx = MF.getContext();
451
452 MCKernelDescriptor KernelDescriptor;
453
454 KernelDescriptor.group_segment_fixed_size =
456 KernelDescriptor.private_segment_fixed_size = PI.ScratchSize;
457
458 Align MaxKernArgAlign;
459 KernelDescriptor.kernarg_size = MCConstantExpr::create(
460 STM.getKernArgSegmentSize(F, MaxKernArgAlign), Ctx);
461
462 KernelDescriptor.compute_pgm_rsrc1 = PI.getComputePGMRSrc1(STM, Ctx);
463 KernelDescriptor.compute_pgm_rsrc2 = PI.getComputePGMRSrc2(Ctx);
464 KernelDescriptor.kernel_code_properties =
465 MCConstantExpr::create(getAmdhsaKernelCodeProperties(MF), Ctx);
466
467 assert(STM.hasGFX90AInsts() ||
468 getMCExprValue(CurrentProgramInfo.ComputePGMRSrc3GFX90A, Ctx) == 0);
469 KernelDescriptor.compute_pgm_rsrc3 = CurrentProgramInfo.ComputePGMRSrc3GFX90A;
470
471 KernelDescriptor.kernarg_preload = MCConstantExpr::create(
472 AMDGPU::hasKernargPreload(STM) ? Info->getNumKernargPreloadedSGPRs() : 0,
473 Ctx);
474
475 return KernelDescriptor;
476}
477
479 // Init target streamer lazily on the first function so that previous passes
480 // can set metadata.
482 initTargetStreamer(*MF.getFunction().getParent());
483
484 ResourceUsage = &getAnalysis<AMDGPUResourceUsageAnalysis>();
485 CurrentProgramInfo.reset(MF);
486
488 MCContext &Ctx = MF.getContext();
489
490 // The starting address of all shader programs must be 256 bytes aligned.
491 // Regular functions just need the basic required instruction alignment.
492 MF.setAlignment(MFI->isEntryFunction() ? Align(256) : Align(4));
493
495
498 // FIXME: This should be an explicit check for Mesa.
499 if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) {
500 MCSectionELF *ConfigSection =
501 Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
502 OutStreamer->switchSection(ConfigSection);
503 }
504
505 if (MFI->isModuleEntryFunction()) {
506 getSIProgramInfo(CurrentProgramInfo, MF);
507 }
508
509 if (STM.isAmdPalOS()) {
510 if (MFI->isEntryFunction())
511 EmitPALMetadata(MF, CurrentProgramInfo);
512 else if (MFI->isModuleEntryFunction())
513 emitPALFunctionMetadata(MF);
514 } else if (!STM.isAmdHsaOS()) {
515 EmitProgramInfoSI(MF, CurrentProgramInfo);
516 }
517
518 DumpCodeInstEmitter = nullptr;
519 if (STM.dumpCode()) {
520 // For -dumpcode, get the assembler out of the streamer. This only works
521 // with -filetype=obj.
522 MCAssembler *Assembler = OutStreamer->getAssemblerPtr();
523 if (Assembler)
524 DumpCodeInstEmitter = Assembler->getEmitterPtr();
525 }
526
527 DisasmLines.clear();
528 HexLines.clear();
530
532
533 emitResourceUsageRemarks(MF, CurrentProgramInfo, MFI->isModuleEntryFunction(),
534 STM.hasMAIInsts());
535
536 if (isVerbose()) {
537 MCSectionELF *CommentSection =
538 Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
539 OutStreamer->switchSection(CommentSection);
540
541 if (!MFI->isEntryFunction()) {
542 OutStreamer->emitRawComment(" Function info:", false);
544 ResourceUsage->getResourceInfo(&MF.getFunction());
545 emitCommonFunctionComments(
546 Info.NumVGPR,
547 STM.hasMAIInsts() ? Info.NumAGPR : std::optional<uint32_t>(),
548 Info.getTotalNumVGPRs(STM),
549 Info.getTotalNumSGPRs(MF.getSubtarget<GCNSubtarget>()),
550 Info.PrivateSegmentSize, getFunctionCodeSize(MF), MFI);
551 return false;
552 }
553
554 OutStreamer->emitRawComment(" Kernel info:", false);
555 emitCommonFunctionComments(
556 getMCExprValue(CurrentProgramInfo.NumArchVGPR, Ctx),
557 STM.hasMAIInsts() ? getMCExprValue(CurrentProgramInfo.NumAccVGPR, Ctx)
558 : std::optional<uint32_t>(),
559 getMCExprValue(CurrentProgramInfo.NumVGPR, Ctx),
560 getMCExprValue(CurrentProgramInfo.NumSGPR, Ctx),
561 getMCExprValue(CurrentProgramInfo.ScratchSize, Ctx),
562 getFunctionCodeSize(MF), MFI);
563
564 OutStreamer->emitRawComment(
565 " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
566 OutStreamer->emitRawComment(
567 " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
568 OutStreamer->emitRawComment(
569 " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
570 " bytes/workgroup (compile time only)", false);
571
572 OutStreamer->emitRawComment(
573 " SGPRBlocks: " +
574 Twine(getMCExprValue(CurrentProgramInfo.SGPRBlocks, Ctx)),
575 false);
576 OutStreamer->emitRawComment(
577 " VGPRBlocks: " +
578 Twine(getMCExprValue(CurrentProgramInfo.VGPRBlocks, Ctx)),
579 false);
580
581 OutStreamer->emitRawComment(
582 " NumSGPRsForWavesPerEU: " +
583 Twine(
584 getMCExprValue(CurrentProgramInfo.NumSGPRsForWavesPerEU, Ctx)),
585 false);
586 OutStreamer->emitRawComment(
587 " NumVGPRsForWavesPerEU: " +
588 Twine(
589 getMCExprValue(CurrentProgramInfo.NumVGPRsForWavesPerEU, Ctx)),
590 false);
591
592 if (STM.hasGFX90AInsts())
593 OutStreamer->emitRawComment(
594 " AccumOffset: " +
595 Twine((getMCExprValue(CurrentProgramInfo.AccumOffset, Ctx) + 1) *
596 4),
597 false);
598
599 OutStreamer->emitRawComment(
600 " Occupancy: " +
601 Twine(getMCExprValue(CurrentProgramInfo.Occupancy, Ctx)),
602 false);
603
604 OutStreamer->emitRawComment(
605 " WaveLimiterHint : " + Twine(MFI->needsWaveLimiter()), false);
606
607 OutStreamer->emitRawComment(
608 " COMPUTE_PGM_RSRC2:SCRATCH_EN: " +
609 Twine(getMCExprValue(CurrentProgramInfo.ScratchEnable, Ctx)),
610 false);
611 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " +
612 Twine(CurrentProgramInfo.UserSGPR),
613 false);
614 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
615 Twine(CurrentProgramInfo.TrapHandlerEnable),
616 false);
617 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_X_EN: " +
618 Twine(CurrentProgramInfo.TGIdXEnable),
619 false);
620 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
621 Twine(CurrentProgramInfo.TGIdYEnable),
622 false);
623 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
624 Twine(CurrentProgramInfo.TGIdZEnable),
625 false);
626 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
627 Twine(CurrentProgramInfo.TIdIGCompCount),
628 false);
629
630 assert(STM.hasGFX90AInsts() ||
631 getMCExprValue(CurrentProgramInfo.ComputePGMRSrc3GFX90A, Ctx) == 0);
632 if (STM.hasGFX90AInsts()) {
633 OutStreamer->emitRawComment(
634 " COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: " +
636 getMCExprValue(CurrentProgramInfo.ComputePGMRSrc3GFX90A, Ctx),
637 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET))),
638 false);
639 OutStreamer->emitRawComment(
640 " COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: " +
642 getMCExprValue(CurrentProgramInfo.ComputePGMRSrc3GFX90A, Ctx),
643 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT))),
644 false);
645 }
646 }
647
648 if (DumpCodeInstEmitter) {
649
650 OutStreamer->switchSection(
651 Context.getELFSection(".AMDGPU.disasm", ELF::SHT_PROGBITS, 0));
652
653 for (size_t i = 0; i < DisasmLines.size(); ++i) {
654 std::string Comment = "\n";
655 if (!HexLines[i].empty()) {
656 Comment = std::string(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
657 Comment += " ; " + HexLines[i] + "\n";
658 }
659
660 OutStreamer->emitBytes(StringRef(DisasmLines[i]));
661 OutStreamer->emitBytes(StringRef(Comment));
662 }
663 }
664
665 return false;
666}
667
668// TODO: Fold this into emitFunctionBodyStart.
669void AMDGPUAsmPrinter::initializeTargetID(const Module &M) {
670 // In the beginning all features are either 'Any' or 'NotSupported',
671 // depending on global target features. This will cover empty modules.
673 getGlobalSTI()->getFeatureString());
674
675 // If module is empty, we are done.
676 if (M.empty())
677 return;
678
679 // If module is not empty, need to find first 'Off' or 'On' feature
680 // setting per feature from functions in module.
681 for (auto &F : M) {
682 auto &TSTargetID = getTargetStreamer()->getTargetID();
683 if ((!TSTargetID->isXnackSupported() || TSTargetID->isXnackOnOrOff()) &&
684 (!TSTargetID->isSramEccSupported() || TSTargetID->isSramEccOnOrOff()))
685 break;
686
688 const IsaInfo::AMDGPUTargetID &STMTargetID = STM.getTargetID();
689 if (TSTargetID->isXnackSupported())
690 if (TSTargetID->getXnackSetting() == IsaInfo::TargetIDSetting::Any)
691 TSTargetID->setXnackSetting(STMTargetID.getXnackSetting());
692 if (TSTargetID->isSramEccSupported())
693 if (TSTargetID->getSramEccSetting() == IsaInfo::TargetIDSetting::Any)
694 TSTargetID->setSramEccSetting(STMTargetID.getSramEccSetting());
695 }
696}
697
698uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
700 const SIInstrInfo *TII = STM.getInstrInfo();
701
702 uint64_t CodeSize = 0;
703
704 for (const MachineBasicBlock &MBB : MF) {
705 for (const MachineInstr &MI : MBB) {
706 // TODO: CodeSize should account for multiple functions.
707
708 // TODO: Should we count size of debug info?
709 if (MI.isDebugInstr())
710 continue;
711
712 CodeSize += TII->getInstSizeInBytes(MI);
713 }
714 }
715
716 return CodeSize;
717}
718
719void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
720 const MachineFunction &MF) {
722 ResourceUsage->getResourceInfo(&MF.getFunction());
724 MCContext &Ctx = MF.getContext();
725
726 auto CreateExpr = [&Ctx](int64_t Value) {
727 return MCConstantExpr::create(Value, Ctx);
728 };
729
730 auto TryGetMCExprValue = [](const MCExpr *Value, uint64_t &Res) -> bool {
731 int64_t Val;
732 if (Value->evaluateAsAbsolute(Val)) {
733 Res = Val;
734 return true;
735 }
736 return false;
737 };
738
739 ProgInfo.NumArchVGPR = CreateExpr(Info.NumVGPR);
740 ProgInfo.NumAccVGPR = CreateExpr(Info.NumAGPR);
741 ProgInfo.NumVGPR = CreateExpr(Info.getTotalNumVGPRs(STM));
742 ProgInfo.AccumOffset =
743 CreateExpr(alignTo(std::max(1, Info.NumVGPR), 4) / 4 - 1);
744 ProgInfo.TgSplit = STM.isTgSplitEnabled();
745 ProgInfo.NumSGPR = CreateExpr(Info.NumExplicitSGPR);
746 ProgInfo.ScratchSize = CreateExpr(Info.PrivateSegmentSize);
747 ProgInfo.VCCUsed = CreateExpr(Info.UsesVCC);
748 ProgInfo.FlatUsed = CreateExpr(Info.UsesFlatScratch);
749 ProgInfo.DynamicCallStack =
750 CreateExpr(Info.HasDynamicallySizedStack || Info.HasRecursion);
751
752 const uint64_t MaxScratchPerWorkitem =
754 uint64_t ScratchSize;
755 if (TryGetMCExprValue(ProgInfo.ScratchSize, ScratchSize) &&
756 ScratchSize > MaxScratchPerWorkitem) {
757 DiagnosticInfoStackSize DiagStackSize(MF.getFunction(), ScratchSize,
758 MaxScratchPerWorkitem, DS_Error);
759 MF.getFunction().getContext().diagnose(DiagStackSize);
760 }
761
763
764 // The calculations related to SGPR/VGPR blocks are
765 // duplicated in part in AMDGPUAsmParser::calculateGPRBlocks, and could be
766 // unified.
768 ProgInfo.VCCUsed, ProgInfo.FlatUsed,
769 getTargetStreamer()->getTargetID()->isXnackOnOrAny(), Ctx);
770
771 // Check the addressable register limit before we add ExtraSGPRs.
773 !STM.hasSGPRInitBug()) {
774 unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
775 uint64_t NumSgpr;
776 if (TryGetMCExprValue(ProgInfo.NumSGPR, NumSgpr) &&
777 NumSgpr > MaxAddressableNumSGPRs) {
778 // This can happen due to a compiler bug or when using inline asm.
781 MF.getFunction(), "addressable scalar registers", NumSgpr,
782 MaxAddressableNumSGPRs, DS_Error, DK_ResourceLimit);
783 Ctx.diagnose(Diag);
784 ProgInfo.NumSGPR = CreateExpr(MaxAddressableNumSGPRs - 1);
785 }
786 }
787
788 // Account for extra SGPRs and VGPRs reserved for debugger use.
789 ProgInfo.NumSGPR = MCBinaryExpr::createAdd(ProgInfo.NumSGPR, ExtraSGPRs, Ctx);
790
791 const Function &F = MF.getFunction();
792
793 // Ensure there are enough SGPRs and VGPRs for wave dispatch, where wave
794 // dispatch registers are function args.
795 unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0;
796
797 if (isShader(F.getCallingConv())) {
798 bool IsPixelShader =
799 F.getCallingConv() == CallingConv::AMDGPU_PS && !STM.isAmdHsaOS();
800
801 // Calculate the number of VGPR registers based on the SPI input registers
802 uint32_t InputEna = 0;
803 uint32_t InputAddr = 0;
804 unsigned LastEna = 0;
805
806 if (IsPixelShader) {
807 // Note for IsPixelShader:
808 // By this stage, all enabled inputs are tagged in InputAddr as well.
809 // We will use InputAddr to determine whether the input counts against the
810 // vgpr total and only use the InputEnable to determine the last input
811 // that is relevant - if extra arguments are used, then we have to honour
812 // the InputAddr for any intermediate non-enabled inputs.
813 InputEna = MFI->getPSInputEnable();
814 InputAddr = MFI->getPSInputAddr();
815
816 // We only need to consider input args up to the last used arg.
817 assert((InputEna || InputAddr) &&
818 "PSInputAddr and PSInputEnable should "
819 "never both be 0 for AMDGPU_PS shaders");
820 // There are some rare circumstances where InputAddr is non-zero and
821 // InputEna can be set to 0. In this case we default to setting LastEna
822 // to 1.
823 LastEna = InputEna ? llvm::Log2_32(InputEna) + 1 : 1;
824 }
825
826 // FIXME: We should be using the number of registers determined during
827 // calling convention lowering to legalize the types.
828 const DataLayout &DL = F.getParent()->getDataLayout();
829 unsigned PSArgCount = 0;
830 unsigned IntermediateVGPR = 0;
831 for (auto &Arg : F.args()) {
832 unsigned NumRegs = (DL.getTypeSizeInBits(Arg.getType()) + 31) / 32;
833 if (Arg.hasAttribute(Attribute::InReg)) {
834 WaveDispatchNumSGPR += NumRegs;
835 } else {
836 // If this is a PS shader and we're processing the PS Input args (first
837 // 16 VGPR), use the InputEna and InputAddr bits to define how many
838 // VGPRs are actually used.
839 // Any extra VGPR arguments are handled as normal arguments (and
840 // contribute to the VGPR count whether they're used or not).
841 if (IsPixelShader && PSArgCount < 16) {
842 if ((1 << PSArgCount) & InputAddr) {
843 if (PSArgCount < LastEna)
844 WaveDispatchNumVGPR += NumRegs;
845 else
846 IntermediateVGPR += NumRegs;
847 }
848 PSArgCount++;
849 } else {
850 // If there are extra arguments we have to include the allocation for
851 // the non-used (but enabled with InputAddr) input arguments
852 if (IntermediateVGPR) {
853 WaveDispatchNumVGPR += IntermediateVGPR;
854 IntermediateVGPR = 0;
855 }
856 WaveDispatchNumVGPR += NumRegs;
857 }
858 }
859 }
861 {ProgInfo.NumSGPR, CreateExpr(WaveDispatchNumSGPR)}, Ctx);
862
864 {ProgInfo.NumVGPR, CreateExpr(WaveDispatchNumVGPR)}, Ctx);
865
867 ProgInfo.NumAccVGPR, ProgInfo.NumArchVGPR, Ctx);
868 }
869
870 // Adjust number of registers used to meet default/requested minimum/maximum
871 // number of waves per execution unit request.
872 unsigned MaxWaves = MFI->getMaxWavesPerEU();
874 {ProgInfo.NumSGPR, CreateExpr(1ul),
875 CreateExpr(STM.getMinNumSGPRs(MaxWaves))},
876 Ctx);
878 {ProgInfo.NumVGPR, CreateExpr(1ul),
879 CreateExpr(STM.getMinNumVGPRs(MaxWaves))},
880 Ctx);
881
883 STM.hasSGPRInitBug()) {
884 unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
885 uint64_t NumSgpr;
886 if (TryGetMCExprValue(ProgInfo.NumSGPR, NumSgpr) &&
887 NumSgpr > MaxAddressableNumSGPRs) {
888 // This can happen due to a compiler bug or when using inline asm to use
889 // the registers which are usually reserved for vcc etc.
891 DiagnosticInfoResourceLimit Diag(MF.getFunction(), "scalar registers",
892 NumSgpr, MaxAddressableNumSGPRs,
894 Ctx.diagnose(Diag);
895 ProgInfo.NumSGPR = CreateExpr(MaxAddressableNumSGPRs);
896 ProgInfo.NumSGPRsForWavesPerEU = CreateExpr(MaxAddressableNumSGPRs);
897 }
898 }
899
900 if (STM.hasSGPRInitBug()) {
901 ProgInfo.NumSGPR =
903 ProgInfo.NumSGPRsForWavesPerEU =
905 }
906
907 if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
909 DiagnosticInfoResourceLimit Diag(MF.getFunction(), "user SGPRs",
910 MFI->getNumUserSGPRs(),
912 Ctx.diagnose(Diag);
913 }
914
915 if (MFI->getLDSSize() >
916 static_cast<unsigned>(STM.getAddressableLocalMemorySize())) {
919 MF.getFunction(), "local memory", MFI->getLDSSize(),
921 Ctx.diagnose(Diag);
922 }
923 // The MCExpr equivalent of getNumSGPRBlocks/getNumVGPRBlocks:
924 // (alignTo(max(1u, NumGPR), GPREncodingGranule) / GPREncodingGranule) - 1
925 auto GetNumGPRBlocks = [&CreateExpr, &Ctx](const MCExpr *NumGPR,
926 unsigned Granule) {
927 const MCExpr *OneConst = CreateExpr(1ul);
928 const MCExpr *GranuleConst = CreateExpr(Granule);
929 const MCExpr *MaxNumGPR =
930 AMDGPUVariadicMCExpr::createMax({NumGPR, OneConst}, Ctx);
931 const MCExpr *AlignToGPR =
932 AMDGPUVariadicMCExpr::createAlignTo(MaxNumGPR, GranuleConst, Ctx);
933 const MCExpr *DivGPR =
934 MCBinaryExpr::createDiv(AlignToGPR, GranuleConst, Ctx);
935 const MCExpr *SubGPR = MCBinaryExpr::createSub(DivGPR, OneConst, Ctx);
936 return SubGPR;
937 };
938
939 ProgInfo.SGPRBlocks = GetNumGPRBlocks(ProgInfo.NumSGPRsForWavesPerEU,
941 ProgInfo.VGPRBlocks = GetNumGPRBlocks(ProgInfo.NumVGPRsForWavesPerEU,
943
944 const SIModeRegisterDefaults Mode = MFI->getMode();
945
946 // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
947 // register.
948 ProgInfo.FloatMode = getFPMode(Mode);
949
950 ProgInfo.IEEEMode = Mode.IEEE;
951
952 // Make clamp modifier on NaN input returns 0.
953 ProgInfo.DX10Clamp = Mode.DX10Clamp;
954
955 unsigned LDSAlignShift;
957 // LDS is allocated in 64 dword blocks.
958 LDSAlignShift = 8;
959 } else {
960 // LDS is allocated in 128 dword blocks.
961 LDSAlignShift = 9;
962 }
963
964 ProgInfo.SGPRSpill = MFI->getNumSpilledSGPRs();
965 ProgInfo.VGPRSpill = MFI->getNumSpilledVGPRs();
966
967 ProgInfo.LDSSize = MFI->getLDSSize();
968 ProgInfo.LDSBlocks =
969 alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
970
971 // The MCExpr equivalent of divideCeil.
972 auto DivideCeil = [&Ctx](const MCExpr *Numerator, const MCExpr *Denominator) {
973 const MCExpr *Ceil =
974 AMDGPUVariadicMCExpr::createAlignTo(Numerator, Denominator, Ctx);
975 return MCBinaryExpr::createDiv(Ceil, Denominator, Ctx);
976 };
977
978 // Scratch is allocated in 64-dword or 256-dword blocks.
979 unsigned ScratchAlignShift =
980 STM.getGeneration() >= AMDGPUSubtarget::GFX11 ? 8 : 10;
981 // We need to program the hardware with the amount of scratch memory that
982 // is used by the entire wave. ProgInfo.ScratchSize is the amount of
983 // scratch memory used per thread.
984 ProgInfo.ScratchBlocks = DivideCeil(
986 CreateExpr(STM.getWavefrontSize()), Ctx),
987 CreateExpr(1ULL << ScratchAlignShift));
988
989 if (getIsaVersion(getGlobalSTI()->getCPU()).Major >= 10) {
990 ProgInfo.WgpMode = STM.isCuModeEnabled() ? 0 : 1;
991 ProgInfo.MemOrdered = 1;
992 }
993
994 // 0 = X, 1 = XY, 2 = XYZ
995 unsigned TIDIGCompCnt = 0;
996 if (MFI->hasWorkItemIDZ())
997 TIDIGCompCnt = 2;
998 else if (MFI->hasWorkItemIDY())
999 TIDIGCompCnt = 1;
1000
1001 // The private segment wave byte offset is the last of the system SGPRs. We
1002 // initially assumed it was allocated, and may have used it. It shouldn't harm
1003 // anything to disable it if we know the stack isn't used here. We may still
1004 // have emitted code reading it to initialize scratch, but if that's unused
1005 // reading garbage should be OK.
1008 MCConstantExpr::create(0, Ctx), Ctx),
1009 ProgInfo.DynamicCallStack, Ctx);
1010
1011 ProgInfo.UserSGPR = MFI->getNumUserSGPRs();
1012 // For AMDHSA, TRAP_HANDLER must be zero, as it is populated by the CP.
1013 ProgInfo.TrapHandlerEnable =
1014 STM.isAmdHsaOS() ? 0 : STM.isTrapHandlerEnabled();
1015 ProgInfo.TGIdXEnable = MFI->hasWorkGroupIDX();
1016 ProgInfo.TGIdYEnable = MFI->hasWorkGroupIDY();
1017 ProgInfo.TGIdZEnable = MFI->hasWorkGroupIDZ();
1018 ProgInfo.TGSizeEnable = MFI->hasWorkGroupInfo();
1019 ProgInfo.TIdIGCompCount = TIDIGCompCnt;
1020 ProgInfo.EXCPEnMSB = 0;
1021 // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
1022 ProgInfo.LdsSize = STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks;
1023 ProgInfo.EXCPEnable = 0;
1024
1025 if (STM.hasGFX90AInsts()) {
1026 // return ((Dst & ~Mask) | (Value << Shift))
1027 auto SetBits = [&Ctx](const MCExpr *Dst, const MCExpr *Value, uint32_t Mask,
1028 uint32_t Shift) {
1029 auto Shft = MCConstantExpr::create(Shift, Ctx);
1030 auto Msk = MCConstantExpr::create(Mask, Ctx);
1031 Dst = MCBinaryExpr::createAnd(Dst, MCUnaryExpr::createNot(Msk, Ctx), Ctx);
1033 Dst, MCBinaryExpr::createShl(Value, Shft, Ctx), Ctx);
1034 return Dst;
1035 };
1036
1037 ProgInfo.ComputePGMRSrc3GFX90A =
1038 SetBits(ProgInfo.ComputePGMRSrc3GFX90A, ProgInfo.AccumOffset,
1039 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET,
1040 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET_SHIFT);
1041 ProgInfo.ComputePGMRSrc3GFX90A =
1042 SetBits(ProgInfo.ComputePGMRSrc3GFX90A, CreateExpr(ProgInfo.TgSplit),
1043 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT,
1044 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT);
1045 }
1046
1048 STM.computeOccupancy(F, ProgInfo.LDSSize), ProgInfo.NumSGPRsForWavesPerEU,
1049 ProgInfo.NumVGPRsForWavesPerEU, STM, Ctx);
1050
1051 const auto [MinWEU, MaxWEU] =
1052 AMDGPU::getIntegerPairAttribute(F, "amdgpu-waves-per-eu", {0, 0}, true);
1053 uint64_t Occupancy;
1054 if (TryGetMCExprValue(ProgInfo.Occupancy, Occupancy) && Occupancy < MinWEU) {
1056 F, F.getSubprogram(),
1057 "failed to meet occupancy target given by 'amdgpu-waves-per-eu' in "
1058 "'" +
1059 F.getName() + "': desired occupancy was " + Twine(MinWEU) +
1060 ", final occupancy is " + Twine(Occupancy));
1061 F.getContext().diagnose(Diag);
1062 }
1063}
1064
1065static unsigned getRsrcReg(CallingConv::ID CallConv) {
1066 switch (CallConv) {
1067 default: [[fallthrough]];
1075 }
1076}
1077
1078void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
1079 const SIProgramInfo &CurrentProgramInfo) {
1081 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1082 unsigned RsrcReg = getRsrcReg(MF.getFunction().getCallingConv());
1083 MCContext &Ctx = MF.getContext();
1084
1085 // (((Value) & Mask) << Shift)
1086 auto SetBits = [&Ctx](const MCExpr *Value, uint32_t Mask, uint32_t Shift) {
1087 const MCExpr *msk = MCConstantExpr::create(Mask, Ctx);
1088 const MCExpr *shft = MCConstantExpr::create(Shift, Ctx);
1090 shft, Ctx);
1091 };
1092
1093 auto EmitResolvedOrExpr = [this](const MCExpr *Value, unsigned Size) {
1094 int64_t Val;
1095 if (Value->evaluateAsAbsolute(Val))
1096 OutStreamer->emitIntValue(static_cast<uint64_t>(Val), Size);
1097 else
1098 OutStreamer->emitValue(Value, Size);
1099 };
1100
1103
1104 EmitResolvedOrExpr(CurrentProgramInfo.getComputePGMRSrc1(STM, Ctx),
1105 /*Size=*/4);
1106
1108 EmitResolvedOrExpr(CurrentProgramInfo.getComputePGMRSrc2(Ctx), /*Size=*/4);
1109
1111
1112 // Sets bits according to S_0286E8_WAVESIZE_* mask and shift values for the
1113 // appropriate generation.
1114 if (STM.getGeneration() >= AMDGPUSubtarget::GFX12) {
1115 EmitResolvedOrExpr(SetBits(CurrentProgramInfo.ScratchBlocks,
1116 /*Mask=*/0x3FFFF, /*Shift=*/12),
1117 /*Size=*/4);
1118 } else if (STM.getGeneration() == AMDGPUSubtarget::GFX11) {
1119 EmitResolvedOrExpr(SetBits(CurrentProgramInfo.ScratchBlocks,
1120 /*Mask=*/0x7FFF, /*Shift=*/12),
1121 /*Size=*/4);
1122 } else {
1123 EmitResolvedOrExpr(SetBits(CurrentProgramInfo.ScratchBlocks,
1124 /*Mask=*/0x1FFF, /*Shift=*/12),
1125 /*Size=*/4);
1126 }
1127
1128 // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
1129 // 0" comment but I don't see a corresponding field in the register spec.
1130 } else {
1131 OutStreamer->emitInt32(RsrcReg);
1132
1133 const MCExpr *GPRBlocks = MCBinaryExpr::createOr(
1134 SetBits(CurrentProgramInfo.VGPRBlocks, /*Mask=*/0x3F, /*Shift=*/0),
1135 SetBits(CurrentProgramInfo.SGPRBlocks, /*Mask=*/0x0F, /*Shift=*/6),
1136 MF.getContext());
1137 EmitResolvedOrExpr(GPRBlocks, /*Size=*/4);
1139
1140 // Sets bits according to S_0286E8_WAVESIZE_* mask and shift values for the
1141 // appropriate generation.
1142 if (STM.getGeneration() >= AMDGPUSubtarget::GFX12) {
1143 EmitResolvedOrExpr(SetBits(CurrentProgramInfo.ScratchBlocks,
1144 /*Mask=*/0x3FFFF, /*Shift=*/12),
1145 /*Size=*/4);
1146 } else if (STM.getGeneration() == AMDGPUSubtarget::GFX11) {
1147 EmitResolvedOrExpr(SetBits(CurrentProgramInfo.ScratchBlocks,
1148 /*Mask=*/0x7FFF, /*Shift=*/12),
1149 /*Size=*/4);
1150 } else {
1151 EmitResolvedOrExpr(SetBits(CurrentProgramInfo.ScratchBlocks,
1152 /*Mask=*/0x1FFF, /*Shift=*/12),
1153 /*Size=*/4);
1154 }
1155 }
1156
1159 unsigned ExtraLDSSize = STM.getGeneration() >= AMDGPUSubtarget::GFX11
1160 ? divideCeil(CurrentProgramInfo.LDSBlocks, 2)
1161 : CurrentProgramInfo.LDSBlocks;
1162 OutStreamer->emitInt32(S_00B02C_EXTRA_LDS_SIZE(ExtraLDSSize));
1164 OutStreamer->emitInt32(MFI->getPSInputEnable());
1166 OutStreamer->emitInt32(MFI->getPSInputAddr());
1167 }
1168
1169 OutStreamer->emitInt32(R_SPILLED_SGPRS);
1170 OutStreamer->emitInt32(MFI->getNumSpilledSGPRs());
1171 OutStreamer->emitInt32(R_SPILLED_VGPRS);
1172 OutStreamer->emitInt32(MFI->getNumSpilledVGPRs());
1173}
1174
1175// Helper function to add common PAL Metadata 3.0+
1177 const SIProgramInfo &CurrentProgramInfo,
1178 CallingConv::ID CC, const GCNSubtarget &ST) {
1179 if (ST.hasIEEEMode())
1180 MD->setHwStage(CC, ".ieee_mode", (bool)CurrentProgramInfo.IEEEMode);
1181
1182 MD->setHwStage(CC, ".wgp_mode", (bool)CurrentProgramInfo.WgpMode);
1183 MD->setHwStage(CC, ".mem_ordered", (bool)CurrentProgramInfo.MemOrdered);
1184
1185 if (AMDGPU::isCompute(CC)) {
1186 MD->setHwStage(CC, ".trap_present",
1187 (bool)CurrentProgramInfo.TrapHandlerEnable);
1188 MD->setHwStage(CC, ".excp_en", CurrentProgramInfo.EXCPEnable);
1189 }
1190
1191 MD->setHwStage(CC, ".lds_size",
1192 (unsigned)(CurrentProgramInfo.LdsSize *
1193 getLdsDwGranularity(ST) * sizeof(uint32_t)));
1194}
1195
1196// This is the equivalent of EmitProgramInfoSI above, but for when the OS type
1197// is AMDPAL. It stores each compute/SPI register setting and other PAL
1198// metadata items into the PALMD::Metadata, combining with any provided by the
1199// frontend as LLVM metadata. Once all functions are written, the PAL metadata
1200// is then written as a single block in the .note section.
1201void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
1202 const SIProgramInfo &CurrentProgramInfo) {
1204 auto CC = MF.getFunction().getCallingConv();
1205 auto MD = getTargetStreamer()->getPALMetadata();
1206 auto &Ctx = MF.getContext();
1207
1208 MD->setEntryPoint(CC, MF.getFunction().getName());
1209 MD->setNumUsedVgprs(
1210 CC, getMCExprValue(CurrentProgramInfo.NumVGPRsForWavesPerEU, Ctx));
1211
1212 // Only set AGPRs for supported devices
1213 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1214 if (STM.hasMAIInsts()) {
1215 MD->setNumUsedAgprs(CC, getMCExprValue(CurrentProgramInfo.NumAccVGPR, Ctx));
1216 }
1217
1218 MD->setNumUsedSgprs(
1219 CC, getMCExprValue(CurrentProgramInfo.NumSGPRsForWavesPerEU, Ctx));
1220 if (MD->getPALMajorVersion() < 3) {
1221 MD->setRsrc1(CC, CurrentProgramInfo.getPGMRSrc1(CC, STM));
1222 if (AMDGPU::isCompute(CC)) {
1223 MD->setRsrc2(CC, CurrentProgramInfo.getComputePGMRSrc2());
1224 } else {
1225 if (getMCExprValue(CurrentProgramInfo.ScratchBlocks, Ctx) > 0)
1226 MD->setRsrc2(CC, S_00B84C_SCRATCH_EN(1));
1227 }
1228 } else {
1229 MD->setHwStage(CC, ".debug_mode", (bool)CurrentProgramInfo.DebugMode);
1230 MD->setHwStage(CC, ".scratch_en",
1231 (bool)getMCExprValue(CurrentProgramInfo.ScratchEnable, Ctx));
1232 EmitPALMetadataCommon(MD, CurrentProgramInfo, CC, STM);
1233 }
1234
1235 // ScratchSize is in bytes, 16 aligned.
1236 MD->setScratchSize(
1237 CC, alignTo(getMCExprValue(CurrentProgramInfo.ScratchSize, Ctx), 16));
1239 unsigned ExtraLDSSize = STM.getGeneration() >= AMDGPUSubtarget::GFX11
1240 ? divideCeil(CurrentProgramInfo.LDSBlocks, 2)
1241 : CurrentProgramInfo.LDSBlocks;
1242 if (MD->getPALMajorVersion() < 3) {
1243 MD->setRsrc2(CC, S_00B02C_EXTRA_LDS_SIZE(ExtraLDSSize));
1244 MD->setSpiPsInputEna(MFI->getPSInputEnable());
1245 MD->setSpiPsInputAddr(MFI->getPSInputAddr());
1246 } else {
1247 // Graphics registers
1248 const unsigned ExtraLdsDwGranularity =
1249 STM.getGeneration() >= AMDGPUSubtarget::GFX11 ? 256 : 128;
1250 MD->setGraphicsRegisters(
1251 ".ps_extra_lds_size",
1252 (unsigned)(ExtraLDSSize * ExtraLdsDwGranularity * sizeof(uint32_t)));
1253
1254 // Set PsInputEna and PsInputAddr .spi_ps_input_ena and .spi_ps_input_addr
1255 static StringLiteral const PsInputFields[] = {
1256 ".persp_sample_ena", ".persp_center_ena",
1257 ".persp_centroid_ena", ".persp_pull_model_ena",
1258 ".linear_sample_ena", ".linear_center_ena",
1259 ".linear_centroid_ena", ".line_stipple_tex_ena",
1260 ".pos_x_float_ena", ".pos_y_float_ena",
1261 ".pos_z_float_ena", ".pos_w_float_ena",
1262 ".front_face_ena", ".ancillary_ena",
1263 ".sample_coverage_ena", ".pos_fixed_pt_ena"};
1264 unsigned PSInputEna = MFI->getPSInputEnable();
1265 unsigned PSInputAddr = MFI->getPSInputAddr();
1266 for (auto [Idx, Field] : enumerate(PsInputFields)) {
1267 MD->setGraphicsRegisters(".spi_ps_input_ena", Field,
1268 (bool)((PSInputEna >> Idx) & 1));
1269 MD->setGraphicsRegisters(".spi_ps_input_addr", Field,
1270 (bool)((PSInputAddr >> Idx) & 1));
1271 }
1272 }
1273 }
1274
1275 // For version 3 and above the wave front size is already set in the metadata
1276 if (MD->getPALMajorVersion() < 3 && STM.isWave32())
1277 MD->setWave32(MF.getFunction().getCallingConv());
1278}
1279
1280void AMDGPUAsmPrinter::emitPALFunctionMetadata(const MachineFunction &MF) {
1281 auto *MD = getTargetStreamer()->getPALMetadata();
1282 const MachineFrameInfo &MFI = MF.getFrameInfo();
1283 StringRef FnName = MF.getFunction().getName();
1284 MD->setFunctionScratchSize(FnName, MFI.getStackSize());
1286 MCContext &Ctx = MF.getContext();
1287
1288 if (MD->getPALMajorVersion() < 3) {
1289 // Set compute registers
1290 MD->setRsrc1(CallingConv::AMDGPU_CS,
1291 CurrentProgramInfo.getPGMRSrc1(CallingConv::AMDGPU_CS, ST));
1292 MD->setRsrc2(CallingConv::AMDGPU_CS,
1293 CurrentProgramInfo.getComputePGMRSrc2());
1294 } else {
1295 EmitPALMetadataCommon(MD, CurrentProgramInfo, CallingConv::AMDGPU_CS, ST);
1296 }
1297
1298 // Set optional info
1299 MD->setFunctionLdsSize(FnName, CurrentProgramInfo.LDSSize);
1300 MD->setFunctionNumUsedVgprs(
1301 FnName, getMCExprValue(CurrentProgramInfo.NumVGPRsForWavesPerEU, Ctx));
1302 MD->setFunctionNumUsedSgprs(
1303 FnName, getMCExprValue(CurrentProgramInfo.NumSGPRsForWavesPerEU, Ctx));
1304}
1305
1306// This is supposed to be log2(Size)
1308 switch (Size) {
1309 case 4:
1310 return AMD_ELEMENT_4_BYTES;
1311 case 8:
1312 return AMD_ELEMENT_8_BYTES;
1313 case 16:
1314 return AMD_ELEMENT_16_BYTES;
1315 default:
1316 llvm_unreachable("invalid private_element_size");
1317 }
1318}
1319
1320void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
1321 const SIProgramInfo &CurrentProgramInfo,
1322 const MachineFunction &MF) const {
1323 const Function &F = MF.getFunction();
1324 assert(F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
1325 F.getCallingConv() == CallingConv::SPIR_KERNEL);
1326
1328 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1329 MCContext &Ctx = MF.getContext();
1330
1332
1334 CurrentProgramInfo.getComputePGMRSrc1(STM) |
1335 (CurrentProgramInfo.getComputePGMRSrc2() << 32);
1337
1338 if (getMCExprValue(CurrentProgramInfo.DynamicCallStack, Ctx))
1340
1343 getElementByteSizeValue(STM.getMaxPrivateElementSize(true)));
1344
1345 const GCNUserSGPRUsageInfo &UserSGPRInfo = MFI->getUserSGPRInfo();
1346 if (UserSGPRInfo.hasPrivateSegmentBuffer()) {
1347 Out.code_properties |=
1349 }
1350
1351 if (UserSGPRInfo.hasDispatchPtr())
1353
1354 if (UserSGPRInfo.hasQueuePtr() && CodeObjectVersion < AMDGPU::AMDHSA_COV5)
1356
1357 if (UserSGPRInfo.hasKernargSegmentPtr())
1359
1360 if (UserSGPRInfo.hasDispatchID())
1362
1363 if (UserSGPRInfo.hasFlatScratchInit())
1365
1366 if (UserSGPRInfo.hasDispatchPtr())
1368
1369 if (STM.isXNACKEnabled())
1371
1372 Align MaxKernArgAlign;
1373 Out.kernarg_segment_byte_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign);
1374 Out.wavefront_sgpr_count = getMCExprValue(CurrentProgramInfo.NumSGPR, Ctx);
1375 Out.workitem_vgpr_count = getMCExprValue(CurrentProgramInfo.NumVGPR, Ctx);
1377 getMCExprValue(CurrentProgramInfo.ScratchSize, Ctx);
1378 Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1379
1380 // kernarg_segment_alignment is specified as log of the alignment.
1381 // The minimum alignment is 16.
1382 // FIXME: The metadata treats the minimum as 4?
1383 Out.kernarg_segment_alignment = Log2(std::max(Align(16), MaxKernArgAlign));
1384}
1385
1387 const char *ExtraCode, raw_ostream &O) {
1388 // First try the generic code, which knows about modifiers like 'c' and 'n'.
1389 if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O))
1390 return false;
1391
1392 if (ExtraCode && ExtraCode[0]) {
1393 if (ExtraCode[1] != 0)
1394 return true; // Unknown modifier.
1395
1396 switch (ExtraCode[0]) {
1397 case 'r':
1398 break;
1399 default:
1400 return true;
1401 }
1402 }
1403
1404 // TODO: Should be able to support other operand types like globals.
1405 const MachineOperand &MO = MI->getOperand(OpNo);
1406 if (MO.isReg()) {
1409 return false;
1410 } else if (MO.isImm()) {
1411 int64_t Val = MO.getImm();
1413 O << Val;
1414 } else if (isUInt<16>(Val)) {
1415 O << format("0x%" PRIx16, static_cast<uint16_t>(Val));
1416 } else if (isUInt<32>(Val)) {
1417 O << format("0x%" PRIx32, static_cast<uint32_t>(Val));
1418 } else {
1419 O << format("0x%" PRIx64, static_cast<uint64_t>(Val));
1420 }
1421 return false;
1422 }
1423 return true;
1424}
1425
1430}
1431
1432void AMDGPUAsmPrinter::emitResourceUsageRemarks(
1433 const MachineFunction &MF, const SIProgramInfo &CurrentProgramInfo,
1434 bool isModuleEntryFunction, bool hasMAIInsts) {
1435 if (!ORE)
1436 return;
1437
1438 const char *Name = "kernel-resource-usage";
1439 const char *Indent = " ";
1440
1441 // If the remark is not specifically enabled, do not output to yaml
1444 return;
1445
1446 auto EmitResourceUsageRemark = [&](StringRef RemarkName,
1447 StringRef RemarkLabel, auto Argument) {
1448 // Add an indent for every line besides the line with the kernel name. This
1449 // makes it easier to tell which resource usage go with which kernel since
1450 // the kernel name will always be displayed first.
1451 std::string LabelStr = RemarkLabel.str() + ": ";
1452 if (RemarkName != "FunctionName")
1453 LabelStr = Indent + LabelStr;
1454
1455 ORE->emit([&]() {
1456 return MachineOptimizationRemarkAnalysis(Name, RemarkName,
1458 &MF.front())
1459 << LabelStr << ore::NV(RemarkName, Argument);
1460 });
1461 };
1462
1463 // FIXME: Formatting here is pretty nasty because clang does not accept
1464 // newlines from diagnostics. This forces us to emit multiple diagnostic
1465 // remarks to simulate newlines. If and when clang does accept newlines, this
1466 // formatting should be aggregated into one remark with newlines to avoid
1467 // printing multiple diagnostic location and diag opts.
1468 MCContext &MCCtx = MF.getContext();
1469 EmitResourceUsageRemark("FunctionName", "Function Name",
1470 MF.getFunction().getName());
1471 EmitResourceUsageRemark("NumSGPR", "SGPRs",
1472 getMCExprValue(CurrentProgramInfo.NumSGPR, MCCtx));
1473 EmitResourceUsageRemark(
1474 "NumVGPR", "VGPRs",
1475 getMCExprValue(CurrentProgramInfo.NumArchVGPR, MCCtx));
1476 if (hasMAIInsts) {
1477 EmitResourceUsageRemark(
1478 "NumAGPR", "AGPRs",
1479 getMCExprValue(CurrentProgramInfo.NumAccVGPR, MCCtx));
1480 }
1481 EmitResourceUsageRemark(
1482 "ScratchSize", "ScratchSize [bytes/lane]",
1483 getMCExprValue(CurrentProgramInfo.ScratchSize, MCCtx));
1484 StringRef DynamicStackStr =
1485 getMCExprValue(CurrentProgramInfo.DynamicCallStack, MCCtx) ? "True"
1486 : "False";
1487 EmitResourceUsageRemark("DynamicStack", "Dynamic Stack", DynamicStackStr);
1488 EmitResourceUsageRemark("Occupancy", "Occupancy [waves/SIMD]",
1489 getMCExprValue(CurrentProgramInfo.Occupancy, MCCtx));
1490 EmitResourceUsageRemark("SGPRSpill", "SGPRs Spill",
1491 CurrentProgramInfo.SGPRSpill);
1492 EmitResourceUsageRemark("VGPRSpill", "VGPRs Spill",
1493 CurrentProgramInfo.VGPRSpill);
1494 if (isModuleEntryFunction)
1495 EmitResourceUsageRemark("BytesLDS", "LDS Size [bytes/block]",
1496 CurrentProgramInfo.LDSSize);
1497}
#define Success
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUAsmPrinter()
static void EmitPALMetadataCommon(AMDGPUPALMetadata *MD, const SIProgramInfo &CurrentProgramInfo, CallingConv::ID CC, const GCNSubtarget &ST)
static unsigned getRsrcReg(CallingConv::ID CallConv)
static amd_element_byte_size_t getElementByteSizeValue(unsigned Size)
static uint32_t getFPMode(SIModeRegisterDefaults Mode)
static AsmPrinter * createAMDGPUAsmPrinterPass(TargetMachine &tm, std::unique_ptr< MCStreamer > &&Streamer)
AMDGPU Assembly printer class.
AMDGPU HSA Metadata Streamer.
AMDHSA kernel descriptor MCExpr struct for use in MC layer.
Analyzes how many registers and other resources are used by functions.
AMDHSA kernel descriptor definitions.
#define AMDHSA_BITS_GET(SRC, MSK)
amd_element_byte_size_t
The values used to define the number of bytes to use for the swizzle element size.
@ AMD_ELEMENT_8_BYTES
@ AMD_ELEMENT_16_BYTES
@ AMD_ELEMENT_4_BYTES
#define AMD_HSA_BITS_SET(dst, mask, val)
@ AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID
@ AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE
@ AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR
@ AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR
@ AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER
@ AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR
@ AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED
@ AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT
@ AMD_CODE_PROPERTY_IS_PTR64
@ AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
std::string Name
uint64_t Size
AMD GCN specific subclass of TargetSubtarget.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
LLVMContext & Context
if(VerifyEach)
const char LLVMTargetMachineRef TM
R600 Assembly printer class.
#define R_00B028_SPI_SHADER_PGM_RSRC1_PS
Definition: SIDefines.h:1046
#define R_0286E8_SPI_TMPRING_SIZE
Definition: SIDefines.h:1184
#define S_00B84C_SCRATCH_EN(x)
Definition: SIDefines.h:1080
#define FP_ROUND_MODE_DP(x)
Definition: SIDefines.h:1166
#define FP_ROUND_ROUND_TO_NEAREST
Definition: SIDefines.h:1158
#define R_0286D0_SPI_PS_INPUT_ADDR
Definition: SIDefines.h:1117
#define R_00B860_COMPUTE_TMPRING_SIZE
Definition: SIDefines.h:1179
#define R_00B428_SPI_SHADER_PGM_RSRC1_HS
Definition: SIDefines.h:1069
#define R_00B328_SPI_SHADER_PGM_RSRC1_ES
Definition: SIDefines.h:1068
#define R_00B528_SPI_SHADER_PGM_RSRC1_LS
Definition: SIDefines.h:1077
#define R_0286CC_SPI_PS_INPUT_ENA
Definition: SIDefines.h:1116
#define R_00B128_SPI_SHADER_PGM_RSRC1_VS
Definition: SIDefines.h:1055
#define FP_DENORM_MODE_DP(x)
Definition: SIDefines.h:1177
#define R_00B848_COMPUTE_PGM_RSRC1
Definition: SIDefines.h:1119
#define R_SPILLED_SGPRS
Definition: SIDefines.h:1198
#define FP_ROUND_MODE_SP(x)
Definition: SIDefines.h:1165
#define FP_DENORM_MODE_SP(x)
Definition: SIDefines.h:1176
#define R_00B228_SPI_SHADER_PGM_RSRC1_GS
Definition: SIDefines.h:1060
#define R_SPILLED_VGPRS
Definition: SIDefines.h:1199
#define S_00B02C_EXTRA_LDS_SIZE(x)
Definition: SIDefines.h:1054
#define R_00B84C_COMPUTE_PGM_RSRC2
Definition: SIDefines.h:1079
#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS
Definition: SIDefines.h:1053
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
void emitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
const MCSubtargetInfo * getGlobalSTI() const
void emitImplicitDef(const MachineInstr *MI) const override
Targets can override this to customize the output of IMPLICIT_DEF instructions in verbose mode.
std::vector< std::string > DisasmLines
void emitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
std::vector< std::string > HexLines
void emitGlobalVariable(const GlobalVariable *GV) override
Emit the specified global variable to the .s file.
void getAnalysisUsage(AnalysisUsage &AU) const override
Record analysis usage.
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
bool runOnMachineFunction(MachineFunction &MF) override
Emit the specified function out to the OutStreamer.
void emitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
bool doFinalization(Module &M) override
Shut down the asmprinter.
void emitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
AMDGPUAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
bool doInitialization(Module &M) override
Set up the AsmPrinter when we are working on a new module.
void emitFunctionBodyStart() override
Targets can override this to emit stuff before the first basic block in the function.
void emitBasicBlockStart(const MachineBasicBlock &MBB) override
Targets can override this to emit stuff at the start of a basic block.
AMDGPUTargetStreamer * getTargetStreamer() const
static void printRegOperand(unsigned RegNo, raw_ostream &O, const MCRegisterInfo &MRI)
void setHwStage(unsigned CC, StringRef field, unsigned Val)
unsigned getAddressableLocalMemorySize() const
unsigned getKernArgSegmentSize(const Function &F, Align &MaxAlign) const
unsigned getWavefrontSize() const
AMDGPUPALMetadata * getPALMetadata()
virtual void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV)
void initializeTargetID(const MCSubtargetInfo &STI)
virtual void EmitAMDKernelCodeT(const amd_kernel_code_t &Header)
virtual bool EmitCodeEnd(const MCSubtargetInfo &STI)
virtual void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type)
virtual void EmitDirectiveAMDGCNTarget()
virtual void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const AMDGPU::MCKernelDescriptor &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr)
const std::optional< AMDGPU::IsaInfo::AMDGPUTargetID > & getTargetID() const
virtual bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI, bool TrapEnabled)
static const AMDGPUVariadicMCExpr * createMax(ArrayRef< const MCExpr * > Args, MCContext &Ctx)
Definition: AMDGPUMCExpr.h:70
static const AMDGPUVariadicMCExpr * createAlignTo(const MCExpr *Value, const MCExpr *Align, MCContext &Ctx)
Definition: AMDGPUMCExpr.h:85
static const AMDGPUVariadicMCExpr * createTotalNumVGPR(const MCExpr *NumAGPR, const MCExpr *NumVGPR, MCContext &Ctx)
static const AMDGPUVariadicMCExpr * createOccupancy(unsigned InitOcc, const MCExpr *NumSGPRs, const MCExpr *NumVGPRs, const GCNSubtarget &STM, MCContext &Ctx)
Mimics GCNSubtarget::computeOccupancy for MCExpr.
static const AMDGPUVariadicMCExpr * createExtraSGPRs(const MCExpr *VCCUsed, const MCExpr *FlatScrUsed, bool XNACKUsed, MCContext &Ctx)
Allow delayed MCExpr resolve of ExtraSGPRs (in case VCCUsed or FlatScrUsed are unresolvable but neede...
void setXnackSetting(TargetIDSetting NewXnackSetting)
Sets xnack setting to NewXnackSetting.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
This class represents an incoming formal argument to a Function.
Definition: Argument.h:31
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:84
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
Definition: AsmPrinter.cpp:399
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:704
virtual void emitGlobalVariable(const GlobalVariable *GV)
Emit the specified global variable to the .s file.
Definition: AsmPrinter.cpp:726
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:87
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:102
virtual void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
void emitFunctionBody()
This method emits the body and trailer for a function.
virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
bool doInitialization(Module &M) override
Set up the AsmPrinter when we are working on a new module.
Definition: AsmPrinter.cpp:450
virtual void emitLinkage(const GlobalValue *GV, MCSymbol *GVSym) const
This emits linkage information about GVSym based on GV, if this is supported by the target.
Definition: AsmPrinter.cpp:659
void getAnalysisUsage(AnalysisUsage &AU) const override
Record analysis usage.
Definition: AsmPrinter.cpp:441
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:395
MachineOptimizationRemarkEmitter * ORE
Optimization remark emitter.
Definition: AsmPrinter.h:114
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:94
bool doFinalization(Module &M) override
Shut down the asmprinter.
virtual void emitBasicBlockStart(const MachineBasicBlock &MBB)
Targets can override this to emit stuff at the start of a basic block.
void emitVisibility(MCSymbol *Sym, unsigned Visibility, bool IsDefinition=true) const
This emits visibility information about symbol, if this is supported by the target.
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:99
bool isVerbose() const
Return true if assembly output should contain comments.
Definition: AsmPrinter.h:265
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:699
virtual void emitFunctionEntryLabel()
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
Diagnostic information for optimization failures.
Diagnostic information for stack size etc.
DISubprogram * getSubprogram() const
Get the attached subprogram.
Definition: Metadata.cpp:1830
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:264
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:356
unsigned getMinNumSGPRs(unsigned WavesPerEU) const
bool hasGFX90AInsts() const
unsigned computeOccupancy(const Function &F, unsigned LDSSize=0, unsigned NumSGPRs=0, unsigned NumVGPRs=0) const
Return occupancy for the given function.
bool hasMAIInsts() const
Definition: GCNSubtarget.h:809
const SIInstrInfo * getInstrInfo() const override
Definition: GCNSubtarget.h:257
bool hasSGPRInitBug() const
bool isTgSplitEnabled() const
Definition: GCNSubtarget.h:600
unsigned getMinNumVGPRs(unsigned WavesPerEU) const
bool isCuModeEnabled() const
Definition: GCNSubtarget.h:604
const AMDGPU::IsaInfo::AMDGPUTargetID & getTargetID() const
Definition: GCNSubtarget.h:293
bool dumpCode() const
Definition: GCNSubtarget.h:504
bool isTrapHandlerEnabled() const
Definition: GCNSubtarget.h:592
bool isWave32() const
unsigned getMaxNumUserSGPRs() const
Definition: GCNSubtarget.h:936
Generation getGeneration() const
Definition: GCNSubtarget.h:308
unsigned getAddressableNumSGPRs() const
unsigned getMaxWaveScratchSize() const
Definition: GCNSubtarget.h:312
bool hasKernargSegmentPtr() const
bool hasPrivateSegmentBuffer() const
MaybeAlign getAlign() const
Returns the alignment of the given variable or function.
Definition: GlobalObject.h:80
VisibilityTypes getVisibility() const
Definition: GlobalValue.h:247
bool isDeclaration() const
Return true if the primary definition of this global value is outside of the current translation unit...
Definition: Globals.cpp:286
unsigned getAddressSpace() const
Definition: GlobalValue.h:204
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:655
Type * getValueType() const
Definition: GlobalValue.h:295
const Constant * getInitializer() const
getInitializer - Return the initializer for this global variable.
bool hasInitializer() const
Definitions have initializers, declarations don't.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
const DiagnosticHandler * getDiagHandlerPtr() const
getDiagHandlerPtr - Returns const raw pointer of DiagnosticHandler set by setDiagnosticHandler.
MCCodeEmitter * getEmitterPtr() const
Definition: MCAssembler.h:330
static const MCBinaryExpr * createAnd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:541
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:536
static const MCBinaryExpr * createOr(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:601
static const MCBinaryExpr * createLOr(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:571
static const MCBinaryExpr * createMul(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:591
static const MCBinaryExpr * createGT(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:556
static const MCBinaryExpr * createDiv(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:546
static const MCBinaryExpr * createShl(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:606
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:621
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
Context object for machine code objects.
Definition: MCContext.h:81
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1073
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
MCContext & getContext() const
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:26
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
bool isDefined() const
isDefined - Check if this symbol is defined (i.e., it has an address).
Definition: MCSymbol.h:250
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:205
bool isVariable() const
isVariable - Check if this is a variable symbol.
Definition: MCSymbol.h:300
void redefineIfPossible()
Prepare this symbol to be redefined.
Definition: MCSymbol.h:232
MCStreamer & getStreamer()
Definition: MCStreamer.h:101
static const MCUnaryExpr * createNot(const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition: MCExpr.h:466
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
void setAlignment(Align A)
setAlignment - Set the alignment of the function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MCContext & getContext() const
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Register getReg() const
getReg - Returns the register number.
Diagnostic information for optimization analysis remarks.
void emit(DiagnosticInfoOptimizationBase &OptDiag)
Emit an optimization remark.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Definition: Module.h:293
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
GCNUserSGPRUsageInfo & getUserSGPRInfo()
SIModeRegisterDefaults getMode() const
unsigned getNumKernargPreloadedSGPRs() const
Represents a location in source code.
Definition: SMLoc.h:23
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:846
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:223
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
const Triple & getTargetTriple() const
const MCSubtargetInfo * getMCSubtargetInfo() const
const STC & getSubtarget(const Function &F) const
This method returns a pointer to the specified type of TargetSubtargetInfo.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:382
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
LLVM Value Representation.
Definition: Value.h:74
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:309
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:690
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ LOCAL_ADDRESS
Address space for local memory.
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
unsigned getLdsDwGranularity(const MCSubtargetInfo &ST)
IsaVersion getIsaVersion(StringRef GPU)
bool isCompute(CallingConv::ID cc)
unsigned getAMDHSACodeObjectVersion(const Module &M)
bool isGFX90A(const MCSubtargetInfo &STI)
bool hasMAIInsts(const MCSubtargetInfo &STI)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
bool isShader(CallingConv::ID cc)
bool isGFX10Plus(const MCSubtargetInfo &STI)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
std::pair< unsigned, unsigned > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:121
@ AMDGPU_CS
Used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:197
@ AMDGPU_VS
Used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (vertex shader if tess...
Definition: CallingConv.h:188
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
Definition: CallingConv.h:200
@ AMDGPU_HS
Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:206
@ AMDGPU_GS
Used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:191
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:194
@ SPIR_KERNEL
Used for SPIR kernel functions.
Definition: CallingConv.h:144
@ AMDGPU_ES
Used for AMDPAL shader stage before geometry shader if geometry is in use.
Definition: CallingConv.h:218
@ AMDGPU_LS
Used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:213
@ SHT_PROGBITS
Definition: ELF.h:1063
@ STT_AMDGPU_HSA_KERNEL
Definition: ELF.h:1336
DiagnosticInfoOptimizationBase::Argument NV
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1680
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
Definition: MathExtras.h:428
auto enumerate(FirstRange &&First, RestRanges &&...Rest)
Given two or more input ranges, returns a new range whose values are are tuples (A,...
Definition: STLExtras.h:2406
static StringRef getCPU(StringRef CPU)
Processes a CPU name.
Target & getTheR600Target()
The target for R600 GPUs.
@ DK_ResourceLimit
AsmPrinter * createR600AsmPrinterPass(TargetMachine &TM, std::unique_ptr< MCStreamer > &&Streamer)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:324
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:125
Target & getTheGCNTarget()
The target for GCN GPUs.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1849
@ DS_Error
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:208
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
AMD Kernel Code Object (amd_kernel_code_t).
uint16_t workitem_vgpr_count
Number of vector registers used by each work-item.
uint32_t code_properties
Code properties.
uint8_t kernarg_segment_alignment
The maximum byte alignment of variables used by the kernel in the specified memory segment.
uint32_t workgroup_group_segment_byte_size
The amount of group segment memory required by a work-group in bytes.
uint16_t wavefront_sgpr_count
Number of scalar registers used by a wavefront.
uint32_t workitem_private_segment_byte_size
The amount of memory required for the combined private, spill and arg segments for a work-item in byt...
uint64_t kernarg_segment_byte_size
The size in bytes of the kernarg segment that holds the values of the arguments to the kernel.
uint64_t compute_pgm_resource_registers
Shader program settings for CS.
const SIFunctionResourceInfo & getResourceInfo(const Function *F) const
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
virtual bool isAnalysisRemarkEnabled(StringRef PassName) const
Return true if analysis remarks are enabled, override to provide different implementation.
Track resource usage for kernels / entry functions.
Definition: SIProgramInfo.h:31
const MCExpr * NumSGPR
Definition: SIProgramInfo.h:70
const MCExpr * ComputePGMRSrc3GFX90A
Definition: SIProgramInfo.h:63
const MCExpr * NumArchVGPR
Definition: SIProgramInfo.h:66
const MCExpr * VGPRBlocks
Definition: SIProgramInfo.h:33
const MCExpr * ScratchBlocks
Definition: SIProgramInfo.h:48
const MCExpr * VCCUsed
Definition: SIProgramInfo.h:90
uint64_t getComputePGMRSrc1(const GCNSubtarget &ST) const
Compute the value of the ComputePGMRsrc1 register.
const MCExpr * FlatUsed
Definition: SIProgramInfo.h:74
uint32_t TrapHandlerEnable
Definition: SIProgramInfo.h:53
const MCExpr * ScratchEnable
Definition: SIProgramInfo.h:51
uint64_t getComputePGMRSrc2() const
Compute the value of the ComputePGMRsrc2 register.
const MCExpr * AccumOffset
Definition: SIProgramInfo.h:68
const MCExpr * NumAccVGPR
Definition: SIProgramInfo.h:67
const MCExpr * DynamicCallStack
Definition: SIProgramInfo.h:87
const MCExpr * SGPRBlocks
Definition: SIProgramInfo.h:34
const MCExpr * NumVGPRsForWavesPerEU
Definition: SIProgramInfo.h:80
const MCExpr * NumVGPR
Definition: SIProgramInfo.h:65
const MCExpr * Occupancy
Definition: SIProgramInfo.h:83
const MCExpr * ScratchSize
Definition: SIProgramInfo.h:44
const MCExpr * NumSGPRsForWavesPerEU
Definition: SIProgramInfo.h:77
void reset(const MachineFunction &MF)
uint64_t getPGMRSrc1(CallingConv::ID CC, const GCNSubtarget &ST) const
static void RegisterAsmPrinter(Target &T, Target::AsmPrinterCtorTy Fn)
RegisterAsmPrinter - Register an AsmPrinter implementation for the given target.