LLVM 18.0.0git
X86DisassemblerDecoderCommon.h
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1//===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is part of the X86 Disassembler.
10// It contains common definitions used by both the disassembler and the table
11// generator.
12// Documentation for the disassembler can be found in X86Disassembler.h.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_SUPPORT_X86DISASSEMBLERDECODERCOMMON_H
17#define LLVM_SUPPORT_X86DISASSEMBLERDECODERCOMMON_H
18
19#include "llvm/Support/DataTypes.h"
20
21namespace llvm {
22namespace X86Disassembler {
23
24#define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers
25#define CONTEXTS_SYM x86DisassemblerContexts
26#define ONEBYTE_SYM x86DisassemblerOneByteOpcodes
27#define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes
28#define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes
29#define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes
30#define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes
31#define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes
32#define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes
33#define THREEDNOW_MAP_SYM x86Disassembler3DNowOpcodes
34#define MAP4_SYM x86DisassemblerMap4Opcodes
35#define MAP5_SYM x86DisassemblerMap5Opcodes
36#define MAP6_SYM x86DisassemblerMap6Opcodes
37#define MAP7_SYM x86DisassemblerMap7Opcodes
38
39#define INSTRUCTIONS_STR "x86DisassemblerInstrSpecifiers"
40#define CONTEXTS_STR "x86DisassemblerContexts"
41#define ONEBYTE_STR "x86DisassemblerOneByteOpcodes"
42#define TWOBYTE_STR "x86DisassemblerTwoByteOpcodes"
43#define THREEBYTE38_STR "x86DisassemblerThreeByte38Opcodes"
44#define THREEBYTE3A_STR "x86DisassemblerThreeByte3AOpcodes"
45#define XOP8_MAP_STR "x86DisassemblerXOP8Opcodes"
46#define XOP9_MAP_STR "x86DisassemblerXOP9Opcodes"
47#define XOPA_MAP_STR "x86DisassemblerXOPAOpcodes"
48#define THREEDNOW_MAP_STR "x86Disassembler3DNowOpcodes"
49#define MAP4_STR "x86DisassemblerMap4Opcodes"
50#define MAP5_STR "x86DisassemblerMap5Opcodes"
51#define MAP6_STR "x86DisassemblerMap6Opcodes"
52#define MAP7_STR "x86DisassemblerMap7Opcodes"
53
54// Attributes of an instruction that must be known before the opcode can be
55// processed correctly. Most of these indicate the presence of particular
56// prefixes, but ATTR_64BIT is simply an attribute of the decoding context.
57enum attributeBits {
58 ATTR_NONE = 0x00,
59 ATTR_64BIT = 0x1 << 0,
60 ATTR_XS = 0x1 << 1,
61 ATTR_XD = 0x1 << 2,
62 ATTR_REXW = 0x1 << 3,
63 ATTR_OPSIZE = 0x1 << 4,
64 ATTR_ADSIZE = 0x1 << 5,
65 ATTR_VEX = 0x1 << 6,
66 ATTR_VEXL = 0x1 << 7,
67 ATTR_EVEX = 0x1 << 8,
68 ATTR_EVEXL2 = 0x1 << 9,
69 ATTR_EVEXK = 0x1 << 10,
70 ATTR_EVEXKZ = 0x1 << 11,
71 ATTR_EVEXB = 0x1 << 12,
72 ATTR_REX2 = 0x1 << 13,
73 ATTR_max = 0x1 << 14,
74};
75
76// Combinations of the above attributes that are relevant to instruction
77// decode. Although other combinations are possible, they can be reduced to
78// these without affecting the ultimately decoded instruction.
79
80// Class name Rank Rationale for rank assignment
81#define INSTRUCTION_CONTEXTS \
82 ENUM_ENTRY(IC, 0, "says nothing about the instruction") \
83 ENUM_ENTRY(IC_64BIT, 1, \
84 "says the instruction applies in 64-bit mode but no more") \
85 ENUM_ENTRY(IC_OPSIZE, 3, \
86 "requires an OPSIZE prefix, so operands change width") \
87 ENUM_ENTRY(IC_ADSIZE, 3, \
88 "requires an ADSIZE prefix, so operands change width") \
89 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
90 ENUM_ENTRY(IC_XD, 2, \
91 "may say something about the opcode but not the operands") \
92 ENUM_ENTRY(IC_XS, 2, \
93 "may say something about the opcode but not the operands") \
94 ENUM_ENTRY(IC_XD_OPSIZE, 3, \
95 "requires an OPSIZE prefix, so operands change width") \
96 ENUM_ENTRY(IC_XS_OPSIZE, 3, \
97 "requires an OPSIZE prefix, so operands change width") \
98 ENUM_ENTRY(IC_XD_ADSIZE, 3, \
99 "requires an ADSIZE prefix, so operands change width") \
100 ENUM_ENTRY(IC_XS_ADSIZE, 3, \
101 "requires an ADSIZE prefix, so operands change width") \
102 ENUM_ENTRY(IC_64BIT_REXW, 5, \
103 "requires a REX.W prefix, so operands change width; overrides " \
104 "IC_OPSIZE") \
105 ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, \
106 "requires a REX.W prefix and 0x67 prefix") \
107 ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \
108 ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \
109 ENUM_ENTRY(IC_64BIT_OPSIZE_ADSIZE, 4, \
110 "Just as meaningful as IC_OPSIZE/IC_ADSIZE") \
111 ENUM_ENTRY(IC_64BIT_XD, 6, "XD instructions are SSE; REX.W is secondary") \
112 ENUM_ENTRY(IC_64BIT_XS, 6, "Just as meaningful as IC_64BIT_XD") \
113 ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \
114 ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \
115 ENUM_ENTRY(IC_64BIT_XD_ADSIZE, 3, "Just as meaningful as IC_XD_ADSIZE") \
116 ENUM_ENTRY(IC_64BIT_XS_ADSIZE, 3, "Just as meaningful as IC_XS_ADSIZE") \
117 ENUM_ENTRY(IC_64BIT_REXW_XS, 7, "OPSIZE could mean a different opcode") \
118 ENUM_ENTRY(IC_64BIT_REXW_XD, 7, "Just as meaningful as IC_64BIT_REXW_XS") \
119 ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 8, \
120 "The Dynamic Duo! Prefer over all else because this changes " \
121 "most operands' meaning") \
122 ENUM_ENTRY(IC_64BIT_REX2, 2, "requires a REX2 prefix") \
123 ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \
124 ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \
125 ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \
126 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \
127 ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \
128 ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \
129 ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \
130 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \
131 ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \
132 ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix") \
133 ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix") \
134 ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \
135 ENUM_ENTRY(IC_VEX_L_W, 4, "requires VEX, L and W") \
136 ENUM_ENTRY(IC_VEX_L_W_XS, 5, "requires VEX, L, W and XS prefix") \
137 ENUM_ENTRY(IC_VEX_L_W_XD, 5, "requires VEX, L, W and XD prefix") \
138 ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize") \
139 ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \
140 ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
141 ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
142 ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
143 ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \
144 ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \
145 ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \
146 ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \
147 ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \
148 ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix") \
149 ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix") \
150 ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \
151 ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \
152 ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \
153 ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \
154 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \
155 ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \
156 ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix") \
157 ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix") \
158 ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \
159 ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \
160 ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \
161 ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \
162 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \
163 ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \
164 ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \
165 ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \
166 ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \
167 ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \
168 ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \
169 ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \
170 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \
171 ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \
172 ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix") \
173 ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix") \
174 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \
175 ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \
176 ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \
177 ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \
178 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \
179 ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \
180 ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix") \
181 ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix") \
182 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \
183 ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \
184 ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \
185 ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \
186 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \
187 ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \
188 ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \
189 ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \
190 ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \
191 ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \
192 ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \
193 ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \
194 ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \
195 ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \
196 ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix") \
197 ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix") \
198 ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \
199 ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \
200 ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \
201 ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \
202 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \
203 ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \
204 ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix") \
205 ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix") \
206 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \
207 ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \
208 ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \
209 ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \
210 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \
211 ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \
212 ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \
213 ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \
214 ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, \
215 "requires EVEX_B, EVEX_K and the OpSize prefix") \
216 ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \
217 ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \
218 ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \
219 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, \
220 "requires EVEX_B, EVEX_K, W, and OpSize") \
221 ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \
222 ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, \
223 "requires EVEX_B, EVEX_K and the L and XS prefix") \
224 ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, \
225 "requires EVEX_B, EVEX_K and the L and XD prefix") \
226 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, \
227 "requires EVEX_B, EVEX_K, L, and OpSize") \
228 ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \
229 ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, \
230 "requires EVEX_B, EVEX_K, L, W and XS prefix") \
231 ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, \
232 "requires EVEX_B, EVEX_K, L, W and XD prefix") \
233 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B, 4, \
234 "requires EVEX_B, EVEX_K, L, W and OpSize") \
235 ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \
236 ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, \
237 "requires EVEX_B, EVEX_K and the L2 and XS prefix") \
238 ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, \
239 "requires EVEX_B, EVEX_K and the L2 and XD prefix") \
240 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, \
241 "requires EVEX_B, EVEX_K, L2, and OpSize") \
242 ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \
243 ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, \
244 "requires EVEX_B, EVEX_K, L2, W and XS prefix") \
245 ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, \
246 "requires EVEX_B, EVEX_K, L2, W and XD prefix") \
247 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B, 4, \
248 "requires EVEX_B, EVEX_K, L2, W and OpSize") \
249 ENUM_ENTRY(IC_EVEX_KZ_B, 1, "requires EVEX_B and EVEX_KZ prefix") \
250 ENUM_ENTRY(IC_EVEX_XS_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XS prefix") \
251 ENUM_ENTRY(IC_EVEX_XD_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XD prefix") \
252 ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B, 2, \
253 "requires EVEX_B, EVEX_KZ and the OpSize prefix") \
254 ENUM_ENTRY(IC_EVEX_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the W prefix") \
255 ENUM_ENTRY(IC_EVEX_W_XS_KZ_B, 4, \
256 "requires EVEX_B, EVEX_KZ, W, and XS prefix") \
257 ENUM_ENTRY(IC_EVEX_W_XD_KZ_B, 4, \
258 "requires EVEX_B, EVEX_KZ, W, and XD prefix") \
259 ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B, 4, \
260 "requires EVEX_B, EVEX_KZ, W, and OpSize") \
261 ENUM_ENTRY(IC_EVEX_L_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L prefix") \
262 ENUM_ENTRY(IC_EVEX_L_XS_KZ_B, 4, \
263 "requires EVEX_B, EVEX_KZ and the L and XS prefix") \
264 ENUM_ENTRY(IC_EVEX_L_XD_KZ_B, 4, \
265 "requires EVEX_B, EVEX_KZ and the L and XD prefix") \
266 ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ_B, 4, \
267 "requires EVEX_B, EVEX_KZ, L, and OpSize") \
268 ENUM_ENTRY(IC_EVEX_L_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L and W") \
269 ENUM_ENTRY(IC_EVEX_L_W_XS_KZ_B, 4, \
270 "requires EVEX_B, EVEX_KZ, L, W and XS prefix") \
271 ENUM_ENTRY(IC_EVEX_L_W_XD_KZ_B, 4, \
272 "requires EVEX_B, EVEX_KZ, L, W and XD prefix") \
273 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ_B, 4, \
274 "requires EVEX_B, EVEX_KZ, L, W and OpSize") \
275 ENUM_ENTRY(IC_EVEX_L2_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L2 prefix") \
276 ENUM_ENTRY(IC_EVEX_L2_XS_KZ_B, 4, \
277 "requires EVEX_B, EVEX_KZ and the L2 and XS prefix") \
278 ENUM_ENTRY(IC_EVEX_L2_XD_KZ_B, 4, \
279 "requires EVEX_B, EVEX_KZ and the L2 and XD prefix") \
280 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ_B, 4, \
281 "requires EVEX_B, EVEX_KZ, L2, and OpSize") \
282 ENUM_ENTRY(IC_EVEX_L2_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L2 and W") \
283 ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ_B, 4, \
284 "requires EVEX_B, EVEX_KZ, L2, W and XS prefix") \
285 ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ_B, 4, \
286 "requires EVEX_B, EVEX_KZ, L2, W and XD prefix") \
287 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ_B, 4, \
288 "requires EVEX_B, EVEX_KZ, L2, W and OpSize") \
289 ENUM_ENTRY(IC_EVEX_KZ, 1, "requires an EVEX_KZ prefix") \
290 ENUM_ENTRY(IC_EVEX_XS_KZ, 2, "requires EVEX_KZ and the XS prefix") \
291 ENUM_ENTRY(IC_EVEX_XD_KZ, 2, "requires EVEX_KZ and the XD prefix") \
292 ENUM_ENTRY(IC_EVEX_OPSIZE_KZ, 2, "requires EVEX_KZ and the OpSize prefix") \
293 ENUM_ENTRY(IC_EVEX_W_KZ, 3, "requires EVEX_KZ and the W prefix") \
294 ENUM_ENTRY(IC_EVEX_W_XS_KZ, 4, "requires EVEX_KZ, W, and XS prefix") \
295 ENUM_ENTRY(IC_EVEX_W_XD_KZ, 4, "requires EVEX_KZ, W, and XD prefix") \
296 ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ, 4, "requires EVEX_KZ, W, and OpSize") \
297 ENUM_ENTRY(IC_EVEX_L_KZ, 3, "requires EVEX_KZ and the L prefix") \
298 ENUM_ENTRY(IC_EVEX_L_XS_KZ, 4, "requires EVEX_KZ and the L and XS prefix") \
299 ENUM_ENTRY(IC_EVEX_L_XD_KZ, 4, "requires EVEX_KZ and the L and XD prefix") \
300 ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ, 4, "requires EVEX_KZ, L, and OpSize") \
301 ENUM_ENTRY(IC_EVEX_L_W_KZ, 3, "requires EVEX_KZ, L and W") \
302 ENUM_ENTRY(IC_EVEX_L_W_XS_KZ, 4, "requires EVEX_KZ, L, W and XS prefix") \
303 ENUM_ENTRY(IC_EVEX_L_W_XD_KZ, 4, "requires EVEX_KZ, L, W and XD prefix") \
304 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L, W and OpSize") \
305 ENUM_ENTRY(IC_EVEX_L2_KZ, 3, "requires EVEX_KZ and the L2 prefix") \
306 ENUM_ENTRY(IC_EVEX_L2_XS_KZ, 4, "requires EVEX_KZ and the L2 and XS prefix") \
307 ENUM_ENTRY(IC_EVEX_L2_XD_KZ, 4, "requires EVEX_KZ and the L2 and XD prefix") \
308 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, and OpSize") \
309 ENUM_ENTRY(IC_EVEX_L2_W_KZ, 3, "requires EVEX_KZ, L2 and W") \
310 ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ, 4, "requires EVEX_KZ, L2, W and XS prefix") \
311 ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ, 4, "requires EVEX_KZ, L2, W and XD prefix") \
312 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize")
313
314#define ENUM_ENTRY(n, r, d) n,
315enum InstructionContext { INSTRUCTION_CONTEXTS IC_max };
316#undef ENUM_ENTRY
317
318// Opcode types, which determine which decode table to use, both in the Intel
319// manual and also for the decoder.
320enum OpcodeType {
321 ONEBYTE = 0,
322 TWOBYTE = 1,
323 THREEBYTE_38 = 2,
324 THREEBYTE_3A = 3,
325 XOP8_MAP = 4,
326 XOP9_MAP = 5,
327 XOPA_MAP = 6,
328 THREEDNOW_MAP = 7,
329 MAP4 = 8,
330 MAP5 = 9,
331 MAP6 = 10,
332 MAP7 = 11
333};
334
335// The following structs are used for the hierarchical decode table. After
336// determining the instruction's class (i.e., which IC_* constant applies to
337// it), the decoder reads the opcode. Some instructions require specific
338// values of the ModR/M byte, so the ModR/M byte indexes into the final table.
339//
340// If a ModR/M byte is not required, "required" is left unset, and the values
341// for each instructionID are identical.
342typedef uint16_t InstrUID;
343
344// ModRMDecisionType - describes the type of ModR/M decision, allowing the
345// consumer to determine the number of entries in it.
346//
347// MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded
348// instruction is the same.
349// MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode
350// corresponds to one instruction; otherwise, it corresponds to
351// a different instruction.
352// MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte
353// divided by 8 is used to select instruction; otherwise, each
354// value of the ModR/M byte could correspond to a different
355// instruction.
356// MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This
357// corresponds to instructions that use reg field as opcode
358// MODRM_FULL - Potentially, each value of the ModR/M byte could correspond
359// to a different instruction.
360#define MODRMTYPES \
361 ENUM_ENTRY(MODRM_ONEENTRY) \
362 ENUM_ENTRY(MODRM_SPLITRM) \
363 ENUM_ENTRY(MODRM_SPLITMISC) \
364 ENUM_ENTRY(MODRM_SPLITREG) \
365 ENUM_ENTRY(MODRM_FULL)
366
367#define ENUM_ENTRY(n) n,
368enum ModRMDecisionType { MODRMTYPES MODRM_max };
369#undef ENUM_ENTRY
370
371#define CASE_ENCODING_RM \
372 case ENCODING_RM: \
373 case ENCODING_RM_CD2: \
374 case ENCODING_RM_CD4: \
375 case ENCODING_RM_CD8: \
376 case ENCODING_RM_CD16: \
377 case ENCODING_RM_CD32: \
378 case ENCODING_RM_CD64
379
380#define CASE_ENCODING_VSIB \
381 case ENCODING_VSIB: \
382 case ENCODING_VSIB_CD2: \
383 case ENCODING_VSIB_CD4: \
384 case ENCODING_VSIB_CD8: \
385 case ENCODING_VSIB_CD16: \
386 case ENCODING_VSIB_CD32: \
387 case ENCODING_VSIB_CD64
388
389// Physical encodings of instruction operands.
390#define ENCODINGS \
391 ENUM_ENTRY(ENCODING_NONE, "") \
392 ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \
393 ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \
394 ENUM_ENTRY(ENCODING_RM_CD2, "R/M operand with CDisp scaling of 2") \
395 ENUM_ENTRY(ENCODING_RM_CD4, "R/M operand with CDisp scaling of 4") \
396 ENUM_ENTRY(ENCODING_RM_CD8, "R/M operand with CDisp scaling of 8") \
397 ENUM_ENTRY(ENCODING_RM_CD16, "R/M operand with CDisp scaling of 16") \
398 ENUM_ENTRY(ENCODING_RM_CD32, "R/M operand with CDisp scaling of 32") \
399 ENUM_ENTRY(ENCODING_RM_CD64, "R/M operand with CDisp scaling of 64") \
400 ENUM_ENTRY(ENCODING_SIB, "Force SIB operand in ModR/M byte.") \
401 ENUM_ENTRY(ENCODING_VSIB, "VSIB operand in ModR/M byte.") \
402 ENUM_ENTRY(ENCODING_VSIB_CD2, "VSIB operand with CDisp scaling of 2") \
403 ENUM_ENTRY(ENCODING_VSIB_CD4, "VSIB operand with CDisp scaling of 4") \
404 ENUM_ENTRY(ENCODING_VSIB_CD8, "VSIB operand with CDisp scaling of 8") \
405 ENUM_ENTRY(ENCODING_VSIB_CD16, "VSIB operand with CDisp scaling of 16") \
406 ENUM_ENTRY(ENCODING_VSIB_CD32, "VSIB operand with CDisp scaling of 32") \
407 ENUM_ENTRY(ENCODING_VSIB_CD64, "VSIB operand with CDisp scaling of 64") \
408 ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \
409 ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \
410 ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \
411 ENUM_ENTRY(ENCODING_IW, "2-byte") \
412 ENUM_ENTRY(ENCODING_ID, "4-byte") \
413 ENUM_ENTRY(ENCODING_IO, "8-byte") \
414 ENUM_ENTRY(ENCODING_RB, \
415 "(AL..DIL, R8B..R15B) Register code added to the opcode byte") \
416 ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \
417 ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \
418 ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \
419 ENUM_ENTRY(ENCODING_FP, "Position on floating-point stack in ModR/M byte.") \
420 ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \
421 ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \
422 ENUM_ENTRY(ENCODING_IRC, "Immediate for static rounding control") \
423 ENUM_ENTRY(ENCODING_Rv, \
424 "Register code of operand size added to the opcode byte") \
425 ENUM_ENTRY(ENCODING_CC, "Condition code encoded in opcode") \
426 ENUM_ENTRY(ENCODING_DUP, \
427 "Duplicate of another operand; ID is encoded in type") \
428 ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix") \
429 ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes")
430
431#define ENUM_ENTRY(n, d) n,
432enum OperandEncoding { ENCODINGS ENCODING_max };
433#undef ENUM_ENTRY
434
435// Semantic interpretations of instruction operands.
436#define TYPES \
437 ENUM_ENTRY(TYPE_NONE, "") \
438 ENUM_ENTRY(TYPE_REL, "immediate address") \
439 ENUM_ENTRY(TYPE_R8, "1-byte register operand") \
440 ENUM_ENTRY(TYPE_R16, "2-byte") \
441 ENUM_ENTRY(TYPE_R32, "4-byte") \
442 ENUM_ENTRY(TYPE_R64, "8-byte") \
443 ENUM_ENTRY(TYPE_IMM, "immediate operand") \
444 ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \
445 ENUM_ENTRY(TYPE_M, "Memory operand") \
446 ENUM_ENTRY(TYPE_MSIB, "Memory operand force sib encoding") \
447 ENUM_ENTRY(TYPE_MVSIBX, "Memory operand using XMM index") \
448 ENUM_ENTRY(TYPE_MVSIBY, "Memory operand using YMM index") \
449 ENUM_ENTRY(TYPE_MVSIBZ, "Memory operand using ZMM index") \
450 ENUM_ENTRY(TYPE_SRCIDX, "memory at source index") \
451 ENUM_ENTRY(TYPE_DSTIDX, "memory at destination index") \
452 ENUM_ENTRY(TYPE_MOFFS, "memory offset (relative to segment base)") \
453 ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \
454 ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \
455 ENUM_ENTRY(TYPE_XMM, "16-byte") \
456 ENUM_ENTRY(TYPE_YMM, "32-byte") \
457 ENUM_ENTRY(TYPE_ZMM, "64-byte") \
458 ENUM_ENTRY(TYPE_VK, "mask register") \
459 ENUM_ENTRY(TYPE_VK_PAIR, "mask register pair") \
460 ENUM_ENTRY(TYPE_TMM, "tile") \
461 ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \
462 ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \
463 ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \
464 ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \
465 ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \
466 ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \
467 ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \
468 ENUM_ENTRY(TYPE_DUP1, "operand 1") \
469 ENUM_ENTRY(TYPE_DUP2, "operand 2") \
470 ENUM_ENTRY(TYPE_DUP3, "operand 3") \
471 ENUM_ENTRY(TYPE_DUP4, "operand 4")
472
473#define ENUM_ENTRY(n, d) n,
474enum OperandType { TYPES TYPE_max };
475#undef ENUM_ENTRY
476
477/// The specification for how to extract and interpret one operand.
478struct OperandSpecifier {
479 uint8_t encoding;
480 uint8_t type;
481};
482
483static const unsigned X86_MAX_OPERANDS = 6;
484
485/// Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode
486/// are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode,
487/// respectively.
488enum DisassemblerMode { MODE_16BIT, MODE_32BIT, MODE_64BIT };
489
490} // namespace X86Disassembler
491} // namespace llvm
492
493#endif
ENCODINGS
#define ENCODINGS
Definition: X86DisassemblerDecoderCommon.h:390
INSTRUCTION_CONTEXTS
#define INSTRUCTION_CONTEXTS
Definition: X86DisassemblerDecoderCommon.h:81
MODRMTYPES
#define MODRMTYPES
Definition: X86DisassemblerDecoderCommon.h:360
uint16_t
llvm::X86Disassembler::DisassemblerMode
DisassemblerMode
Decoding mode for the Intel disassembler.
Definition: X86DisassemblerDecoderCommon.h:488
llvm::X86Disassembler::X86_MAX_OPERANDS
static const unsigned X86_MAX_OPERANDS
Definition: X86DisassemblerDecoderCommon.h:483
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::X86Disassembler::OperandSpecifier
The specification for how to extract and interpret one operand.
Definition: X86DisassemblerDecoderCommon.h:478
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