LLVM
15.0.0git
include
llvm
Support
X86DisassemblerDecoderCommon.h
Go to the documentation of this file.
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//===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the X86 Disassembler.
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// It contains common definitions used by both the disassembler and the table
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// generator.
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// Documentation for the disassembler can be found in X86Disassembler.h.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_SUPPORT_X86DISASSEMBLERDECODERCOMMON_H
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#define LLVM_SUPPORT_X86DISASSEMBLERDECODERCOMMON_H
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#include "
llvm/Support/DataTypes.h
"
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namespace
llvm
{
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namespace
X86Disassembler {
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#define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers
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#define CONTEXTS_SYM x86DisassemblerContexts
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#define ONEBYTE_SYM x86DisassemblerOneByteOpcodes
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#define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes
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#define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes
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#define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes
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#define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes
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#define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes
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#define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes
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#define THREEDNOW_MAP_SYM x86Disassembler3DNowOpcodes
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#define MAP5_SYM x86DisassemblerMap5Opcodes
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#define MAP6_SYM x86DisassemblerMap6Opcodes
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#define INSTRUCTIONS_STR "x86DisassemblerInstrSpecifiers"
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#define CONTEXTS_STR "x86DisassemblerContexts"
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#define ONEBYTE_STR "x86DisassemblerOneByteOpcodes"
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#define TWOBYTE_STR "x86DisassemblerTwoByteOpcodes"
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#define THREEBYTE38_STR "x86DisassemblerThreeByte38Opcodes"
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#define THREEBYTE3A_STR "x86DisassemblerThreeByte3AOpcodes"
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#define XOP8_MAP_STR "x86DisassemblerXOP8Opcodes"
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#define XOP9_MAP_STR "x86DisassemblerXOP9Opcodes"
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#define XOPA_MAP_STR "x86DisassemblerXOPAOpcodes"
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#define THREEDNOW_MAP_STR "x86Disassembler3DNowOpcodes"
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#define MAP5_STR "x86DisassemblerMap5Opcodes"
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#define MAP6_STR "x86DisassemblerMap6Opcodes"
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// Attributes of an instruction that must be known before the opcode can be
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// processed correctly. Most of these indicate the presence of particular
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// prefixes, but ATTR_64BIT is simply an attribute of the decoding context.
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enum
attributeBits
{
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ATTR_NONE
= 0x00,
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ATTR_64BIT
= 0x1 << 0,
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ATTR_XS
= 0x1 << 1,
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ATTR_XD
= 0x1 << 2,
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ATTR_REXW
= 0x1 << 3,
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ATTR_OPSIZE
= 0x1 << 4,
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ATTR_ADSIZE
= 0x1 << 5,
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ATTR_VEX
= 0x1 << 6,
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ATTR_VEXL
= 0x1 << 7,
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ATTR_EVEX
= 0x1 << 8,
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ATTR_EVEXL2
= 0x1 << 9,
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ATTR_EVEXK
= 0x1 << 10,
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ATTR_EVEXKZ
= 0x1 << 11,
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ATTR_EVEXB
= 0x1 << 12,
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ATTR_max
= 0x1 << 13,
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};
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// Combinations of the above attributes that are relevant to instruction
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// decode. Although other combinations are possible, they can be reduced to
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// these without affecting the ultimately decoded instruction.
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// Class name Rank Rationale for rank assignment
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#define INSTRUCTION_CONTEXTS \
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ENUM_ENTRY(IC, 0, "says nothing about the instruction") \
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ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \
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"64-bit mode but no more") \
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ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
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"operands change width") \
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ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \
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"operands change width") \
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ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
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ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \
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"but not the operands") \
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ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \
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"but not the operands") \
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ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
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"operands change width") \
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ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
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"operands change width") \
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ENUM_ENTRY(IC_XD_ADSIZE, 3, "requires an ADSIZE prefix, so " \
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"operands change width") \
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ENUM_ENTRY(IC_XS_ADSIZE, 3, "requires an ADSIZE prefix, so " \
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"operands change width") \
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ENUM_ENTRY(IC_64BIT_REXW, 5, "requires a REX.W prefix, so operands "\
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"change width; overrides IC_OPSIZE") \
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ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \
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"prefix") \
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ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \
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ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \
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ENUM_ENTRY(IC_64BIT_OPSIZE_ADSIZE, 4, "Just as meaningful as IC_OPSIZE/" \
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"IC_ADSIZE") \
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ENUM_ENTRY(IC_64BIT_XD, 6, "XD instructions are SSE; REX.W is " \
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"secondary") \
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ENUM_ENTRY(IC_64BIT_XS, 6, "Just as meaningful as IC_64BIT_XD") \
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ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \
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ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \
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ENUM_ENTRY(IC_64BIT_XD_ADSIZE, 3, "Just as meaningful as IC_XD_ADSIZE") \
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ENUM_ENTRY(IC_64BIT_XS_ADSIZE, 3, "Just as meaningful as IC_XS_ADSIZE") \
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ENUM_ENTRY(IC_64BIT_REXW_XS, 7, "OPSIZE could mean a different " \
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"opcode") \
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ENUM_ENTRY(IC_64BIT_REXW_XD, 7, "Just as meaningful as " \
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"IC_64BIT_REXW_XS") \
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ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 8, "The Dynamic Duo! Prefer over all " \
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"else because this changes most " \
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"operands' meaning") \
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ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \
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ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \
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ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \
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ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \
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ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \
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ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \
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ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \
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ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \
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ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \
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ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\
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ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\
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ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \
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ENUM_ENTRY(IC_VEX_L_W, 4, "requires VEX, L and W") \
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ENUM_ENTRY(IC_VEX_L_W_XS, 5, "requires VEX, L, W and XS prefix") \
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ENUM_ENTRY(IC_VEX_L_W_XD, 5, "requires VEX, L, W and XD prefix") \
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ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize") \
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ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \
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ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
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ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
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ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
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ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \
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ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \
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ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \
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ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \
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ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \
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ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \
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ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \
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ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \
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ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \
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ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \
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ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \
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ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \
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ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \
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ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \
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ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \
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ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \
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ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \
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ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \
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ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \
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ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \
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ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \
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ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \
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ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \
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ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \
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ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \
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ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \
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ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \
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ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \
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ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \
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ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \
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ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \
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ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \
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ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \
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ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \
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ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \
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ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \
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ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \
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ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \
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ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \
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ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \
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ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L2, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_KZ_B, 1, "requires EVEX_B and EVEX_KZ prefix") \
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ENUM_ENTRY(IC_EVEX_XS_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XS prefix") \
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ENUM_ENTRY(IC_EVEX_XD_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XD prefix") \
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ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the OpSize prefix") \
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ENUM_ENTRY(IC_EVEX_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the W prefix") \
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ENUM_ENTRY(IC_EVEX_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XS prefix") \
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ENUM_ENTRY(IC_EVEX_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XD prefix") \
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ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L prefix") \
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ENUM_ENTRY(IC_EVEX_L_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L and W") \
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ENUM_ENTRY(IC_EVEX_L_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L2 prefix") \
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ENUM_ENTRY(IC_EVEX_L2_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L2_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L2 and W") \
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ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_KZ, 1, "requires an EVEX_KZ prefix") \
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ENUM_ENTRY(IC_EVEX_XS_KZ, 2, "requires EVEX_KZ and the XS prefix") \
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ENUM_ENTRY(IC_EVEX_XD_KZ, 2, "requires EVEX_KZ and the XD prefix") \
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ENUM_ENTRY(IC_EVEX_OPSIZE_KZ, 2, "requires EVEX_KZ and the OpSize prefix") \
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ENUM_ENTRY(IC_EVEX_W_KZ, 3, "requires EVEX_KZ and the W prefix") \
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ENUM_ENTRY(IC_EVEX_W_XS_KZ, 4, "requires EVEX_KZ, W, and XS prefix") \
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ENUM_ENTRY(IC_EVEX_W_XD_KZ, 4, "requires EVEX_KZ, W, and XD prefix") \
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ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ, 4, "requires EVEX_KZ, W, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L_KZ, 3, "requires EVEX_KZ and the L prefix") \
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ENUM_ENTRY(IC_EVEX_L_XS_KZ, 4, "requires EVEX_KZ and the L and XS prefix")\
265
ENUM_ENTRY(IC_EVEX_L_XD_KZ, 4, "requires EVEX_KZ and the L and XD prefix")\
266
ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ, 4, "requires EVEX_KZ, L, and OpSize") \
267
ENUM_ENTRY(IC_EVEX_L_W_KZ, 3, "requires EVEX_KZ, L and W") \
268
ENUM_ENTRY(IC_EVEX_L_W_XS_KZ, 4, "requires EVEX_KZ, L, W and XS prefix") \
269
ENUM_ENTRY(IC_EVEX_L_W_XD_KZ, 4, "requires EVEX_KZ, L, W and XD prefix") \
270
ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L, W and OpSize") \
271
ENUM_ENTRY(IC_EVEX_L2_KZ, 3, "requires EVEX_KZ and the L2 prefix") \
272
ENUM_ENTRY(IC_EVEX_L2_XS_KZ, 4, "requires EVEX_KZ and the L2 and XS prefix")\
273
ENUM_ENTRY(IC_EVEX_L2_XD_KZ, 4, "requires EVEX_KZ and the L2 and XD prefix")\
274
ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, and OpSize") \
275
ENUM_ENTRY(IC_EVEX_L2_W_KZ, 3, "requires EVEX_KZ, L2 and W") \
276
ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ, 4, "requires EVEX_KZ, L2, W and XS prefix") \
277
ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ, 4, "requires EVEX_KZ, L2, W and XD prefix") \
278
ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize")
279
280
#define ENUM_ENTRY(n, r, d) n,
281
enum
InstructionContext
{
282
INSTRUCTION_CONTEXTS
283
IC_max
284
};
285
#undef ENUM_ENTRY
286
287
// Opcode types, which determine which decode table to use, both in the Intel
288
// manual and also for the decoder.
289
enum
OpcodeType
{
290
ONEBYTE
= 0,
291
TWOBYTE
= 1,
292
THREEBYTE_38
= 2,
293
THREEBYTE_3A
= 3,
294
XOP8_MAP
= 4,
295
XOP9_MAP
= 5,
296
XOPA_MAP
= 6,
297
THREEDNOW_MAP
= 7,
298
MAP5
= 8,
299
MAP6
= 9
300
};
301
302
// The following structs are used for the hierarchical decode table. After
303
// determining the instruction's class (i.e., which IC_* constant applies to
304
// it), the decoder reads the opcode. Some instructions require specific
305
// values of the ModR/M byte, so the ModR/M byte indexes into the final table.
306
//
307
// If a ModR/M byte is not required, "required" is left unset, and the values
308
// for each instructionID are identical.
309
typedef
uint16_t
InstrUID
;
310
311
// ModRMDecisionType - describes the type of ModR/M decision, allowing the
312
// consumer to determine the number of entries in it.
313
//
314
// MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded
315
// instruction is the same.
316
// MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode
317
// corresponds to one instruction; otherwise, it corresponds to
318
// a different instruction.
319
// MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte
320
// divided by 8 is used to select instruction; otherwise, each
321
// value of the ModR/M byte could correspond to a different
322
// instruction.
323
// MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This
324
// corresponds to instructions that use reg field as opcode
325
// MODRM_FULL - Potentially, each value of the ModR/M byte could correspond
326
// to a different instruction.
327
#define MODRMTYPES \
328
ENUM_ENTRY(MODRM_ONEENTRY) \
329
ENUM_ENTRY(MODRM_SPLITRM) \
330
ENUM_ENTRY(MODRM_SPLITMISC) \
331
ENUM_ENTRY(MODRM_SPLITREG) \
332
ENUM_ENTRY(MODRM_FULL)
333
334
#define ENUM_ENTRY(n) n,
335
enum
ModRMDecisionType
{
336
MODRMTYPES
337
MODRM_max
338
};
339
#undef ENUM_ENTRY
340
341
#define CASE_ENCODING_RM \
342
case ENCODING_RM: \
343
case ENCODING_RM_CD2: \
344
case ENCODING_RM_CD4: \
345
case ENCODING_RM_CD8: \
346
case ENCODING_RM_CD16: \
347
case ENCODING_RM_CD32: \
348
case ENCODING_RM_CD64
349
350
#define CASE_ENCODING_VSIB \
351
case ENCODING_VSIB: \
352
case ENCODING_VSIB_CD2: \
353
case ENCODING_VSIB_CD4: \
354
case ENCODING_VSIB_CD8: \
355
case ENCODING_VSIB_CD16: \
356
case ENCODING_VSIB_CD32: \
357
case ENCODING_VSIB_CD64
358
359
// Physical encodings of instruction operands.
360
#define ENCODINGS \
361
ENUM_ENTRY(ENCODING_NONE, "") \
362
ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \
363
ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \
364
ENUM_ENTRY(ENCODING_RM_CD2, "R/M operand with CDisp scaling of 2") \
365
ENUM_ENTRY(ENCODING_RM_CD4, "R/M operand with CDisp scaling of 4") \
366
ENUM_ENTRY(ENCODING_RM_CD8, "R/M operand with CDisp scaling of 8") \
367
ENUM_ENTRY(ENCODING_RM_CD16,"R/M operand with CDisp scaling of 16") \
368
ENUM_ENTRY(ENCODING_RM_CD32,"R/M operand with CDisp scaling of 32") \
369
ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64") \
370
ENUM_ENTRY(ENCODING_SIB, "Force SIB operand in ModR/M byte.") \
371
ENUM_ENTRY(ENCODING_VSIB, "VSIB operand in ModR/M byte.") \
372
ENUM_ENTRY(ENCODING_VSIB_CD2, "VSIB operand with CDisp scaling of 2") \
373
ENUM_ENTRY(ENCODING_VSIB_CD4, "VSIB operand with CDisp scaling of 4") \
374
ENUM_ENTRY(ENCODING_VSIB_CD8, "VSIB operand with CDisp scaling of 8") \
375
ENUM_ENTRY(ENCODING_VSIB_CD16,"VSIB operand with CDisp scaling of 16") \
376
ENUM_ENTRY(ENCODING_VSIB_CD32,"VSIB operand with CDisp scaling of 32") \
377
ENUM_ENTRY(ENCODING_VSIB_CD64,"VSIB operand with CDisp scaling of 64") \
378
ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \
379
ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \
380
ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \
381
ENUM_ENTRY(ENCODING_IW, "2-byte") \
382
ENUM_ENTRY(ENCODING_ID, "4-byte") \
383
ENUM_ENTRY(ENCODING_IO, "8-byte") \
384
ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8B..R15B) Register code added to " \
385
"the opcode byte") \
386
ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \
387
ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \
388
ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \
389
ENUM_ENTRY(ENCODING_FP, "Position on floating-point stack in ModR/M " \
390
"byte.") \
391
\
392
ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \
393
ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \
394
ENUM_ENTRY(ENCODING_IRC, "Immediate for static rounding control") \
395
ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \
396
"opcode byte") \
397
ENUM_ENTRY(ENCODING_CC, "Condition code encoded in opcode") \
398
ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \
399
"in type") \
400
ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix") \
401
ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes")
402
403
#define ENUM_ENTRY(n, d) n,
404
enum
OperandEncoding
{
405
ENCODINGS
406
ENCODING_max
407
};
408
#undef ENUM_ENTRY
409
410
// Semantic interpretations of instruction operands.
411
#define TYPES \
412
ENUM_ENTRY(TYPE_NONE, "") \
413
ENUM_ENTRY(TYPE_REL, "immediate address") \
414
ENUM_ENTRY(TYPE_R8, "1-byte register operand") \
415
ENUM_ENTRY(TYPE_R16, "2-byte") \
416
ENUM_ENTRY(TYPE_R32, "4-byte") \
417
ENUM_ENTRY(TYPE_R64, "8-byte") \
418
ENUM_ENTRY(TYPE_IMM, "immediate operand") \
419
ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \
420
ENUM_ENTRY(TYPE_M, "Memory operand") \
421
ENUM_ENTRY(TYPE_MSIB, "Memory operand force sib encoding") \
422
ENUM_ENTRY(TYPE_MVSIBX, "Memory operand using XMM index") \
423
ENUM_ENTRY(TYPE_MVSIBY, "Memory operand using YMM index") \
424
ENUM_ENTRY(TYPE_MVSIBZ, "Memory operand using ZMM index") \
425
ENUM_ENTRY(TYPE_SRCIDX, "memory at source index") \
426
ENUM_ENTRY(TYPE_DSTIDX, "memory at destination index") \
427
ENUM_ENTRY(TYPE_MOFFS, "memory offset (relative to segment base)") \
428
ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \
429
ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \
430
ENUM_ENTRY(TYPE_XMM, "16-byte") \
431
ENUM_ENTRY(TYPE_YMM, "32-byte") \
432
ENUM_ENTRY(TYPE_ZMM, "64-byte") \
433
ENUM_ENTRY(TYPE_VK, "mask register") \
434
ENUM_ENTRY(TYPE_VK_PAIR, "mask register pair") \
435
ENUM_ENTRY(TYPE_TMM, "tile") \
436
ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \
437
ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \
438
ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \
439
ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \
440
\
441
ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \
442
ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \
443
ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \
444
ENUM_ENTRY(TYPE_DUP1, "operand 1") \
445
ENUM_ENTRY(TYPE_DUP2, "operand 2") \
446
ENUM_ENTRY(TYPE_DUP3, "operand 3") \
447
ENUM_ENTRY(TYPE_DUP4, "operand 4") \
448
449
#define ENUM_ENTRY(n, d) n,
450
enum
OperandType
{
451
TYPES
452
TYPE_max
453
};
454
#undef ENUM_ENTRY
455
456
/// The specification for how to extract and interpret one operand.
457
struct
OperandSpecifier
{
458
uint8_t
encoding
;
459
uint8_t
type
;
460
};
461
462
static
const
unsigned
X86_MAX_OPERANDS
= 6;
463
464
/// Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode
465
/// are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode,
466
/// respectively.
467
enum
DisassemblerMode
{
468
MODE_16BIT
,
469
MODE_32BIT
,
470
MODE_64BIT
471
};
472
473
}
// namespace X86Disassembler
474
}
// namespace llvm
475
476
#endif
llvm::X86Disassembler::MODE_16BIT
@ MODE_16BIT
Definition:
X86DisassemblerDecoderCommon.h:468
llvm::X86Disassembler::MODE_64BIT
@ MODE_64BIT
Definition:
X86DisassemblerDecoderCommon.h:470
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition:
AddressRanges.h:17
llvm::X86Disassembler::ATTR_REXW
@ ATTR_REXW
Definition:
X86DisassemblerDecoderCommon.h:58
TYPES
#define TYPES
Definition:
X86DisassemblerDecoderCommon.h:411
llvm::X86Disassembler::ENCODING_max
@ ENCODING_max
Definition:
X86DisassemblerDecoderCommon.h:406
llvm::X86Disassembler::X86_MAX_OPERANDS
static const unsigned X86_MAX_OPERANDS
Definition:
X86DisassemblerDecoderCommon.h:462
llvm::X86Disassembler::MODE_32BIT
@ MODE_32BIT
Definition:
X86DisassemblerDecoderCommon.h:469
llvm::X86Disassembler::ATTR_EVEX
@ ATTR_EVEX
Definition:
X86DisassemblerDecoderCommon.h:63
llvm::X86Disassembler::MODRM_max
@ MODRM_max
Definition:
X86DisassemblerDecoderCommon.h:337
llvm::X86Disassembler::ATTR_EVEXK
@ ATTR_EVEXK
Definition:
X86DisassemblerDecoderCommon.h:65
llvm::X86Disassembler::ATTR_XS
@ ATTR_XS
Definition:
X86DisassemblerDecoderCommon.h:56
llvm::X86Disassembler::InstructionContext
InstructionContext
Definition:
X86DisassemblerDecoderCommon.h:281
llvm::X86Disassembler::ATTR_EVEXL2
@ ATTR_EVEXL2
Definition:
X86DisassemblerDecoderCommon.h:64
llvm::X86Disassembler::MAP5
@ MAP5
Definition:
X86DisassemblerDecoderCommon.h:298
llvm::X86Disassembler::THREEBYTE_38
@ THREEBYTE_38
Definition:
X86DisassemblerDecoderCommon.h:292
llvm::X86Disassembler::XOPA_MAP
@ XOPA_MAP
Definition:
X86DisassemblerDecoderCommon.h:296
llvm::X86Disassembler::attributeBits
attributeBits
Definition:
X86DisassemblerDecoderCommon.h:53
llvm::X86Disassembler::OperandEncoding
OperandEncoding
Definition:
X86DisassemblerDecoderCommon.h:404
llvm::X86Disassembler::ATTR_VEX
@ ATTR_VEX
Definition:
X86DisassemblerDecoderCommon.h:61
llvm::X86Disassembler::IC_max
@ IC_max
Definition:
X86DisassemblerDecoderCommon.h:283
llvm::X86Disassembler::ATTR_OPSIZE
@ ATTR_OPSIZE
Definition:
X86DisassemblerDecoderCommon.h:59
llvm::X86Disassembler::ATTR_EVEXB
@ ATTR_EVEXB
Definition:
X86DisassemblerDecoderCommon.h:67
llvm::X86Disassembler::ATTR_VEXL
@ ATTR_VEXL
Definition:
X86DisassemblerDecoderCommon.h:62
llvm::X86Disassembler::XOP8_MAP
@ XOP8_MAP
Definition:
X86DisassemblerDecoderCommon.h:294
llvm::X86Disassembler::ModRMDecisionType
ModRMDecisionType
Definition:
X86DisassemblerDecoderCommon.h:335
llvm::X86Disassembler::ONEBYTE
@ ONEBYTE
Definition:
X86DisassemblerDecoderCommon.h:290
llvm::X86Disassembler::ATTR_ADSIZE
@ ATTR_ADSIZE
Definition:
X86DisassemblerDecoderCommon.h:60
ENCODINGS
#define ENCODINGS
Definition:
X86DisassemblerDecoderCommon.h:360
llvm::X86Disassembler::ATTR_EVEXKZ
@ ATTR_EVEXKZ
Definition:
X86DisassemblerDecoderCommon.h:66
llvm::X86Disassembler::OperandSpecifier::encoding
uint8_t encoding
Definition:
X86DisassemblerDecoderCommon.h:458
llvm::X86Disassembler::XOP9_MAP
@ XOP9_MAP
Definition:
X86DisassemblerDecoderCommon.h:295
llvm::X86Disassembler::OpcodeType
OpcodeType
Definition:
X86DisassemblerDecoderCommon.h:289
INSTRUCTION_CONTEXTS
#define INSTRUCTION_CONTEXTS
Definition:
X86DisassemblerDecoderCommon.h:76
llvm::X86Disassembler::MAP6
@ MAP6
Definition:
X86DisassemblerDecoderCommon.h:299
llvm::X86Disassembler::OperandSpecifier
The specification for how to extract and interpret one operand.
Definition:
X86DisassemblerDecoderCommon.h:457
MODRMTYPES
#define MODRMTYPES
Definition:
X86DisassemblerDecoderCommon.h:327
llvm::X86Disassembler::ATTR_XD
@ ATTR_XD
Definition:
X86DisassemblerDecoderCommon.h:57
llvm::X86Disassembler::TYPE_max
@ TYPE_max
Definition:
X86DisassemblerDecoderCommon.h:452
uint16_t
llvm::X86Disassembler::ATTR_max
@ ATTR_max
Definition:
X86DisassemblerDecoderCommon.h:68
llvm::X86Disassembler::OperandSpecifier::type
uint8_t type
Definition:
X86DisassemblerDecoderCommon.h:459
llvm::X86Disassembler::TWOBYTE
@ TWOBYTE
Definition:
X86DisassemblerDecoderCommon.h:291
llvm::X86Disassembler::DisassemblerMode
DisassemblerMode
Decoding mode for the Intel disassembler.
Definition:
X86DisassemblerDecoderCommon.h:467
DataTypes.h
llvm::X86Disassembler::OperandType
OperandType
Definition:
X86DisassemblerDecoderCommon.h:450
llvm::X86Disassembler::InstrUID
uint16_t InstrUID
Definition:
X86DisassemblerDecoderCommon.h:309
llvm::X86Disassembler::THREEDNOW_MAP
@ THREEDNOW_MAP
Definition:
X86DisassemblerDecoderCommon.h:297
llvm::X86Disassembler::ATTR_64BIT
@ ATTR_64BIT
Definition:
X86DisassemblerDecoderCommon.h:55
llvm::X86Disassembler::THREEBYTE_3A
@ THREEBYTE_3A
Definition:
X86DisassemblerDecoderCommon.h:293
llvm::X86Disassembler::ATTR_NONE
@ ATTR_NONE
Definition:
X86DisassemblerDecoderCommon.h:54
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