LLVM  14.0.0git
LiveDebugVariables.cpp
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1 //===- LiveDebugVariables.cpp - Tracking debug info variables -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the LiveDebugVariables analysis.
10 //
11 // Remove all DBG_VALUE instructions referencing virtual registers and replace
12 // them with a data structure tracking where live user variables are kept - in a
13 // virtual register or in a stack slot.
14 //
15 // Allow the data structure to be updated during register allocation when values
16 // are moved between registers and stack slots. Finally emit new DBG_VALUE
17 // instructions after register allocation is complete.
18 //
19 //===----------------------------------------------------------------------===//
20 
21 #include "LiveDebugVariables.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/IntervalMap.h"
25 #include "llvm/ADT/MapVector.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/SmallSet.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/ADT/StringRef.h"
41 #include "llvm/CodeGen/Passes.h"
49 #include "llvm/Config/llvm-config.h"
51 #include "llvm/IR/DebugLoc.h"
52 #include "llvm/IR/Function.h"
53 #include "llvm/IR/Metadata.h"
54 #include "llvm/InitializePasses.h"
55 #include "llvm/MC/MCRegisterInfo.h"
56 #include "llvm/Pass.h"
57 #include "llvm/Support/Casting.h"
59 #include "llvm/Support/Debug.h"
62 #include <algorithm>
63 #include <cassert>
64 #include <iterator>
65 #include <memory>
66 #include <utility>
67 
68 using namespace llvm;
69 
70 #define DEBUG_TYPE "livedebugvars"
71 
72 static cl::opt<bool>
73 EnableLDV("live-debug-variables", cl::init(true),
74  cl::desc("Enable the live debug variables pass"), cl::Hidden);
75 
76 STATISTIC(NumInsertedDebugValues, "Number of DBG_VALUEs inserted");
77 STATISTIC(NumInsertedDebugLabels, "Number of DBG_LABELs inserted");
78 
79 char LiveDebugVariables::ID = 0;
80 
82  "Debug Variable Analysis", false, false)
86  "Debug Variable Analysis", false, false)
87 
88 void LiveDebugVariables::getAnalysisUsage(AnalysisUsage &AU) const {
89  AU.addRequired<MachineDominatorTree>();
90  AU.addRequiredTransitive<LiveIntervals>();
91  AU.setPreservesAll();
93 }
94 
97 }
98 
99 enum : unsigned { UndefLocNo = ~0U };
100 
101 namespace {
102 /// Describes a debug variable value by location number and expression along
103 /// with some flags about the original usage of the location.
104 class DbgVariableValue {
105 public:
106  DbgVariableValue(ArrayRef<unsigned> NewLocs, bool WasIndirect, bool WasList,
107  const DIExpression &Expr)
108  : WasIndirect(WasIndirect), WasList(WasList), Expression(&Expr) {
109  assert(!(WasIndirect && WasList) &&
110  "DBG_VALUE_LISTs should not be indirect.");
111  SmallVector<unsigned> LocNoVec;
112  for (unsigned LocNo : NewLocs) {
113  auto It = find(LocNoVec, LocNo);
114  if (It == LocNoVec.end())
115  LocNoVec.push_back(LocNo);
116  else {
117  // Loc duplicates an element in LocNos; replace references to Op
118  // with references to the duplicating element.
119  unsigned OpIdx = LocNoVec.size();
120  unsigned DuplicatingIdx = std::distance(LocNoVec.begin(), It);
121  Expression =
122  DIExpression::replaceArg(Expression, OpIdx, DuplicatingIdx);
123  }
124  }
125  // FIXME: Debug values referencing 64+ unique machine locations are rare and
126  // currently unsupported for performance reasons. If we can verify that
127  // performance is acceptable for such debug values, we can increase the
128  // bit-width of LocNoCount to 14 to enable up to 16384 unique machine
129  // locations. We will also need to verify that this does not cause issues
130  // with LiveDebugVariables' use of IntervalMap.
131  if (LocNoVec.size() < 64) {
132  LocNoCount = LocNoVec.size();
133  if (LocNoCount > 0) {
134  LocNos = std::make_unique<unsigned[]>(LocNoCount);
135  std::copy(LocNoVec.begin(), LocNoVec.end(), loc_nos_begin());
136  }
137  } else {
138  LLVM_DEBUG(dbgs() << "Found debug value with 64+ unique machine "
139  "locations, dropping...\n");
140  LocNoCount = 1;
141  // Turn this into an undef debug value list; right now, the simplest form
142  // of this is an expression with one arg, and an undef debug operand.
143  Expression =
144  DIExpression::get(Expr.getContext(), {dwarf::DW_OP_LLVM_arg, 0,
145  dwarf::DW_OP_stack_value});
146  if (auto FragmentInfoOpt = Expr.getFragmentInfo())
148  Expression, FragmentInfoOpt->OffsetInBits,
149  FragmentInfoOpt->SizeInBits);
150  LocNos = std::make_unique<unsigned[]>(LocNoCount);
151  LocNos[0] = UndefLocNo;
152  }
153  }
154 
155  DbgVariableValue() : LocNoCount(0), WasIndirect(false), WasList(false) {}
156  DbgVariableValue(const DbgVariableValue &Other)
157  : LocNoCount(Other.LocNoCount), WasIndirect(Other.getWasIndirect()),
158  WasList(Other.getWasList()), Expression(Other.getExpression()) {
159  if (Other.getLocNoCount()) {
160  LocNos.reset(new unsigned[Other.getLocNoCount()]);
161  std::copy(Other.loc_nos_begin(), Other.loc_nos_end(), loc_nos_begin());
162  }
163  }
164 
165  DbgVariableValue &operator=(const DbgVariableValue &Other) {
166  if (this == &Other)
167  return *this;
168  if (Other.getLocNoCount()) {
169  LocNos.reset(new unsigned[Other.getLocNoCount()]);
170  std::copy(Other.loc_nos_begin(), Other.loc_nos_end(), loc_nos_begin());
171  } else {
172  LocNos.release();
173  }
174  LocNoCount = Other.getLocNoCount();
175  WasIndirect = Other.getWasIndirect();
176  WasList = Other.getWasList();
177  Expression = Other.getExpression();
178  return *this;
179  }
180 
181  const DIExpression *getExpression() const { return Expression; }
182  uint8_t getLocNoCount() const { return LocNoCount; }
183  bool containsLocNo(unsigned LocNo) const {
184  return is_contained(loc_nos(), LocNo);
185  }
186  bool getWasIndirect() const { return WasIndirect; }
187  bool getWasList() const { return WasList; }
188  bool isUndef() const { return LocNoCount == 0 || containsLocNo(UndefLocNo); }
189 
190  DbgVariableValue decrementLocNosAfterPivot(unsigned Pivot) const {
191  SmallVector<unsigned, 4> NewLocNos;
192  for (unsigned LocNo : loc_nos())
193  NewLocNos.push_back(LocNo != UndefLocNo && LocNo > Pivot ? LocNo - 1
194  : LocNo);
195  return DbgVariableValue(NewLocNos, WasIndirect, WasList, *Expression);
196  }
197 
198  DbgVariableValue remapLocNos(ArrayRef<unsigned> LocNoMap) const {
199  SmallVector<unsigned> NewLocNos;
200  for (unsigned LocNo : loc_nos())
201  // Undef values don't exist in locations (and thus not in LocNoMap
202  // either) so skip over them. See getLocationNo().
203  NewLocNos.push_back(LocNo == UndefLocNo ? UndefLocNo : LocNoMap[LocNo]);
204  return DbgVariableValue(NewLocNos, WasIndirect, WasList, *Expression);
205  }
206 
207  DbgVariableValue changeLocNo(unsigned OldLocNo, unsigned NewLocNo) const {
208  SmallVector<unsigned> NewLocNos;
209  NewLocNos.assign(loc_nos_begin(), loc_nos_end());
210  auto OldLocIt = find(NewLocNos, OldLocNo);
211  assert(OldLocIt != NewLocNos.end() && "Old location must be present.");
212  *OldLocIt = NewLocNo;
213  return DbgVariableValue(NewLocNos, WasIndirect, WasList, *Expression);
214  }
215 
216  bool hasLocNoGreaterThan(unsigned LocNo) const {
217  return any_of(loc_nos(),
218  [LocNo](unsigned ThisLocNo) { return ThisLocNo > LocNo; });
219  }
220 
221  void printLocNos(llvm::raw_ostream &OS) const {
222  for (const unsigned &Loc : loc_nos())
223  OS << (&Loc == loc_nos_begin() ? " " : ", ") << Loc;
224  }
225 
226  friend inline bool operator==(const DbgVariableValue &LHS,
227  const DbgVariableValue &RHS) {
228  if (std::tie(LHS.LocNoCount, LHS.WasIndirect, LHS.WasList,
229  LHS.Expression) !=
230  std::tie(RHS.LocNoCount, RHS.WasIndirect, RHS.WasList, RHS.Expression))
231  return false;
232  return std::equal(LHS.loc_nos_begin(), LHS.loc_nos_end(),
233  RHS.loc_nos_begin());
234  }
235 
236  friend inline bool operator!=(const DbgVariableValue &LHS,
237  const DbgVariableValue &RHS) {
238  return !(LHS == RHS);
239  }
240 
241  unsigned *loc_nos_begin() { return LocNos.get(); }
242  const unsigned *loc_nos_begin() const { return LocNos.get(); }
243  unsigned *loc_nos_end() { return LocNos.get() + LocNoCount; }
244  const unsigned *loc_nos_end() const { return LocNos.get() + LocNoCount; }
245  ArrayRef<unsigned> loc_nos() const {
246  return ArrayRef<unsigned>(LocNos.get(), LocNoCount);
247  }
248 
249 private:
250  // IntervalMap requires the value object to be very small, to the extent
251  // that we do not have enough room for an std::vector. Using a C-style array
252  // (with a unique_ptr wrapper for convenience) allows us to optimize for this
253  // specific case by packing the array size into only 6 bits (it is highly
254  // unlikely that any debug value will need 64+ locations).
255  std::unique_ptr<unsigned[]> LocNos;
256  uint8_t LocNoCount : 6;
257  bool WasIndirect : 1;
258  bool WasList : 1;
259  const DIExpression *Expression = nullptr;
260 };
261 } // namespace
262 
263 /// Map of where a user value is live to that value.
265 
266 /// Map of stack slot offsets for spilled locations.
267 /// Non-spilled locations are not added to the map.
269 
270 /// Cache to save the location where it can be used as the starting
271 /// position as input for calling MachineBasicBlock::SkipPHIsLabelsAndDebug.
272 /// This is to prevent MachineBasicBlock::SkipPHIsLabelsAndDebug from
273 /// repeatedly searching the same set of PHIs/Labels/Debug instructions
274 /// if it is called many times for the same block.
275 using BlockSkipInstsMap =
277 
278 namespace {
279 
280 class LDVImpl;
281 
282 /// A user value is a part of a debug info user variable.
283 ///
284 /// A DBG_VALUE instruction notes that (a sub-register of) a virtual register
285 /// holds part of a user variable. The part is identified by a byte offset.
286 ///
287 /// UserValues are grouped into equivalence classes for easier searching. Two
288 /// user values are related if they are held by the same virtual register. The
289 /// equivalence class is the transitive closure of that relation.
290 class UserValue {
291  const DILocalVariable *Variable; ///< The debug info variable we are part of.
292  /// The part of the variable we describe.
294  DebugLoc dl; ///< The debug location for the variable. This is
295  ///< used by dwarf writer to find lexical scope.
296  UserValue *leader; ///< Equivalence class leader.
297  UserValue *next = nullptr; ///< Next value in equivalence class, or null.
298 
299  /// Numbered locations referenced by locmap.
301 
302  /// Map of slot indices where this value is live.
303  LocMap locInts;
304 
305  /// Set of interval start indexes that have been trimmed to the
306  /// lexical scope.
307  SmallSet<SlotIndex, 2> trimmedDefs;
308 
309  /// Insert a DBG_VALUE into MBB at Idx for DbgValue.
310  void insertDebugValue(MachineBasicBlock *MBB, SlotIndex StartIdx,
311  SlotIndex StopIdx, DbgVariableValue DbgValue,
312  ArrayRef<bool> LocSpills,
313  ArrayRef<unsigned> SpillOffsets, LiveIntervals &LIS,
314  const TargetInstrInfo &TII,
315  const TargetRegisterInfo &TRI,
316  BlockSkipInstsMap &BBSkipInstsMap);
317 
318  /// Replace OldLocNo ranges with NewRegs ranges where NewRegs
319  /// is live. Returns true if any changes were made.
320  bool splitLocation(unsigned OldLocNo, ArrayRef<Register> NewRegs,
321  LiveIntervals &LIS);
322 
323 public:
324  /// Create a new UserValue.
325  UserValue(const DILocalVariable *var,
327  LocMap::Allocator &alloc)
328  : Variable(var), Fragment(Fragment), dl(std::move(L)), leader(this),
329  locInts(alloc) {}
330 
331  /// Get the leader of this value's equivalence class.
332  UserValue *getLeader() {
333  UserValue *l = leader;
334  while (l != l->leader)
335  l = l->leader;
336  return leader = l;
337  }
338 
339  /// Return the next UserValue in the equivalence class.
340  UserValue *getNext() const { return next; }
341 
342  /// Merge equivalence classes.
343  static UserValue *merge(UserValue *L1, UserValue *L2) {
344  L2 = L2->getLeader();
345  if (!L1)
346  return L2;
347  L1 = L1->getLeader();
348  if (L1 == L2)
349  return L1;
350  // Splice L2 before L1's members.
351  UserValue *End = L2;
352  while (End->next) {
353  End->leader = L1;
354  End = End->next;
355  }
356  End->leader = L1;
357  End->next = L1->next;
358  L1->next = L2;
359  return L1;
360  }
361 
362  /// Return the location number that matches Loc.
363  ///
364  /// For undef values we always return location number UndefLocNo without
365  /// inserting anything in locations. Since locations is a vector and the
366  /// location number is the position in the vector and UndefLocNo is ~0,
367  /// we would need a very big vector to put the value at the right position.
368  unsigned getLocationNo(const MachineOperand &LocMO) {
369  if (LocMO.isReg()) {
370  if (LocMO.getReg() == 0)
371  return UndefLocNo;
372  // For register locations we dont care about use/def and other flags.
373  for (unsigned i = 0, e = locations.size(); i != e; ++i)
374  if (locations[i].isReg() &&
375  locations[i].getReg() == LocMO.getReg() &&
376  locations[i].getSubReg() == LocMO.getSubReg())
377  return i;
378  } else
379  for (unsigned i = 0, e = locations.size(); i != e; ++i)
380  if (LocMO.isIdenticalTo(locations[i]))
381  return i;
382  locations.push_back(LocMO);
383  // We are storing a MachineOperand outside a MachineInstr.
384  locations.back().clearParent();
385  // Don't store def operands.
386  if (locations.back().isReg()) {
387  if (locations.back().isDef())
388  locations.back().setIsDead(false);
389  locations.back().setIsUse();
390  }
391  return locations.size() - 1;
392  }
393 
394  /// Remove (recycle) a location number. If \p LocNo still is used by the
395  /// locInts nothing is done.
396  void removeLocationIfUnused(unsigned LocNo) {
397  // Bail out if LocNo still is used.
398  for (LocMap::const_iterator I = locInts.begin(); I.valid(); ++I) {
399  const DbgVariableValue &DbgValue = I.value();
400  if (DbgValue.containsLocNo(LocNo))
401  return;
402  }
403  // Remove the entry in the locations vector, and adjust all references to
404  // location numbers above the removed entry.
405  locations.erase(locations.begin() + LocNo);
406  for (LocMap::iterator I = locInts.begin(); I.valid(); ++I) {
407  const DbgVariableValue &DbgValue = I.value();
408  if (DbgValue.hasLocNoGreaterThan(LocNo))
409  I.setValueUnchecked(DbgValue.decrementLocNosAfterPivot(LocNo));
410  }
411  }
412 
413  /// Ensure that all virtual register locations are mapped.
414  void mapVirtRegs(LDVImpl *LDV);
415 
416  /// Add a definition point to this user value.
417  void addDef(SlotIndex Idx, ArrayRef<MachineOperand> LocMOs, bool IsIndirect,
418  bool IsList, const DIExpression &Expr) {
420  for (const MachineOperand &Op : LocMOs)
421  Locs.push_back(getLocationNo(Op));
422  DbgVariableValue DbgValue(Locs, IsIndirect, IsList, Expr);
423  // Add a singular (Idx,Idx) -> value mapping.
424  LocMap::iterator I = locInts.find(Idx);
425  if (!I.valid() || I.start() != Idx)
426  I.insert(Idx, Idx.getNextSlot(), std::move(DbgValue));
427  else
428  // A later DBG_VALUE at the same SlotIndex overrides the old location.
429  I.setValue(std::move(DbgValue));
430  }
431 
432  /// Extend the current definition as far as possible down.
433  ///
434  /// Stop when meeting an existing def or when leaving the live
435  /// range of VNI. End points where VNI is no longer live are added to Kills.
436  ///
437  /// We only propagate DBG_VALUES locally here. LiveDebugValues performs a
438  /// data-flow analysis to propagate them beyond basic block boundaries.
439  ///
440  /// \param Idx Starting point for the definition.
441  /// \param DbgValue value to propagate.
442  /// \param LiveIntervalInfo For each location number key in this map,
443  /// restricts liveness to where the LiveRange has the value equal to the\
444  /// VNInfo.
445  /// \param [out] Kills Append end points of VNI's live range to Kills.
446  /// \param LIS Live intervals analysis.
447  void extendDef(SlotIndex Idx, DbgVariableValue DbgValue,
448  SmallDenseMap<unsigned, std::pair<LiveRange *, const VNInfo *>>
449  &LiveIntervalInfo,
450  Optional<std::pair<SlotIndex, SmallVector<unsigned>>> &Kills,
451  LiveIntervals &LIS);
452 
453  /// The value in LI may be copies to other registers. Determine if
454  /// any of the copies are available at the kill points, and add defs if
455  /// possible.
456  ///
457  /// \param DbgValue Location number of LI->reg, and DIExpression.
458  /// \param LocIntervals Scan for copies of the value for each location in the
459  /// corresponding LiveInterval->reg.
460  /// \param KilledAt The point where the range of DbgValue could be extended.
461  /// \param [in,out] NewDefs Append (Idx, DbgValue) of inserted defs here.
462  void addDefsFromCopies(
463  DbgVariableValue DbgValue,
464  SmallVectorImpl<std::pair<unsigned, LiveInterval *>> &LocIntervals,
465  SlotIndex KilledAt,
466  SmallVectorImpl<std::pair<SlotIndex, DbgVariableValue>> &NewDefs,
468 
469  /// Compute the live intervals of all locations after collecting all their
470  /// def points.
471  void computeIntervals(MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
473 
474  /// Replace OldReg ranges with NewRegs ranges where NewRegs is
475  /// live. Returns true if any changes were made.
476  bool splitRegister(Register OldReg, ArrayRef<Register> NewRegs,
477  LiveIntervals &LIS);
478 
479  /// Rewrite virtual register locations according to the provided virtual
480  /// register map. Record the stack slot offsets for the locations that
481  /// were spilled.
482  void rewriteLocations(VirtRegMap &VRM, const MachineFunction &MF,
483  const TargetInstrInfo &TII,
484  const TargetRegisterInfo &TRI,
485  SpillOffsetMap &SpillOffsets);
486 
487  /// Recreate DBG_VALUE instruction from data structures.
488  void emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
489  const TargetInstrInfo &TII,
490  const TargetRegisterInfo &TRI,
491  const SpillOffsetMap &SpillOffsets,
492  BlockSkipInstsMap &BBSkipInstsMap);
493 
494  /// Return DebugLoc of this UserValue.
495  const DebugLoc &getDebugLoc() { return dl; }
496 
497  void print(raw_ostream &, const TargetRegisterInfo *);
498 };
499 
500 /// A user label is a part of a debug info user label.
501 class UserLabel {
502  const DILabel *Label; ///< The debug info label we are part of.
503  DebugLoc dl; ///< The debug location for the label. This is
504  ///< used by dwarf writer to find lexical scope.
505  SlotIndex loc; ///< Slot used by the debug label.
506 
507  /// Insert a DBG_LABEL into MBB at Idx.
508  void insertDebugLabel(MachineBasicBlock *MBB, SlotIndex Idx,
509  LiveIntervals &LIS, const TargetInstrInfo &TII,
510  BlockSkipInstsMap &BBSkipInstsMap);
511 
512 public:
513  /// Create a new UserLabel.
514  UserLabel(const DILabel *label, DebugLoc L, SlotIndex Idx)
515  : Label(label), dl(std::move(L)), loc(Idx) {}
516 
517  /// Does this UserLabel match the parameters?
518  bool matches(const DILabel *L, const DILocation *IA,
519  const SlotIndex Index) const {
520  return Label == L && dl->getInlinedAt() == IA && loc == Index;
521  }
522 
523  /// Recreate DBG_LABEL instruction from data structures.
524  void emitDebugLabel(LiveIntervals &LIS, const TargetInstrInfo &TII,
525  BlockSkipInstsMap &BBSkipInstsMap);
526 
527  /// Return DebugLoc of this UserLabel.
528  const DebugLoc &getDebugLoc() { return dl; }
529 
530  void print(raw_ostream &, const TargetRegisterInfo *);
531 };
532 
533 /// Implementation of the LiveDebugVariables pass.
534 class LDVImpl {
537  MachineFunction *MF = nullptr;
538  LiveIntervals *LIS;
539  const TargetRegisterInfo *TRI;
540 
541  /// Position and VReg of a PHI instruction during register allocation.
542  struct PHIValPos {
543  SlotIndex SI; /// Slot where this PHI occurs.
544  Register Reg; /// VReg this PHI occurs in.
545  unsigned SubReg; /// Qualifiying subregister for Reg.
546  };
547 
548  /// Map from debug instruction number to PHI position during allocation.
549  std::map<unsigned, PHIValPos> PHIValToPos;
550  /// Index of, for each VReg, which debug instruction numbers and corresponding
551  /// PHIs are sensitive to splitting. Each VReg may have multiple PHI defs,
552  /// at different positions.
554 
555  /// Record for any debug instructions unlinked from their blocks during
556  /// regalloc. Stores the instr and it's location, so that they can be
557  /// re-inserted after regalloc is over.
558  struct InstrPos {
559  MachineInstr *MI; ///< Debug instruction, unlinked from it's block.
560  SlotIndex Idx; ///< Slot position where MI should be re-inserted.
561  MachineBasicBlock *MBB; ///< Block that MI was in.
562  };
563 
564  /// Collection of stored debug instructions, preserved until after regalloc.
565  SmallVector<InstrPos, 32> StashedDebugInstrs;
566 
567  /// Whether emitDebugValues is called.
568  bool EmitDone = false;
569 
570  /// Whether the machine function is modified during the pass.
571  bool ModifiedMF = false;
572 
573  /// All allocated UserValue instances.
575 
576  /// All allocated UserLabel instances.
578 
579  /// Map virtual register to eq class leader.
580  using VRMap = DenseMap<unsigned, UserValue *>;
581  VRMap virtRegToEqClass;
582 
583  /// Map to find existing UserValue instances.
585  UVMap userVarMap;
586 
587  /// Find or create a UserValue.
588  UserValue *getUserValue(const DILocalVariable *Var,
590  const DebugLoc &DL);
591 
592  /// Find the EC leader for VirtReg or null.
593  UserValue *lookupVirtReg(Register VirtReg);
594 
595  /// Add DBG_VALUE instruction to our maps.
596  ///
597  /// \param MI DBG_VALUE instruction
598  /// \param Idx Last valid SLotIndex before instruction.
599  ///
600  /// \returns True if the DBG_VALUE instruction should be deleted.
601  bool handleDebugValue(MachineInstr &MI, SlotIndex Idx);
602 
603  /// Track variable location debug instructions while using the instruction
604  /// referencing implementation. Such debug instructions do not need to be
605  /// updated during regalloc because they identify instructions rather than
606  /// register locations. However, they needs to be removed from the
607  /// MachineFunction during regalloc, then re-inserted later, to avoid
608  /// disrupting the allocator.
609  ///
610  /// \param MI Any DBG_VALUE / DBG_INSTR_REF / DBG_PHI instruction
611  /// \param Idx Last valid SlotIndex before instruction
612  ///
613  /// \returns Iterator to continue processing from after unlinking.
614  MachineBasicBlock::iterator handleDebugInstr(MachineInstr &MI, SlotIndex Idx);
615 
616  /// Add DBG_LABEL instruction to UserLabel.
617  ///
618  /// \param MI DBG_LABEL instruction
619  /// \param Idx Last valid SlotIndex before instruction.
620  ///
621  /// \returns True if the DBG_LABEL instruction should be deleted.
622  bool handleDebugLabel(MachineInstr &MI, SlotIndex Idx);
623 
624  /// Collect and erase all DBG_VALUE instructions, adding a UserValue def
625  /// for each instruction.
626  ///
627  /// \param mf MachineFunction to be scanned.
628  /// \param InstrRef Whether to operate in instruction referencing mode. If
629  /// true, most of LiveDebugVariables doesn't run.
630  ///
631  /// \returns True if any debug values were found.
632  bool collectDebugValues(MachineFunction &mf, bool InstrRef);
633 
634  /// Compute the live intervals of all user values after collecting all
635  /// their def points.
636  void computeIntervals();
637 
638 public:
639  LDVImpl(LiveDebugVariables *ps) : pass(*ps) {}
640 
641  bool runOnMachineFunction(MachineFunction &mf, bool InstrRef);
642 
643  /// Release all memory.
644  void clear() {
645  MF = nullptr;
646  PHIValToPos.clear();
647  RegToPHIIdx.clear();
648  StashedDebugInstrs.clear();
649  userValues.clear();
650  userLabels.clear();
651  virtRegToEqClass.clear();
652  userVarMap.clear();
653  // Make sure we call emitDebugValues if the machine function was modified.
654  assert((!ModifiedMF || EmitDone) &&
655  "Dbg values are not emitted in LDV");
656  EmitDone = false;
657  ModifiedMF = false;
658  }
659 
660  /// Map virtual register to an equivalence class.
661  void mapVirtReg(Register VirtReg, UserValue *EC);
662 
663  /// Replace any PHI referring to OldReg with its corresponding NewReg, if
664  /// present.
665  void splitPHIRegister(Register OldReg, ArrayRef<Register> NewRegs);
666 
667  /// Replace all references to OldReg with NewRegs.
668  void splitRegister(Register OldReg, ArrayRef<Register> NewRegs);
669 
670  /// Recreate DBG_VALUE instruction from data structures.
671  void emitDebugValues(VirtRegMap *VRM);
672 
673  void print(raw_ostream&);
674 };
675 
676 } // end anonymous namespace
677 
678 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
679 static void printDebugLoc(const DebugLoc &DL, raw_ostream &CommentOS,
680  const LLVMContext &Ctx) {
681  if (!DL)
682  return;
683 
684  auto *Scope = cast<DIScope>(DL.getScope());
685  // Omit the directory, because it's likely to be long and uninteresting.
686  CommentOS << Scope->getFilename();
687  CommentOS << ':' << DL.getLine();
688  if (DL.getCol() != 0)
689  CommentOS << ':' << DL.getCol();
690 
691  DebugLoc InlinedAtDL = DL.getInlinedAt();
692  if (!InlinedAtDL)
693  return;
694 
695  CommentOS << " @[ ";
696  printDebugLoc(InlinedAtDL, CommentOS, Ctx);
697  CommentOS << " ]";
698 }
699 
700 static void printExtendedName(raw_ostream &OS, const DINode *Node,
701  const DILocation *DL) {
702  const LLVMContext &Ctx = Node->getContext();
703  StringRef Res;
704  unsigned Line = 0;
705  if (const auto *V = dyn_cast<const DILocalVariable>(Node)) {
706  Res = V->getName();
707  Line = V->getLine();
708  } else if (const auto *L = dyn_cast<const DILabel>(Node)) {
709  Res = L->getName();
710  Line = L->getLine();
711  }
712 
713  if (!Res.empty())
714  OS << Res << "," << Line;
715  auto *InlinedAt = DL ? DL->getInlinedAt() : nullptr;
716  if (InlinedAt) {
717  if (DebugLoc InlinedAtDL = InlinedAt) {
718  OS << " @[";
719  printDebugLoc(InlinedAtDL, OS, Ctx);
720  OS << "]";
721  }
722  }
723 }
724 
726  OS << "!\"";
727  printExtendedName(OS, Variable, dl);
728 
729  OS << "\"\t";
730  for (LocMap::const_iterator I = locInts.begin(); I.valid(); ++I) {
731  OS << " [" << I.start() << ';' << I.stop() << "):";
732  if (I.value().isUndef())
733  OS << " undef";
734  else {
735  I.value().printLocNos(OS);
736  if (I.value().getWasIndirect())
737  OS << " ind";
738  else if (I.value().getWasList())
739  OS << " list";
740  }
741  }
742  for (unsigned i = 0, e = locations.size(); i != e; ++i) {
743  OS << " Loc" << i << '=';
744  locations[i].print(OS, TRI);
745  }
746  OS << '\n';
747 }
748 
750  OS << "!\"";
751  printExtendedName(OS, Label, dl);
752 
753  OS << "\"\t";
754  OS << loc;
755  OS << '\n';
756 }
757 
758 void LDVImpl::print(raw_ostream &OS) {
759  OS << "********** DEBUG VARIABLES **********\n";
760  for (auto &userValue : userValues)
761  userValue->print(OS, TRI);
762  OS << "********** DEBUG LABELS **********\n";
763  for (auto &userLabel : userLabels)
764  userLabel->print(OS, TRI);
765 }
766 #endif
767 
768 void UserValue::mapVirtRegs(LDVImpl *LDV) {
769  for (unsigned i = 0, e = locations.size(); i != e; ++i)
770  if (locations[i].isReg() &&
771  Register::isVirtualRegister(locations[i].getReg()))
772  LDV->mapVirtReg(locations[i].getReg(), this);
773 }
774 
775 UserValue *LDVImpl::getUserValue(const DILocalVariable *Var,
777  const DebugLoc &DL) {
778  // FIXME: Handle partially overlapping fragments. See
779  // https://reviews.llvm.org/D70121#1849741.
780  DebugVariable ID(Var, Fragment, DL->getInlinedAt());
781  UserValue *&UV = userVarMap[ID];
782  if (!UV) {
783  userValues.push_back(
784  std::make_unique<UserValue>(Var, Fragment, DL, allocator));
785  UV = userValues.back().get();
786  }
787  return UV;
788 }
789 
790 void LDVImpl::mapVirtReg(Register VirtReg, UserValue *EC) {
791  assert(Register::isVirtualRegister(VirtReg) && "Only map VirtRegs");
792  UserValue *&Leader = virtRegToEqClass[VirtReg];
793  Leader = UserValue::merge(Leader, EC);
794 }
795 
796 UserValue *LDVImpl::lookupVirtReg(Register VirtReg) {
797  if (UserValue *UV = virtRegToEqClass.lookup(VirtReg))
798  return UV->getLeader();
799  return nullptr;
800 }
801 
802 bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotIndex Idx) {
803  // DBG_VALUE loc, offset, variable, expr
804  // DBG_VALUE_LIST variable, expr, locs...
805  if (!MI.isDebugValue()) {
806  LLVM_DEBUG(dbgs() << "Can't handle non-DBG_VALUE*: " << MI);
807  return false;
808  }
809  if (!MI.getDebugVariableOp().isMetadata()) {
810  LLVM_DEBUG(dbgs() << "Can't handle DBG_VALUE* with invalid variable: "
811  << MI);
812  return false;
813  }
814  if (MI.isNonListDebugValue() &&
815  (MI.getNumOperands() != 4 ||
816  !(MI.getDebugOffset().isImm() || MI.getDebugOffset().isReg()))) {
817  LLVM_DEBUG(dbgs() << "Can't handle malformed DBG_VALUE: " << MI);
818  return false;
819  }
820 
821  // Detect invalid DBG_VALUE instructions, with a debug-use of a virtual
822  // register that hasn't been defined yet. If we do not remove those here, then
823  // the re-insertion of the DBG_VALUE instruction after register allocation
824  // will be incorrect.
825  bool Discard = false;
826  for (const MachineOperand &Op : MI.debug_operands()) {
827  if (Op.isReg() && Register::isVirtualRegister(Op.getReg())) {
828  const Register Reg = Op.getReg();
829  if (!LIS->hasInterval(Reg)) {
830  // The DBG_VALUE is described by a virtual register that does not have a
831  // live interval. Discard the DBG_VALUE.
832  Discard = true;
833  LLVM_DEBUG(dbgs() << "Discarding debug info (no LIS interval): " << Idx
834  << " " << MI);
835  } else {
836  // The DBG_VALUE is only valid if either Reg is live out from Idx, or
837  // Reg is defined dead at Idx (where Idx is the slot index for the
838  // instruction preceding the DBG_VALUE).
839  const LiveInterval &LI = LIS->getInterval(Reg);
840  LiveQueryResult LRQ = LI.Query(Idx);
841  if (!LRQ.valueOutOrDead()) {
842  // We have found a DBG_VALUE with the value in a virtual register that
843  // is not live. Discard the DBG_VALUE.
844  Discard = true;
845  LLVM_DEBUG(dbgs() << "Discarding debug info (reg not live): " << Idx
846  << " " << MI);
847  }
848  }
849  }
850  }
851 
852  // Get or create the UserValue for (variable,offset) here.
853  bool IsIndirect = MI.isDebugOffsetImm();
854  if (IsIndirect)
855  assert(MI.getDebugOffset().getImm() == 0 &&
856  "DBG_VALUE with nonzero offset");
857  bool IsList = MI.isDebugValueList();
858  const DILocalVariable *Var = MI.getDebugVariable();
859  const DIExpression *Expr = MI.getDebugExpression();
860  UserValue *UV = getUserValue(Var, Expr->getFragmentInfo(), MI.getDebugLoc());
861  if (!Discard)
862  UV->addDef(Idx,
863  ArrayRef<MachineOperand>(MI.debug_operands().begin(),
864  MI.debug_operands().end()),
865  IsIndirect, IsList, *Expr);
866  else {
868  MO.setIsDebug();
869  // We should still pass a list the same size as MI.debug_operands() even if
870  // all MOs are undef, so that DbgVariableValue can correctly adjust the
871  // expression while removing the duplicated undefs.
872  SmallVector<MachineOperand, 4> UndefMOs(MI.getNumDebugOperands(), MO);
873  UV->addDef(Idx, UndefMOs, false, IsList, *Expr);
874  }
875  return true;
876 }
877 
878 MachineBasicBlock::iterator LDVImpl::handleDebugInstr(MachineInstr &MI,
879  SlotIndex Idx) {
880  assert(MI.isDebugValue() || MI.isDebugRef() || MI.isDebugPHI());
881 
882  // In instruction referencing mode, there should be no DBG_VALUE instructions
883  // that refer to virtual registers. They might still refer to constants.
884  if (MI.isDebugValue())
885  assert(!MI.getOperand(0).isReg() || !MI.getOperand(0).getReg().isVirtual());
886 
887  // Unlink the instruction, store it in the debug instructions collection.
888  auto NextInst = std::next(MI.getIterator());
889  auto *MBB = MI.getParent();
890  MI.removeFromParent();
891  StashedDebugInstrs.push_back({&MI, Idx, MBB});
892  return NextInst;
893 }
894 
895 bool LDVImpl::handleDebugLabel(MachineInstr &MI, SlotIndex Idx) {
896  // DBG_LABEL label
897  if (MI.getNumOperands() != 1 || !MI.getOperand(0).isMetadata()) {
898  LLVM_DEBUG(dbgs() << "Can't handle " << MI);
899  return false;
900  }
901 
902  // Get or create the UserLabel for label here.
903  const DILabel *Label = MI.getDebugLabel();
904  const DebugLoc &DL = MI.getDebugLoc();
905  bool Found = false;
906  for (auto const &L : userLabels) {
907  if (L->matches(Label, DL->getInlinedAt(), Idx)) {
908  Found = true;
909  break;
910  }
911  }
912  if (!Found)
913  userLabels.push_back(std::make_unique<UserLabel>(Label, DL, Idx));
914 
915  return true;
916 }
917 
918 bool LDVImpl::collectDebugValues(MachineFunction &mf, bool InstrRef) {
919  bool Changed = false;
920  for (MachineBasicBlock &MBB : mf) {
921  for (MachineBasicBlock::iterator MBBI = MBB.begin(), MBBE = MBB.end();
922  MBBI != MBBE;) {
923  // Use the first debug instruction in the sequence to get a SlotIndex
924  // for following consecutive debug instructions.
925  if (!MBBI->isDebugOrPseudoInstr()) {
926  ++MBBI;
927  continue;
928  }
929  // Debug instructions has no slot index. Use the previous
930  // non-debug instruction's SlotIndex as its SlotIndex.
931  SlotIndex Idx =
932  MBBI == MBB.begin()
933  ? LIS->getMBBStartIdx(&MBB)
934  : LIS->getInstructionIndex(*std::prev(MBBI)).getRegSlot();
935  // Handle consecutive debug instructions with the same slot index.
936  do {
937  // In instruction referencing mode, pass each instr to handleDebugInstr
938  // to be unlinked. Ignore DBG_VALUE_LISTs -- they refer to vregs, and
939  // need to go through the normal live interval splitting process.
940  if (InstrRef && (MBBI->isNonListDebugValue() || MBBI->isDebugPHI() ||
941  MBBI->isDebugRef())) {
942  MBBI = handleDebugInstr(*MBBI, Idx);
943  Changed = true;
944  // In normal debug mode, use the dedicated DBG_VALUE / DBG_LABEL handler
945  // to track things through register allocation, and erase the instr.
946  } else if ((MBBI->isDebugValue() && handleDebugValue(*MBBI, Idx)) ||
947  (MBBI->isDebugLabel() && handleDebugLabel(*MBBI, Idx))) {
948  MBBI = MBB.erase(MBBI);
949  Changed = true;
950  } else
951  ++MBBI;
952  } while (MBBI != MBBE && MBBI->isDebugOrPseudoInstr());
953  }
954  }
955  return Changed;
956 }
957 
958 void UserValue::extendDef(
959  SlotIndex Idx, DbgVariableValue DbgValue,
960  SmallDenseMap<unsigned, std::pair<LiveRange *, const VNInfo *>>
961  &LiveIntervalInfo,
962  Optional<std::pair<SlotIndex, SmallVector<unsigned>>> &Kills,
963  LiveIntervals &LIS) {
964  SlotIndex Start = Idx;
965  MachineBasicBlock *MBB = LIS.getMBBFromIndex(Start);
966  SlotIndex Stop = LIS.getMBBEndIdx(MBB);
967  LocMap::iterator I = locInts.find(Start);
968 
969  // Limit to the intersection of the VNIs' live ranges.
970  for (auto &LII : LiveIntervalInfo) {
971  LiveRange *LR = LII.second.first;
972  assert(LR && LII.second.second && "Missing range info for Idx.");
973  LiveInterval::Segment *Segment = LR->getSegmentContaining(Start);
974  assert(Segment && Segment->valno == LII.second.second &&
975  "Invalid VNInfo for Idx given?");
976  if (Segment->end < Stop) {
977  Stop = Segment->end;
978  Kills = {Stop, {LII.first}};
979  } else if (Segment->end == Stop && Kills.hasValue()) {
980  // If multiple locations end at the same place, track all of them in
981  // Kills.
982  Kills->second.push_back(LII.first);
983  }
984  }
985 
986  // There could already be a short def at Start.
987  if (I.valid() && I.start() <= Start) {
988  // Stop when meeting a different location or an already extended interval.
989  Start = Start.getNextSlot();
990  if (I.value() != DbgValue || I.stop() != Start) {
991  // Clear `Kills`, as we have a new def available.
992  Kills = None;
993  return;
994  }
995  // This is a one-slot placeholder. Just skip it.
996  ++I;
997  }
998 
999  // Limited by the next def.
1000  if (I.valid() && I.start() < Stop) {
1001  Stop = I.start();
1002  // Clear `Kills`, as we have a new def available.
1003  Kills = None;
1004  }
1005 
1006  if (Start < Stop) {
1007  DbgVariableValue ExtDbgValue(DbgValue);
1008  I.insert(Start, Stop, std::move(ExtDbgValue));
1009  }
1010 }
1011 
1012 void UserValue::addDefsFromCopies(
1013  DbgVariableValue DbgValue,
1014  SmallVectorImpl<std::pair<unsigned, LiveInterval *>> &LocIntervals,
1015  SlotIndex KilledAt,
1016  SmallVectorImpl<std::pair<SlotIndex, DbgVariableValue>> &NewDefs,
1018  // Don't track copies from physregs, there are too many uses.
1019  if (any_of(LocIntervals, [](auto LocI) {
1020  return !Register::isVirtualRegister(LocI.second->reg());
1021  }))
1022  return;
1023 
1024  // Collect all the (vreg, valno) pairs that are copies of LI.
1025  SmallDenseMap<unsigned,
1027  CopyValues;
1028  for (auto &LocInterval : LocIntervals) {
1029  unsigned LocNo = LocInterval.first;
1030  LiveInterval *LI = LocInterval.second;
1031  for (MachineOperand &MO : MRI.use_nodbg_operands(LI->reg())) {
1032  MachineInstr *MI = MO.getParent();
1033  // Copies of the full value.
1034  if (MO.getSubReg() || !MI->isCopy())
1035  continue;
1036  Register DstReg = MI->getOperand(0).getReg();
1037 
1038  // Don't follow copies to physregs. These are usually setting up call
1039  // arguments, and the argument registers are always call clobbered. We are
1040  // better off in the source register which could be a callee-saved
1041  // register, or it could be spilled.
1042  if (!Register::isVirtualRegister(DstReg))
1043  continue;
1044 
1045  // Is the value extended to reach this copy? If not, another def may be
1046  // blocking it, or we are looking at a wrong value of LI.
1047  SlotIndex Idx = LIS.getInstructionIndex(*MI);
1048  LocMap::iterator I = locInts.find(Idx.getRegSlot(true));
1049  if (!I.valid() || I.value() != DbgValue)
1050  continue;
1051 
1052  if (!LIS.hasInterval(DstReg))
1053  continue;
1054  LiveInterval *DstLI = &LIS.getInterval(DstReg);
1055  const VNInfo *DstVNI = DstLI->getVNInfoAt(Idx.getRegSlot());
1056  assert(DstVNI && DstVNI->def == Idx.getRegSlot() && "Bad copy value");
1057  CopyValues[LocNo].push_back(std::make_pair(DstLI, DstVNI));
1058  }
1059  }
1060 
1061  if (CopyValues.empty())
1062  return;
1063 
1064 #if !defined(NDEBUG)
1065  for (auto &LocInterval : LocIntervals)
1066  LLVM_DEBUG(dbgs() << "Got " << CopyValues[LocInterval.first].size()
1067  << " copies of " << *LocInterval.second << '\n');
1068 #endif
1069 
1070  // Try to add defs of the copied values for the kill point. Check that there
1071  // isn't already a def at Idx.
1072  LocMap::iterator I = locInts.find(KilledAt);
1073  if (I.valid() && I.start() <= KilledAt)
1074  return;
1075  DbgVariableValue NewValue(DbgValue);
1076  for (auto &LocInterval : LocIntervals) {
1077  unsigned LocNo = LocInterval.first;
1078  bool FoundCopy = false;
1079  for (auto &LIAndVNI : CopyValues[LocNo]) {
1080  LiveInterval *DstLI = LIAndVNI.first;
1081  const VNInfo *DstVNI = LIAndVNI.second;
1082  if (DstLI->getVNInfoAt(KilledAt) != DstVNI)
1083  continue;
1084  LLVM_DEBUG(dbgs() << "Kill at " << KilledAt << " covered by valno #"
1085  << DstVNI->id << " in " << *DstLI << '\n');
1086  MachineInstr *CopyMI = LIS.getInstructionFromIndex(DstVNI->def);
1087  assert(CopyMI && CopyMI->isCopy() && "Bad copy value");
1088  unsigned NewLocNo = getLocationNo(CopyMI->getOperand(0));
1089  NewValue = NewValue.changeLocNo(LocNo, NewLocNo);
1090  FoundCopy = true;
1091  break;
1092  }
1093  // If there are any killed locations we can't find a copy for, we can't
1094  // extend the variable value.
1095  if (!FoundCopy)
1096  return;
1097  }
1098  I.insert(KilledAt, KilledAt.getNextSlot(), NewValue);
1099  NewDefs.push_back(std::make_pair(KilledAt, NewValue));
1100 }
1101 
1102 void UserValue::computeIntervals(MachineRegisterInfo &MRI,
1103  const TargetRegisterInfo &TRI,
1104  LiveIntervals &LIS, LexicalScopes &LS) {
1106 
1107  // Collect all defs to be extended (Skipping undefs).
1108  for (LocMap::const_iterator I = locInts.begin(); I.valid(); ++I)
1109  if (!I.value().isUndef())
1110  Defs.push_back(std::make_pair(I.start(), I.value()));
1111 
1112  // Extend all defs, and possibly add new ones along the way.
1113  for (unsigned i = 0; i != Defs.size(); ++i) {
1114  SlotIndex Idx = Defs[i].first;
1115  DbgVariableValue DbgValue = Defs[i].second;
1118  bool ShouldExtendDef = false;
1119  for (unsigned LocNo : DbgValue.loc_nos()) {
1120  const MachineOperand &LocMO = locations[LocNo];
1121  if (!LocMO.isReg() || !Register::isVirtualRegister(LocMO.getReg())) {
1122  ShouldExtendDef |= !LocMO.isReg();
1123  continue;
1124  }
1125  ShouldExtendDef = true;
1126  LiveInterval *LI = nullptr;
1127  const VNInfo *VNI = nullptr;
1128  if (LIS.hasInterval(LocMO.getReg())) {
1129  LI = &LIS.getInterval(LocMO.getReg());
1130  VNI = LI->getVNInfoAt(Idx);
1131  }
1132  if (LI && VNI)
1133  LIs[LocNo] = {LI, VNI};
1134  }
1135  if (ShouldExtendDef) {
1137  extendDef(Idx, DbgValue, LIs, Kills, LIS);
1138 
1139  if (Kills) {
1140  SmallVector<std::pair<unsigned, LiveInterval *>, 2> KilledLocIntervals;
1141  bool AnySubreg = false;
1142  for (unsigned LocNo : Kills->second) {
1143  const MachineOperand &LocMO = this->locations[LocNo];
1144  if (LocMO.getSubReg()) {
1145  AnySubreg = true;
1146  break;
1147  }
1148  LiveInterval *LI = &LIS.getInterval(LocMO.getReg());
1149  KilledLocIntervals.push_back({LocNo, LI});
1150  }
1151 
1152  // FIXME: Handle sub-registers in addDefsFromCopies. The problem is that
1153  // if the original location for example is %vreg0:sub_hi, and we find a
1154  // full register copy in addDefsFromCopies (at the moment it only
1155  // handles full register copies), then we must add the sub1 sub-register
1156  // index to the new location. However, that is only possible if the new
1157  // virtual register is of the same regclass (or if there is an
1158  // equivalent sub-register in that regclass). For now, simply skip
1159  // handling copies if a sub-register is involved.
1160  if (!AnySubreg)
1161  addDefsFromCopies(DbgValue, KilledLocIntervals, Kills->first, Defs,
1162  MRI, LIS);
1163  }
1164  }
1165 
1166  // For physregs, we only mark the start slot idx. DwarfDebug will see it
1167  // as if the DBG_VALUE is valid up until the end of the basic block, or
1168  // the next def of the physical register. So we do not need to extend the
1169  // range. It might actually happen that the DBG_VALUE is the last use of
1170  // the physical register (e.g. if this is an unused input argument to a
1171  // function).
1172  }
1173 
1174  // The computed intervals may extend beyond the range of the debug
1175  // location's lexical scope. In this case, splitting of an interval
1176  // can result in an interval outside of the scope being created,
1177  // causing extra unnecessary DBG_VALUEs to be emitted. To prevent
1178  // this, trim the intervals to the lexical scope in the case of inlined
1179  // variables, since heavy inlining may cause production of dramatically big
1180  // number of DBG_VALUEs to be generated.
1181  if (!dl.getInlinedAt())
1182  return;
1183 
1184  LexicalScope *Scope = LS.findLexicalScope(dl);
1185  if (!Scope)
1186  return;
1187 
1188  SlotIndex PrevEnd;
1189  LocMap::iterator I = locInts.begin();
1190 
1191  // Iterate over the lexical scope ranges. Each time round the loop
1192  // we check the intervals for overlap with the end of the previous
1193  // range and the start of the next. The first range is handled as
1194  // a special case where there is no PrevEnd.
1195  for (const InsnRange &Range : Scope->getRanges()) {
1196  SlotIndex RStart = LIS.getInstructionIndex(*Range.first);
1197  SlotIndex REnd = LIS.getInstructionIndex(*Range.second);
1198 
1199  // Variable locations at the first instruction of a block should be
1200  // based on the block's SlotIndex, not the first instruction's index.
1201  if (Range.first == Range.first->getParent()->begin())
1202  RStart = LIS.getSlotIndexes()->getIndexBefore(*Range.first);
1203 
1204  // At the start of each iteration I has been advanced so that
1205  // I.stop() >= PrevEnd. Check for overlap.
1206  if (PrevEnd && I.start() < PrevEnd) {
1207  SlotIndex IStop = I.stop();
1208  DbgVariableValue DbgValue = I.value();
1209 
1210  // Stop overlaps previous end - trim the end of the interval to
1211  // the scope range.
1212  I.setStopUnchecked(PrevEnd);
1213  ++I;
1214 
1215  // If the interval also overlaps the start of the "next" (i.e.
1216  // current) range create a new interval for the remainder (which
1217  // may be further trimmed).
1218  if (RStart < IStop)
1219  I.insert(RStart, IStop, DbgValue);
1220  }
1221 
1222  // Advance I so that I.stop() >= RStart, and check for overlap.
1223  I.advanceTo(RStart);
1224  if (!I.valid())
1225  return;
1226 
1227  if (I.start() < RStart) {
1228  // Interval start overlaps range - trim to the scope range.
1229  I.setStartUnchecked(RStart);
1230  // Remember that this interval was trimmed.
1231  trimmedDefs.insert(RStart);
1232  }
1233 
1234  // The end of a lexical scope range is the last instruction in the
1235  // range. To convert to an interval we need the index of the
1236  // instruction after it.
1237  REnd = REnd.getNextIndex();
1238 
1239  // Advance I to first interval outside current range.
1240  I.advanceTo(REnd);
1241  if (!I.valid())
1242  return;
1243 
1244  PrevEnd = REnd;
1245  }
1246 
1247  // Check for overlap with end of final range.
1248  if (PrevEnd && I.start() < PrevEnd)
1249  I.setStopUnchecked(PrevEnd);
1250 }
1251 
1252 void LDVImpl::computeIntervals() {
1253  LexicalScopes LS;
1254  LS.initialize(*MF);
1255 
1256  for (unsigned i = 0, e = userValues.size(); i != e; ++i) {
1257  userValues[i]->computeIntervals(MF->getRegInfo(), *TRI, *LIS, LS);
1258  userValues[i]->mapVirtRegs(this);
1259  }
1260 }
1261 
1262 bool LDVImpl::runOnMachineFunction(MachineFunction &mf, bool InstrRef) {
1263  clear();
1264  MF = &mf;
1265  LIS = &pass.getAnalysis<LiveIntervals>();
1266  TRI = mf.getSubtarget().getRegisterInfo();
1267  LLVM_DEBUG(dbgs() << "********** COMPUTING LIVE DEBUG VARIABLES: "
1268  << mf.getName() << " **********\n");
1269 
1270  bool Changed = collectDebugValues(mf, InstrRef);
1271  computeIntervals();
1272  LLVM_DEBUG(print(dbgs()));
1273 
1274  // Collect the set of VReg / SlotIndexs where PHIs occur; index the sensitive
1275  // VRegs too, for when we're notified of a range split.
1276  SlotIndexes *Slots = LIS->getSlotIndexes();
1277  for (const auto &PHIIt : MF->DebugPHIPositions) {
1278  const MachineFunction::DebugPHIRegallocPos &Position = PHIIt.second;
1279  MachineBasicBlock *MBB = Position.MBB;
1280  Register Reg = Position.Reg;
1281  unsigned SubReg = Position.SubReg;
1282  SlotIndex SI = Slots->getMBBStartIdx(MBB);
1283  PHIValPos VP = {SI, Reg, SubReg};
1284  PHIValToPos.insert(std::make_pair(PHIIt.first, VP));
1285  RegToPHIIdx[Reg].push_back(PHIIt.first);
1286  }
1287 
1288  ModifiedMF = Changed;
1289  return Changed;
1290 }
1291 
1293  for (MachineBasicBlock &MBB : mf) {
1295  if (MI.isDebugInstr())
1296  MBB.erase(&MI);
1297  }
1298 }
1299 
1300 bool LiveDebugVariables::runOnMachineFunction(MachineFunction &mf) {
1301  if (!EnableLDV)
1302  return false;
1303  if (!mf.getFunction().getSubprogram()) {
1304  removeDebugInstrs(mf);
1305  return false;
1306  }
1307 
1308  // Have we been asked to track variable locations using instruction
1309  // referencing?
1310  bool InstrRef = mf.useDebugInstrRef();
1311 
1312  if (!pImpl)
1313  pImpl = new LDVImpl(this);
1314  return static_cast<LDVImpl *>(pImpl)->runOnMachineFunction(mf, InstrRef);
1315 }
1316 
1317 void LiveDebugVariables::releaseMemory() {
1318  if (pImpl)
1319  static_cast<LDVImpl*>(pImpl)->clear();
1320 }
1321 
1323  if (pImpl)
1324  delete static_cast<LDVImpl*>(pImpl);
1325 }
1326 
1327 //===----------------------------------------------------------------------===//
1328 // Live Range Splitting
1329 //===----------------------------------------------------------------------===//
1330 
1331 bool
1332 UserValue::splitLocation(unsigned OldLocNo, ArrayRef<Register> NewRegs,
1333  LiveIntervals& LIS) {
1334  LLVM_DEBUG({
1335  dbgs() << "Splitting Loc" << OldLocNo << '\t';
1336  print(dbgs(), nullptr);
1337  });
1338  bool DidChange = false;
1339  LocMap::iterator LocMapI;
1340  LocMapI.setMap(locInts);
1341  for (Register NewReg : NewRegs) {
1342  LiveInterval *LI = &LIS.getInterval(NewReg);
1343  if (LI->empty())
1344  continue;
1345 
1346  // Don't allocate the new LocNo until it is needed.
1347  unsigned NewLocNo = UndefLocNo;
1348 
1349  // Iterate over the overlaps between locInts and LI.
1350  LocMapI.find(LI->beginIndex());
1351  if (!LocMapI.valid())
1352  continue;
1353  LiveInterval::iterator LII = LI->advanceTo(LI->begin(), LocMapI.start());
1354  LiveInterval::iterator LIE = LI->end();
1355  while (LocMapI.valid() && LII != LIE) {
1356  // At this point, we know that LocMapI.stop() > LII->start.
1357  LII = LI->advanceTo(LII, LocMapI.start());
1358  if (LII == LIE)
1359  break;
1360 
1361  // Now LII->end > LocMapI.start(). Do we have an overlap?
1362  if (LocMapI.value().containsLocNo(OldLocNo) &&
1363  LII->start < LocMapI.stop()) {
1364  // Overlapping correct location. Allocate NewLocNo now.
1365  if (NewLocNo == UndefLocNo) {
1366  MachineOperand MO = MachineOperand::CreateReg(LI->reg(), false);
1367  MO.setSubReg(locations[OldLocNo].getSubReg());
1368  NewLocNo = getLocationNo(MO);
1369  DidChange = true;
1370  }
1371 
1372  SlotIndex LStart = LocMapI.start();
1373  SlotIndex LStop = LocMapI.stop();
1374  DbgVariableValue OldDbgValue = LocMapI.value();
1375 
1376  // Trim LocMapI down to the LII overlap.
1377  if (LStart < LII->start)
1378  LocMapI.setStartUnchecked(LII->start);
1379  if (LStop > LII->end)
1380  LocMapI.setStopUnchecked(LII->end);
1381 
1382  // Change the value in the overlap. This may trigger coalescing.
1383  LocMapI.setValue(OldDbgValue.changeLocNo(OldLocNo, NewLocNo));
1384 
1385  // Re-insert any removed OldDbgValue ranges.
1386  if (LStart < LocMapI.start()) {
1387  LocMapI.insert(LStart, LocMapI.start(), OldDbgValue);
1388  ++LocMapI;
1389  assert(LocMapI.valid() && "Unexpected coalescing");
1390  }
1391  if (LStop > LocMapI.stop()) {
1392  ++LocMapI;
1393  LocMapI.insert(LII->end, LStop, OldDbgValue);
1394  --LocMapI;
1395  }
1396  }
1397 
1398  // Advance to the next overlap.
1399  if (LII->end < LocMapI.stop()) {
1400  if (++LII == LIE)
1401  break;
1402  LocMapI.advanceTo(LII->start);
1403  } else {
1404  ++LocMapI;
1405  if (!LocMapI.valid())
1406  break;
1407  LII = LI->advanceTo(LII, LocMapI.start());
1408  }
1409  }
1410  }
1411 
1412  // Finally, remove OldLocNo unless it is still used by some interval in the
1413  // locInts map. One case when OldLocNo still is in use is when the register
1414  // has been spilled. In such situations the spilled register is kept as a
1415  // location until rewriteLocations is called (VirtRegMap is mapping the old
1416  // register to the spill slot). So for a while we can have locations that map
1417  // to virtual registers that have been removed from both the MachineFunction
1418  // and from LiveIntervals.
1419  //
1420  // We may also just be using the location for a value with a different
1421  // expression.
1422  removeLocationIfUnused(OldLocNo);
1423 
1424  LLVM_DEBUG({
1425  dbgs() << "Split result: \t";
1426  print(dbgs(), nullptr);
1427  });
1428  return DidChange;
1429 }
1430 
1431 bool
1432 UserValue::splitRegister(Register OldReg, ArrayRef<Register> NewRegs,
1433  LiveIntervals &LIS) {
1434  bool DidChange = false;
1435  // Split locations referring to OldReg. Iterate backwards so splitLocation can
1436  // safely erase unused locations.
1437  for (unsigned i = locations.size(); i ; --i) {
1438  unsigned LocNo = i-1;
1439  const MachineOperand *Loc = &locations[LocNo];
1440  if (!Loc->isReg() || Loc->getReg() != OldReg)
1441  continue;
1442  DidChange |= splitLocation(LocNo, NewRegs, LIS);
1443  }
1444  return DidChange;
1445 }
1446 
1447 void LDVImpl::splitPHIRegister(Register OldReg, ArrayRef<Register> NewRegs) {
1448  auto RegIt = RegToPHIIdx.find(OldReg);
1449  if (RegIt == RegToPHIIdx.end())
1450  return;
1451 
1452  std::vector<std::pair<Register, unsigned>> NewRegIdxes;
1453  // Iterate over all the debug instruction numbers affected by this split.
1454  for (unsigned InstrID : RegIt->second) {
1455  auto PHIIt = PHIValToPos.find(InstrID);
1456  assert(PHIIt != PHIValToPos.end());
1457  const SlotIndex &Slot = PHIIt->second.SI;
1458  assert(OldReg == PHIIt->second.Reg);
1459 
1460  // Find the new register that covers this position.
1461  for (auto NewReg : NewRegs) {
1462  const LiveInterval &LI = LIS->getInterval(NewReg);
1463  auto LII = LI.find(Slot);
1464  if (LII != LI.end() && LII->start <= Slot) {
1465  // This new register covers this PHI position, record this for indexing.
1466  NewRegIdxes.push_back(std::make_pair(NewReg, InstrID));
1467  // Record that this value lives in a different VReg now.
1468  PHIIt->second.Reg = NewReg;
1469  break;
1470  }
1471  }
1472 
1473  // If we do not find a new register covering this PHI, then register
1474  // allocation has dropped its location, for example because it's not live.
1475  // The old VReg will not be mapped to a physreg, and the instruction
1476  // number will have been optimized out.
1477  }
1478 
1479  // Re-create register index using the new register numbers.
1480  RegToPHIIdx.erase(RegIt);
1481  for (auto &RegAndInstr : NewRegIdxes)
1482  RegToPHIIdx[RegAndInstr.first].push_back(RegAndInstr.second);
1483 }
1484 
1485 void LDVImpl::splitRegister(Register OldReg, ArrayRef<Register> NewRegs) {
1486  // Consider whether this split range affects any PHI locations.
1487  splitPHIRegister(OldReg, NewRegs);
1488 
1489  // Check whether any intervals mapped by a DBG_VALUE were split and need
1490  // updating.
1491  bool DidChange = false;
1492  for (UserValue *UV = lookupVirtReg(OldReg); UV; UV = UV->getNext())
1493  DidChange |= UV->splitRegister(OldReg, NewRegs, *LIS);
1494 
1495  if (!DidChange)
1496  return;
1497 
1498  // Map all of the new virtual registers.
1499  UserValue *UV = lookupVirtReg(OldReg);
1500  for (Register NewReg : NewRegs)
1501  mapVirtReg(NewReg, UV);
1502 }
1503 
1506  if (pImpl)
1507  static_cast<LDVImpl*>(pImpl)->splitRegister(OldReg, NewRegs);
1508 }
1509 
1510 void UserValue::rewriteLocations(VirtRegMap &VRM, const MachineFunction &MF,
1511  const TargetInstrInfo &TII,
1512  const TargetRegisterInfo &TRI,
1513  SpillOffsetMap &SpillOffsets) {
1514  // Build a set of new locations with new numbers so we can coalesce our
1515  // IntervalMap if two vreg intervals collapse to the same physical location.
1516  // Use MapVector instead of SetVector because MapVector::insert returns the
1517  // position of the previously or newly inserted element. The boolean value
1518  // tracks if the location was produced by a spill.
1519  // FIXME: This will be problematic if we ever support direct and indirect
1520  // frame index locations, i.e. expressing both variables in memory and
1521  // 'int x, *px = &x'. The "spilled" bit must become part of the location.
1523  SmallVector<unsigned, 4> LocNoMap(locations.size());
1524  for (unsigned I = 0, E = locations.size(); I != E; ++I) {
1525  bool Spilled = false;
1526  unsigned SpillOffset = 0;
1527  MachineOperand Loc = locations[I];
1528  // Only virtual registers are rewritten.
1529  if (Loc.isReg() && Loc.getReg() &&
1531  Register VirtReg = Loc.getReg();
1532  if (VRM.isAssignedReg(VirtReg) &&
1533  Register::isPhysicalRegister(VRM.getPhys(VirtReg))) {
1534  // This can create a %noreg operand in rare cases when the sub-register
1535  // index is no longer available. That means the user value is in a
1536  // non-existent sub-register, and %noreg is exactly what we want.
1537  Loc.substPhysReg(VRM.getPhys(VirtReg), TRI);
1538  } else if (VRM.getStackSlot(VirtReg) != VirtRegMap::NO_STACK_SLOT) {
1539  // Retrieve the stack slot offset.
1540  unsigned SpillSize;
1541  const MachineRegisterInfo &MRI = MF.getRegInfo();
1542  const TargetRegisterClass *TRC = MRI.getRegClass(VirtReg);
1543  bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize,
1544  SpillOffset, MF);
1545 
1546  // FIXME: Invalidate the location if the offset couldn't be calculated.
1547  (void)Success;
1548 
1549  Loc = MachineOperand::CreateFI(VRM.getStackSlot(VirtReg));
1550  Spilled = true;
1551  } else {
1552  Loc.setReg(0);
1553  Loc.setSubReg(0);
1554  }
1555  }
1556 
1557  // Insert this location if it doesn't already exist and record a mapping
1558  // from the old number to the new number.
1559  auto InsertResult = NewLocations.insert({Loc, {Spilled, SpillOffset}});
1560  unsigned NewLocNo = std::distance(NewLocations.begin(), InsertResult.first);
1561  LocNoMap[I] = NewLocNo;
1562  }
1563 
1564  // Rewrite the locations and record the stack slot offsets for spills.
1565  locations.clear();
1566  SpillOffsets.clear();
1567  for (auto &Pair : NewLocations) {
1568  bool Spilled;
1569  unsigned SpillOffset;
1570  std::tie(Spilled, SpillOffset) = Pair.second;
1571  locations.push_back(Pair.first);
1572  if (Spilled) {
1573  unsigned NewLocNo = std::distance(&*NewLocations.begin(), &Pair);
1574  SpillOffsets[NewLocNo] = SpillOffset;
1575  }
1576  }
1577 
1578  // Update the interval map, but only coalesce left, since intervals to the
1579  // right use the old location numbers. This should merge two contiguous
1580  // DBG_VALUE intervals with different vregs that were allocated to the same
1581  // physical register.
1582  for (LocMap::iterator I = locInts.begin(); I.valid(); ++I) {
1583  I.setValueUnchecked(I.value().remapLocNos(LocNoMap));
1584  I.setStart(I.start());
1585  }
1586 }
1587 
1588 /// Find an iterator for inserting a DBG_VALUE instruction.
1591  BlockSkipInstsMap &BBSkipInstsMap) {
1592  SlotIndex Start = LIS.getMBBStartIdx(MBB);
1593  Idx = Idx.getBaseIndex();
1594 
1595  // Try to find an insert location by going backwards from Idx.
1596  MachineInstr *MI;
1597  while (!(MI = LIS.getInstructionFromIndex(Idx))) {
1598  // We've reached the beginning of MBB.
1599  if (Idx == Start) {
1600  // Retrieve the last PHI/Label/Debug location found when calling
1601  // SkipPHIsLabelsAndDebug last time. Start searching from there.
1602  //
1603  // Note the iterator kept in BBSkipInstsMap is one step back based
1604  // on the iterator returned by SkipPHIsLabelsAndDebug last time.
1605  // One exception is when SkipPHIsLabelsAndDebug returns MBB->begin(),
1606  // BBSkipInstsMap won't save it. This is to consider the case that
1607  // new instructions may be inserted at the beginning of MBB after
1608  // last call of SkipPHIsLabelsAndDebug. If we save MBB->begin() in
1609  // BBSkipInstsMap, after new non-phi/non-label/non-debug instructions
1610  // are inserted at the beginning of the MBB, the iterator in
1611  // BBSkipInstsMap won't point to the beginning of the MBB anymore.
1612  // Therefore The next search in SkipPHIsLabelsAndDebug will skip those
1613  // newly added instructions and that is unwanted.
1615  auto MapIt = BBSkipInstsMap.find(MBB);
1616  if (MapIt == BBSkipInstsMap.end())
1617  BeginIt = MBB->begin();
1618  else
1619  BeginIt = std::next(MapIt->second);
1620  auto I = MBB->SkipPHIsLabelsAndDebug(BeginIt);
1621  if (I != BeginIt)
1622  BBSkipInstsMap[MBB] = std::prev(I);
1623  return I;
1624  }
1625  Idx = Idx.getPrevIndex();
1626  }
1627 
1628  // Don't insert anything after the first terminator, though.
1629  return MI->isTerminator() ? MBB->getFirstTerminator() :
1630  std::next(MachineBasicBlock::iterator(MI));
1631 }
1632 
1633 /// Find an iterator for inserting the next DBG_VALUE instruction
1634 /// (or end if no more insert locations found).
1637  SlotIndex StopIdx, ArrayRef<MachineOperand> LocMOs,
1638  LiveIntervals &LIS, const TargetRegisterInfo &TRI) {
1640  for (const MachineOperand &LocMO : LocMOs)
1641  if (LocMO.isReg())
1642  Regs.push_back(LocMO.getReg());
1643  if (Regs.empty())
1644  return MBB->instr_end();
1645 
1646  // Find the next instruction in the MBB that define the register Reg.
1647  while (I != MBB->end() && !I->isTerminator()) {
1648  if (!LIS.isNotInMIMap(*I) &&
1650  break;
1651  if (any_of(Regs, [&I, &TRI](Register &Reg) {
1652  return I->definesRegister(Reg, &TRI);
1653  }))
1654  // The insert location is directly after the instruction/bundle.
1655  return std::next(I);
1656  ++I;
1657  }
1658  return MBB->end();
1659 }
1660 
1661 void UserValue::insertDebugValue(MachineBasicBlock *MBB, SlotIndex StartIdx,
1662  SlotIndex StopIdx, DbgVariableValue DbgValue,
1663  ArrayRef<bool> LocSpills,
1664  ArrayRef<unsigned> SpillOffsets,
1665  LiveIntervals &LIS, const TargetInstrInfo &TII,
1666  const TargetRegisterInfo &TRI,
1667  BlockSkipInstsMap &BBSkipInstsMap) {
1668  SlotIndex MBBEndIdx = LIS.getMBBEndIdx(&*MBB);
1669  // Only search within the current MBB.
1670  StopIdx = (MBBEndIdx < StopIdx) ? MBBEndIdx : StopIdx;
1672  findInsertLocation(MBB, StartIdx, LIS, BBSkipInstsMap);
1673  // Undef values don't exist in locations so create new "noreg" register MOs
1674  // for them. See getLocationNo().
1676  if (DbgValue.isUndef()) {
1677  MOs.assign(DbgValue.loc_nos().size(),
1679  /* Reg */ 0, /* isDef */ false, /* isImp */ false,
1680  /* isKill */ false, /* isDead */ false,
1681  /* isUndef */ false, /* isEarlyClobber */ false,
1682  /* SubReg */ 0, /* isDebug */ true));
1683  } else {
1684  for (unsigned LocNo : DbgValue.loc_nos())
1685  MOs.push_back(locations[LocNo]);
1686  }
1687 
1688  ++NumInsertedDebugValues;
1689 
1690  assert(cast<DILocalVariable>(Variable)
1691  ->isValidLocationForIntrinsic(getDebugLoc()) &&
1692  "Expected inlined-at fields to agree");
1693 
1694  // If the location was spilled, the new DBG_VALUE will be indirect. If the
1695  // original DBG_VALUE was indirect, we need to add DW_OP_deref to indicate
1696  // that the original virtual register was a pointer. Also, add the stack slot
1697  // offset for the spilled register to the expression.
1698  const DIExpression *Expr = DbgValue.getExpression();
1699  bool IsIndirect = DbgValue.getWasIndirect();
1700  bool IsList = DbgValue.getWasList();
1701  for (unsigned I = 0, E = LocSpills.size(); I != E; ++I) {
1702  if (LocSpills[I]) {
1703  if (!IsList) {
1704  uint8_t DIExprFlags = DIExpression::ApplyOffset;
1705  if (IsIndirect)
1706  DIExprFlags |= DIExpression::DerefAfter;
1707  Expr = DIExpression::prepend(Expr, DIExprFlags, SpillOffsets[I]);
1708  IsIndirect = true;
1709  } else {
1711  DIExpression::appendOffset(Ops, SpillOffsets[I]);
1712  Ops.push_back(dwarf::DW_OP_deref);
1713  Expr = DIExpression::appendOpsToArg(Expr, Ops, I);
1714  }
1715  }
1716 
1717  assert((!LocSpills[I] || MOs[I].isFI()) &&
1718  "a spilled location must be a frame index");
1719  }
1720 
1721  unsigned DbgValueOpcode =
1722  IsList ? TargetOpcode::DBG_VALUE_LIST : TargetOpcode::DBG_VALUE;
1723  do {
1724  BuildMI(*MBB, I, getDebugLoc(), TII.get(DbgValueOpcode), IsIndirect, MOs,
1725  Variable, Expr);
1726 
1727  // Continue and insert DBG_VALUES after every redefinition of a register
1728  // associated with the debug value within the range
1729  I = findNextInsertLocation(MBB, I, StopIdx, MOs, LIS, TRI);
1730  } while (I != MBB->end());
1731 }
1732 
1733 void UserLabel::insertDebugLabel(MachineBasicBlock *MBB, SlotIndex Idx,
1734  LiveIntervals &LIS, const TargetInstrInfo &TII,
1735  BlockSkipInstsMap &BBSkipInstsMap) {
1737  findInsertLocation(MBB, Idx, LIS, BBSkipInstsMap);
1738  ++NumInsertedDebugLabels;
1739  BuildMI(*MBB, I, getDebugLoc(), TII.get(TargetOpcode::DBG_LABEL))
1740  .addMetadata(Label);
1741 }
1742 
1743 void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
1744  const TargetInstrInfo &TII,
1745  const TargetRegisterInfo &TRI,
1746  const SpillOffsetMap &SpillOffsets,
1747  BlockSkipInstsMap &BBSkipInstsMap) {
1749 
1750  for (LocMap::const_iterator I = locInts.begin(); I.valid();) {
1751  SlotIndex Start = I.start();
1752  SlotIndex Stop = I.stop();
1753  DbgVariableValue DbgValue = I.value();
1754 
1755  SmallVector<bool> SpilledLocs;
1756  SmallVector<unsigned> LocSpillOffsets;
1757  for (unsigned LocNo : DbgValue.loc_nos()) {
1758  auto SpillIt =
1759  !DbgValue.isUndef() ? SpillOffsets.find(LocNo) : SpillOffsets.end();
1760  bool Spilled = SpillIt != SpillOffsets.end();
1761  SpilledLocs.push_back(Spilled);
1762  LocSpillOffsets.push_back(Spilled ? SpillIt->second : 0);
1763  }
1764 
1765  // If the interval start was trimmed to the lexical scope insert the
1766  // DBG_VALUE at the previous index (otherwise it appears after the
1767  // first instruction in the range).
1768  if (trimmedDefs.count(Start))
1769  Start = Start.getPrevIndex();
1770 
1771  LLVM_DEBUG(auto &dbg = dbgs(); dbg << "\t[" << Start << ';' << Stop << "):";
1772  DbgValue.printLocNos(dbg));
1774  SlotIndex MBBEnd = LIS.getMBBEndIdx(&*MBB);
1775 
1776  LLVM_DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd);
1777  insertDebugValue(&*MBB, Start, Stop, DbgValue, SpilledLocs, LocSpillOffsets,
1778  LIS, TII, TRI, BBSkipInstsMap);
1779  // This interval may span multiple basic blocks.
1780  // Insert a DBG_VALUE into each one.
1781  while (Stop > MBBEnd) {
1782  // Move to the next block.
1783  Start = MBBEnd;
1784  if (++MBB == MFEnd)
1785  break;
1786  MBBEnd = LIS.getMBBEndIdx(&*MBB);
1787  LLVM_DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd);
1788  insertDebugValue(&*MBB, Start, Stop, DbgValue, SpilledLocs,
1789  LocSpillOffsets, LIS, TII, TRI, BBSkipInstsMap);
1790  }
1791  LLVM_DEBUG(dbgs() << '\n');
1792  if (MBB == MFEnd)
1793  break;
1794 
1795  ++I;
1796  }
1797 }
1798 
1799 void UserLabel::emitDebugLabel(LiveIntervals &LIS, const TargetInstrInfo &TII,
1800  BlockSkipInstsMap &BBSkipInstsMap) {
1801  LLVM_DEBUG(dbgs() << "\t" << loc);
1803 
1804  LLVM_DEBUG(dbgs() << ' ' << printMBBReference(*MBB));
1805  insertDebugLabel(&*MBB, loc, LIS, TII, BBSkipInstsMap);
1806 
1807  LLVM_DEBUG(dbgs() << '\n');
1808 }
1809 
1810 void LDVImpl::emitDebugValues(VirtRegMap *VRM) {
1811  LLVM_DEBUG(dbgs() << "********** EMITTING LIVE DEBUG VARIABLES **********\n");
1812  if (!MF)
1813  return;
1814 
1815  BlockSkipInstsMap BBSkipInstsMap;
1816  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1817  SpillOffsetMap SpillOffsets;
1818  for (auto &userValue : userValues) {
1819  LLVM_DEBUG(userValue->print(dbgs(), TRI));
1820  userValue->rewriteLocations(*VRM, *MF, *TII, *TRI, SpillOffsets);
1821  userValue->emitDebugValues(VRM, *LIS, *TII, *TRI, SpillOffsets,
1822  BBSkipInstsMap);
1823  }
1824  LLVM_DEBUG(dbgs() << "********** EMITTING LIVE DEBUG LABELS **********\n");
1825  for (auto &userLabel : userLabels) {
1826  LLVM_DEBUG(userLabel->print(dbgs(), TRI));
1827  userLabel->emitDebugLabel(*LIS, *TII, BBSkipInstsMap);
1828  }
1829 
1830  LLVM_DEBUG(dbgs() << "********** EMITTING DEBUG PHIS **********\n");
1831 
1832  auto Slots = LIS->getSlotIndexes();
1833  for (auto &It : PHIValToPos) {
1834  // For each ex-PHI, identify its physreg location or stack slot, and emit
1835  // a DBG_PHI for it.
1836  unsigned InstNum = It.first;
1837  auto Slot = It.second.SI;
1838  Register Reg = It.second.Reg;
1839  unsigned SubReg = It.second.SubReg;
1840 
1841  MachineBasicBlock *OrigMBB = Slots->getMBBFromIndex(Slot);
1842  if (VRM->isAssignedReg(Reg) &&
1844  unsigned PhysReg = VRM->getPhys(Reg);
1845  if (SubReg != 0)
1846  PhysReg = TRI->getSubReg(PhysReg, SubReg);
1847 
1848  auto Builder = BuildMI(*OrigMBB, OrigMBB->begin(), DebugLoc(),
1849  TII->get(TargetOpcode::DBG_PHI));
1850  Builder.addReg(PhysReg);
1851  Builder.addImm(InstNum);
1852  } else if (VRM->getStackSlot(Reg) != VirtRegMap::NO_STACK_SLOT) {
1853  const MachineRegisterInfo &MRI = MF->getRegInfo();
1854  const TargetRegisterClass *TRC = MRI.getRegClass(Reg);
1855  unsigned SpillSize, SpillOffset;
1856 
1857  // Test whether this location is legal with the given subreg.
1858  bool Success =
1859  TII->getStackSlotRange(TRC, SubReg, SpillSize, SpillOffset, *MF);
1860 
1861  if (Success) {
1862  auto Builder = BuildMI(*OrigMBB, OrigMBB->begin(), DebugLoc(),
1863  TII->get(TargetOpcode::DBG_PHI));
1864  Builder.addFrameIndex(VRM->getStackSlot(Reg));
1865  Builder.addImm(InstNum);
1866  }
1867  }
1868  // If there was no mapping for a value ID, it's optimized out. Create no
1869  // DBG_PHI, and any variables using this value will become optimized out.
1870  }
1871  MF->DebugPHIPositions.clear();
1872 
1873  LLVM_DEBUG(dbgs() << "********** EMITTING INSTR REFERENCES **********\n");
1874 
1875  // Re-insert any debug instrs back in the position they were. We must
1876  // re-insert in the same order to ensure that debug instructions don't swap,
1877  // which could re-order assignments. Do so in a batch -- once we find the
1878  // insert position, insert all instructions at the same SlotIdx. They are
1879  // guaranteed to appear in-sequence in StashedDebugInstrs because we insert
1880  // them in order.
1881  for (auto StashIt = StashedDebugInstrs.begin();
1882  StashIt != StashedDebugInstrs.end(); ++StashIt) {
1883  SlotIndex Idx = StashIt->Idx;
1884  MachineBasicBlock *MBB = StashIt->MBB;
1885  MachineInstr *MI = StashIt->MI;
1886 
1887  auto EmitInstsHere = [this, &StashIt, MBB, Idx,
1888  MI](MachineBasicBlock::iterator InsertPos) {
1889  // Insert this debug instruction.
1890  MBB->insert(InsertPos, MI);
1891 
1892  // Look at subsequent stashed debug instructions: if they're at the same
1893  // index, insert those too.
1894  auto NextItem = std::next(StashIt);
1895  while (NextItem != StashedDebugInstrs.end() && NextItem->Idx == Idx) {
1896  assert(NextItem->MBB == MBB && "Instrs with same slot index should be"
1897  "in the same block");
1898  MBB->insert(InsertPos, NextItem->MI);
1899  StashIt = NextItem;
1900  NextItem = std::next(StashIt);
1901  };
1902  };
1903 
1904  // Start block index: find the first non-debug instr in the block, and
1905  // insert before it.
1906  if (Idx == Slots->getMBBStartIdx(MBB)) {
1907  MachineBasicBlock::iterator InsertPos =
1908  findInsertLocation(MBB, Idx, *LIS, BBSkipInstsMap);
1909  EmitInstsHere(InsertPos);
1910  continue;
1911  }
1912 
1913  if (MachineInstr *Pos = Slots->getInstructionFromIndex(Idx)) {
1914  // Insert at the end of any debug instructions.
1915  auto PostDebug = std::next(Pos->getIterator());
1916  PostDebug = skipDebugInstructionsForward(PostDebug, MBB->instr_end());
1917  EmitInstsHere(PostDebug);
1918  } else {
1919  // Insert position disappeared; walk forwards through slots until we
1920  // find a new one.
1921  SlotIndex End = Slots->getMBBEndIdx(MBB);
1922  for (; Idx < End; Idx = Slots->getNextNonNullIndex(Idx)) {
1923  Pos = Slots->getInstructionFromIndex(Idx);
1924  if (Pos) {
1925  EmitInstsHere(Pos->getIterator());
1926  break;
1927  }
1928  }
1929 
1930  // We have reached the end of the block and didn't find anywhere to
1931  // insert! It's not safe to discard any debug instructions; place them
1932  // in front of the first terminator, or in front of end().
1933  if (Idx >= End) {
1934  auto TermIt = MBB->getFirstTerminator();
1935  EmitInstsHere(TermIt);
1936  }
1937  }
1938  }
1939 
1940  EmitDone = true;
1941  BBSkipInstsMap.clear();
1942 }
1943 
1945  if (pImpl)
1946  static_cast<LDVImpl*>(pImpl)->emitDebugValues(VRM);
1947 }
1948 
1949 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1951  if (pImpl)
1952  static_cast<LDVImpl*>(pImpl)->print(dbgs());
1953 }
1954 #endif
llvm::DIExpression::prepend
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
Definition: DebugInfoMetadata.cpp:1305
llvm::LiveRange::find
iterator find(SlotIndex Pos)
find - Return an iterator pointing to the first segment that ends after Pos, or end().
Definition: LiveInterval.cpp:350
i
i
Definition: README.txt:29
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:510
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::SmallVectorImpl::erase
iterator erase(const_iterator CI)
Definition: SmallVector.h:714
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::DIExpression::createFragmentExpression
static Optional< DIExpression * > createFragmentExpression(const DIExpression *Expr, unsigned OffsetInBits, unsigned SizeInBits)
Create a DIExpression to describe one part of an aggregate variable that is fragmented across multipl...
Definition: DebugInfoMetadata.cpp:1457
llvm::LiveRange::empty
bool empty() const
Definition: LiveInterval.h:374
llvm::LiveIntervals::getSlotIndexes
SlotIndexes * getSlotIndexes() const
Definition: LiveIntervals.h:211
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:791
llvm::IntervalMap::const_iterator::stop
const KeyT & stop() const
stop - Return the end of the current interval.
Definition: IntervalMap.h:1373
print
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
Definition: ArchiveWriter.cpp:147
Metadata.h
llvm::SlotIndex::isEarlierEqualInstr
static bool isEarlierEqualInstr(SlotIndex A, SlotIndex B)
Return true if A refers to the same instruction as B or an earlier one.
Definition: SlotIndexes.h:209
llvm::SharedLiveDebugValues::LDVImpl
Definition: LiveDebugValues.h:26
DebugInfoMetadata.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
StringRef.h
Pass.h
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::LiveIntervals::isNotInMIMap
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
Definition: LiveIntervals.h:221
llvm::LiveQueryResult::valueOutOrDead
VNInfo * valueOutOrDead() const
Returns the value alive at the end of the instruction, if any.
Definition: LiveInterval.h:129
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1177
Statistic.h
LiveDebugVariables.h
llvm::MachineFunction::useDebugInstrRef
bool useDebugInstrRef() const
Returns true if the function's variable locations should be tracked with instruction referencing.
Definition: MachineFunction.cpp:1231
llvm::MachineFunction::end
iterator end()
Definition: MachineFunction.h:825
llvm::LiveRange::advanceTo
iterator advanceTo(iterator I, SlotIndex Pos)
advanceTo - Advance the specified iterator to point to the Segment containing the specified position,...
Definition: LiveInterval.h:263
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:119
llvm::LexicalScope
LexicalScope - This class is used to track scope information.
Definition: LexicalScopes.h:44
llvm::Function::getSubprogram
DISubprogram * getSubprogram() const
Get the attached subprogram.
Definition: Metadata.cpp:1541
llvm::LiveIntervals::getInstructionFromIndex
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
Definition: LiveIntervals.h:231
llvm::VirtRegMap
Definition: VirtRegMap.h:33
MapVector.h
llvm::SmallDenseMap
Definition: DenseMap.h:880
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
MachineBasicBlock.h
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::VNInfo::def
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
llvm::IntervalMap::iterator
Definition: IntervalMap.h:1526
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::DILocation
Debug location.
Definition: DebugInfoMetadata.h:1580
DenseMap.h
TargetInstrInfo.h
llvm::VirtRegMap::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: VirtRegMap.h:88
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
llvm::operator!=
bool operator!=(uint64_t V1, const APInt &V2)
Definition: APInt.h:1988
llvm::Optional
Definition: APInt.h:33
llvm::MachineInstr::isCopy
bool isCopy() const
Definition: MachineInstr.h:1285
llvm::MapVector
This class implements a map that also provides access to all stored values in a deterministic order.
Definition: MapVector.h:37
llvm::SlotIndexes::getMBBEndIdx
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:476
llvm::IntervalMap::const_iterator
Definition: IntervalMap.h:1297
STLExtras.h
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2596
RHS
Value * RHS
Definition: X86PartialReduction.cpp:74
llvm::LiveQueryResult
Result of a LiveRange query.
Definition: LiveInterval.h:90
SpecialSubKind::allocator
@ allocator
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::LiveIntervals::getMBBFromIndex
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Definition: LiveIntervals.h:255
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::MDNode::get
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Definition: Metadata.h:1233
removeDebugInstrs
static void removeDebugInstrs(MachineFunction &mf)
Definition: LiveDebugVariables.cpp:1292
llvm::LiveIntervals::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
Definition: LiveIntervals.h:226
MachineRegisterInfo.h
llvm::lltok::equal
@ equal
Definition: LLToken.h:25
isUndef
static bool isUndef(ArrayRef< int > Mask)
Definition: HexagonISelDAGToDAGHVX.cpp:909
llvm::LiveRange::beginIndex
SlotIndex beginIndex() const
beginIndex - Return the lowest numbered slot covered.
Definition: LiveInterval.h:377
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1298
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
clear
static void clear(coro::Shape &Shape)
Definition: Coroutines.cpp:233
llvm::LiveDebugVariables::splitRegister
void splitRegister(Register OldReg, ArrayRef< Register > NewRegs, LiveIntervals &LIS)
splitRegister - Move any user variables in OldReg to the live ranges in NewRegs where they are live.
Definition: LiveDebugVariables.cpp:1505
CommandLine.h
LHS
Value * LHS
Definition: X86PartialReduction.cpp:73
llvm::DIExpression::appendOpsToArg
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
Definition: DebugInfoMetadata.cpp:1321
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:651
llvm::MapVector::begin
iterator begin()
Definition: MapVector.h:70
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineRegisterInfo::use_nodbg_operands
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:526
TargetMachine.h
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
L2
add sub stmia L5 ldr L2
Definition: README.txt:201
llvm::LiveRange::begin
iterator begin()
Definition: LiveInterval.h:215
llvm::IntervalMap::const_iterator::start
const KeyT & start() const
start - Return the beginning of the current interval.
Definition: IntervalMap.h:1370
llvm::LiveIntervals::getMBBStartIdx
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
Definition: LiveIntervals.h:236
llvm::DILocalVariable
Local variable.
Definition: DebugInfoMetadata.h:3104
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::DIExpression::ApplyOffset
@ ApplyOffset
Definition: DebugInfoMetadata.h:2803
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::MachineOperand::setSubReg
void setSubReg(unsigned subReg)
Definition: MachineOperand.h:471
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::IntervalMap::iterator::setStartUnchecked
void setStartUnchecked(KeyT a)
setStartUnchecked - Move the start of the current interval without checking for coalescing or overlap...
Definition: IntervalMap.h:1565
l
This requires reassociating to forms of expressions that are already something that reassoc doesn t think about yet These two functions should generate the same code on big endian int * l
Definition: README.txt:100
false
Definition: StackSlotColoring.cpp:142
TargetOpcodes.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
merge
static LoopDeletionResult merge(LoopDeletionResult A, LoopDeletionResult B)
Definition: LoopDeletion.cpp:53
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
pass
modulo schedule Modulo Schedule test pass
Definition: ModuloSchedule.cpp:2099
LexicalScopes.h
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::MachineOperand::CreateFI
static MachineOperand CreateFI(int Idx)
Definition: MachineOperand.h:823
llvm::SlotIndexes
SlotIndexes pass.
Definition: SlotIndexes.h:314
DebugLoc.h
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
llvm::SlotIndexes::getInstructionFromIndex
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
Definition: SlotIndexes.h:403
llvm::VirtRegMap::isAssignedReg
bool isAssignedReg(Register virtReg) const
returns true if the specified virtual register is not mapped to a stack slot or rematerialized.
Definition: VirtRegMap.h:177
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::None
const NoneType None
Definition: None.h:23
llvm::initializeLiveDebugVariablesPass
void initializeLiveDebugVariablesPass(PassRegistry &)
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::SlotIndexes::getIndexBefore
SlotIndex getIndexBefore(const MachineInstr &MI) const
getIndexBefore - Returns the index of the last indexed instruction before MI, or the start index of i...
Definition: SlotIndexes.h:422
llvm::IntervalMap::Allocator
typename Sizer::Allocator Allocator
Definition: IntervalMap.h:964
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
Passes.h
llvm::IntervalMap::const_iterator::valid
bool valid() const
valid - Return true if the current position is valid, false for end().
Definition: IntervalMap.h:1364
llvm::SlotIndex::getPrevIndex
SlotIndex getPrevIndex() const
Returns the previous index.
Definition: SlotIndexes.h:299
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
llvm::IntervalMap::const_iterator::setMap
void setMap(const IntervalMap &m)
setMap - Change the map iterated over.
Definition: IntervalMap.h:1361
llvm::cl::opt< bool >
findInsertLocation
static MachineBasicBlock::iterator findInsertLocation(MachineBasicBlock *MBB, SlotIndex Idx, LiveIntervals &LIS, BlockSkipInstsMap &BBSkipInstsMap)
Find an iterator for inserting a DBG_VALUE instruction.
Definition: LiveDebugVariables.cpp:1590
llvm::SlotIndex::getBaseIndex
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
Definition: SlotIndexes.h:241
llvm::IntervalMap::const_iterator::advanceTo
void advanceTo(KeyT x)
advanceTo - Move to the first interval with stop >= x, or end().
Definition: IntervalMap.h:1448
LiveDebugValues::DbgValue
Class recording the (high level) value of a variable.
Definition: InstrRefBasedImpl.h:225
llvm::SlotIndexes::getMBBStartIdx
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:466
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:152
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::clear
void clear()
Definition: DenseMap.h:111
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
LiveIntervals.h
llvm::LiveRange
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
llvm::find
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1669
llvm::LiveIntervals::getMBBEndIdx
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
Definition: LiveIntervals.h:241
VirtRegMap.h
llvm::VNInfo::id
unsigned id
The ID number of this value.
Definition: LiveInterval.h:58
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::LiveDebugVariables::LiveDebugVariables
LiveDebugVariables()
Definition: LiveDebugVariables.cpp:95
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::IntervalMap::const_iterator::value
const ValT & value() const
value - Return the mapped value at the current interval.
Definition: IntervalMap.h:1376
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap< unsigned, unsigned >
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::VirtRegMap::getPhys
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:106
Debug
bool Debug
Definition: PassBuilderBindings.cpp:51
llvm::LiveDebugVariables::dump
void dump() const
dump - Print data structures to dbgs().
Definition: LiveDebugVariables.cpp:1950
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::make_early_inc_range
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:642
MCRegisterInfo.h
llvm::DebugVariable
Identifies a unique instance of a variable.
Definition: DebugInfoMetadata.h:3670
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1714
ArrayRef.h
llvm::LiveRange::Query
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:533
TargetPassConfig.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::DenseMapBase::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:150
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:546
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::IntervalMap::find
const_iterator find(KeyT x) const
find - Return an iterator pointing to the first interval ending at or after x, or end().
Definition: IntervalMap.h:1126
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::operator==
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1986
llvm::SlotIndexes::getMBBFromIndex
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Returns the basic block which the given index falls in.
Definition: SlotIndexes.h:514
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::LiveDebugVariables
Definition: LiveDebugVariables.h:32
llvm::MachineOperand::setIsDebug
void setIsDebug(bool Val=true)
Definition: MachineOperand.h:528
llvm::SlotIndex::getRegSlot
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:254
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:114
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:650
llvm::DIExpression::replaceArg
static DIExpression * replaceArg(const DIExpression *Expr, uint64_t OldArg, uint64_t NewArg)
Create a copy of Expr with each instance of DW_OP_LLVM_arg, \p OldArg replaced with DW_OP_LLVM_arg,...
Definition: DebugInfoMetadata.cpp:1345
llvm::MachineBasicBlock::instr_end
instr_iterator instr_end()
Definition: MachineBasicBlock.h:258
llvm::MachineFunction
Definition: MachineFunction.h:241
getDebugLoc
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
Definition: MachineInstrBundle.cpp:109
llvm::Expression
Class representing an expression and its matching format.
Definition: FileCheckImpl.h:237
llvm::IntervalMap::iterator::insert
void insert(KeyT a, KeyT b, ValT y)
insert - Insert mapping [a;b] -> y before the current position.
Definition: IntervalMap.h:1787
llvm::InsnRange
std::pair< const MachineInstr *, const MachineInstr * > InsnRange
InsnRange - This is used to track range of instructions with identical lexical scope.
Definition: LexicalScopes.h:39
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:241
llvm::skipDebugInstructionsForward
IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator.
Definition: MachineBasicBlock.h:1223
llvm::ArrayRef< unsigned >
EnableLDV
static cl::opt< bool > EnableLDV("live-debug-variables", cl::init(true), cl::desc("Enable the live debug variables pass"), cl::Hidden)
llvm::MapVector::insert
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: MapVector.h:118
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1656
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::DINode
Tagged DWARF-like metadata node.
Definition: DebugInfoMetadata.h:127
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::SlotIndex::getNextIndex
SlotIndex getNextIndex() const
Returns the next index.
Definition: SlotIndexes.h:279
llvm::MachineFunction::DebugPHIRegallocPos
Location of a PHI instruction that is also a debug-info variable value, for the duration of register ...
Definition: MachineFunction.h:502
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SlotIndex::getNextSlot
SlotIndex getNextSlot() const
Returns the next slot in the index list.
Definition: SlotIndexes.h:269
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(LiveDebugVariables, DEBUG_TYPE, "Debug Variable Analysis", false, false) INITIALIZE_PASS_END(LiveDebugVariables
llvm::IntervalMap::iterator::setValue
void setValue(ValT x)
setValue - Change the mapped value of the current interval.
Definition: IntervalMap.h:1719
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
llvm::DenseMapBase::empty
LLVM_NODISCARD bool empty() const
Definition: DenseMap.h:97
llvm::MDNode::getContext
LLVMContext & getContext() const
Definition: Metadata.h:967
llvm::DIExpression::getFragmentInfo
static Optional< FragmentInfo > getFragmentInfo(expr_op_iterator Start, expr_op_iterator End)
Retrieve the details of this fragment expression.
Definition: DebugInfoMetadata.cpp:1228
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
printExtendedName
static void printExtendedName(raw_ostream &OS, const DINode *Node, const DILocation *DL)
Definition: LiveDebugVariables.cpp:700
llvm::DIExpression::appendOffset
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
Definition: DebugInfoMetadata.cpp:1237
llvm::LiveRange::iterator
Segments::iterator iterator
Definition: LiveInterval.h:212
llvm::pdb::PDB_SymType::Label
@ Label
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:607
llvm::DIExpression::DerefAfter
@ DerefAfter
Definition: DebugInfoMetadata.h:2805
llvm::DenseMapBase::end
iterator end()
Definition: DenseMap.h:83
llvm::SmallVectorImpl::assign
void assign(size_type NumElts, ValueParamT Elt)
Definition: SmallVector.h:678
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1311
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
Success
#define Success
Definition: AArch64Disassembler.cpp:266
llvm::AArch64CC::LS
@ LS
Definition: AArch64BaseInfo.h:264
Casting.h
llvm::pdb::PDB_LocType::Slot
@ Slot
Function.h
llvm::IntervalMap::const_iterator::find
void find(KeyT x)
find - Move to the first interval with stop >= x, or end().
Definition: IntervalMap.h:1438
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::VNInfo
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
llvm::LiveRange::getVNInfoAt
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:413
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:581
llvm::SlotIndexes::getNextNonNullIndex
SlotIndex getNextNonNullIndex(SlotIndex Index)
Returns the next non-null index, if one exists.
Definition: SlotIndexes.h:409
LiveInterval.h
llvm::IntervalMap::iterator::setStopUnchecked
void setStopUnchecked(KeyT b)
setStopUnchecked - Move the end of the current interval without checking for coalescing or overlaps.
Definition: IntervalMap.h:1571
DEBUG_TYPE
#define DEBUG_TYPE
Definition: LiveDebugVariables.cpp:70
llvm::VirtRegMap::NO_STACK_SLOT
@ NO_STACK_SLOT
Definition: VirtRegMap.h:37
SmallVector.h
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:272
MachineInstrBuilder.h
IntervalMap.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
llvm::IntervalMap::begin
const_iterator begin() const
Definition: IntervalMap.h:1100
printDebugLoc
static void printDebugLoc(const DebugLoc &DL, raw_ostream &CommentOS, const LLVMContext &Ctx)
Definition: LiveDebugVariables.cpp:679
llvm::LiveInterval::reg
Register reg() const
Definition: LiveInterval.h:711
llvm::LiveRange::getSegmentContaining
const Segment * getSegmentContaining(SlotIndex Idx) const
Return the segment that contains the specified index, or null if there is none.
Definition: LiveInterval.h:400
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::IntervalMap
Definition: IntervalMap.h:938
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:236
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
MachineOperand.h
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1094
llvm::MachineOperand::substPhysReg
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
Definition: MachineOperand.cpp:87
llvm::MachineFunction::DebugPHIPositions
DenseMap< unsigned, DebugPHIRegallocPos > DebugPHIPositions
Map of debug instruction numbers to the position of their PHI instructions during register allocation...
Definition: MachineFunction.h:513
llvm::LiveDebugVariables::~LiveDebugVariables
~LiveDebugVariables() override
Definition: LiveDebugVariables.cpp:1322
llvm::DILabel
Label.
Definition: DebugInfoMetadata.h:3194
llvm::MachineBasicBlock::SkipPHIsLabelsAndDebug
iterator SkipPHIsLabelsAndDebug(iterator I, bool SkipPseudoOp=true)
Return the first instruction in MBB after I that is not a PHI, label or debug.
Definition: MachineBasicBlock.cpp:224
llvm::LiveIntervals::hasInterval
bool hasInterval(Register Reg) const
Definition: LiveIntervals.h:125
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
SlotIndexes.h
llvm::cl::desc
Definition: CommandLine.h:412
raw_ostream.h
findNextInsertLocation
static MachineBasicBlock::iterator findNextInsertLocation(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, SlotIndex StopIdx, ArrayRef< MachineOperand > LocMOs, LiveIntervals &LIS, const TargetRegisterInfo &TRI)
Find an iterator for inserting the next DBG_VALUE instruction (or end if no more insert locations fou...
Definition: LiveDebugVariables.cpp:1636
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:46
llvm::LexicalScopes
LexicalScopes - This class provides interface to collect and use lexical scoping information from mac...
Definition: LexicalScopes.h:141
llvm::LiveDebugVariables::ID
static char ID
Definition: LiveDebugVariables.h:36
MachineFunction.h
llvm::MachineInstrBundleIterator< MachineInstr >
copy
we should consider alternate ways to model stack dependencies Lots of things could be done in WebAssemblyTargetTransformInfo cpp there are numerous optimization related hooks that can be overridden in WebAssemblyTargetLowering Instead of the OptimizeReturned which should consider preserving the returned attribute through to MachineInstrs and extending the MemIntrinsicResults pass to do this optimization on calls too That would also let the WebAssemblyPeephole pass clean up dead defs for such as it does for stores Consider implementing and or getMachineCombinerPatterns Find a clean way to fix the problem which leads to the Shrink Wrapping pass being run after the WebAssembly PEI pass When setting multiple variables to the same we currently get code like const It could be done with a smaller encoding like local tee $pop5 local copy
Definition: README.txt:101
InitializePasses.h
TargetRegisterInfo.h
Debug.h
UndefLocNo
@ UndefLocNo
Definition: LiveDebugVariables.cpp:99
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:274
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::LiveRange::end
iterator end()
Definition: LiveInterval.h:216
llvm::LiveDebugVariables::emitDebugValues
void emitDebugValues(VirtRegMap *VRM)
emitDebugValues - Emit new DBG_VALUE instructions reflecting the changes that happened during registe...
Definition: LiveDebugVariables.cpp:1944
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1198
llvm::MachineOperand::isIdenticalTo
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Definition: MachineOperand.cpp:287
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:572
MachineDominators.h
SmallSet.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::VirtRegMap::getStackSlot
int getStackSlot(Register virtReg) const
returns the stack slot mapped to the specified virtual register
Definition: VirtRegMap.h:188