38 for (
auto &
T :
block.terminators())
46 if (
op.isReg() &&
op.isDef())
80 if (
auto *Instr =
MRI->getUniqueVRegDef(
Value)) {
unsigned const MachineRegisterInfo * MRI
Given that RA is a live value
This file declares a specialization of the GenericSSAContext<X> template class for Machine IR.
unify loop Fixup each natural loop to have a single exit block
void setFunction(MachineFunction &Fn)
MachineBasicBlock * getDefBlock(Register) const
Get the defining block of a value.
static MachineBasicBlock * getEntryBlock(MachineFunction &F)
static bool isConstantOrUndefValuePhi(const MachineInstr &Phi)
static void appendBlockDefs(SmallVectorImpl< Register > &defs, const MachineBasicBlock &block)
static const Register ValueRefNull
static void appendBlockTerms(SmallVectorImpl< MachineInstr * > &terms, MachineBasicBlock &block)
Printable print(const MachineBasicBlock *Block) const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
MachineOperand class - Representation of each machine instruction operand.
Simple wrapper around std::function<void(raw_ostream&)>.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
This is an optimization pass for GlobalISel generic memory operations.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.