LLVM 17.0.0git
MachineSSAContext.cpp
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1//===- MachineSSAContext.cpp ------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// This file defines a specialization of the GenericSSAContext<X>
11/// template class for Machine IR.
12///
13//===----------------------------------------------------------------------===//
14
21
22using namespace llvm;
23
25
27 MF = &Fn;
28 RegInfo = &MF->getRegInfo();
29}
30
32 return &F.front();
33}
34
37 const MachineBasicBlock &block) {
38 for (auto &T : block.terminators())
39 terms.push_back(&T);
40}
41
43 const MachineBasicBlock &block) {
44 for (const MachineInstr &instr : block.instrs()) {
45 for (const MachineOperand &op : instr.operands()) {
46 if (op.isReg() && op.isDef())
47 defs.push_back(op.getReg());
48 }
49 }
50}
51
52/// Get the defining block of a value.
54 if (!value)
55 return nullptr;
56 return RegInfo->getVRegDef(value)->getParent();
57}
58
60 return Phi.isConstantValuePHI();
61}
62
64 if (!Block)
65 return Printable([](raw_ostream &Out) { Out << "<nullptr>"; });
66 return Printable([Block](raw_ostream &Out) { Block->printName(Out); });
67}
68
70 return Printable([I](raw_ostream &Out) { I->print(Out); });
71}
72
74 auto *MRI = RegInfo;
75 return Printable([MRI, Value](raw_ostream &Out) {
76 Out << printReg(Value, MRI->getTargetRegisterInfo(), 0, MRI);
77
78 if (Value) {
79 // Try to print the definition.
80 if (auto *Instr = MRI->getUniqueVRegDef(Value)) {
81 Out << ": ";
82 Instr->print(Out);
83 }
84 }
85 });
86}
unsigned const MachineRegisterInfo * MRI
Given that RA is a live value
#define op(i)
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares a specialization of the GenericSSAContext<X> template class for Machine IR.
unify loop Fixup each natural loop to have a single exit block
MachineBasicBlock * getDefBlock(Register) const
Get the defining block of a value.
static MachineBasicBlock * getEntryBlock(MachineFunction &F)
static bool isConstantOrUndefValuePhi(const MachineInstr &Phi)
static void appendBlockDefs(SmallVectorImpl< Register > &defs, const MachineBasicBlock &block)
static void appendBlockTerms(SmallVectorImpl< MachineInstr * > &terms, MachineBasicBlock &block)
Printable print(const MachineBasicBlock *Block) const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
Definition: MachineInstr.h:68
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
MachineOperand class - Representation of each machine instruction operand.
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
void push_back(const T &Elt)
Definition: SmallVector.h:416
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.