19#define DEBUG_TYPE "ppc-reg-bank-info"
21#define GET_TARGET_REGBANK_IMPL
22#include "PPCGenRegisterBank.inc"
25#include "PPCGenRegisterBankInfo.def"
35 case PPC::G8RCRegClassID:
36 case PPC::G8RC_NOX0RegClassID:
37 case PPC::G8RC_and_G8RC_NOX0RegClassID:
38 case PPC::GPRCRegClassID:
39 case PPC::GPRC_NOR0RegClassID:
40 case PPC::GPRC_and_GPRC_NOR0RegClassID:
42 case PPC::VSFRCRegClassID:
43 case PPC::SPILLTOVSRRC_and_VSFRCRegClassID:
44 case PPC::SPILLTOVSRRC_and_VFRCRegClassID:
45 case PPC::SPILLTOVSRRC_and_F4RCRegClassID:
46 case PPC::F8RCRegClassID:
47 case PPC::VFRCRegClassID:
48 case PPC::VSSRCRegClassID:
49 case PPC::F4RCRegClassID:
51 case PPC::CRRCRegClassID:
52 case PPC::CRBITRCRegClassID:
61 const unsigned Opc =
MI.getOpcode();
77 unsigned NumOperands =
MI.getNumOperands();
84 case TargetOpcode::G_ADD:
85 case TargetOpcode::G_SUB:
87 case TargetOpcode::G_AND:
88 case TargetOpcode::G_OR:
89 case TargetOpcode::G_XOR:
91 case TargetOpcode::G_SEXT:
92 case TargetOpcode::G_ZEXT:
93 case TargetOpcode::G_ANYEXT:
95 "This code is for instructions with 3 or less operands");
98 case TargetOpcode::G_FADD:
99 case TargetOpcode::G_FSUB:
100 case TargetOpcode::G_FMUL:
101 case TargetOpcode::G_FDIV: {
105 assert((
Size == 32 ||
Size == 64) &&
"Unsupported floating point types!\n");
109 case TargetOpcode::G_FCMP: {
110 unsigned CmpSize =
MRI.getType(
MI.getOperand(2).getReg()).getSizeInBits();
118 case TargetOpcode::G_CONSTANT:
121 case TargetOpcode::G_FPTOUI:
122 case TargetOpcode::G_FPTOSI: {
131 case TargetOpcode::G_UITOFP:
132 case TargetOpcode::G_SITOFP: {
141 case TargetOpcode::G_LOAD: {
144 if (
any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
153 return onlyUsesFP(UseMI, MRI, TRI);
164 case TargetOpcode::G_STORE: {
178 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
198 case TargetOpcode::G_FADD:
199 case TargetOpcode::G_FSUB:
200 case TargetOpcode::G_FMUL:
201 case TargetOpcode::G_FMA:
202 case TargetOpcode::G_FDIV:
203 case TargetOpcode::G_FCONSTANT:
204 case TargetOpcode::G_FPEXT:
205 case TargetOpcode::G_FPTRUNC:
206 case TargetOpcode::G_FCEIL:
207 case TargetOpcode::G_FFLOOR:
208 case TargetOpcode::G_FNEARBYINT:
209 case TargetOpcode::G_FNEG:
210 case TargetOpcode::G_FCOS:
211 case TargetOpcode::G_FSIN:
212 case TargetOpcode::G_FLOG10:
213 case TargetOpcode::G_FLOG:
214 case TargetOpcode::G_FLOG2:
215 case TargetOpcode::G_FSQRT:
216 case TargetOpcode::G_FABS:
217 case TargetOpcode::G_FEXP:
218 case TargetOpcode::G_FRINT:
219 case TargetOpcode::G_INTRINSIC_TRUNC:
220 case TargetOpcode::G_INTRINSIC_ROUND:
221 case TargetOpcode::G_FMAXNUM:
222 case TargetOpcode::G_FMINNUM:
223 case TargetOpcode::G_FMAXIMUM:
224 case TargetOpcode::G_FMINIMUM:
241 unsigned Depth)
const {
242 unsigned Op =
MI.getOpcode();
243 if (Op == TargetOpcode::G_INTRINSIC &&
isFPIntrinsic(
MI.getIntrinsicID()))
252 if (Op != TargetOpcode::COPY && !
MI.isPHI() &&
258 if (RB == &PPC::FPRRegBank)
260 if (RB == &PPC::GPRRegBank)
267 if (!
MI.isPHI() ||
Depth > MaxFPRSearchDepth)
272 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1);
281 unsigned Depth)
const {
282 switch (
MI.getOpcode()) {
283 case TargetOpcode::G_FPTOSI:
284 case TargetOpcode::G_FPTOUI:
285 case TargetOpcode::G_FCMP:
286 case TargetOpcode::G_LROUND:
287 case TargetOpcode::G_LLROUND:
300 unsigned Depth)
const {
301 switch (
MI.getOpcode()) {
302 case TargetOpcode::G_SITOFP:
303 case TargetOpcode::G_UITOFP:
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
static bool isPreISelGenericFloatingPointOpcode(unsigned Opc)
Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...
static bool isFPIntrinsic(unsigned ID)
unsigned const TargetRegisterInfo * TRI
This file declares the targeting of the RegisterBankInfo class for PowerPC.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx RBIdx)
Get the pointer to the ValueMapping representing the RegisterBank at RBIdx.
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override
Get a register bank that covers RC.
PPCRegisterBankInfo(const TargetRegisterInfo &TRI)
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
bool isValid() const
Check whether this object is valid.
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
unsigned getID() const
Return the register class ID number.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Helper struct that represents how a value is mapped through different register banks.