35#define DEBUG_TYPE "mips-reg-info"
37#define GET_REGINFO_TARGET_DESC
38#include "MipsGenRegisterInfo.inc"
49 assert(Kind == 0 &&
"this should only be used for default case");
50 return ArePtrs64bit ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
56 switch (RC->
getID()) {
59 case Mips::GPR32RegClassID:
60 case Mips::GPR64RegClassID:
61 case Mips::DSPRRegClassID: {
63 return 28 - TFI->
hasFP(MF);
65 case Mips::FGR32RegClassID:
67 case Mips::AFGR64RegClassID:
69 case Mips::FGR64RegClassID:
83 if (
F.hasFnAttribute(
"interrupt")) {
85 return Subtarget.
hasMips64r6() ? CSR_Interrupt_64R6_SaveList
86 : CSR_Interrupt_64_SaveList;
88 return Subtarget.
hasMips32r6() ? CSR_Interrupt_32R6_SaveList
89 : CSR_Interrupt_32_SaveList;
95 return CSR_N64_SingleFloat_SaveList;
97 return CSR_N64_SaveList;
103 return CSR_N32_SingleFloat_SaveList;
105 return CSR_N32_SaveList;
110 return CSR_O32_SingleFloat_SaveList;
113 return CSR_O32_FP64_SaveList;
116 return CSR_O32_FPXX_SaveList;
118 return CSR_O32_SaveList;
128 return CSR_N64_SingleFloat_RegMask;
130 return CSR_N64_RegMask;
136 return CSR_N32_SingleFloat_RegMask;
138 return CSR_N32_RegMask;
143 return CSR_O32_SingleFloat_RegMask;
146 return CSR_O32_FP64_RegMask;
149 return CSR_O32_FPXX_RegMask;
151 return CSR_O32_RegMask;
155 return CSR_Mips16RetHelper_RegMask;
160 static const MCPhysReg ReservedGPR32[] = {
161 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
164 static const MCPhysReg ReservedGPR64[] = {
165 Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
185 for (
MCPhysReg Reg : Mips::AFGR64RegClass)
189 for (
MCPhysReg Reg : Mips::FGR64RegClass)
222 for (
MCPhysReg Reg : Mips::MSACtrlRegClass)
255 errs() <<
"<--------->\n"
258 int FrameIndex =
MI.getOperand(FIOperandNum).getIndex();
263 <<
"spOffset : " << spOffset <<
"\n"
264 <<
"stackSize : " << stackSize <<
"\n"
269 eliminateFI(
MI, FIOperandNum, FrameIndex, stackSize, spOffset);
281 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
283 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
284 (IsN64 ? Mips::SP_64 : Mips::SP);
299 unsigned FP = Subtarget.
isGP32bit() ? Mips::FP : Mips::FP_64;
300 unsigned BP = Subtarget.
isGP32bit() ? Mips::S7 : Mips::S7_64;
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file implements the BitVector class.
uint64_t IntrinsicInst * II
SI optimize exec mask operations pre RA
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
MachineInstrBundleIterator< MachineInstr > iterator
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Representation of each machine instruction.
bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
static unsigned getPICCallReg()
Get PIC indirect call register.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Register getFrameRegister(const MachineFunction &MF) const override
Debug information queries.
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Stack Frame Processing Methods.
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
static const uint32_t * getMips16RetHelperMask()
bool canRealignStack(const MachineFunction &MF) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
MipsRegisterInfo(const MipsSubtarget &STI)
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Mips Callee Saved Registers.
const TargetRegisterClass * getPointerRegClass(unsigned Kind) const override
Code Generation virtual methods...
bool inMips16Mode() const
bool isSingleFloat() const
bool useSmallSection() const
const TargetFrameLowering * getFrameLowering() const override
const MipsABIInfo & getABI() const
Wrapper class representing virtual and physical registers.
Information about stack frame layout on the target.
bool hasFP(const MachineFunction &MF) const
hasFP - Return true if the specified function should have a dedicated frame pointer register.
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
unsigned getID() const
Return the register class ID number.
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
virtual const TargetFrameLowering * getFrameLowering() const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ABI raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...