LLVM  14.0.0git
LiveRangeEdit.cpp
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1 //===-- LiveRangeEdit.cpp - Basic tools for editing a register live range -===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // The LiveRangeEdit class represents changes done to a virtual register when it
10 // is spilled or split.
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Support/Debug.h"
22 
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "regalloc"
26 
27 STATISTIC(NumDCEDeleted, "Number of instructions deleted by DCE");
28 STATISTIC(NumDCEFoldedLoads, "Number of single use loads folded after DCE");
29 STATISTIC(NumFracRanges, "Number of live ranges fractured by DCE");
30 
31 void LiveRangeEdit::Delegate::anchor() { }
32 
33 LiveInterval &LiveRangeEdit::createEmptyIntervalFrom(Register OldReg,
34  bool createSubRanges) {
35  Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
36  if (VRM)
37  VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
38 
39  LiveInterval &LI = LIS.createEmptyInterval(VReg);
40  if (Parent && !Parent->isSpillable())
41  LI.markNotSpillable();
42  if (createSubRanges) {
43  // Create empty subranges if the OldReg's interval has them. Do not create
44  // the main range here---it will be constructed later after the subranges
45  // have been finalized.
46  LiveInterval &OldLI = LIS.getInterval(OldReg);
48  for (LiveInterval::SubRange &S : OldLI.subranges())
49  LI.createSubRange(Alloc, S.LaneMask);
50  }
51  return LI;
52 }
53 
55  Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
56  if (VRM) {
57  VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
58  }
59  // FIXME: Getting the interval here actually computes it.
60  // In theory, this may not be what we want, but in practice
61  // the createEmptyIntervalFrom API is used when this is not
62  // the case. Generally speaking we just want to annotate the
63  // LiveInterval when it gets created but we cannot do that at
64  // the moment.
65  if (Parent && !Parent->isSpillable())
66  LIS.getInterval(VReg).markNotSpillable();
67  return VReg;
68 }
69 
71  const MachineInstr *DefMI,
72  AAResults *aa) {
73  assert(DefMI && "Missing instruction");
74  ScannedRemattable = true;
76  return false;
77  Remattable.insert(VNI);
78  return true;
79 }
80 
81 void LiveRangeEdit::scanRemattable(AAResults *aa) {
82  for (VNInfo *VNI : getParent().valnos) {
83  if (VNI->isUnused())
84  continue;
85  unsigned Original = VRM->getOriginal(getReg());
86  LiveInterval &OrigLI = LIS.getInterval(Original);
87  VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
88  if (!OrigVNI)
89  continue;
91  if (!DefMI)
92  continue;
93  checkRematerializable(OrigVNI, DefMI, aa);
94  }
95  ScannedRemattable = true;
96 }
97 
99  if (!ScannedRemattable)
100  scanRemattable(aa);
101  return !Remattable.empty();
102 }
103 
104 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
105 /// OrigIdx are also available with the same value at UseIdx.
107  SlotIndex OrigIdx,
108  SlotIndex UseIdx) const {
109  OrigIdx = OrigIdx.getRegSlot(true);
110  UseIdx = std::max(UseIdx, UseIdx.getRegSlot(true));
111  for (const MachineOperand &MO : OrigMI->operands()) {
112  if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
113  continue;
114 
115  // We can't remat physreg uses, unless it is a constant or target wants
116  // to ignore this use.
117  if (Register::isPhysicalRegister(MO.getReg())) {
118  if (MRI.isConstantPhysReg(MO.getReg()) || TII.isIgnorableUse(MO))
119  continue;
120  return false;
121  }
122 
123  LiveInterval &li = LIS.getInterval(MO.getReg());
124  const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
125  if (!OVNI)
126  continue;
127 
128  // Don't allow rematerialization immediately after the original def.
129  // It would be incorrect if OrigMI redefines the register.
130  // See PR14098.
131  if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
132  return false;
133 
134  if (OVNI != li.getVNInfoAt(UseIdx))
135  return false;
136 
137  // Check that subrange is live at UseIdx.
138  if (MO.getSubReg()) {
140  LaneBitmask LM = TRI->getSubRegIndexLaneMask(MO.getSubReg());
141  for (LiveInterval::SubRange &SR : li.subranges()) {
142  if ((SR.LaneMask & LM).none())
143  continue;
144  if (!SR.liveAt(UseIdx))
145  return false;
146  // Early exit if all used lanes are checked. No need to continue.
147  LM &= ~SR.LaneMask;
148  if (LM.none())
149  break;
150  }
151  }
152  }
153  return true;
154 }
155 
157  SlotIndex UseIdx, bool cheapAsAMove) {
158  assert(ScannedRemattable && "Call anyRematerializable first");
159 
160  // Use scanRemattable info.
161  if (!Remattable.count(OrigVNI))
162  return false;
163 
164  // No defining instruction provided.
165  SlotIndex DefIdx;
166  assert(RM.OrigMI && "No defining instruction for remattable value");
167  DefIdx = LIS.getInstructionIndex(*RM.OrigMI);
168 
169  // If only cheap remats were requested, bail out early.
170  if (cheapAsAMove && !TII.isAsCheapAsAMove(*RM.OrigMI))
171  return false;
172 
173  // Verify that all used registers are available with the same values.
174  if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
175  return false;
176 
177  return true;
178 }
179 
182  unsigned DestReg,
183  const Remat &RM,
184  const TargetRegisterInfo &tri,
185  bool Late) {
186  assert(RM.OrigMI && "Invalid remat");
187  TII.reMaterialize(MBB, MI, DestReg, 0, *RM.OrigMI, tri);
188  // DestReg of the cloned instruction cannot be Dead. Set isDead of DestReg
189  // to false anyway in case the isDead flag of RM.OrigMI's dest register
190  // is true.
191  (*--MI).getOperand(0).setIsDead(false);
192  Rematted.insert(RM.ParentVNI);
193  return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot();
194 }
195 
197  if (TheDelegate && TheDelegate->LRE_CanEraseVirtReg(Reg))
198  LIS.removeInterval(Reg);
199 }
200 
201 bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
203  MachineInstr *DefMI = nullptr, *UseMI = nullptr;
204 
205  // Check that there is a single def and a single use.
206  for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg())) {
207  MachineInstr *MI = MO.getParent();
208  if (MO.isDef()) {
209  if (DefMI && DefMI != MI)
210  return false;
211  if (!MI->canFoldAsLoad())
212  return false;
213  DefMI = MI;
214  } else if (!MO.isUndef()) {
215  if (UseMI && UseMI != MI)
216  return false;
217  // FIXME: Targets don't know how to fold subreg uses.
218  if (MO.getSubReg())
219  return false;
220  UseMI = MI;
221  }
222  }
223  if (!DefMI || !UseMI)
224  return false;
225 
226  // Since we're moving the DefMI load, make sure we're not extending any live
227  // ranges.
229  LIS.getInstructionIndex(*UseMI)))
230  return false;
231 
232  // We also need to make sure it is safe to move the load.
233  // Assume there are stores between DefMI and UseMI.
234  bool SawStore = true;
235  if (!DefMI->isSafeToMove(nullptr, SawStore))
236  return false;
237 
238  LLVM_DEBUG(dbgs() << "Try to fold single def: " << *DefMI
239  << " into single use: " << *UseMI);
240 
242  if (UseMI->readsWritesVirtualRegister(LI->reg(), &Ops).second)
243  return false;
244 
245  MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS);
246  if (!FoldMI)
247  return false;
248  LLVM_DEBUG(dbgs() << " folded: " << *FoldMI);
249  LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI);
250  // Update the call site info.
252  UseMI->getMF()->moveCallSiteInfo(UseMI, FoldMI);
254  DefMI->addRegisterDead(LI->reg(), nullptr);
255  Dead.push_back(DefMI);
256  ++NumDCEFoldedLoads;
257  return true;
258 }
259 
260 bool LiveRangeEdit::useIsKill(const LiveInterval &LI,
261  const MachineOperand &MO) const {
262  const MachineInstr &MI = *MO.getParent();
264  if (LI.Query(Idx).isKill())
265  return true;
267  unsigned SubReg = MO.getSubReg();
269  for (const LiveInterval::SubRange &S : LI.subranges()) {
270  if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
271  return true;
272  }
273  return false;
274 }
275 
276 /// Find all live intervals that need to shrink, then remove the instruction.
277 void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink,
278  AAResults *AA) {
279  assert(MI->allDefsAreDead() && "Def isn't really dead");
280  SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
281 
282  // Never delete a bundled instruction.
283  if (MI->isBundled()) {
284  return;
285  }
286  // Never delete inline asm.
287  if (MI->isInlineAsm()) {
288  LLVM_DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
289  return;
290  }
291 
292  // Use the same criteria as DeadMachineInstructionElim.
293  bool SawStore = false;
294  if (!MI->isSafeToMove(nullptr, SawStore)) {
295  LLVM_DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
296  return;
297  }
298 
299  LLVM_DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
300 
301  // Collect virtual registers to be erased after MI is gone.
302  SmallVector<unsigned, 8> RegsToErase;
303  bool ReadsPhysRegs = false;
304  bool isOrigDef = false;
305  unsigned Dest;
306  // Only optimize rematerialize case when the instruction has one def, since
307  // otherwise we could leave some dead defs in the code. This case is
308  // extremely rare.
309  if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
310  MI->getDesc().getNumDefs() == 1) {
311  Dest = MI->getOperand(0).getReg();
312  unsigned Original = VRM->getOriginal(Dest);
313  LiveInterval &OrigLI = LIS.getInterval(Original);
314  VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
315  // The original live-range may have been shrunk to
316  // an empty live-range. It happens when it is dead, but
317  // we still keep it around to be able to rematerialize
318  // other values that depend on it.
319  if (OrigVNI)
320  isOrigDef = SlotIndex::isSameInstr(OrigVNI->def, Idx);
321  }
322 
323  bool HasLiveVRegUses = false;
324 
325  // Check for live intervals that may shrink
326  for (const MachineOperand &MO : MI->operands()) {
327  if (!MO.isReg())
328  continue;
329  Register Reg = MO.getReg();
331  // Check if MI reads any unreserved physregs.
332  if (Reg && MO.readsReg() && !MRI.isReserved(Reg))
333  ReadsPhysRegs = true;
334  else if (MO.isDef())
335  LIS.removePhysRegDefAt(Reg.asMCReg(), Idx);
336  continue;
337  }
338  LiveInterval &LI = LIS.getInterval(Reg);
339 
340  // Shrink read registers, unless it is likely to be expensive and
341  // unlikely to change anything. We typically don't want to shrink the
342  // PIC base register that has lots of uses everywhere.
343  // Always shrink COPY uses that probably come from live range splitting.
344  if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MO.isDef())) ||
345  (MO.readsReg() && (MRI.hasOneNonDBGUse(Reg) || useIsKill(LI, MO))))
346  ToShrink.insert(&LI);
347  else if (MO.readsReg())
348  HasLiveVRegUses = true;
349 
350  // Remove defined value.
351  if (MO.isDef()) {
352  if (TheDelegate && LI.getVNInfoAt(Idx) != nullptr)
353  TheDelegate->LRE_WillShrinkVirtReg(LI.reg());
354  LIS.removeVRegDefAt(LI, Idx);
355  if (LI.empty())
356  RegsToErase.push_back(Reg);
357  }
358  }
359 
360  // Currently, we don't support DCE of physreg live ranges. If MI reads
361  // any unreserved physregs, don't erase the instruction, but turn it into
362  // a KILL instead. This way, the physreg live ranges don't end up
363  // dangling.
364  // FIXME: It would be better to have something like shrinkToUses() for
365  // physregs. That could potentially enable more DCE and it would free up
366  // the physreg. It would not happen often, though.
367  if (ReadsPhysRegs) {
368  MI->setDesc(TII.get(TargetOpcode::KILL));
369  // Remove all operands that aren't physregs.
370  for (unsigned i = MI->getNumOperands(); i; --i) {
371  const MachineOperand &MO = MI->getOperand(i-1);
372  if (MO.isReg() && Register::isPhysicalRegister(MO.getReg()))
373  continue;
374  MI->RemoveOperand(i-1);
375  }
376  LLVM_DEBUG(dbgs() << "Converted physregs to:\t" << *MI);
377  } else {
378  // If the dest of MI is an original reg and MI is reMaterializable,
379  // don't delete the inst. Replace the dest with a new reg, and keep
380  // the inst for remat of other siblings. The inst is saved in
381  // LiveRangeEdit::DeadRemats and will be deleted after all the
382  // allocations of the func are done.
383  // However, immediately delete instructions which have unshrunk virtual
384  // register uses. That may provoke RA to split an interval at the KILL
385  // and later result in an invalid live segment end.
386  if (isOrigDef && DeadRemats && !HasLiveVRegUses &&
387  TII.isTriviallyReMaterializable(*MI, AA)) {
388  LiveInterval &NewLI = createEmptyIntervalFrom(Dest, false);
389  VNInfo *VNI = NewLI.getNextValue(Idx, LIS.getVNInfoAllocator());
390  NewLI.addSegment(LiveInterval::Segment(Idx, Idx.getDeadSlot(), VNI));
391  pop_back();
392  DeadRemats->insert(MI);
394  MI->substituteRegister(Dest, NewLI.reg(), 0, TRI);
395  MI->getOperand(0).setIsDead(true);
396  } else {
397  if (TheDelegate)
398  TheDelegate->LRE_WillEraseInstruction(MI);
400  MI->eraseFromParent();
401  ++NumDCEDeleted;
402  }
403  }
404 
405  // Erase any virtregs that are now empty and unused. There may be <undef>
406  // uses around. Keep the empty live range in that case.
407  for (unsigned i = 0, e = RegsToErase.size(); i != e; ++i) {
408  Register Reg = RegsToErase[i];
409  if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) {
410  ToShrink.remove(&LIS.getInterval(Reg));
411  eraseVirtReg(Reg);
412  }
413  }
414 }
415 
417  ArrayRef<Register> RegsBeingSpilled,
418  AAResults *AA) {
419  ToShrinkSet ToShrink;
420 
421  for (;;) {
422  // Erase all dead defs.
423  while (!Dead.empty())
424  eliminateDeadDef(Dead.pop_back_val(), ToShrink, AA);
425 
426  if (ToShrink.empty())
427  break;
428 
429  // Shrink just one live interval. Then delete new dead defs.
430  LiveInterval *LI = ToShrink.pop_back_val();
431  if (foldAsLoad(LI, Dead))
432  continue;
433  unsigned VReg = LI->reg();
434  if (TheDelegate)
435  TheDelegate->LRE_WillShrinkVirtReg(VReg);
436  if (!LIS.shrinkToUses(LI, &Dead))
437  continue;
438 
439  // Don't create new intervals for a register being spilled.
440  // The new intervals would have to be spilled anyway so its not worth it.
441  // Also they currently aren't spilled so creating them and not spilling
442  // them results in incorrect code.
443  if (llvm::is_contained(RegsBeingSpilled, VReg))
444  continue;
445 
446  // LI may have been separated, create new intervals.
447  LI->RenumberValues();
449  LIS.splitSeparateComponents(*LI, SplitLIs);
450  if (!SplitLIs.empty())
451  ++NumFracRanges;
452 
453  Register Original = VRM ? VRM->getOriginal(VReg) : Register();
454  for (const LiveInterval *SplitLI : SplitLIs) {
455  // If LI is an original interval that hasn't been split yet, make the new
456  // intervals their own originals instead of referring to LI. The original
457  // interval must contain all the split products, and LI doesn't.
458  if (Original != VReg && Original != 0)
459  VRM->setIsSplitFromReg(SplitLI->reg(), Original);
460  if (TheDelegate)
461  TheDelegate->LRE_DidCloneVirtReg(SplitLI->reg(), VReg);
462  }
463  }
464 }
465 
466 // Keep track of new virtual registers created via
467 // MachineRegisterInfo::createVirtualRegister.
468 void
469 LiveRangeEdit::MRI_NoteNewVirtualRegister(Register VReg) {
470  if (VRM)
471  VRM->grow();
472 
473  NewRegs.push_back(VReg);
474 }
475 
477  VirtRegAuxInfo &VRAI) {
478  for (unsigned I = 0, Size = size(); I < Size; ++I) {
479  LiveInterval &LI = LIS.getInterval(get(I));
480  if (MRI.recomputeRegClass(LI.reg()))
481  LLVM_DEBUG({
482  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
483  dbgs() << "Inflated " << printReg(LI.reg()) << " to "
484  << TRI->getRegClassName(MRI.getRegClass(LI.reg())) << '\n';
485  });
487  }
488 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::LaneBitmask
Definition: LaneBitmask.h:40
i
i
Definition: README.txt:29
llvm::LiveRangeEdit::Remat
Remat - Information needed to rematerialize at a specific location.
Definition: LiveRangeEdit.h:195
llvm::LiveRangeEdit::checkRematerializable
bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, AAResults *)
checkRematerializable - Manually add VNI to the list of rematerializable values if DefMI may be remat...
Definition: LiveRangeEdit.cpp:70
llvm::MachineInstr::addRegisterDead
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
Definition: MachineInstr.cpp:1938
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:22
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::LiveRange::empty
bool empty() const
Definition: LiveInterval.h:374
llvm::LiveIntervals::getSlotIndexes
SlotIndexes * getSlotIndexes() const
Definition: LiveIntervals.h:211
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:50
llvm::LiveRangeEdit::calculateRegClassAndHint
void calculateRegClassAndHint(MachineFunction &, VirtRegAuxInfo &)
calculateRegClassAndHint - Recompute register class and hint for each new register.
Definition: LiveRangeEdit.cpp:476
llvm::LiveInterval::createSubRange
SubRange * createSubRange(BumpPtrAllocator &Allocator, LaneBitmask LaneMask)
Creates a new empty subregister live range.
Definition: LiveInterval.h:779
llvm::MachineInstr::isSafeToMove
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Definition: MachineInstr.cpp:1215
aa
aa
Definition: AliasAnalysis.cpp:848
llvm::MachineRegisterInfo::recomputeRegClass
bool recomputeRegClass(Register Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
Definition: MachineRegisterInfo.cpp:122
llvm::LiveRangeEdit::Delegate::LRE_CanEraseVirtReg
virtual bool LRE_CanEraseVirtReg(Register)
Called when a virtual register is no longer used.
Definition: LiveRangeEdit.h:58
llvm::LiveRangeEdit::createFrom
Register createFrom(Register OldReg)
createFrom - Create a new virtual register based on OldReg.
Definition: LiveRangeEdit.cpp:54
llvm::LiveInterval::isSpillable
bool isSpillable() const
isSpillable - Can this interval be spilled?
Definition: LiveInterval.h:813
llvm::SmallVector< unsigned, 8 >
Statistic.h
llvm::VirtRegAuxInfo
Calculate auxiliary information for a virtual register such as its spill weight and allocation hint.
Definition: CalcSpillWeights.h:46
llvm::VirtRegMap::getOriginal
Register getOriginal(Register VirtReg) const
getOriginal - Return the original virtual register that VirtReg descends from through splitting.
Definition: VirtRegMap.h:170
llvm::LiveIntervals::getInstructionFromIndex
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
Definition: LiveIntervals.h:231
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:153
llvm::VNInfo::def
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::MachineFunction::moveCallSiteInfo
void moveCallSiteInfo(const MachineInstr *Old, const MachineInstr *New)
Move the call site info from Old to \New call site info.
Definition: MachineFunction.cpp:952
llvm::LiveIntervals::removeInterval
void removeInterval(Register Reg)
Interval removal.
Definition: LiveIntervals.h:145
TargetInstrInfo.h
llvm::LiveRangeEdit::eliminateDeadDefs
void eliminateDeadDefs(SmallVectorImpl< MachineInstr * > &Dead, ArrayRef< Register > RegsBeingSpilled=None, AAResults *AA=nullptr)
eliminateDeadDefs - Try to delete machine instructions that are now dead (allDefsAreDead returns true...
Definition: LiveRangeEdit.cpp:416
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:666
llvm::LiveRangeEdit::getReg
Register getReg() const
Definition: LiveRangeEdit.h:149
llvm::LiveRangeEdit::Delegate::LRE_WillEraseInstruction
virtual void LRE_WillEraseInstruction(MachineInstr *MI)
Called immediately before erasing a dead machine instruction.
Definition: LiveRangeEdit.h:54
llvm::VirtRegAuxInfo::calculateSpillWeightAndHint
void calculateSpillWeightAndHint(LiveInterval &LI)
(re)compute li's spill weight and allocation hint.
Definition: CalcSpillWeights.cpp:140
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1564
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::LiveIntervals::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
Definition: LiveIntervals.h:226
MachineRegisterInfo.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::LiveRangeEdit::get
Register get(unsigned idx) const
Definition: LiveRangeEdit.h:157
llvm::TargetRegisterInfo::getSubRegIndexLaneMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:377
llvm::AAResults
Definition: AliasAnalysis.h:507
llvm::LiveRangeEdit::anyRematerializable
bool anyRematerializable(AAResults *)
anyRematerializable - Return true if any parent values may be rematerializable.
Definition: LiveRangeEdit.cpp:98
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:928
llvm::LiveRange::addSegment
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
Definition: LiveInterval.cpp:548
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MachineRegisterInfo::reg_nodbg_operands
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:337
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineInstr::shouldUpdateCallSiteInfo
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
Definition: MachineInstr.cpp:703
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::SlotIndex::getDeadSlot
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:259
llvm::LiveRangeEdit::eraseVirtReg
void eraseVirtReg(Register Reg)
eraseVirtReg - Notify the delegate that Reg is no longer in use, and try to erase it from LIS.
Definition: LiveRangeEdit.cpp:196
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::SetVector::empty
bool empty() const
Determine if the SetVector is empty or not.
Definition: SetVector.h:71
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SlotIndexes::insertMachineInstrInMaps
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
Definition: SlotIndexes.h:535
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::LiveRangeEdit::getParent
LiveInterval & getParent() const
Definition: LiveRangeEdit.h:144
llvm::VirtRegMap::setIsSplitFromReg
void setIsSplitFromReg(Register virtReg, Register SReg)
records virtReg is a split live interval from SReg.
Definition: VirtRegMap.h:154
llvm::LiveIntervals::removePhysRegDefAt
void removePhysRegDefAt(MCRegister Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
Definition: LiveIntervals.cpp:1718
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
llvm::LiveRange::RenumberValues
void RenumberValues()
RenumberValues - Renumber all values in order of appearance and remove unused values.
Definition: LiveInterval.cpp:531
llvm::LiveIntervals::ReplaceMachineInstrInMaps
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
Definition: LiveIntervals.h:280
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
LiveIntervals.h
VirtRegMap.h
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:745
llvm::BumpPtrAllocatorImpl
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:63
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::LiveRangeEdit::pop_back
void pop_back()
pop_back - It allows LiveRangeEdit users to drop new registers.
Definition: LiveRangeEdit.h:167
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1657
llvm::SlotIndex::isSameInstr
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:197
llvm::LiveRange::getNextValue
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:323
llvm::LiveRange::Query
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:533
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::TargetInstrInfo::isAsCheapAsAMove
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
Definition: TargetInstrInfo.h:374
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineInstr::readsWritesVirtualRegister
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Definition: MachineInstr.cpp:995
llvm::LiveIntervals::shrinkToUses
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses.
Definition: LiveIntervals.cpp:456
llvm::LiveRangeEdit::canRematerializeAt
bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx, bool cheapAsAMove)
canRematerializeAt - Determine if ParentVNI can be rematerialized at UseIdx.
Definition: LiveRangeEdit.cpp:156
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::SlotIndex::getRegSlot
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:254
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:114
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:482
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LiveRangeEdit::rematerializeAt
SlotIndex rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &, bool Late=false)
rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an instruction into MBB before...
Definition: LiveRangeEdit.cpp:180
llvm::LaneBitmask::none
constexpr bool none() const
Definition: LaneBitmask.h:52
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:417
llvm::TargetInstrInfo::reMaterialize
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
Definition: TargetInstrInfo.cpp:419
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::LiveIntervals::createEmptyInterval
LiveInterval & createEmptyInterval(Register Reg)
Interval creation.
Definition: LiveIntervals.h:131
llvm::LiveInterval::SubRange
A live range for subregisters.
Definition: LiveInterval.h:687
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
llvm::TargetInstrInfo::isTriviallyReMaterializable
bool isTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
Definition: TargetInstrInfo.h:124
LiveRangeEdit.h
llvm::VirtRegMap::grow
void grow()
Definition: VirtRegMap.cpp:78
llvm::MachineRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition: MachineRegisterInfo.cpp:511
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::LiveRangeEdit::allUsesAvailableAt
bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx, SlotIndex UseIdx) const
allUsesAvailableAt - Return true if all registers used by OrigMI at OrigIdx are also available with t...
Definition: LiveRangeEdit.cpp:106
llvm::TargetInstrInfo::isIgnorableUse
virtual bool isIgnorableUse(const MachineOperand &MO) const
Given MO is a PhysReg use return if it can be ignored for the purpose of instruction rematerializatio...
Definition: TargetInstrInfo.h:134
llvm::MachineOperand::readsReg
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
Definition: MachineOperand.h:458
llvm::LiveRangeEdit::Delegate::LRE_DidCloneVirtReg
virtual void LRE_DidCloneVirtReg(Register New, Register Old)
Called after cloning a virtual register.
Definition: LiveRangeEdit.h:65
llvm::VNInfo
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
llvm::LiveRange::getVNInfoAt
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:413
llvm::LiveInterval::markNotSpillable
void markNotSpillable()
markNotSpillable - Mark interval as not spillable
Definition: LiveInterval.h:816
llvm::TargetInstrInfo::foldMemoryOperand
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
Definition: TargetInstrInfo.cpp:560
llvm::LiveRangeEdit::size
unsigned size() const
Definition: LiveRangeEdit.h:155
llvm::LiveIntervals::RemoveMachineInstrFromMaps
void RemoveMachineInstrFromMaps(MachineInstr &MI)
Definition: LiveIntervals.h:276
llvm::LiveIntervals::splitSeparateComponents
void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)
Split separate components in LiveInterval LI into separate intervals.
Definition: LiveIntervals.cpp:1744
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::LiveInterval::reg
Register reg() const
Definition: LiveInterval.h:711
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::SmallVectorImpl< MachineInstr * >
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:62
llvm::LiveIntervals::hasInterval
bool hasInterval(Register Reg) const
Definition: LiveIntervals.h:125
CalcSpillWeights.h
llvm::MachineRegisterInfo::reg_nodbg_empty
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Definition: MachineRegisterInfo.h:377
raw_ostream.h
llvm::LiveRangeEdit::Delegate::LRE_WillShrinkVirtReg
virtual void LRE_WillShrinkVirtReg(Register)
Called before shrinking the live range of a virtual register.
Definition: LiveRangeEdit.h:61
llvm::SetVector
A vector that has set insertion semantics.
Definition: SetVector.h:39
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:680
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::SetVector::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SetVector.h:231
llvm::LiveIntervals::removeVRegDefAt
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos.
Definition: LiveIntervals.cpp:1726
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:618
Debug.h
llvm::LiveQueryResult::isKill
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:112
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::LiveIntervals::getVNInfoAllocator
VNInfo::Allocator & getVNInfoAllocator()
Definition: LiveIntervals.h:284
llvm::LiveInterval::subranges
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:769