LLVM  16.0.0git
LiveRangeEdit.cpp
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1 //===-- LiveRangeEdit.cpp - Basic tools for editing a register live range -===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // The LiveRangeEdit class represents changes done to a virtual register when it
10 // is spilled or split.
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Support/Debug.h"
22 
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "regalloc"
26 
27 STATISTIC(NumDCEDeleted, "Number of instructions deleted by DCE");
28 STATISTIC(NumDCEFoldedLoads, "Number of single use loads folded after DCE");
29 STATISTIC(NumFracRanges, "Number of live ranges fractured by DCE");
30 STATISTIC(NumReMaterialization, "Number of instructions rematerialized");
31 
32 void LiveRangeEdit::Delegate::anchor() { }
33 
34 LiveInterval &LiveRangeEdit::createEmptyIntervalFrom(Register OldReg,
35  bool createSubRanges) {
36  Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
37  if (VRM)
38  VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
39 
40  LiveInterval &LI = LIS.createEmptyInterval(VReg);
41  if (Parent && !Parent->isSpillable())
42  LI.markNotSpillable();
43  if (createSubRanges) {
44  // Create empty subranges if the OldReg's interval has them. Do not create
45  // the main range here---it will be constructed later after the subranges
46  // have been finalized.
47  LiveInterval &OldLI = LIS.getInterval(OldReg);
49  for (LiveInterval::SubRange &S : OldLI.subranges())
50  LI.createSubRange(Alloc, S.LaneMask);
51  }
52  return LI;
53 }
54 
56  Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
57  if (VRM) {
58  VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
59  }
60  // FIXME: Getting the interval here actually computes it.
61  // In theory, this may not be what we want, but in practice
62  // the createEmptyIntervalFrom API is used when this is not
63  // the case. Generally speaking we just want to annotate the
64  // LiveInterval when it gets created but we cannot do that at
65  // the moment.
66  if (Parent && !Parent->isSpillable())
67  LIS.getInterval(VReg).markNotSpillable();
68  return VReg;
69 }
70 
72  const MachineInstr *DefMI) {
73  assert(DefMI && "Missing instruction");
74  ScannedRemattable = true;
76  return false;
77  Remattable.insert(VNI);
78  return true;
79 }
80 
81 void LiveRangeEdit::scanRemattable() {
82  for (VNInfo *VNI : getParent().valnos) {
83  if (VNI->isUnused())
84  continue;
85  unsigned Original = VRM->getOriginal(getReg());
86  LiveInterval &OrigLI = LIS.getInterval(Original);
87  VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
88  if (!OrigVNI)
89  continue;
91  if (!DefMI)
92  continue;
93  checkRematerializable(OrigVNI, DefMI);
94  }
95  ScannedRemattable = true;
96 }
97 
99  if (!ScannedRemattable)
100  scanRemattable();
101  return !Remattable.empty();
102 }
103 
104 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
105 /// OrigIdx are also available with the same value at UseIdx.
107  SlotIndex OrigIdx,
108  SlotIndex UseIdx) const {
109  OrigIdx = OrigIdx.getRegSlot(true);
110  UseIdx = std::max(UseIdx, UseIdx.getRegSlot(true));
111  for (const MachineOperand &MO : OrigMI->operands()) {
112  if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
113  continue;
114 
115  // We can't remat physreg uses, unless it is a constant or target wants
116  // to ignore this use.
117  if (Register::isPhysicalRegister(MO.getReg())) {
118  if (MRI.isConstantPhysReg(MO.getReg()) || TII.isIgnorableUse(MO))
119  continue;
120  return false;
121  }
122 
123  LiveInterval &li = LIS.getInterval(MO.getReg());
124  const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
125  if (!OVNI)
126  continue;
127 
128  // Don't allow rematerialization immediately after the original def.
129  // It would be incorrect if OrigMI redefines the register.
130  // See PR14098.
131  if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
132  return false;
133 
134  if (OVNI != li.getVNInfoAt(UseIdx))
135  return false;
136 
137  // Check that subrange is live at UseIdx.
138  if (li.hasSubRanges()) {
140  unsigned SubReg = MO.getSubReg();
142  : MRI.getMaxLaneMaskForVReg(MO.getReg());
143  for (LiveInterval::SubRange &SR : li.subranges()) {
144  if ((SR.LaneMask & LM).none())
145  continue;
146  if (!SR.liveAt(UseIdx))
147  return false;
148  // Early exit if all used lanes are checked. No need to continue.
149  LM &= ~SR.LaneMask;
150  if (LM.none())
151  break;
152  }
153  }
154  }
155  return true;
156 }
157 
159  SlotIndex UseIdx, bool cheapAsAMove) {
160  assert(ScannedRemattable && "Call anyRematerializable first");
161 
162  // Use scanRemattable info.
163  if (!Remattable.count(OrigVNI))
164  return false;
165 
166  // No defining instruction provided.
167  SlotIndex DefIdx;
168  assert(RM.OrigMI && "No defining instruction for remattable value");
169  DefIdx = LIS.getInstructionIndex(*RM.OrigMI);
170 
171  // If only cheap remats were requested, bail out early.
172  if (cheapAsAMove && !TII.isAsCheapAsAMove(*RM.OrigMI))
173  return false;
174 
175  // Verify that all used registers are available with the same values.
176  if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
177  return false;
178 
179  return true;
180 }
181 
184  unsigned DestReg,
185  const Remat &RM,
186  const TargetRegisterInfo &tri,
187  bool Late,
188  unsigned SubIdx,
189  MachineInstr *ReplaceIndexMI) {
190  assert(RM.OrigMI && "Invalid remat");
191  TII.reMaterialize(MBB, MI, DestReg, SubIdx, *RM.OrigMI, tri);
192  // DestReg of the cloned instruction cannot be Dead. Set isDead of DestReg
193  // to false anyway in case the isDead flag of RM.OrigMI's dest register
194  // is true.
195  (*--MI).getOperand(0).setIsDead(false);
196  Rematted.insert(RM.ParentVNI);
197  ++NumReMaterialization;
198 
199  if (ReplaceIndexMI)
200  return LIS.ReplaceMachineInstrInMaps(*ReplaceIndexMI, *MI).getRegSlot();
201  return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot();
202 }
203 
205  if (TheDelegate && TheDelegate->LRE_CanEraseVirtReg(Reg))
206  LIS.removeInterval(Reg);
207 }
208 
209 bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
211  MachineInstr *DefMI = nullptr, *UseMI = nullptr;
212 
213  // Check that there is a single def and a single use.
214  for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg())) {
215  MachineInstr *MI = MO.getParent();
216  if (MO.isDef()) {
217  if (DefMI && DefMI != MI)
218  return false;
219  if (!MI->canFoldAsLoad())
220  return false;
221  DefMI = MI;
222  } else if (!MO.isUndef()) {
223  if (UseMI && UseMI != MI)
224  return false;
225  // FIXME: Targets don't know how to fold subreg uses.
226  if (MO.getSubReg())
227  return false;
228  UseMI = MI;
229  }
230  }
231  if (!DefMI || !UseMI)
232  return false;
233 
234  // Since we're moving the DefMI load, make sure we're not extending any live
235  // ranges.
237  LIS.getInstructionIndex(*UseMI)))
238  return false;
239 
240  // We also need to make sure it is safe to move the load.
241  // Assume there are stores between DefMI and UseMI.
242  bool SawStore = true;
243  if (!DefMI->isSafeToMove(nullptr, SawStore))
244  return false;
245 
246  LLVM_DEBUG(dbgs() << "Try to fold single def: " << *DefMI
247  << " into single use: " << *UseMI);
248 
250  if (UseMI->readsWritesVirtualRegister(LI->reg(), &Ops).second)
251  return false;
252 
253  MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS);
254  if (!FoldMI)
255  return false;
256  LLVM_DEBUG(dbgs() << " folded: " << *FoldMI);
257  LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI);
258  // Update the call site info.
260  UseMI->getMF()->moveCallSiteInfo(UseMI, FoldMI);
262  DefMI->addRegisterDead(LI->reg(), nullptr);
263  Dead.push_back(DefMI);
264  ++NumDCEFoldedLoads;
265  return true;
266 }
267 
268 bool LiveRangeEdit::useIsKill(const LiveInterval &LI,
269  const MachineOperand &MO) const {
270  const MachineInstr &MI = *MO.getParent();
272  if (LI.Query(Idx).isKill())
273  return true;
275  unsigned SubReg = MO.getSubReg();
277  for (const LiveInterval::SubRange &S : LI.subranges()) {
278  if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
279  return true;
280  }
281  return false;
282 }
283 
284 /// Find all live intervals that need to shrink, then remove the instruction.
285 void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink) {
286  assert(MI->allDefsAreDead() && "Def isn't really dead");
287  SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
288 
289  // Never delete a bundled instruction.
290  if (MI->isBundled()) {
291  return;
292  }
293  // Never delete inline asm.
294  if (MI->isInlineAsm()) {
295  LLVM_DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
296  return;
297  }
298 
299  // Use the same criteria as DeadMachineInstructionElim.
300  bool SawStore = false;
301  if (!MI->isSafeToMove(nullptr, SawStore)) {
302  LLVM_DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
303  return;
304  }
305 
306  LLVM_DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
307 
308  // Collect virtual registers to be erased after MI is gone.
309  SmallVector<unsigned, 8> RegsToErase;
310  bool ReadsPhysRegs = false;
311  bool isOrigDef = false;
312  Register Dest;
313  unsigned DestSubReg;
314  // Only optimize rematerialize case when the instruction has one def, since
315  // otherwise we could leave some dead defs in the code. This case is
316  // extremely rare.
317  if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
318  MI->getDesc().getNumDefs() == 1) {
319  Dest = MI->getOperand(0).getReg();
320  DestSubReg = MI->getOperand(0).getSubReg();
321  unsigned Original = VRM->getOriginal(Dest);
322  LiveInterval &OrigLI = LIS.getInterval(Original);
323  VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
324  // The original live-range may have been shrunk to
325  // an empty live-range. It happens when it is dead, but
326  // we still keep it around to be able to rematerialize
327  // other values that depend on it.
328  if (OrigVNI)
329  isOrigDef = SlotIndex::isSameInstr(OrigVNI->def, Idx);
330  }
331 
332  bool HasLiveVRegUses = false;
333 
334  // Check for live intervals that may shrink
335  for (const MachineOperand &MO : MI->operands()) {
336  if (!MO.isReg())
337  continue;
338  Register Reg = MO.getReg();
340  // Check if MI reads any unreserved physregs.
341  if (Reg && MO.readsReg() && !MRI.isReserved(Reg))
342  ReadsPhysRegs = true;
343  else if (MO.isDef())
344  LIS.removePhysRegDefAt(Reg.asMCReg(), Idx);
345  continue;
346  }
347  LiveInterval &LI = LIS.getInterval(Reg);
348 
349  // Shrink read registers, unless it is likely to be expensive and
350  // unlikely to change anything. We typically don't want to shrink the
351  // PIC base register that has lots of uses everywhere.
352  // Always shrink COPY uses that probably come from live range splitting.
353  if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MO.isDef())) ||
354  (MO.readsReg() && (MRI.hasOneNonDBGUse(Reg) || useIsKill(LI, MO))))
355  ToShrink.insert(&LI);
356  else if (MO.readsReg())
357  HasLiveVRegUses = true;
358 
359  // Remove defined value.
360  if (MO.isDef()) {
361  if (TheDelegate && LI.getVNInfoAt(Idx) != nullptr)
362  TheDelegate->LRE_WillShrinkVirtReg(LI.reg());
363  LIS.removeVRegDefAt(LI, Idx);
364  if (LI.empty())
365  RegsToErase.push_back(Reg);
366  }
367  }
368 
369  // Currently, we don't support DCE of physreg live ranges. If MI reads
370  // any unreserved physregs, don't erase the instruction, but turn it into
371  // a KILL instead. This way, the physreg live ranges don't end up
372  // dangling.
373  // FIXME: It would be better to have something like shrinkToUses() for
374  // physregs. That could potentially enable more DCE and it would free up
375  // the physreg. It would not happen often, though.
376  if (ReadsPhysRegs) {
377  MI->setDesc(TII.get(TargetOpcode::KILL));
378  // Remove all operands that aren't physregs.
379  for (unsigned i = MI->getNumOperands(); i; --i) {
380  const MachineOperand &MO = MI->getOperand(i-1);
381  if (MO.isReg() && Register::isPhysicalRegister(MO.getReg()))
382  continue;
383  MI->removeOperand(i-1);
384  }
385  LLVM_DEBUG(dbgs() << "Converted physregs to:\t" << *MI);
386  } else {
387  // If the dest of MI is an original reg and MI is reMaterializable,
388  // don't delete the inst. Replace the dest with a new reg, and keep
389  // the inst for remat of other siblings. The inst is saved in
390  // LiveRangeEdit::DeadRemats and will be deleted after all the
391  // allocations of the func are done.
392  // However, immediately delete instructions which have unshrunk virtual
393  // register uses. That may provoke RA to split an interval at the KILL
394  // and later result in an invalid live segment end.
395  if (isOrigDef && DeadRemats && !HasLiveVRegUses &&
397  LiveInterval &NewLI = createEmptyIntervalFrom(Dest, false);
398  VNInfo::Allocator &Alloc = LIS.getVNInfoAllocator();
399  VNInfo *VNI = NewLI.getNextValue(Idx, Alloc);
400  NewLI.addSegment(LiveInterval::Segment(Idx, Idx.getDeadSlot(), VNI));
401 
402  if (DestSubReg) {
404  auto *SR = NewLI.createSubRange(
405  Alloc, TRI->getSubRegIndexLaneMask(DestSubReg));
406  SR->addSegment(LiveInterval::Segment(Idx, Idx.getDeadSlot(),
407  SR->getNextValue(Idx, Alloc)));
408  }
409 
410  pop_back();
411  DeadRemats->insert(MI);
413  MI->substituteRegister(Dest, NewLI.reg(), 0, TRI);
414  MI->getOperand(0).setIsDead(true);
415  } else {
416  if (TheDelegate)
417  TheDelegate->LRE_WillEraseInstruction(MI);
419  MI->eraseFromParent();
420  ++NumDCEDeleted;
421  }
422  }
423 
424  // Erase any virtregs that are now empty and unused. There may be <undef>
425  // uses around. Keep the empty live range in that case.
426  for (unsigned i = 0, e = RegsToErase.size(); i != e; ++i) {
427  Register Reg = RegsToErase[i];
428  if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) {
429  ToShrink.remove(&LIS.getInterval(Reg));
430  eraseVirtReg(Reg);
431  }
432  }
433 }
434 
436  ArrayRef<Register> RegsBeingSpilled) {
437  ToShrinkSet ToShrink;
438 
439  for (;;) {
440  // Erase all dead defs.
441  while (!Dead.empty())
442  eliminateDeadDef(Dead.pop_back_val(), ToShrink);
443 
444  if (ToShrink.empty())
445  break;
446 
447  // Shrink just one live interval. Then delete new dead defs.
448  LiveInterval *LI = ToShrink.pop_back_val();
449  if (foldAsLoad(LI, Dead))
450  continue;
451  unsigned VReg = LI->reg();
452  if (TheDelegate)
453  TheDelegate->LRE_WillShrinkVirtReg(VReg);
454  if (!LIS.shrinkToUses(LI, &Dead))
455  continue;
456 
457  // Don't create new intervals for a register being spilled.
458  // The new intervals would have to be spilled anyway so its not worth it.
459  // Also they currently aren't spilled so creating them and not spilling
460  // them results in incorrect code.
461  if (llvm::is_contained(RegsBeingSpilled, VReg))
462  continue;
463 
464  // LI may have been separated, create new intervals.
465  LI->RenumberValues();
467  LIS.splitSeparateComponents(*LI, SplitLIs);
468  if (!SplitLIs.empty())
469  ++NumFracRanges;
470 
471  Register Original = VRM ? VRM->getOriginal(VReg) : Register();
472  for (const LiveInterval *SplitLI : SplitLIs) {
473  // If LI is an original interval that hasn't been split yet, make the new
474  // intervals their own originals instead of referring to LI. The original
475  // interval must contain all the split products, and LI doesn't.
476  if (Original != VReg && Original != 0)
477  VRM->setIsSplitFromReg(SplitLI->reg(), Original);
478  if (TheDelegate)
479  TheDelegate->LRE_DidCloneVirtReg(SplitLI->reg(), VReg);
480  }
481  }
482 }
483 
484 // Keep track of new virtual registers created via
485 // MachineRegisterInfo::createVirtualRegister.
486 void
487 LiveRangeEdit::MRI_NoteNewVirtualRegister(Register VReg) {
488  if (VRM)
489  VRM->grow();
490 
491  NewRegs.push_back(VReg);
492 }
493 
495  VirtRegAuxInfo &VRAI) {
496  for (unsigned I = 0, Size = size(); I < Size; ++I) {
497  LiveInterval &LI = LIS.getInterval(get(I));
498  if (MRI.recomputeRegClass(LI.reg()))
499  LLVM_DEBUG({
500  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
501  dbgs() << "Inflated " << printReg(LI.reg()) << " to "
502  << TRI->getRegClassName(MRI.getRegClass(LI.reg())) << '\n';
503  });
505  }
506 }
llvm::LaneBitmask
Definition: LaneBitmask.h:40
i
i
Definition: README.txt:29
llvm::LiveRangeEdit::Remat
Remat - Information needed to rematerialize at a specific location.
Definition: LiveRangeEdit.h:192
llvm::MachineInstr::addRegisterDead
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
Definition: MachineInstr.cpp:1956
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:107
llvm::LiveRange::empty
bool empty() const
Definition: LiveInterval.h:382
llvm::LiveIntervals::getSlotIndexes
SlotIndexes * getSlotIndexes() const
Definition: LiveIntervals.h:209
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::LiveRangeEdit::calculateRegClassAndHint
void calculateRegClassAndHint(MachineFunction &, VirtRegAuxInfo &)
calculateRegClassAndHint - Recompute register class and hint for each new register.
Definition: LiveRangeEdit.cpp:494
llvm::LiveInterval::createSubRange
SubRange * createSubRange(BumpPtrAllocator &Allocator, LaneBitmask LaneMask)
Creates a new empty subregister live range.
Definition: LiveInterval.h:785
llvm::MachineInstr::isSafeToMove
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Definition: MachineInstr.cpp:1227
llvm::MachineRegisterInfo::recomputeRegClass
bool recomputeRegClass(Register Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
Definition: MachineRegisterInfo.cpp:120
llvm::LiveRangeEdit::anyRematerializable
bool anyRematerializable()
anyRematerializable - Return true if any parent values may be rematerializable.
Definition: LiveRangeEdit.cpp:98
llvm::LiveRangeEdit::Delegate::LRE_CanEraseVirtReg
virtual bool LRE_CanEraseVirtReg(Register)
Called when a virtual register is no longer used.
Definition: LiveRangeEdit.h:57
llvm::LiveRangeEdit::createFrom
Register createFrom(Register OldReg)
createFrom - Create a new virtual register based on OldReg.
Definition: LiveRangeEdit.cpp:55
llvm::LiveInterval::isSpillable
bool isSpillable() const
isSpillable - Can this interval be spilled?
Definition: LiveInterval.h:819
llvm::SmallVector< unsigned, 8 >
Statistic.h
llvm::VirtRegAuxInfo
Calculate auxiliary information for a virtual register such as its spill weight and allocation hint.
Definition: CalcSpillWeights.h:45
llvm::VirtRegMap::getOriginal
Register getOriginal(Register VirtReg) const
getOriginal - Return the original virtual register that VirtReg descends from through splitting.
Definition: VirtRegMap.h:169
llvm::LiveIntervals::getInstructionFromIndex
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
Definition: LiveIntervals.h:225
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:151
llvm::VNInfo::def
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
llvm::TargetInstrInfo::isTriviallyReMaterializable
bool isTriviallyReMaterializable(const MachineInstr &MI) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
Definition: TargetInstrInfo.h:130
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::MachineFunction::moveCallSiteInfo
void moveCallSiteInfo(const MachineInstr *Old, const MachineInstr *New)
Move the call site info from Old to \New call site info.
Definition: MachineFunction.cpp:954
llvm::LiveIntervals::removeInterval
void removeInterval(Register Reg)
Interval removal.
Definition: LiveIntervals.h:143
TargetInstrInfo.h
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:678
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::LiveRangeEdit::getReg
Register getReg() const
Definition: LiveRangeEdit.h:147
llvm::LiveRangeEdit::Delegate::LRE_WillEraseInstruction
virtual void LRE_WillEraseInstruction(MachineInstr *MI)
Called immediately before erasing a dead machine instruction.
Definition: LiveRangeEdit.h:53
llvm::VirtRegAuxInfo::calculateSpillWeightAndHint
void calculateSpillWeightAndHint(LiveInterval &LI)
(re)compute li's spill weight and allocation hint.
Definition: CalcSpillWeights.cpp:140
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::LiveIntervals::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
Definition: LiveIntervals.h:220
MachineRegisterInfo.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::LiveRangeEdit::get
Register get(unsigned idx) const
Definition: LiveRangeEdit.h:155
llvm::TargetRegisterInfo::getSubRegIndexLaneMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:381
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:930
llvm::LiveRange::addSegment
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
Definition: LiveInterval.cpp:533
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MachineRegisterInfo::reg_nodbg_operands
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:345
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineInstr::shouldUpdateCallSiteInfo
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
Definition: MachineInstr.cpp:715
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::SlotIndex::getDeadSlot
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:264
llvm::LiveRangeEdit::eraseVirtReg
void eraseVirtReg(Register Reg)
eraseVirtReg - Notify the delegate that Reg is no longer in use, and try to erase it from LIS.
Definition: LiveRangeEdit.cpp:204
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:686
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:82
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:237
llvm::SetVector::empty
bool empty() const
Determine if the SetVector is empty or not.
Definition: SetVector.h:72
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::SlotIndexes::insertMachineInstrInMaps
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
Definition: SlotIndexes.h:540
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:647
llvm::VirtRegMap::setIsSplitFromReg
void setIsSplitFromReg(Register virtReg, Register SReg)
records virtReg is a split live interval from SReg.
Definition: VirtRegMap.h:153
llvm::LiveIntervals::removePhysRegDefAt
void removePhysRegDefAt(MCRegister Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
Definition: LiveIntervals.cpp:1712
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::LiveRange::RenumberValues
void RenumberValues()
RenumberValues - Renumber all values in order of appearance and remove unused values.
Definition: LiveInterval.cpp:516
llvm::LiveIntervals::ReplaceMachineInstrInMaps
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
Definition: LiveIntervals.h:274
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
LiveIntervals.h
VirtRegMap.h
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:777
llvm::BumpPtrAllocatorImpl
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:63
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::LiveRangeEdit::pop_back
void pop_back()
pop_back - It allows LiveRangeEdit users to drop new registers.
Definition: LiveRangeEdit.h:165
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1843
llvm::SlotIndex::isSameInstr
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:198
llvm::LiveRange::getNextValue
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:331
llvm::LiveRange::Query
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:541
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::TargetInstrInfo::isAsCheapAsAMove
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
Definition: TargetInstrInfo.h:377
llvm::LiveRangeEdit::rematerializeAt
SlotIndex rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &, bool Late=false, unsigned SubIdx=0, MachineInstr *ReplaceIndexMI=nullptr)
rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an instruction into MBB before...
Definition: LiveRangeEdit.cpp:182
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineInstr::readsWritesVirtualRegister
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Definition: MachineInstr.cpp:1007
llvm::LiveIntervals::shrinkToUses
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses.
Definition: LiveIntervals.cpp:449
llvm::LiveRangeEdit::canRematerializeAt
bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx, bool cheapAsAMove)
canRematerializeAt - Determine if ParentVNI can be rematerialized at UseIdx.
Definition: LiveRangeEdit.cpp:158
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::SlotIndex::getRegSlot
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:259
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:112
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:487
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::SetVector::pop_back_val
T pop_back_val()
Definition: SetVector.h:232
llvm::LaneBitmask::none
constexpr bool none() const
Definition: LaneBitmask.h:52
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:415
llvm::TargetInstrInfo::reMaterialize
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
Definition: TargetInstrInfo.cpp:418
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::LiveIntervals::createEmptyInterval
LiveInterval & createEmptyInterval(Register Reg)
Interval creation.
Definition: LiveIntervals.h:129
llvm::LiveInterval::SubRange
A live range for subregisters.
Definition: LiveInterval.h:693
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
LiveRangeEdit.h
llvm::VirtRegMap::grow
void grow()
Definition: VirtRegMap.cpp:78
llvm::MachineRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition: MachineRegisterInfo.cpp:515
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::LiveRangeEdit::allUsesAvailableAt
bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx, SlotIndex UseIdx) const
allUsesAvailableAt - Return true if all registers used by OrigMI at OrigIdx are also available with t...
Definition: LiveRangeEdit.cpp:106
llvm::LiveRangeEdit::getParent
const LiveInterval & getParent() const
Definition: LiveRangeEdit.h:142
llvm::MachineRegisterInfo::getMaxLaneMaskForVReg
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Definition: MachineRegisterInfo.cpp:495
llvm::TargetInstrInfo::isIgnorableUse
virtual bool isIgnorableUse(const MachineOperand &MO) const
Given MO is a PhysReg use return if it can be ignored for the purpose of instruction rematerializatio...
Definition: TargetInstrInfo.h:139
llvm::MachineOperand::readsReg
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
Definition: MachineOperand.h:457
llvm::LiveRangeEdit::Delegate::LRE_DidCloneVirtReg
virtual void LRE_DidCloneVirtReg(Register New, Register Old)
Called after cloning a virtual register.
Definition: LiveRangeEdit.h:64
llvm::VNInfo
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
llvm::LiveRange::getVNInfoAt
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:421
llvm::LiveInterval::markNotSpillable
void markNotSpillable()
markNotSpillable - Mark interval as not spillable
Definition: LiveInterval.h:822
llvm::TargetInstrInfo::foldMemoryOperand
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
Definition: TargetInstrInfo.cpp:559
llvm::LiveRangeEdit::size
unsigned size() const
Definition: LiveRangeEdit.h:153
llvm::LiveIntervals::RemoveMachineInstrFromMaps
void RemoveMachineInstrFromMaps(MachineInstr &MI)
Definition: LiveIntervals.h:270
llvm::LiveIntervals::splitSeparateComponents
void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)
Split separate components in LiveInterval LI into separate intervals.
Definition: LiveIntervals.cpp:1738
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:108
llvm::LiveInterval::reg
Register reg() const
Definition: LiveInterval.h:717
llvm::LiveInterval::hasSubRanges
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:803
llvm::SmallVectorImpl< MachineInstr * >
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:50
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::LiveIntervals::hasInterval
bool hasInterval(Register Reg) const
Definition: LiveIntervals.h:123
CalcSpillWeights.h
llvm::MachineRegisterInfo::reg_nodbg_empty
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Definition: MachineRegisterInfo.h:385
llvm::LiveRangeEdit::checkRematerializable
bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI)
checkRematerializable - Manually add VNI to the list of rematerializable values if DefMI may be remat...
Definition: LiveRangeEdit.cpp:71
raw_ostream.h
llvm::LiveRangeEdit::Delegate::LRE_WillShrinkVirtReg
virtual void LRE_WillShrinkVirtReg(Register)
Called before shrinking the live range of a virtual register.
Definition: LiveRangeEdit.h:60
llvm::SetVector
A vector that has set insertion semantics.
Definition: SetVector.h:40
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:692
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::LiveIntervals::removeVRegDefAt
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos.
Definition: LiveIntervals.cpp:1720
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:641
Debug.h
llvm::LiveQueryResult::isKill
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:112
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::LiveIntervals::getVNInfoAllocator
VNInfo::Allocator & getVNInfoAllocator()
Definition: LiveIntervals.h:278
llvm::LiveRangeEdit::eliminateDeadDefs
void eliminateDeadDefs(SmallVectorImpl< MachineInstr * > &Dead, ArrayRef< Register > RegsBeingSpilled=None)
eliminateDeadDefs - Try to delete machine instructions that are now dead (allDefsAreDead returns true...
Definition: LiveRangeEdit.cpp:435
llvm::LiveInterval::subranges
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:775