LLVM  14.0.0git
LiveRangeEdit.cpp
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1 //===-- LiveRangeEdit.cpp - Basic tools for editing a register live range -===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // The LiveRangeEdit class represents changes done to a virtual register when it
10 // is spilled or split.
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Support/Debug.h"
22 
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "regalloc"
26 
27 STATISTIC(NumDCEDeleted, "Number of instructions deleted by DCE");
28 STATISTIC(NumDCEFoldedLoads, "Number of single use loads folded after DCE");
29 STATISTIC(NumFracRanges, "Number of live ranges fractured by DCE");
30 
31 void LiveRangeEdit::Delegate::anchor() { }
32 
33 LiveInterval &LiveRangeEdit::createEmptyIntervalFrom(Register OldReg,
34  bool createSubRanges) {
35  Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
36  if (VRM)
37  VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
38 
39  LiveInterval &LI = LIS.createEmptyInterval(VReg);
40  if (Parent && !Parent->isSpillable())
41  LI.markNotSpillable();
42  if (createSubRanges) {
43  // Create empty subranges if the OldReg's interval has them. Do not create
44  // the main range here---it will be constructed later after the subranges
45  // have been finalized.
46  LiveInterval &OldLI = LIS.getInterval(OldReg);
48  for (LiveInterval::SubRange &S : OldLI.subranges())
49  LI.createSubRange(Alloc, S.LaneMask);
50  }
51  return LI;
52 }
53 
55  Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
56  if (VRM) {
57  VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
58  }
59  // FIXME: Getting the interval here actually computes it.
60  // In theory, this may not be what we want, but in practice
61  // the createEmptyIntervalFrom API is used when this is not
62  // the case. Generally speaking we just want to annotate the
63  // LiveInterval when it gets created but we cannot do that at
64  // the moment.
65  if (Parent && !Parent->isSpillable())
66  LIS.getInterval(VReg).markNotSpillable();
67  return VReg;
68 }
69 
71  const MachineInstr *DefMI,
72  AAResults *aa) {
73  assert(DefMI && "Missing instruction");
74  ScannedRemattable = true;
76  return false;
77  Remattable.insert(VNI);
78  return true;
79 }
80 
81 void LiveRangeEdit::scanRemattable(AAResults *aa) {
82  for (VNInfo *VNI : getParent().valnos) {
83  if (VNI->isUnused())
84  continue;
85  unsigned Original = VRM->getOriginal(getReg());
86  LiveInterval &OrigLI = LIS.getInterval(Original);
87  VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
88  if (!OrigVNI)
89  continue;
91  if (!DefMI)
92  continue;
93  checkRematerializable(OrigVNI, DefMI, aa);
94  }
95  ScannedRemattable = true;
96 }
97 
99  if (!ScannedRemattable)
100  scanRemattable(aa);
101  return !Remattable.empty();
102 }
103 
104 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
105 /// OrigIdx are also available with the same value at UseIdx.
107  SlotIndex OrigIdx,
108  SlotIndex UseIdx) const {
109  OrigIdx = OrigIdx.getRegSlot(true);
110  UseIdx = std::max(UseIdx, UseIdx.getRegSlot(true));
111  for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
112  const MachineOperand &MO = OrigMI->getOperand(i);
113  if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
114  continue;
115 
116  // We can't remat physreg uses, unless it is a constant or target wants
117  // to ignore this use.
119  if (MRI.isConstantPhysReg(MO.getReg()) || TII.isIgnorableUse(MO))
120  continue;
121  return false;
122  }
123 
124  LiveInterval &li = LIS.getInterval(MO.getReg());
125  const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
126  if (!OVNI)
127  continue;
128 
129  // Don't allow rematerialization immediately after the original def.
130  // It would be incorrect if OrigMI redefines the register.
131  // See PR14098.
132  if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
133  return false;
134 
135  if (OVNI != li.getVNInfoAt(UseIdx))
136  return false;
137  }
138  return true;
139 }
140 
142  SlotIndex UseIdx, bool cheapAsAMove) {
143  assert(ScannedRemattable && "Call anyRematerializable first");
144 
145  // Use scanRemattable info.
146  if (!Remattable.count(OrigVNI))
147  return false;
148 
149  // No defining instruction provided.
150  SlotIndex DefIdx;
151  assert(RM.OrigMI && "No defining instruction for remattable value");
152  DefIdx = LIS.getInstructionIndex(*RM.OrigMI);
153 
154  // If only cheap remats were requested, bail out early.
155  if (cheapAsAMove && !TII.isAsCheapAsAMove(*RM.OrigMI))
156  return false;
157 
158  // Verify that all used registers are available with the same values.
159  if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
160  return false;
161 
162  return true;
163 }
164 
167  unsigned DestReg,
168  const Remat &RM,
169  const TargetRegisterInfo &tri,
170  bool Late) {
171  assert(RM.OrigMI && "Invalid remat");
172  TII.reMaterialize(MBB, MI, DestReg, 0, *RM.OrigMI, tri);
173  // DestReg of the cloned instruction cannot be Dead. Set isDead of DestReg
174  // to false anyway in case the isDead flag of RM.OrigMI's dest register
175  // is true.
176  (*--MI).getOperand(0).setIsDead(false);
177  Rematted.insert(RM.ParentVNI);
178  return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot();
179 }
180 
182  if (TheDelegate && TheDelegate->LRE_CanEraseVirtReg(Reg))
183  LIS.removeInterval(Reg);
184 }
185 
186 bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
188  MachineInstr *DefMI = nullptr, *UseMI = nullptr;
189 
190  // Check that there is a single def and a single use.
191  for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg())) {
192  MachineInstr *MI = MO.getParent();
193  if (MO.isDef()) {
194  if (DefMI && DefMI != MI)
195  return false;
196  if (!MI->canFoldAsLoad())
197  return false;
198  DefMI = MI;
199  } else if (!MO.isUndef()) {
200  if (UseMI && UseMI != MI)
201  return false;
202  // FIXME: Targets don't know how to fold subreg uses.
203  if (MO.getSubReg())
204  return false;
205  UseMI = MI;
206  }
207  }
208  if (!DefMI || !UseMI)
209  return false;
210 
211  // Since we're moving the DefMI load, make sure we're not extending any live
212  // ranges.
214  LIS.getInstructionIndex(*UseMI)))
215  return false;
216 
217  // We also need to make sure it is safe to move the load.
218  // Assume there are stores between DefMI and UseMI.
219  bool SawStore = true;
220  if (!DefMI->isSafeToMove(nullptr, SawStore))
221  return false;
222 
223  LLVM_DEBUG(dbgs() << "Try to fold single def: " << *DefMI
224  << " into single use: " << *UseMI);
225 
227  if (UseMI->readsWritesVirtualRegister(LI->reg(), &Ops).second)
228  return false;
229 
230  MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS);
231  if (!FoldMI)
232  return false;
233  LLVM_DEBUG(dbgs() << " folded: " << *FoldMI);
234  LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI);
235  // Update the call site info.
237  UseMI->getMF()->moveCallSiteInfo(UseMI, FoldMI);
239  DefMI->addRegisterDead(LI->reg(), nullptr);
240  Dead.push_back(DefMI);
241  ++NumDCEFoldedLoads;
242  return true;
243 }
244 
245 bool LiveRangeEdit::useIsKill(const LiveInterval &LI,
246  const MachineOperand &MO) const {
247  const MachineInstr &MI = *MO.getParent();
249  if (LI.Query(Idx).isKill())
250  return true;
252  unsigned SubReg = MO.getSubReg();
254  for (const LiveInterval::SubRange &S : LI.subranges()) {
255  if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
256  return true;
257  }
258  return false;
259 }
260 
261 /// Find all live intervals that need to shrink, then remove the instruction.
262 void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink,
263  AAResults *AA) {
264  assert(MI->allDefsAreDead() && "Def isn't really dead");
265  SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
266 
267  // Never delete a bundled instruction.
268  if (MI->isBundled()) {
269  return;
270  }
271  // Never delete inline asm.
272  if (MI->isInlineAsm()) {
273  LLVM_DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
274  return;
275  }
276 
277  // Use the same criteria as DeadMachineInstructionElim.
278  bool SawStore = false;
279  if (!MI->isSafeToMove(nullptr, SawStore)) {
280  LLVM_DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
281  return;
282  }
283 
284  LLVM_DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
285 
286  // Collect virtual registers to be erased after MI is gone.
287  SmallVector<unsigned, 8> RegsToErase;
288  bool ReadsPhysRegs = false;
289  bool isOrigDef = false;
290  unsigned Dest;
291  // Only optimize rematerialize case when the instruction has one def, since
292  // otherwise we could leave some dead defs in the code. This case is
293  // extremely rare.
294  if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
295  MI->getDesc().getNumDefs() == 1) {
296  Dest = MI->getOperand(0).getReg();
297  unsigned Original = VRM->getOriginal(Dest);
298  LiveInterval &OrigLI = LIS.getInterval(Original);
299  VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
300  // The original live-range may have been shrunk to
301  // an empty live-range. It happens when it is dead, but
302  // we still keep it around to be able to rematerialize
303  // other values that depend on it.
304  if (OrigVNI)
305  isOrigDef = SlotIndex::isSameInstr(OrigVNI->def, Idx);
306  }
307 
308  bool HasLiveVRegUses = false;
309 
310  // Check for live intervals that may shrink
311  for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
312  MOE = MI->operands_end(); MOI != MOE; ++MOI) {
313  if (!MOI->isReg())
314  continue;
315  Register Reg = MOI->getReg();
317  // Check if MI reads any unreserved physregs.
318  if (Reg && MOI->readsReg() && !MRI.isReserved(Reg))
319  ReadsPhysRegs = true;
320  else if (MOI->isDef())
321  LIS.removePhysRegDefAt(Reg.asMCReg(), Idx);
322  continue;
323  }
324  LiveInterval &LI = LIS.getInterval(Reg);
325 
326  // Shrink read registers, unless it is likely to be expensive and
327  // unlikely to change anything. We typically don't want to shrink the
328  // PIC base register that has lots of uses everywhere.
329  // Always shrink COPY uses that probably come from live range splitting.
330  if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MOI->isDef())) ||
331  (MOI->readsReg() && (MRI.hasOneNonDBGUse(Reg) || useIsKill(LI, *MOI))))
332  ToShrink.insert(&LI);
333  else if (MOI->readsReg())
334  HasLiveVRegUses = true;
335 
336  // Remove defined value.
337  if (MOI->isDef()) {
338  if (TheDelegate && LI.getVNInfoAt(Idx) != nullptr)
339  TheDelegate->LRE_WillShrinkVirtReg(LI.reg());
340  LIS.removeVRegDefAt(LI, Idx);
341  if (LI.empty())
342  RegsToErase.push_back(Reg);
343  }
344  }
345 
346  // Currently, we don't support DCE of physreg live ranges. If MI reads
347  // any unreserved physregs, don't erase the instruction, but turn it into
348  // a KILL instead. This way, the physreg live ranges don't end up
349  // dangling.
350  // FIXME: It would be better to have something like shrinkToUses() for
351  // physregs. That could potentially enable more DCE and it would free up
352  // the physreg. It would not happen often, though.
353  if (ReadsPhysRegs) {
354  MI->setDesc(TII.get(TargetOpcode::KILL));
355  // Remove all operands that aren't physregs.
356  for (unsigned i = MI->getNumOperands(); i; --i) {
357  const MachineOperand &MO = MI->getOperand(i-1);
358  if (MO.isReg() && Register::isPhysicalRegister(MO.getReg()))
359  continue;
360  MI->RemoveOperand(i-1);
361  }
362  LLVM_DEBUG(dbgs() << "Converted physregs to:\t" << *MI);
363  } else {
364  // If the dest of MI is an original reg and MI is reMaterializable,
365  // don't delete the inst. Replace the dest with a new reg, and keep
366  // the inst for remat of other siblings. The inst is saved in
367  // LiveRangeEdit::DeadRemats and will be deleted after all the
368  // allocations of the func are done.
369  // However, immediately delete instructions which have unshrunk virtual
370  // register uses. That may provoke RA to split an interval at the KILL
371  // and later result in an invalid live segment end.
372  if (isOrigDef && DeadRemats && !HasLiveVRegUses &&
373  TII.isTriviallyReMaterializable(*MI, AA)) {
374  LiveInterval &NewLI = createEmptyIntervalFrom(Dest, false);
375  VNInfo *VNI = NewLI.getNextValue(Idx, LIS.getVNInfoAllocator());
376  NewLI.addSegment(LiveInterval::Segment(Idx, Idx.getDeadSlot(), VNI));
377  pop_back();
378  DeadRemats->insert(MI);
380  MI->substituteRegister(Dest, NewLI.reg(), 0, TRI);
381  MI->getOperand(0).setIsDead(true);
382  } else {
383  if (TheDelegate)
384  TheDelegate->LRE_WillEraseInstruction(MI);
386  MI->eraseFromParent();
387  ++NumDCEDeleted;
388  }
389  }
390 
391  // Erase any virtregs that are now empty and unused. There may be <undef>
392  // uses around. Keep the empty live range in that case.
393  for (unsigned i = 0, e = RegsToErase.size(); i != e; ++i) {
394  Register Reg = RegsToErase[i];
395  if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) {
396  ToShrink.remove(&LIS.getInterval(Reg));
397  eraseVirtReg(Reg);
398  }
399  }
400 }
401 
403  ArrayRef<Register> RegsBeingSpilled,
404  AAResults *AA) {
405  ToShrinkSet ToShrink;
406 
407  for (;;) {
408  // Erase all dead defs.
409  while (!Dead.empty())
410  eliminateDeadDef(Dead.pop_back_val(), ToShrink, AA);
411 
412  if (ToShrink.empty())
413  break;
414 
415  // Shrink just one live interval. Then delete new dead defs.
416  LiveInterval *LI = ToShrink.pop_back_val();
417  if (foldAsLoad(LI, Dead))
418  continue;
419  unsigned VReg = LI->reg();
420  if (TheDelegate)
421  TheDelegate->LRE_WillShrinkVirtReg(VReg);
422  if (!LIS.shrinkToUses(LI, &Dead))
423  continue;
424 
425  // Don't create new intervals for a register being spilled.
426  // The new intervals would have to be spilled anyway so its not worth it.
427  // Also they currently aren't spilled so creating them and not spilling
428  // them results in incorrect code.
429  bool BeingSpilled = false;
430  for (unsigned i = 0, e = RegsBeingSpilled.size(); i != e; ++i) {
431  if (VReg == RegsBeingSpilled[i]) {
432  BeingSpilled = true;
433  break;
434  }
435  }
436 
437  if (BeingSpilled) continue;
438 
439  // LI may have been separated, create new intervals.
440  LI->RenumberValues();
442  LIS.splitSeparateComponents(*LI, SplitLIs);
443  if (!SplitLIs.empty())
444  ++NumFracRanges;
445 
446  Register Original = VRM ? VRM->getOriginal(VReg) : Register();
447  for (const LiveInterval *SplitLI : SplitLIs) {
448  // If LI is an original interval that hasn't been split yet, make the new
449  // intervals their own originals instead of referring to LI. The original
450  // interval must contain all the split products, and LI doesn't.
451  if (Original != VReg && Original != 0)
452  VRM->setIsSplitFromReg(SplitLI->reg(), Original);
453  if (TheDelegate)
454  TheDelegate->LRE_DidCloneVirtReg(SplitLI->reg(), VReg);
455  }
456  }
457 }
458 
459 // Keep track of new virtual registers created via
460 // MachineRegisterInfo::createVirtualRegister.
461 void
462 LiveRangeEdit::MRI_NoteNewVirtualRegister(Register VReg) {
463  if (VRM)
464  VRM->grow();
465 
466  NewRegs.push_back(VReg);
467 }
468 
470  VirtRegAuxInfo &VRAI) {
471  for (unsigned I = 0, Size = size(); I < Size; ++I) {
472  LiveInterval &LI = LIS.getInterval(get(I));
473  if (MRI.recomputeRegClass(LI.reg()))
474  LLVM_DEBUG({
475  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
476  dbgs() << "Inflated " << printReg(LI.reg()) << " to "
477  << TRI->getRegClassName(MRI.getRegClass(LI.reg())) << '\n';
478  });
480  }
481 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::LaneBitmask
Definition: LaneBitmask.h:40
i
i
Definition: README.txt:29
llvm::LiveRangeEdit::Remat
Remat - Information needed to rematerialize at a specific location.
Definition: LiveRangeEdit.h:197
llvm::LiveRangeEdit::checkRematerializable
bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, AAResults *)
checkRematerializable - Manually add VNI to the list of rematerializable values if DefMI may be remat...
Definition: LiveRangeEdit.cpp:70
llvm::MachineInstr::addRegisterDead
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
Definition: MachineInstr.cpp:1957
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::LiveRange::empty
bool empty() const
Definition: LiveInterval.h:374
llvm::LiveIntervals::getSlotIndexes
SlotIndexes * getSlotIndexes() const
Definition: LiveIntervals.h:211
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::LiveRangeEdit::calculateRegClassAndHint
void calculateRegClassAndHint(MachineFunction &, VirtRegAuxInfo &)
calculateRegClassAndHint - Recompute register class and hint for each new register.
Definition: LiveRangeEdit.cpp:469
llvm::LiveInterval::createSubRange
SubRange * createSubRange(BumpPtrAllocator &Allocator, LaneBitmask LaneMask)
Creates a new empty subregister live range.
Definition: LiveInterval.h:779
llvm::MachineInstr::isSafeToMove
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Definition: MachineInstr.cpp:1232
aa
aa
Definition: AliasAnalysis.cpp:846
llvm::MachineRegisterInfo::recomputeRegClass
bool recomputeRegClass(Register Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
Definition: MachineRegisterInfo.cpp:122
llvm::LiveRangeEdit::Delegate::LRE_CanEraseVirtReg
virtual bool LRE_CanEraseVirtReg(Register)
Called when a virtual register is no longer used.
Definition: LiveRangeEdit.h:60
llvm::LiveRangeEdit::createFrom
Register createFrom(Register OldReg)
createFrom - Create a new virtual register based on OldReg.
Definition: LiveRangeEdit.cpp:54
llvm::LiveInterval::isSpillable
bool isSpillable() const
isSpillable - Can this interval be spilled?
Definition: LiveInterval.h:813
llvm::SmallVector< unsigned, 8 >
Statistic.h
llvm::VirtRegAuxInfo
Calculate auxiliary information for a virtual register such as its spill weight and allocation hint.
Definition: CalcSpillWeights.h:46
llvm::VirtRegMap::getOriginal
Register getOriginal(Register VirtReg) const
getOriginal - Return the original virtual register that VirtReg descends from through splitting.
Definition: VirtRegMap.h:170
llvm::LiveIntervals::getInstructionFromIndex
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
Definition: LiveIntervals.h:231
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:153
llvm::VNInfo::def
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::MachineFunction::moveCallSiteInfo
void moveCallSiteInfo(const MachineInstr *Old, const MachineInstr *New)
Move the call site info from Old to \New call site info.
Definition: MachineFunction.cpp:948
llvm::LiveIntervals::removeInterval
void removeInterval(Register Reg)
Interval removal.
Definition: LiveIntervals.h:145
TargetInstrInfo.h
llvm::LiveRangeEdit::eliminateDeadDefs
void eliminateDeadDefs(SmallVectorImpl< MachineInstr * > &Dead, ArrayRef< Register > RegsBeingSpilled=None, AAResults *AA=nullptr)
eliminateDeadDefs - Try to delete machine instructions that are now dead (allDefsAreDead returns true...
Definition: LiveRangeEdit.cpp:402
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:663
llvm::LiveRangeEdit::getReg
Register getReg() const
Definition: LiveRangeEdit.h:151
llvm::LiveRangeEdit::Delegate::LRE_WillEraseInstruction
virtual void LRE_WillEraseInstruction(MachineInstr *MI)
Called immediately before erasing a dead machine instruction.
Definition: LiveRangeEdit.h:56
llvm::VirtRegAuxInfo::calculateSpillWeightAndHint
void calculateSpillWeightAndHint(LiveInterval &LI)
(re)compute li's spill weight and allocation hint.
Definition: CalcSpillWeights.cpp:139
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::LiveIntervals::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
Definition: LiveIntervals.h:226
MachineRegisterInfo.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::LiveRangeEdit::get
Register get(unsigned idx) const
Definition: LiveRangeEdit.h:159
llvm::TargetRegisterInfo::getSubRegIndexLaneMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:377
llvm::AAResults
Definition: AliasAnalysis.h:508
llvm::LiveRangeEdit::anyRematerializable
bool anyRematerializable(AAResults *)
anyRematerializable - Return true if any parent values may be rematerializable.
Definition: LiveRangeEdit.cpp:98
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:915
llvm::LiveRange::addSegment
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
Definition: LiveInterval.cpp:548
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MachineRegisterInfo::reg_nodbg_operands
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:337
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineInstr::shouldUpdateCallSiteInfo
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
Definition: MachineInstr.cpp:720
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::SlotIndex::getDeadSlot
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:259
llvm::LiveRangeEdit::eraseVirtReg
void eraseVirtReg(Register Reg)
eraseVirtReg - Notify the delegate that Reg is no longer in use, and try to erase it from LIS.
Definition: LiveRangeEdit.cpp:181
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::SetVector::empty
bool empty() const
Determine if the SetVector is empty or not.
Definition: SetVector.h:72
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SlotIndexes::insertMachineInstrInMaps
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
Definition: SlotIndexes.h:535
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::LiveRangeEdit::getParent
LiveInterval & getParent() const
Definition: LiveRangeEdit.h:146
llvm::VirtRegMap::setIsSplitFromReg
void setIsSplitFromReg(Register virtReg, Register SReg)
records virtReg is a split live interval from SReg.
Definition: VirtRegMap.h:154
llvm::LiveIntervals::removePhysRegDefAt
void removePhysRegDefAt(MCRegister Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
Definition: LiveIntervals.cpp:1724
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::LiveRange::RenumberValues
void RenumberValues()
RenumberValues - Renumber all values in order of appearance and remove unused values.
Definition: LiveInterval.cpp:531
llvm::LiveIntervals::ReplaceMachineInstrInMaps
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
Definition: LiveIntervals.h:280
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
LiveIntervals.h
VirtRegMap.h
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:745
llvm::BumpPtrAllocatorImpl
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:67
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::LiveRangeEdit::pop_back
void pop_back()
pop_back - It allows LiveRangeEdit users to drop new registers.
Definition: LiveRangeEdit.h:169
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::SlotIndex::isSameInstr
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:197
llvm::LiveRange::getNextValue
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:323
llvm::LiveRange::Query
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:533
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::TargetInstrInfo::isAsCheapAsAMove
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
Definition: TargetInstrInfo.h:374
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineInstr::readsWritesVirtualRegister
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Definition: MachineInstr.cpp:1012
llvm::LiveIntervals::shrinkToUses
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses.
Definition: LiveIntervals.cpp:456
llvm::LiveRangeEdit::canRematerializeAt
bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx, bool cheapAsAMove)
canRematerializeAt - Determine if ParentVNI can be rematerialized at UseIdx.
Definition: LiveRangeEdit.cpp:141
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::SlotIndex::getRegSlot
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:254
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:114
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:472
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LiveRangeEdit::rematerializeAt
SlotIndex rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &, bool Late=false)
rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an instruction into MBB before...
Definition: LiveRangeEdit.cpp:165
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:419
llvm::TargetInstrInfo::reMaterialize
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
Definition: TargetInstrInfo.cpp:419
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::LiveIntervals::createEmptyInterval
LiveInterval & createEmptyInterval(Register Reg)
Interval creation.
Definition: LiveIntervals.h:131
llvm::LiveInterval::SubRange
A live range for subregisters.
Definition: LiveInterval.h:687
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
llvm::TargetInstrInfo::isTriviallyReMaterializable
bool isTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
Definition: TargetInstrInfo.h:124
LiveRangeEdit.h
llvm::VirtRegMap::grow
void grow()
Definition: VirtRegMap.cpp:78
llvm::MachineRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition: MachineRegisterInfo.cpp:513
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::LiveRangeEdit::allUsesAvailableAt
bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx, SlotIndex UseIdx) const
allUsesAvailableAt - Return true if all registers used by OrigMI at OrigIdx are also available with t...
Definition: LiveRangeEdit.cpp:106
llvm::TargetInstrInfo::isIgnorableUse
virtual bool isIgnorableUse(const MachineOperand &MO) const
Given MO is a PhysReg use return if it can be ignored for the purpose of instruction rematerializatio...
Definition: TargetInstrInfo.h:134
llvm::MachineOperand::readsReg
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
Definition: MachineOperand.h:458
llvm::LiveRangeEdit::Delegate::LRE_DidCloneVirtReg
virtual void LRE_DidCloneVirtReg(Register New, Register Old)
Called after cloning a virtual register.
Definition: LiveRangeEdit.h:67
llvm::VNInfo
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
llvm::LiveRange::getVNInfoAt
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:413
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:50
llvm::LiveInterval::markNotSpillable
void markNotSpillable()
markNotSpillable - Mark interval as not spillable
Definition: LiveInterval.h:816
llvm::TargetInstrInfo::foldMemoryOperand
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
Definition: TargetInstrInfo.cpp:560
llvm::LiveRangeEdit::size
unsigned size() const
Definition: LiveRangeEdit.h:157
llvm::LiveIntervals::RemoveMachineInstrFromMaps
void RemoveMachineInstrFromMaps(MachineInstr &MI)
Definition: LiveIntervals.h:276
llvm::LiveIntervals::splitSeparateComponents
void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)
Split separate components in LiveInterval LI into separate intervals.
Definition: LiveIntervals.cpp:1750
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:492
llvm::LiveInterval::reg
Register reg() const
Definition: LiveInterval.h:711
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::SmallVectorImpl< MachineInstr * >
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:62
llvm::LiveIntervals::hasInterval
bool hasInterval(Register Reg) const
Definition: LiveIntervals.h:125
CalcSpillWeights.h
llvm::MachineRegisterInfo::reg_nodbg_empty
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Definition: MachineRegisterInfo.h:377
raw_ostream.h
llvm::LiveRangeEdit::Delegate::LRE_WillShrinkVirtReg
virtual void LRE_WillShrinkVirtReg(Register)
Called before shrinking the live range of a virtual register.
Definition: LiveRangeEdit.h:63
llvm::SetVector
A vector that has set insertion semantics.
Definition: SetVector.h:40
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:677
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::SetVector::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SetVector.h:232
llvm::LiveIntervals::removeVRegDefAt
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos.
Definition: LiveIntervals.cpp:1732
Debug.h
llvm::LiveQueryResult::isKill
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:112
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::LiveIntervals::getVNInfoAllocator
VNInfo::Allocator & getVNInfoAllocator()
Definition: LiveIntervals.h:284
llvm::LiveInterval::subranges
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:769