32#define DEBUG_TYPE "calcspillweights"
35 LLVM_DEBUG(
dbgs() <<
"********** Compute Spill Weights **********\n"
36 <<
"********** Function: " << MF.
getName() <<
'\n');
39 for (
unsigned I = 0, E =
MRI.getNumVirtRegs();
I != E; ++
I) {
41 if (
MRI.reg_nodbg_empty(Reg))
53 if (
MI->getOperand(0).getReg() == Reg) {
54 Sub =
MI->getOperand(0).getSubReg();
55 HReg =
MI->getOperand(1).getReg();
56 HSub =
MI->getOperand(1).getSubReg();
58 Sub =
MI->getOperand(1).getSubReg();
59 HReg =
MI->getOperand(0).getReg();
60 HSub =
MI->getOperand(0).getSubReg();
67 return Sub == HSub ? HReg :
Register();
76 return TRI.getMatchingSuperReg(CopiedPReg, Sub, RC);
97 assert(
MI &&
"Dead valno in interval");
102 while (
TII.isFullCopyInstr(*
MI)) {
104 if (
MI->getOperand(0).getReg() != Reg)
108 Reg =
MI->getOperand(1).getReg();
112 if (!Reg.isVirtual() || VRM.
getOriginal(Reg) != Original)
119 assert(VNI &&
"Copy from non-existing value");
123 assert(
MI &&
"Dead valno in interval");
126 if (!
TII.isTriviallyReMaterializable(*
MI))
132bool VirtRegAuxInfo::isLiveAtStatepointVarArg(
LiveInterval &LI) {
135 MachineInstr *MI = MO.getParent();
136 if (MI->getOpcode() != TargetOpcode::STATEPOINT)
138 return StatepointOpers(MI).getVarIdx() <= MO.getOperandNo();
154 if (
MI->isInlineAsm() &&
MI->mayFoldInlineAsmRegOp(
MI->getOperandNo(&MO)))
167 float TotalWeight = 0;
168 unsigned NumInstr = 0;
171 std::pair<unsigned, Register> TargetHint =
MRI.getRegAllocationHint(LI.
reg());
187 bool IsLocalSplitArtifact = Start &&
End;
190 bool ShouldUpdateLI = !IsLocalSplitArtifact;
192 if (IsLocalSplitArtifact) {
195 "start and end are expected to be in the same basic block");
212 CopyHint(
Register R,
float W) :
Reg(R), Weight(W) {}
213 bool operator<(
const CopyHint &Rhs)
const {
215 if (
Reg.isPhysical() != Rhs.Reg.isPhysical())
216 return Reg.isPhysical();
217 if (Weight != Rhs.Weight)
218 return (Weight > Rhs.Weight);
219 return Reg.id() < Rhs.Reg.id();
223 bool IsExiting =
false;
224 std::set<CopyHint> CopyHints;
227 I =
MRI.reg_instr_nodbg_begin(LI.
reg()),
228 E =
MRI.reg_instr_nodbg_end();
235 if (IsLocalSplitArtifact && ((SI < *Start) || (SI > *
End)))
239 bool identityCopy =
false;
240 auto DestSrc =
TII.isCopyInstr(*
MI);
244 identityCopy = DestRegOp->
getReg() == SrcRegOp->
getReg() &&
248 if (identityCopy ||
MI->isImplicitDef())
255 if (
TII.isUnspillableTerminator(
MI) &&
256 MI->definesRegister(LI.
reg(),
nullptr)) {
266 if (
MI->getParent() !=
MBB) {
267 MBB =
MI->getParent();
274 std::tie(Reads,
Writes) =
MI->readsWritesVirtualRegister(LI.
reg());
281 TotalWeight += Weight;
285 if (!
TII.isCopyInstr(*
MI))
294 CopyHints.
insert(CopyHint(HintReg, HWeight));
298 if (ShouldUpdateLI && CopyHints.size()) {
300 if (TargetHint.first == 0 && TargetHint.second)
301 MRI.clearSimpleHint(LI.
reg());
304 for (
const auto &Hint : CopyHints) {
305 if (!HintedRegs.
insert(Hint.Reg).second ||
306 (TargetHint.first != 0 && Hint.Reg == TargetHint.second))
309 MRI.addRegAllocationHint(LI.
reg(), Hint.Reg);
313 TotalWeight *= 1.01F;
342 if (IsLocalSplitArtifact)
343 return normalize(TotalWeight, Start->distance(*
End), NumInstr);
unsigned const MachineRegisterInfo * MRI
static bool canMemFoldInlineAsm(LiveInterval &LI, const MachineRegisterInfo &MRI)
SmallVector< uint32_t, 0 > Writes
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallPtrSet class.
This file defines the SmallSet class.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
LiveInterval - This class represents the liveness of a register, or stack slot.
void markNotSpillable()
markNotSpillable - Mark interval as not spillable
bool isSpillable() const
isSpillable - Can this interval be spilled?
unsigned getSize() const
getSize - Returns the sum of sizes of all the LiveRange's.
void setWeight(float Value)
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndexes * getSlotIndexes() const
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
ArrayRef< SlotIndex > getRegMaskSlots() const
Returns a sorted array of slot indices of all instructions with register mask operands.
LiveInterval & getInterval(Register Reg)
static float getSpillWeight(bool isDef, bool isUse, const MachineBlockFrequencyInfo *MBFI, const MachineInstr &MI)
Calculate the spill weight to assign to a single instruction.
bool isLiveOutOfMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Result of a LiveRange query.
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
bool isLiveAtIndexes(ArrayRef< SlotIndex > Slots) const
bool isZeroLength(SlotIndexes *Indexes) const
Returns true if the live range is zero length, i.e.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
bool isLoopExiting(const BlockT *BB) const
True if terminator in the block can branch to another block that is outside of the current loop.
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Represents a single loop in the control flow graph.
Wrapper class representing physical registers. Should be passed by value.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
Register getReg() const
getReg - Returns the register number.
defusechain_iterator - This class provides iterator support for machine operands in the function that...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
iterator_range< reg_iterator > reg_operands(Register Reg) const
Wrapper class representing virtual and physical registers.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
SlotIndex - An opaque wrapper around machine indexes.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
TargetInstrInfo - Interface to description of machine instruction set.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
VNInfo - Value Number Information.
bool isUnused() const
Returns true if this value is unused.
SlotIndex def
The index of the defining instruction.
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
static Register copyHint(const MachineInstr *MI, unsigned Reg, const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI)
Return the preferred allocation register for reg, given a COPY instruction.
float weightCalcHelper(LiveInterval &LI, SlotIndex *Start=nullptr, SlotIndex *End=nullptr)
Helper function for weight calculations.
void calculateSpillWeightsAndHints()
Compute spill weights and allocation hints for all virtual register live intervals.
virtual float normalize(float UseDefFreq, unsigned Size, unsigned NumInstr)
Weight normalization function.
static bool isRematerializable(const LiveInterval &LI, const LiveIntervals &LIS, const VirtRegMap &VRM, const TargetInstrInfo &TII)
Determine if all values in LI are rematerializable.
void calculateSpillWeightAndHint(LiveInterval &LI)
(re)compute li's spill weight and allocation hint.
Register getOriginal(Register VirtReg) const
getOriginal - Return the original virtual register that VirtReg descends from through splitting.
MachineRegisterInfo & getRegInfo() const
This is an optimization pass for GlobalISel generic memory operations.
float stack_float_t
Type to force float point values onto the stack, so that x86 doesn't add hidden precision,...
bool operator<(int64_t V1, const APSInt &V2)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.