32#include "llvm/Config/llvm-config.h"
49#define DEBUG_TYPE "regbankselect"
56 "Run the Fast mode (default mapping)"),
57 clEnumValN(RegBankSelect::Mode::Greedy,
"regbankselect-greedy",
58 "Use the Greedy mode (best local mapping)")));
63 "Assign register bank of generic virtual registers",
69 "Assign register bank of generic virtual registers",
false,
77 LLVM_DEBUG(
dbgs() <<
"RegBankSelect mode overrided by command line\n");
83 assert(
RBI &&
"Cannot work without RegisterBankInfo");
86 TPC = &getAnalysis<TargetPassConfig>();
88 MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
89 MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
95 MORE = std::make_unique<MachineOptimizationRemarkEmitter>(MF,
MBFI);
112 bool &OnlyAssign)
const {
124 OnlyAssign = CurRegBank ==
nullptr;
126 if (CurRegBank)
dbgs() << *CurRegBank;
else dbgs() <<
"none";
127 dbgs() <<
" against ";
128 assert(DesiredRegBank &&
"The mapping must be valid");
129 dbgs() << *DesiredRegBank <<
'\n';);
130 return CurRegBank == DesiredRegBank;
139 "need new vreg for each breakdown");
142 assert(!NewVRegs.empty() &&
"We should not have to repair");
157 "We are about to create several defs for Dst");
179 MergeOp = TargetOpcode::G_BUILD_VECTOR;
186 "don't understand this value breakdown");
188 MergeOp = TargetOpcode::G_CONCAT_VECTORS;
191 MergeOp = TargetOpcode::G_MERGE_VALUES;
198 MergeBuilder.
addUse(SrcReg);
205 UnMergeBuilder.
addDef(DefReg);
218 std::unique_ptr<MachineInstr *[]> NewInstrs(
222 for (
const std::unique_ptr<InsertPoint> &InsertPt : RepairPt) {
228 InsertPt->insert(*CurMI);
229 NewInstrs[
Idx++] = CurMI;
240 assert(MO.
isReg() &&
"We should only repair register operand");
262 if (IsSameNumOfValues) {
282 if (
Cost != std::numeric_limits<unsigned>::max())
286 return std::numeric_limits<unsigned>::max();
293 "Do not know how to map this instruction");
302 if (CurCost <
Cost) {
305 BestMapping = CurMapping;
315 BestMapping = *PossibleMappings.
begin();
319 assert(BestMapping &&
"No suitable mapping for instruction");
327 assert(RepairPt.
hasSplit() &&
"We should not have to adjust for split");
330 assert((
MI.isPHI() ||
MI.isTerminator()) &&
"Why do we split?");
333 "Repairing placement does not match operand");
339 assert((!
MI.isPHI() || !MO.
isDef()) &&
"Need split for phi def?");
343 if (
MI.isTerminator()) {
344 assert(&
MI != &(*
MI.getParent()->getFirstTerminator()) &&
345 "Need to split for the first terminator?!");
367 "This code is for the def of a terminator");
402 if (Reg.isPhysical()) {
414 assert(&
MI == &(*
MI.getParent()->getFirstTerminator()) &&
415 "Do not know which outgoing edges are relevant");
418 "Do not know where each terminator ends up");
432 assert(
false &&
"Repairing cost may not be accurate");
446 assert((
MBFI || !BestCost) &&
"Costs comparison require MBFI");
453 bool Saturated =
Cost.addLocalCost(InstrMapping.
getCost());
454 assert(!Saturated &&
"Possible mapping saturated the cost");
458 if (BestCost &&
Cost > *BestCost) {
459 LLVM_DEBUG(
dbgs() <<
"Mapping is too expensive from the start\n");
468 for (
unsigned OpIdx = 0, EndOpIdx = InstrMapping.
getNumOperands();
469 OpIdx != EndOpIdx; ++OpIdx) {
482 InstrMapping.getOperandMapping(OpIdx);
515 if (!BestCost || Saturated)
520 assert(
MBFI &&
MBPI &&
"Cost computation requires MBFI and MBPI");
535 if (RepairCost == std::numeric_limits<unsigned>::max())
539 const uint64_t PercentageForBias = 5;
540 uint64_t Bias = (RepairCost * PercentageForBias + 99) / 100;
545 assert(((RepairCost < RepairCost * PercentageForBias) &&
546 (RepairCost * PercentageForBias <
547 RepairCost * PercentageForBias + 99)) &&
548 "Repairing involves more than a billion of instructions?!");
549 for (
const std::unique_ptr<InsertPoint> &InsertPt : RepairPt) {
550 assert(InsertPt->canMaterialize() &&
"We should not have made it here");
552 if (!InsertPt->isSplit())
553 Saturated =
Cost.addLocalCost(RepairCost);
555 uint64_t CostForInsertPt = RepairCost;
558 assert(CostForInsertPt + Bias > CostForInsertPt &&
559 "Repairing + split bias overflows");
560 CostForInsertPt += Bias;
561 uint64_t PtCost = InsertPt->frequency(*
this) * CostForInsertPt;
563 if ((Saturated = PtCost < CostForInsertPt))
566 Saturated =
Cost.addNonLocalCost(PtCost);
571 if (BestCost &&
Cost > *BestCost) {
572 LLVM_DEBUG(
dbgs() <<
"Mapping is too expensive, stop processing\n");
594 if (!RepairPt.canMaterialize() ||
598 "This should not make its way in the list");
599 unsigned OpIdx = RepairPt.getOpIdx();
602 InstrMapping.getOperandMapping(OpIdx);
605 switch (RepairPt.getKind()) {
608 "Reassignment should only be for simple mapping");
613 if (
MI.isDebugInstr())
625 LLVM_DEBUG(
dbgs() <<
"Actual mapping of the operands: " << OpdMapper <<
'\n');
634 unsigned Opc =
MI.getOpcode();
636 assert((Opc == TargetOpcode::G_ASSERT_ZEXT ||
637 Opc == TargetOpcode::G_ASSERT_SEXT ||
638 Opc == TargetOpcode::G_ASSERT_ALIGN) &&
639 "Unexpected hint opcode!");
646 assert(RB &&
"Expected source register to have a register bank?");
647 LLVM_DEBUG(
dbgs() <<
"... Hint always uses source's register bank.\n");
665 if (PossibleMappings.
empty())
691 while (!WorkList.
empty()) {
701 if (
MI.isInlineAsm())
705 if (
MI.isImplicitDef())
710 "unable to map instruction",
MI);
724 "instruction is not legal", *
MI);
763 : Kind(Kind), OpIdx(OpIdx),
766 assert(MO.
isReg() &&
"Trying to repair a non-reg operand");
772 bool Before = !MO.
isDef();
775 if (!
MI.isPHI() && !
MI.isTerminator()) {
788 if (It !=
MI.getParent()->end())
800 for (
auto Begin = Pred.
begin(); It != Begin && It->isTerminator(); --It)
801 if (It->modifiesRegister(Reg, &
TRI)) {
812 if (It == Pred.
end())
823 auto REnd =
MI.getParent()->rend();
825 for (; It != REnd && It->isTerminator(); ++It) {
827 "copy insertion in middle of terminators not handled");
845 "Do not know where to split");
848 for (
auto &Succ : Src.successors())
872 InsertPoints.emplace_back(&Point);
877 : Instr(Instr), Before(Before) {
881 "Splitting before phis requires more points");
883 "Splitting between phis does not make sense");
886void RegBankSelect::InstrInsertPoint::materialize() {
911 return Instr.isTerminator();
914 return Instr.getPrevNode() && Instr.getPrevNode()->isTerminator();
935void RegBankSelect::EdgeInsertPoint::materialize() {
940 assert(Src.isSuccessor(DstOrSplit) && DstOrSplit->isPredecessor(&Src) &&
941 "This point has already been split");
943 assert(NewBB &&
"Invalid call to materialize");
969 assert(Src.succ_size() > 1 && DstOrSplit->pred_size() > 1 &&
970 "Edge is not critical");
971 return Src.canSplitCriticalEdge(DstOrSplit);
975 : LocalFreq(LocalFreq.getFrequency()) {}
979 if (LocalCost +
Cost < LocalCost) {
984 return isSaturated();
989 if (NonLocalCost +
Cost < NonLocalCost) {
993 NonLocalCost +=
Cost;
994 return isSaturated();
997bool RegBankSelect::MappingCost::isSaturated()
const {
1003 *
this = ImpossibleCost();
1017 if ((*
this == ImpossibleCost()) || (
Cost == ImpossibleCost()))
1018 return (*
this == ImpossibleCost()) < (
Cost == ImpossibleCost());
1021 if (isSaturated() ||
Cost.isSaturated())
1022 return isSaturated() <
Cost.isSaturated();
1035 if (NonLocalCost ==
Cost.NonLocalCost)
1038 return LocalCost <
Cost.LocalCost;
1042 ThisLocalAdjust = 0;
1043 OtherLocalAdjust = 0;
1044 if (LocalCost <
Cost.LocalCost)
1045 OtherLocalAdjust =
Cost.LocalCost - LocalCost;
1047 ThisLocalAdjust = LocalCost -
Cost.LocalCost;
1049 ThisLocalAdjust = LocalCost;
1050 OtherLocalAdjust =
Cost.LocalCost;
1056 if (NonLocalCost <
Cost.NonLocalCost)
1057 OtherNonLocalAdjust =
Cost.NonLocalCost - NonLocalCost;
1059 ThisNonLocalAdjust = NonLocalCost -
Cost.NonLocalCost;
1061 uint64_t ThisScaledCost = ThisLocalAdjust * LocalFreq;
1063 bool ThisOverflows = ThisLocalAdjust && (ThisScaledCost < ThisLocalAdjust ||
1064 ThisScaledCost < LocalFreq);
1065 uint64_t OtherScaledCost = OtherLocalAdjust *
Cost.LocalFreq;
1067 bool OtherOverflows =
1069 (OtherScaledCost < OtherLocalAdjust || OtherScaledCost <
Cost.LocalFreq);
1071 ThisOverflows |= ThisNonLocalAdjust &&
1072 ThisScaledCost + ThisNonLocalAdjust < ThisNonLocalAdjust;
1073 ThisScaledCost += ThisNonLocalAdjust;
1074 OtherOverflows |= OtherNonLocalAdjust &&
1075 OtherScaledCost + OtherNonLocalAdjust < OtherNonLocalAdjust;
1076 OtherScaledCost += OtherNonLocalAdjust;
1079 if (ThisOverflows && OtherOverflows)
1082 if (ThisOverflows || OtherOverflows)
1083 return ThisOverflows < OtherOverflows;
1085 return ThisScaledCost < OtherScaledCost;
1089 return LocalCost ==
Cost.LocalCost && NonLocalCost ==
Cost.NonLocalCost &&
1090 LocalFreq ==
Cost.LocalFreq;
1093#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1101 if (*
this == ImpossibleCost()) {
1105 if (isSaturated()) {
1109 OS << LocalFreq <<
" * " << LocalCost <<
" + " << NonLocalCost;
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
#define LLVM_LIKELY(EXPR)
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Interface for Targets to specify which operations they can successfully select and how the others sho...
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
static cl::opt< RegBankSelect::Mode > RegBankSelectMode(cl::desc("Mode of the RegBankSelect pass"), cl::Hidden, cl::Optional, cl::values(clEnumValN(RegBankSelect::Mode::Fast, "regbankselect-fast", "Run the Fast mode (default mapping)"), clEnumValN(RegBankSelect::Mode::Greedy, "regbankselect-greedy", "Use the Greedy mode (best local mapping)")))
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
Target-Independent Code Generator Pass Configuration Options pass.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
uint64_t getFrequency() const
Returns the frequency as a fixpoint number scaled by the entry frequency.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool hasProperty(Property P) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineFunctionProperties & getProperties() const
Get the function properties.
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
MachineFunction & getMF()
Getter for the function we currently build.
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
void setMF(MachineFunction &MF)
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block.
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
void setRegBank(Register Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
Pass interface - Implemented by all 'passes'.
Insertion point on an edge.
uint64_t frequency(const Pass &P) const override
Frequency of the insertion point.
bool canMaterialize() const override
Check whether this insertion point can be materialized.
Abstract class used to represent an insertion point in a CFG.
virtual bool canMaterialize() const
Check whether this insertion point can be materialized.
virtual bool isSplit() const
Does this point involve splitting an edge or block? As soon as getPoint is called and thus,...
Insertion point before or after an instruction.
InstrInsertPoint(MachineInstr &Instr, bool Before=true)
Create an insertion point before (Before=true) or after Instr.
bool isSplit() const override
Does this point involve splitting an edge or block? As soon as getPoint is called and thus,...
uint64_t frequency(const Pass &P) const override
Frequency of the insertion point.
Insertion point at the beginning or end of a basic block.
uint64_t frequency(const Pass &P) const override
Frequency of the insertion point.
Helper class used to represent the cost for mapping an instruction.
void saturate()
Saturate the cost to the maximal representable value.
bool operator==(const MappingCost &Cost) const
Check if this is equal to Cost.
bool addLocalCost(uint64_t Cost)
Add Cost to the local cost.
void dump() const
Print this on dbgs() stream.
static MappingCost ImpossibleCost()
Return an instance of MappingCost that represents an impossible mapping.
bool addNonLocalCost(uint64_t Cost)
Add Cost to the non-local cost.
bool operator<(const MappingCost &Cost) const
Check if this is less than Cost.
void print(raw_ostream &OS) const
Print this on OS;.
Struct used to represent the placement of a repairing point for a given operand.
unsigned getNumInsertPoints() const
bool canMaterialize() const
RepairingPlacement(MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo &TRI, Pass &P, RepairingKind Kind=RepairingKind::Insert)
Create a repairing placement for the OpIdx-th operand of MI.
unsigned getOpIdx() const
RepairingKind
Define the kind of action this repairing needs.
@ Insert
Reparing code needs to happen before InsertPoints.
@ None
Nothing to repair, just drop this action.
@ Reassign
(Re)assign the register bank of the operand.
@ Impossible
Mark this repairing placement as impossible.
void switchTo(RepairingKind NewKind)
Change the type of this repairing placement to NewKind.
void addInsertPoint(MachineBasicBlock &MBB, bool Beginning)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Mode
List of the modes supported by the RegBankSelect pass.
@ Fast
Assign the register banks as fast as possible (default).
bool checkFunctionIsLegal(MachineFunction &MF) const
Check that our input is fully legal: we require the function to have the Legalized property,...
MachineIRBuilder MIRBuilder
Helper class used for every code morphing.
MachineBlockFrequencyInfo * MBFI
Get the frequency of blocks.
Mode OptMode
Optimization mode of the pass.
const RegisterBankInfo::InstructionMapping & findBestMapping(MachineInstr &MI, RegisterBankInfo::InstructionMappings &PossibleMappings, SmallVectorImpl< RepairingPlacement > &RepairPts)
Find the best mapping for MI from PossibleMappings.
bool assignInstr(MachineInstr &MI)
Assign the register bank of each operand of MI.
bool assignRegisterBanks(MachineFunction &MF)
Walk through MF and assign a register bank to every virtual register that are still mapped to nothing...
void init(MachineFunction &MF)
Initialize the field members using MF.
void tryAvoidingSplit(RegBankSelect::RepairingPlacement &RepairPt, const MachineOperand &MO, const RegisterBankInfo::ValueMapping &ValMapping) const
When RepairPt involves splitting to repair MO for the given ValMapping, try to change the way we repa...
const TargetRegisterInfo * TRI
Information on the register classes for the current function.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
MachineBranchProbabilityInfo * MBPI
Get the frequency of the edges.
bool assignmentMatch(Register Reg, const RegisterBankInfo::ValueMapping &ValMapping, bool &OnlyAssign) const
Check if Reg is already assigned what is described by ValMapping.
uint64_t getRepairCost(const MachineOperand &MO, const RegisterBankInfo::ValueMapping &ValMapping) const
Return the cost of the instruction needed to map MO to ValMapping.
MappingCost computeMapping(MachineInstr &MI, const RegisterBankInfo::InstructionMapping &InstrMapping, SmallVectorImpl< RepairingPlacement > &RepairPts, const MappingCost *BestCost=nullptr)
Compute the cost of mapping MI with InstrMapping and compute the repairing placement for such mapping...
bool repairReg(MachineOperand &MO, const RegisterBankInfo::ValueMapping &ValMapping, RegBankSelect::RepairingPlacement &RepairPt, const iterator_range< SmallVectorImpl< Register >::const_iterator > &NewVRegs)
Insert repairing code for Reg as specified by ValMapping.
MachineRegisterInfo * MRI
MRI contains all the register class/bank information that this pass uses and updates.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetPassConfig * TPC
Current target configuration. Controls how the pass handles errors.
const RegisterBankInfo * RBI
Interface to the target lowering info related to register banks.
std::unique_ptr< MachineOptimizationRemarkEmitter > MORE
Current optimization remark emitter. Used to report failures.
bool applyMapping(MachineInstr &MI, const RegisterBankInfo::InstructionMapping &InstrMapping, SmallVectorImpl< RepairingPlacement > &RepairPts)
Apply Mapping to MI.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned getNumOperands() const
Get the number of operands.
unsigned getCost() const
Get the cost.
bool verify(const MachineInstr &MI) const
Verifiy that this mapping makes sense for MI.
bool isValid() const
Check whether this object is valid.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
void createVRegs(unsigned OpIdx)
Create as many new virtual registers as needed for the mapping of the OpIdx-th operand.
iterator_range< SmallVectorImpl< Register >::const_iterator > getVRegs(unsigned OpIdx, bool ForDebug=false) const
Get all the virtual registers required to map the OpIdx-th operand of the instruction.
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
void applyMapping(const OperandsMapper &OpdMapper) const
Apply OpdMapper.getInstrMapping() to OpdMapper.getMI().
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const
Get the possible mapping for MI.
virtual unsigned getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const
Get the cost of using ValMapping to decompose a register.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
reference emplace_back(ArgTypes &&... Args)
typename SuperClass::const_iterator const_iterator
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Target-Independent Code Generator Pass Configuration Options.
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
A range adaptor for a pair of iterators.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
This is an optimization pass for GlobalISel generic memory operations.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
cl::opt< bool > DisableGISelLegalityCheck
auto reverse(ContainerTy &&C)
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
const MachineInstr * machineFunctionIsIllegal(const MachineFunction &MF)
Checks that MIR is fully legal, returns an illegal instruction if it's not, nullptr otherwise.
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
iterator_range< pointer_iterator< WrappedIteratorT > > make_pointer_range(RangeT &&Range)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
const RegisterBank * RegBank
Register bank where the partial value lives.
unsigned Length
Length of this mapping in bits.
Helper struct that represents how a value is mapped through different register banks.
bool partsAllUniform() const
unsigned NumBreakDowns
Number of partial mapping to break down this value.
const PartialMapping * BreakDown
How the value is broken down between the different register banks.