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44 #define DEBUG_TYPE "optimize-mips-pic-call"
48 cl::desc(
"Load target address from GOT"),
58 using CntRegP = std::pair<unsigned, unsigned>;
69 bool isVisited()
const;
70 void preVisit(ScopedHTType &ScopedHT);
75 ScopedHTType::ScopeTy *HTScope;
82 StringRef getPassName()
const override {
return "Mips OptimizePICCall"; }
93 bool visitNode(MBBInfo &
MBBI);
114 ScopedHTType ScopedHT;
125 if (
MI.getNumOperands() == 0)
154 Register SrcReg =
I->getOperand(0).getReg();
155 unsigned DstReg =
getRegTy(SrcReg, MF) ==
MVT::i32 ? Mips::T9 : Mips::T9_64;
156 BuildMI(*
MBB,
I,
I->getDebugLoc(),
TII.get(TargetOpcode::COPY), DstReg)
158 I->getOperand(0).setReg(DstReg);
168 unsigned Reg = Ty ==
MVT::i32 ? Mips::GP : Mips::GP_64;
170 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I) {
185 bool MBBInfo::isVisited()
const {
return HTScope; }
187 void MBBInfo::preVisit(ScopedHTType &ScopedHT) {
188 HTScope =
new ScopedHTType::ScopeTy(ScopedHT);
191 void MBBInfo::postVisit() {
202 bool Changed =
false;
206 while (!WorkList.empty()) {
211 if (
MBBI.isVisited()) {
218 MBBI.preVisit(ScopedHT);
219 Changed |= visitNode(
MBBI);
221 WorkList.append(Node->begin(), Node->end());
227 bool OptimizePICCall::visitNode(MBBInfo &
MBBI) {
228 bool Changed =
false;
237 if (!isCallViaRegister(*
I,
Reg, Entry))
241 unsigned N = getCount(Entry);
257 incCntAndSetReg(Entry,
Reg);
302 unsigned OptimizePICCall::getCount(
ValueType Entry) {
303 return ScopedHT.lookup(Entry).first;
307 unsigned Reg = ScopedHT.lookup(Entry).second;
312 void OptimizePICCall::incCntAndSetReg(
ValueType Entry,
unsigned Reg) {
313 CntRegP
P = ScopedHT.lookup(Entry);
314 ScopedHT.insert(Entry, std::make_pair(
P.first + 1,
Reg));
319 return new OptimizePICCall();
This is an optimization pass for GlobalISel generic memory operations.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
virtual const TargetInstrInfo * getInstrInfo() const
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Reg
All possible values of the reg field in the ModR/M byte.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachineDomTreeNode * getRootNode() const
BumpPtrAllocatorImpl BumpPtrAllocator
The standard BumpPtrAllocator which just uses the default template parameters.
unsigned const TargetRegisterInfo * TRI
vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
An information struct used to provide DenseMap with the various necessary components for a given valu...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetInstrInfo - Interface to description of machine instruction set.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool inMips16Mode() const
FunctionPass * createMipsOptimizePICCallPass()
Return an OptimizeCall object.
const MachineOperand & getOperand(unsigned i) const
Represent the analysis usage information of a pass.
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
static MVT::SimpleValueType getRegTy(unsigned Reg, MachineFunction &MF)
Return type of register Reg.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static void eraseGPOpnd(MachineInstr &MI)
Search MI's operands for register GP and erase it.
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
@ MO_GOT_CALL
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static cl::opt< bool > LoadTargetFromGOT("mips-load-target-from-got", cl::init(true), cl::desc("Load target address from GOT"), cl::Hidden)
unsigned getTargetFlags() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
initializer< Ty > init(const Ty &Val)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getReg() const
getReg - Returns the register number.
StringRef - Represent a constant reference to a string, i.e.
MachineBasicBlock MachineBasicBlock::iterator MBBI
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static MachineOperand * getCallTargetRegOpnd(MachineInstr &MI)
Return the first MachineOperand of MI if it is a used virtual register.
Base class for the actual dominator tree node.
PointerUnion< const Value *, const PseudoSourceValue * > ValueType
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
RecyclingAllocator - This class wraps an Allocator, adding the functionality of recycling deleted obj...
static void setCallTargetReg(MachineBasicBlock *MBB, MachineBasicBlock::iterator I)
Do the following transformation:
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void setReg(Register Reg)
Change the register this operand corresponds to.
MachineInstrBuilder MachineInstrBuilder & DefMI
unsigned getNumOperands() const
Retuns the total number of operands.
FunctionPass class - This class is used to implement most global optimizations.
AnalysisUsage & addRequired()
static cl::opt< bool > EraseGPOpnd("mips-erase-gp-opnd", cl::init(true), cl::desc("Erase GP Operand"), cl::Hidden)
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class.