Go to the documentation of this file.
50 if (Mips::ACC64RegClass.
contains(Src))
51 return std::make_pair((
unsigned)Mips::PseudoMFHI,
52 (
unsigned)Mips::PseudoMFLO);
54 if (Mips::ACC64DSPRegClass.
contains(Src))
55 return std::make_pair((
unsigned)Mips::MFHI_DSP, (
unsigned)Mips::MFLO_DSP);
57 if (Mips::ACC128RegClass.
contains(Src))
58 return std::make_pair((
unsigned)Mips::PseudoMFHI64,
59 (
unsigned)Mips::PseudoMFLO64);
61 return std::make_pair(0, 0);
80 unsigned MFLoOpc,
unsigned RegSize);
99 : MF(MF_),
MRI(MF.getRegInfo()),
102 RegInfo(*Subtarget.getRegisterInfo()) {}
105 bool Expanded =
false;
107 for (
auto &
MBB : MF) {
109 Expanded |= expandInstr(
MBB,
I++);
116 switch(
I->getOpcode()) {
117 case Mips::LOAD_CCOND_DSP:
118 expandLoadCCond(
MBB,
I);
120 case Mips::STORE_CCOND_DSP:
121 expandStoreCCond(
MBB,
I);
123 case Mips::LOAD_ACC64:
124 case Mips::LOAD_ACC64DSP:
125 expandLoadACC(
MBB,
I, 4);
127 case Mips::LOAD_ACC128:
128 expandLoadACC(
MBB,
I, 8);
130 case Mips::STORE_ACC64:
131 expandStoreACC(
MBB,
I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4);
133 case Mips::STORE_ACC64DSP:
134 expandStoreACC(
MBB,
I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4);
136 case Mips::STORE_ACC128:
137 expandStoreACC(
MBB,
I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8);
140 if (expandBuildPairF64(
MBB,
I,
false))
143 case Mips::BuildPairF64_64:
144 if (expandBuildPairF64(
MBB,
I,
true))
148 if (expandExtractElementF64(
MBB,
I,
false))
151 case Mips::ExtractElementF64_64:
152 if (expandExtractElementF64(
MBB,
I,
true))
155 case TargetOpcode::COPY:
156 if (!expandCopy(
MBB,
I))
171 assert(
I->getOperand(0).isReg() &&
I->getOperand(1).isFI());
175 Register Dst =
I->getOperand(0).getReg(), FI =
I->getOperand(1).getIndex();
177 TII.loadRegFromStack(
MBB,
I, VR, FI, RC, &RegInfo, 0);
186 assert(
I->getOperand(0).isReg() &&
I->getOperand(1).isFI());
190 Register Src =
I->getOperand(0).getReg(), FI =
I->getOperand(1).getIndex();
194 TII.storeRegToStack(
MBB,
I, VR,
true, FI, RC, &RegInfo, 0);
204 assert(
I->getOperand(0).isReg() &&
I->getOperand(1).isFI());
209 Register Dst =
I->getOperand(0).getReg(), FI =
I->getOperand(1).getIndex();
210 Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
211 Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
215 TII.loadRegFromStack(
MBB,
I, VR0, FI, RC, &RegInfo, 0);
222 unsigned MFHiOpc,
unsigned MFLoOpc,
229 assert(
I->getOperand(0).isReg() &&
I->getOperand(1).isFI());
234 Register Src =
I->getOperand(0).getReg(), FI =
I->getOperand(1).getIndex();
239 TII.storeRegToStack(
MBB,
I, VR0,
true, FI, RC, &RegInfo, 0);
241 TII.storeRegToStack(
MBB,
I, VR1,
true, FI, RC, &RegInfo,
RegSize);
245 Register Src =
I->getOperand(1).getReg();
246 std::pair<unsigned, unsigned> Opcodes =
getMFHiLoOpc(Src);
251 return expandCopyACC(
MBB,
I, Opcodes.first, Opcodes.second);
255 unsigned MFHiOpc,
unsigned MFLoOpc) {
261 unsigned Dst =
I->getOperand(0).getReg(), Src =
I->getOperand(1).getReg();
263 unsigned VRegSize = RegInfo.getRegSizeInBits(*DstRC) / 16;
268 Register DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
269 Register DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
305 if (
I->getNumOperands() == 4 &&
I->getOperand(3).isReg()
306 &&
I->getOperand(3).getReg() == Mips::SP) {
307 Register DstReg =
I->getOperand(0).getReg();
308 Register LoReg =
I->getOperand(1).getReg();
309 Register HiReg =
I->getOperand(2).getReg();
314 assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
315 !Subtarget.isFP64bit());
319 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
324 if (!Subtarget.isLittle())
326 TII.storeRegToStack(
MBB,
I, LoReg,
I->getOperand(1).isKill(), FI, RC,
328 TII.storeRegToStack(
MBB,
I, HiReg,
I->getOperand(2).isKill(), FI, RC,
330 TII.loadRegFromStack(
MBB,
I, DstReg, FI, RC2, &RegInfo, 0);
349 Register DstReg =
I->getOperand(0).getReg();
350 BuildMI(
MBB,
I,
I->getDebugLoc(),
TII.get(Mips::IMPLICIT_DEF), DstReg);
370 if (
I->getNumOperands() == 4 &&
I->getOperand(3).isReg()
371 &&
I->getOperand(3).getReg() == Mips::SP) {
372 Register DstReg =
I->getOperand(0).getReg();
375 int64_t
Offset = 4 * (Subtarget.isLittle() ?
N : (1 -
N));
380 assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
381 !Subtarget.isFP64bit());
384 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
390 TII.storeRegToStack(
MBB,
I, SrcReg, Op1.
isKill(), FI, RC, &RegInfo, 0);
391 TII.loadRegFromStack(
MBB,
I, DstReg, FI, RC2, &RegInfo,
Offset);
414 unsigned SP =
ABI.GetStackPtr();
415 unsigned FP =
ABI.GetFramePtr();
416 unsigned ZERO =
ABI.GetNullPtr();
417 unsigned MOVE =
ABI.GetGPRMoveOp();
418 unsigned ADDiu =
ABI.GetPtrAddiuOp();
422 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
434 TII.adjustStackPtr(SP, -StackSize,
MBB,
MBBI);
443 emitInterruptPrologueStub(MF,
MBB);
450 for (
unsigned i = 0;
i < CSI.size(); ++
i)
463 MRI->getDwarfRegNum(RegInfo.getSubReg(
Reg, Mips::sub_lo),
true);
465 MRI->getDwarfRegNum(RegInfo.getSubReg(
Reg, Mips::sub_hi),
true);
480 unsigned Reg0 =
MRI->getDwarfRegNum(
Reg,
true);
481 unsigned Reg1 =
MRI->getDwarfRegNum(
Reg,
true) + 1;
498 nullptr,
MRI->getDwarfRegNum(
Reg,
true), Offset));
507 for (
int I = 0;
I < 4; ++
I) {
515 for (
int I = 0;
I < 4; ++
I) {
517 unsigned Reg =
MRI->getDwarfRegNum(
ABI.GetEhDataReg(
I),
true);
533 nullptr,
MRI->getDwarfRegNum(
FP,
true)));
537 if (RegInfo.hasStackRealignment(MF)) {
542 "Function's alignment size requirement is not supported.");
559 void MipsSEFrameLowering::emitInterruptPrologueStub(
572 "\"interrupt\" attribute is not supported on pre-MIPS32R2 or "
581 "static relocation model on MIPS at the present time.");
585 "O32 ABI on MIPS32R2+ at the present time.");
594 if (IntKind ==
"eic") {
633 unsigned InsPosition = 8;
634 unsigned InsSize = 0;
635 unsigned SrcReg = Mips::ZERO;
639 if (IntKind ==
"eic") {
654 assert(InsSize != 0 &&
"Unknown interrupt type!");
700 unsigned SP =
ABI.GetStackPtr();
701 unsigned FP =
ABI.GetFramePtr();
702 unsigned ZERO =
ABI.GetNullPtr();
703 unsigned MOVE =
ABI.GetGPRMoveOp();
719 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
727 for (
int J = 0; J < 4; ++J) {
734 emitInterruptEpilogueStub(MF,
MBB);
746 void MipsSEFrameLowering::emitInterruptEpilogueStub(
783 FrameReg =
hasFP(MF) ?
ABI.GetFramePtr() :
ABI.GetStackPtr();
785 FrameReg =
hasBP(MF) ?
ABI.GetBasePtr() :
ABI.GetStackPtr();
805 bool IsRAAndRetAddrIsTaken = (
Reg == Mips::RA ||
Reg == Mips::RA_64)
807 if (!IsRAAndRetAddrIsTaken)
812 bool IsLOHI = (
Reg == Mips::LO0 ||
Reg == Mips::LO0_64 ||
813 Reg == Mips::HI0 ||
Reg == Mips::HI0_64);
815 if (IsLOHI && Func.hasFnAttribute(
"interrupt")) {
823 Op = (
Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64;
831 bool IsKill = !IsRAAndRetAddrIsTaken;
865 unsigned RA =
ABI.IsN64() ? Mips::RA_64 : Mips::RA;
866 unsigned FP =
ABI.GetFramePtr();
867 unsigned BP =
ABI.IsN64() ? Mips::S7_64 : Mips::S7;
888 if (ExpandPseudo(MF).
expand()) {
893 Mips::GPR64RegClass : Mips::GPR32RegClass;
909 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass;
StringSwitch & Case(StringLiteral S, T Value)
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Generic address nodes are lowered to some combination of target independent and machine specific ABI
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
bool ArePtrs64bit() const
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
virtual void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const MCContext & getContext() const
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
const MCRegisterInfo * getRegisterInfo() const
LLVM_NODISCARD R Default(T Value)
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
return AArch64::GPR64RegClass contains(Reg)
void createISRRegFI(MachineFunction &MF)
Reg
All possible values of the reg field in the ModR/M byte.
const MipsABIInfo & getABI() const
int getOffsetAdjustment() const
Return the correction for frame offsets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static void setAliasRegs(MachineFunction &MF, BitVector &SavedRegs, unsigned Reg)
Mark Reg and all registers aliasing it in the bitset.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
ScalarTy getFixed() const
int getISRRegFI(Register Reg) const
const MipsInstrInfo * getInstrInfo() const override
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
unsigned const TargetRegisterInfo * TRI
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
const MipsFrameLowering * createMipsSEFrameLowering(const MipsSubtarget &ST)
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const MipsRegisterInfo * getRegisterInfo() const override
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
TargetInstrInfo - Interface to description of machine instruction set.
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
bool isReturnAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned Log2(Align A)
Returns the log2 of the alignment.
uint64_t estimateStackSize(const MachineFunction &MF) const
const HexagonInstrInfo * TII
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
This class contains meta information specific to a module.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
@ AND
Bitwise operators - logical and, logical or, logical xor.
const MipsSubtarget & STI
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
StringRef getValueAsString() const
Return the attribute's value as a string.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
MachineModuleInfo & getMMI() const
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
void createEhDataRegsFI(MachineFunction &MF)
static Expected< BitVector > expand(StringRef S, StringRef Original)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
bool hasBP(const MachineFunction &MF) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getReg() const
getReg - Returns the register number.
SI optimize exec mask operations pre RA
bool callsEhReturn() const
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
MachineInstrBundleIterator< MachineInstr > iterator
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
static std::pair< unsigned, unsigned > getMFHiLoOpc(unsigned Src)
StringRef - Represent a constant reference to a string, i.e.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
MachineBasicBlock MachineBasicBlock::iterator MBBI
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
int getEhDataRegFI(unsigned Reg) const
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Wrapper class representing virtual and physical registers.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
constexpr bool isInt< 16 >(int64_t x)
Function & getFunction()
Return the LLVM function that this machine code represents.
@ ZERO
Special weight used for cases with exact zero probability.
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
uint64_t value() const
This is a hole in the type system and should not be abused.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned getKillRegState(bool B)
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
A switch()-like statement whose cases are string literals.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
bool useSoftFloat() const
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Reloc::Model getRelocationModel() const
@ Kill
The last use of a register.
MCRegAliasIterator enumerates all registers aliasing Reg.