#include "Target/Mips/MipsSEInstrInfo.h"

Inheritance diagram for llvm::MipsSEInstrInfo:

Public Member Functions
	MipsSEInstrInfo (const MipsSubtarget &STI)

const MipsRegisterInfo &	getRegisterInfo () const override
	getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

Register	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
	isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.

Register	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
	isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.

void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override

void	storeRegToStack (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, int64_t Offset) const override

void	loadRegFromStack (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, int64_t Offset) const override

bool	expandPostRAPseudo (MachineInstr &MI) const override

bool	isBranchWithImm (unsigned Opc) const override
	isBranchWithImm - Return true if the branch contains an immediate operand (

unsigned	getOppositeBranchOpc (unsigned Opc) const override
	getOppositeBranchOpc - Return the inverse of the specified opcode, e.g.

void	adjustStackPtr (unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
	Adjust SP by Amount bytes.

unsigned	loadImmediate (int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned *NewImm) const
	Emit a series of instructions to load an immediate.

Public Member Functions inherited from llvm::MipsInstrInfo
	MipsInstrInfo (const MipsSubtarget &STI, unsigned UncondBrOpc)

bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
	Branch Analysis.

unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock TBB, MachineBasicBlock FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
	reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.

BranchType	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify, SmallVectorImpl< MachineInstr * > &BranchInstrs) const

unsigned	getEquivalentCompactForm (const MachineBasicBlock::iterator I) const
	Determine the opcode of a non-delay slot form for a branch if one exists.

bool	isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
	Determine if the branch target is in range.

bool	SafeInForbiddenSlot (const MachineInstr &MI) const
	Predicate to determine if an instruction can go in a forbidden slot.

bool	SafeInFPUDelaySlot (const MachineInstr &MIInSlot, const MachineInstr &FPUMI) const
	Predicate to determine if an instruction can go in an FPU delay slot.

bool	SafeInLoadDelaySlot (const MachineInstr &MIInSlot, const MachineInstr &LoadMI) const
	Predicate to determine if an instruction can go in a load delay slot.

bool	HasForbiddenSlot (const MachineInstr &MI) const
	Predicate to determine if an instruction has a forbidden slot.

bool	HasFPUDelaySlot (const MachineInstr &MI) const
	Predicate to determine if an instruction has an FPU delay slot.

bool	HasLoadDelaySlot (const MachineInstr &MI) const
	Predicate to determine if an instruction has a load delay slot.

void	insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
	Insert nop instruction when hazard condition is found.

MachineInstrBuilder	insertNop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL) const
	Insert an ISA appropriate `nop`.

virtual const MipsRegisterInfo &	getRegisterInfo () const =0
	getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

virtual unsigned	getOppositeBranchOpc (unsigned Opc) const =0

virtual bool	isBranchWithImm (unsigned Opc) const

unsigned	getInstSizeInBytes (const MachineInstr &MI) const override
	Return the number of bytes of code the specified instruction may be.

void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, Register VReg) const override

void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, Register VReg) const override

virtual void	storeRegToStack (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, int64_t Offset) const =0

virtual void	loadRegFromStack (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, int64_t Offset) const =0

virtual void	adjustStackPtr (unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const =0

MachineInstrBuilder	genInstrWithNewOpc (unsigned NewOpc, MachineBasicBlock::iterator I) const
	Create an instruction which has the same operands and memory operands as MI but has a new opcode.

bool	findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override

bool	verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override
	Perform target specific instruction verification.

std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override

ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override

std::optional< RegImmPair >	isAddImmediate (const MachineInstr &MI, Register Reg) const override

std::optional< ParamLoadedValue >	describeLoadedValue (const MachineInstr &MI, Register Reg) const override

Protected Member Functions
std::optional< DestSourcePair >	isCopyInstrImpl (const MachineInstr &MI) const override
	If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands.

Protected Member Functions inherited from llvm::MipsInstrInfo
bool	isZeroImm (const MachineOperand &op) const

MachineMemOperand *	GetMemOperand (MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const

Additional Inherited Members
Public Types inherited from llvm::MipsInstrInfo
enum	BranchType { BT_None , BT_NoBranch , BT_Uncond , BT_Cond , BT_CondUncond , BT_Indirect }

Static Public Member Functions inherited from llvm::MipsInstrInfo
static const MipsInstrInfo *	create (MipsSubtarget &STI)

Protected Attributes inherited from llvm::MipsInstrInfo
const MipsSubtarget &	Subtarget

unsigned	UncondBrOpc

Detailed Description

Definition at line 21 of file MipsSEInstrInfo.h.

Constructor & Destructor Documentation

◆ MipsSEInstrInfo()

MipsSEInstrInfo::MipsSEInstrInfo ( const MipsSubtarget & STI )

explicit

Definition at line 33 of file MipsSEInstrInfo.cpp.

Member Function Documentation

◆ adjustStackPtr()

void MipsSEInstrInfo::adjustStackPtr	(	unsigned	SP,
		int64_t	Amount,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I
	)		const

overridevirtual

Adjust SP by Amount bytes.

Implements llvm::MipsInstrInfo.

Definition at line 559 of file MipsSEInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::get(), llvm::MipsSubtarget::getABI(), I, llvm::RegState::Kill, loadImmediate(), MBB, and llvm::MipsInstrInfo::Subtarget.

◆ copyPhysReg()

void MipsSEInstrInfo::copyPhysReg	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const DebugLoc &	DL,
		MCRegister	DestReg,
		MCRegister	SrcReg,
		bool	KillSrc
	)		const

override

Definition at line 83 of file MipsSEInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), llvm::RegState::Define, DL, llvm::get(), llvm::getKillRegState(), I, llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::MipsSubtarget::inMicroMipsMode(), isMicroMips(), MBB, and llvm::MipsInstrInfo::Subtarget.

◆ expandPostRAPseudo()

bool MipsSEInstrInfo::expandPostRAPseudo ( MachineInstr & MI ) const

override

Definition at line 373 of file MipsSEInstrInfo.cpp.

References llvm::MachineBasicBlock::erase(), llvm::MipsSubtarget::inMicroMipsMode(), isMicroMips(), MBB, MI, and llvm::MipsInstrInfo::Subtarget.

◆ getOppositeBranchOpc()

unsigned MipsSEInstrInfo::getOppositeBranchOpc ( unsigned Opc ) const

overridevirtual

getOppositeBranchOpc - Return the inverse of the specified opcode, e.g.

turning BEQ to BNE.

Implements llvm::MipsInstrInfo.

Definition at line 472 of file MipsSEInstrInfo.cpp.

References llvm_unreachable.

◆ getRegisterInfo()

const MipsRegisterInfo & MipsSEInstrInfo::getRegisterInfo ( ) const

overridevirtual

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Implements llvm::MipsInstrInfo.

Definition at line 36 of file MipsSEInstrInfo.cpp.

◆ isBranchWithImm()

bool MipsSEInstrInfo::isBranchWithImm ( unsigned Opc ) const

overridevirtual

isBranchWithImm - Return true if the branch contains an immediate operand (

See also: lib/Target/Mips/MipsBranchExpansion.cpp).

Reimplemented from llvm::MipsInstrInfo.

Definition at line 458 of file MipsSEInstrInfo.cpp.

◆ isCopyInstrImpl()

std::optional< DestSourcePair > MipsSEInstrInfo::isCopyInstrImpl ( const MachineInstr & MI ) const

overrideprotected

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands.

We check for the common case of 'or', as it's MIPS' preferred instruction for GPRs but we have to check the operands to ensure that is the case.

Other move instructions for MIPS are directly identifiable.

Definition at line 207 of file MipsSEInstrInfo.cpp.

References isORCopyInst(), and MI.

◆ isLoadFromStackSlot()

Register MipsSEInstrInfo::isLoadFromStackSlot	(	const MachineInstr &	MI,
		int &	FrameIndex
	)		const

override

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Definition at line 45 of file MipsSEInstrInfo.cpp.

References llvm::MipsInstrInfo::isZeroImm(), and MI.

◆ isStoreToStackSlot()

Register MipsSEInstrInfo::isStoreToStackSlot	(	const MachineInstr &	MI,
		int &	FrameIndex
	)		const

override

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Definition at line 67 of file MipsSEInstrInfo.cpp.

References llvm::MipsInstrInfo::isZeroImm(), and MI.

◆ loadImmediate()

unsigned MipsSEInstrInfo::loadImmediate	(	int64_t	Imm,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	II,
		const DebugLoc &	DL,
		unsigned *	NewImm
	)		const

Emit a series of instructions to load an immediate.

This function generates the sequence of instructions needed to get the result of adding register REG and immediate IMM.

If NewImm is a non-NULL parameter, the last instruction is not emitted, but instead its immediate operand is returned in NewImm.

Definition at line 587 of file MipsSEInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MipsAnalyzeImmediate::Analyze(), assert(), llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::get(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), II, llvm::MipsSubtarget::isABI_N64(), llvm::RegState::Kill, MBB, llvm::SmallVectorBase< Size_T >::size(), Size, and llvm::MipsInstrInfo::Subtarget.

Referenced by adjustStackPtr().

◆ loadRegFromStack()

void MipsSEInstrInfo::loadRegFromStack	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		Register	DestReg,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI,
		int64_t	Offset
	)		const

overridevirtual

◆ storeRegToStack()

void MipsSEInstrInfo::storeRegToStack	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		Register	SrcReg,
		bool	isKill,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI,
		int64_t	Offset
	)		const

overridevirtual

The documentation for this class was generated from the following files:

lib/Target/Mips/MipsSEInstrInfo.h
lib/Target/Mips/MipsSEInstrInfo.cpp

Public Member Functions

Protected Member Functions

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ MipsSEInstrInfo()

Member Function Documentation

◆ adjustStackPtr()

◆ copyPhysReg()

◆ expandPostRAPseudo()

◆ getOppositeBranchOpc()

◆ getRegisterInfo()

◆ isBranchWithImm()

◆ isCopyInstrImpl()

◆ isLoadFromStackSlot()

◆ isStoreToStackSlot()

◆ loadImmediate()

◆ loadRegFromStack()

◆ storeRegToStack()