LLVM  10.0.0svn
MipsTargetStreamer.cpp
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1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Mips specific target streamer methods.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsTargetStreamer.h"
14 #include "MipsInstPrinter.h"
16 #include "MipsELFStreamer.h"
17 #include "MipsMCExpr.h"
18 #include "MipsMCTargetDesc.h"
19 #include "MipsTargetObjectFile.h"
20 #include "llvm/BinaryFormat/ELF.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCSectionELF.h"
24 #include "llvm/MC/MCSymbolELF.h"
28 
29 using namespace llvm;
30 
31 namespace {
32 static cl::opt<bool> RoundSectionSizes(
33  "mips-round-section-sizes", cl::init(false),
34  cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
35 } // end anonymous namespace
36 
38  : MCTargetStreamer(S), GPReg(Mips::GP), ModuleDirectiveAllowed(true) {
40 }
63 }
73 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
74  unsigned ReturnReg) {}
75 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
76 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
77 }
80 }
101 }
104 }
110  // .cplocal $reg
111  // This directive forces to use the alternate register for context pointer.
112  // For example
113  // .cplocal $4
114  // jal foo
115  // expands to
116  // ld $25, %call16(foo)($4)
117  // jalr $25
118 
119  if (!getABI().IsN32() && !getABI().IsN64())
120  return;
121 
122  GPReg = RegNo;
123 
125 }
127  int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
128  const MCSubtargetInfo *STI) {
130  return true;
131 }
132 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
133  const MCSymbol &Sym, bool IsReg) {
134 }
135 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
136  bool SaveLocationIsRegister) {}
137 
139 
142  report_fatal_error("+nooddspreg is only valid for O32");
143 }
156 }
160 }
161 
162 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
163  const MCSubtargetInfo *STI) {
164  MCInst TmpInst;
165  TmpInst.setOpcode(Opcode);
166  TmpInst.addOperand(MCOperand::createReg(Reg0));
167  TmpInst.setLoc(IDLoc);
168  getStreamer().EmitInstruction(TmpInst, *STI);
169 }
170 
171 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
172  SMLoc IDLoc, const MCSubtargetInfo *STI) {
173  MCInst TmpInst;
174  TmpInst.setOpcode(Opcode);
175  TmpInst.addOperand(MCOperand::createReg(Reg0));
176  TmpInst.addOperand(Op1);
177  TmpInst.setLoc(IDLoc);
178  getStreamer().EmitInstruction(TmpInst, *STI);
179 }
180 
181 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
182  SMLoc IDLoc, const MCSubtargetInfo *STI) {
183  emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
184 }
185 
186 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
187  SMLoc IDLoc, const MCSubtargetInfo *STI) {
188  emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
189 }
190 
191 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
192  SMLoc IDLoc, const MCSubtargetInfo *STI) {
193  MCInst TmpInst;
194  TmpInst.setOpcode(Opcode);
195  TmpInst.addOperand(MCOperand::createImm(Imm1));
196  TmpInst.addOperand(MCOperand::createImm(Imm2));
197  TmpInst.setLoc(IDLoc);
198  getStreamer().EmitInstruction(TmpInst, *STI);
199 }
200 
201 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
202  MCOperand Op2, SMLoc IDLoc,
203  const MCSubtargetInfo *STI) {
204  MCInst TmpInst;
205  TmpInst.setOpcode(Opcode);
206  TmpInst.addOperand(MCOperand::createReg(Reg0));
207  TmpInst.addOperand(MCOperand::createReg(Reg1));
208  TmpInst.addOperand(Op2);
209  TmpInst.setLoc(IDLoc);
210  getStreamer().EmitInstruction(TmpInst, *STI);
211 }
212 
213 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
214  unsigned Reg2, SMLoc IDLoc,
215  const MCSubtargetInfo *STI) {
216  emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
217 }
218 
219 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
220  int16_t Imm, SMLoc IDLoc,
221  const MCSubtargetInfo *STI) {
222  emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
223 }
224 
225 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
226  unsigned Reg1, int16_t Imm0, int16_t Imm1,
227  int16_t Imm2, SMLoc IDLoc,
228  const MCSubtargetInfo *STI) {
229  MCInst TmpInst;
230  TmpInst.setOpcode(Opcode);
231  TmpInst.addOperand(MCOperand::createReg(Reg0));
232  TmpInst.addOperand(MCOperand::createReg(Reg1));
233  TmpInst.addOperand(MCOperand::createImm(Imm0));
234  TmpInst.addOperand(MCOperand::createImm(Imm1));
235  TmpInst.addOperand(MCOperand::createImm(Imm2));
236  TmpInst.setLoc(IDLoc);
237  getStreamer().EmitInstruction(TmpInst, *STI);
238 }
239 
240 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
241  unsigned TrgReg, bool Is64Bit,
242  const MCSubtargetInfo *STI) {
243  emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
244  STI);
245 }
246 
247 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
248  int16_t ShiftAmount, SMLoc IDLoc,
249  const MCSubtargetInfo *STI) {
250  if (ShiftAmount >= 32) {
251  emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
252  return;
253  }
254 
255  emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
256 }
257 
259  const MCSubtargetInfo *STI) {
260  if (hasShortDelaySlot)
261  emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
262  else
263  emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
264 }
265 
267  const FeatureBitset &Features = STI->getFeatureBits();
268  if (Features[Mips::FeatureMicroMips])
269  emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
270  else
271  emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
272 }
273 
274 /// Emit the $gp restore operation for .cprestore.
276  const MCSubtargetInfo *STI) {
277  emitLoadWithImmOffset(Mips::LW, GPReg, Mips::SP, Offset, GPReg, IDLoc, STI);
278 }
279 
280 /// Emit a store instruction with an immediate offset.
282  unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
283  function_ref<unsigned()> GetATReg, SMLoc IDLoc,
284  const MCSubtargetInfo *STI) {
285  if (isInt<16>(Offset)) {
286  emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
287  return;
288  }
289 
290  // sw $8, offset($8) => lui $at, %hi(offset)
291  // add $at, $at, $8
292  // sw $8, %lo(offset)($at)
293 
294  unsigned ATReg = GetATReg();
295  if (!ATReg)
296  return;
297 
298  unsigned LoOffset = Offset & 0x0000ffff;
299  unsigned HiOffset = (Offset & 0xffff0000) >> 16;
300 
301  // If msb of LoOffset is 1(negative number) we must increment HiOffset
302  // to account for the sign-extension of the low part.
303  if (LoOffset & 0x8000)
304  HiOffset++;
305 
306  // Generate the base address in ATReg.
307  emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
308  if (BaseReg != Mips::ZERO)
309  emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
310  // Emit the store with the adjusted base and offset.
311  emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
312 }
313 
314 /// Emit a store instruction with an symbol offset. Symbols are assumed to be
315 /// out of range for a simm16 will be expanded to appropriate instructions.
317  unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand,
318  MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc,
319  const MCSubtargetInfo *STI) {
320  // sw $8, sym => lui $at, %hi(sym)
321  // sw $8, %lo(sym)($at)
322 
323  // Generate the base address in ATReg.
324  emitRX(Mips::LUi, ATReg, HiOperand, IDLoc, STI);
325  if (BaseReg != Mips::ZERO)
326  emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
327  // Emit the store with the adjusted base and offset.
328  emitRRX(Opcode, SrcReg, ATReg, LoOperand, IDLoc, STI);
329 }
330 
331 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
332 /// permitted to be the same register iff DstReg is distinct from BaseReg and
333 /// DstReg is a GPR. It is the callers responsibility to identify such cases
334 /// and pass the appropriate register in TmpReg.
335 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
336  unsigned BaseReg, int64_t Offset,
337  unsigned TmpReg, SMLoc IDLoc,
338  const MCSubtargetInfo *STI) {
339  if (isInt<16>(Offset)) {
340  emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
341  return;
342  }
343 
344  // 1) lw $8, offset($9) => lui $8, %hi(offset)
345  // add $8, $8, $9
346  // lw $8, %lo(offset)($9)
347  // 2) lw $8, offset($8) => lui $at, %hi(offset)
348  // add $at, $at, $8
349  // lw $8, %lo(offset)($at)
350 
351  unsigned LoOffset = Offset & 0x0000ffff;
352  unsigned HiOffset = (Offset & 0xffff0000) >> 16;
353 
354  // If msb of LoOffset is 1(negative number) we must increment HiOffset
355  // to account for the sign-extension of the low part.
356  if (LoOffset & 0x8000)
357  HiOffset++;
358 
359  // Generate the base address in TmpReg.
360  emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
361  if (BaseReg != Mips::ZERO)
362  emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
363  // Emit the load with the adjusted base and offset.
364  emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
365 }
366 
367 /// Emit a load instruction with an symbol offset. Symbols are assumed to be
368 /// out of range for a simm16 will be expanded to appropriate instructions.
369 /// DstReg and TmpReg are permitted to be the same register iff DstReg is a
370 /// GPR. It is the callers responsibility to identify such cases and pass the
371 /// appropriate register in TmpReg.
372 void MipsTargetStreamer::emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg,
373  unsigned BaseReg,
374  MCOperand &HiOperand,
375  MCOperand &LoOperand,
376  unsigned TmpReg, SMLoc IDLoc,
377  const MCSubtargetInfo *STI) {
378  // 1) lw $8, sym => lui $8, %hi(sym)
379  // lw $8, %lo(sym)($8)
380  // 2) ldc1 $f0, sym => lui $at, %hi(sym)
381  // ldc1 $f0, %lo(sym)($at)
382 
383  // Generate the base address in TmpReg.
384  emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
385  if (BaseReg != Mips::ZERO)
386  emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
387  // Emit the load with the adjusted base and offset.
388  emitRRX(Opcode, DstReg, TmpReg, LoOperand, IDLoc, STI);
389 }
390 
393  : MipsTargetStreamer(S), OS(OS) {}
394 
396  OS << "\t.set\tmicromips\n";
398 }
399 
401  OS << "\t.set\tnomicromips\n";
403 }
404 
406  OS << "\t.set\tmips16\n";
408 }
409 
411  OS << "\t.set\tnomips16\n";
413 }
414 
416  OS << "\t.set\treorder\n";
418 }
419 
421  OS << "\t.set\tnoreorder\n";
423 }
424 
426  OS << "\t.set\tmacro\n";
428 }
429 
431  OS << "\t.set\tnomacro\n";
433 }
434 
436  OS << "\t.set\tmsa\n";
438 }
439 
441  OS << "\t.set\tnomsa\n";
443 }
444 
446  OS << "\t.set\tmt\n";
448 }
449 
451  OS << "\t.set\tnomt\n";
453 }
454 
456  OS << "\t.set\tcrc\n";
458 }
459 
461  OS << "\t.set\tnocrc\n";
463 }
464 
466  OS << "\t.set\tvirt\n";
468 }
469 
471  OS << "\t.set\tnovirt\n";
473 }
474 
476  OS << "\t.set\tginv\n";
478 }
479 
481  OS << "\t.set\tnoginv\n";
483 }
484 
486  OS << "\t.set\tat\n";
488 }
489 
491  OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
493 }
494 
496  OS << "\t.set\tnoat\n";
498 }
499 
501  OS << "\t.end\t" << Name << '\n';
502 }
503 
505  OS << "\t.ent\t" << Symbol.getName() << '\n';
506 }
507 
508 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
509 
510 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
511 
513  OS << "\t.nan\tlegacy\n";
514 }
515 
517  OS << "\t.option\tpic0\n";
518 }
519 
521  OS << "\t.option\tpic2\n";
522 }
523 
526  OS << "\t.insn\n";
527 }
528 
529 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
530  unsigned ReturnReg) {
531  OS << "\t.frame\t$"
532  << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
533  << StackSize << ",$"
534  << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
535 }
536 
538  OS << "\t.set arch=" << Arch << "\n";
540 }
541 
543  OS << "\t.set\tmips0\n";
545 }
546 
548  OS << "\t.set\tmips1\n";
550 }
551 
553  OS << "\t.set\tmips2\n";
555 }
556 
558  OS << "\t.set\tmips3\n";
560 }
561 
563  OS << "\t.set\tmips4\n";
565 }
566 
568  OS << "\t.set\tmips5\n";
570 }
571 
573  OS << "\t.set\tmips32\n";
575 }
576 
578  OS << "\t.set\tmips32r2\n";
580 }
581 
583  OS << "\t.set\tmips32r3\n";
585 }
586 
588  OS << "\t.set\tmips32r5\n";
590 }
591 
593  OS << "\t.set\tmips32r6\n";
595 }
596 
598  OS << "\t.set\tmips64\n";
600 }
601 
603  OS << "\t.set\tmips64r2\n";
605 }
606 
608  OS << "\t.set\tmips64r3\n";
610 }
611 
613  OS << "\t.set\tmips64r5\n";
615 }
616 
618  OS << "\t.set\tmips64r6\n";
620 }
621 
623  OS << "\t.set\tdsp\n";
625 }
626 
628  OS << "\t.set\tdspr2\n";
630 }
631 
633  OS << "\t.set\tnodsp\n";
635 }
636 
638  OS << "\t.set\tpop\n";
640 }
641 
643  OS << "\t.set\tpush\n";
645 }
646 
648  OS << "\t.set\tsoftfloat\n";
650 }
651 
653  OS << "\t.set\thardfloat\n";
655 }
656 
657 // Print a 32 bit hex number with all numbers.
658 static void printHex32(unsigned Value, raw_ostream &OS) {
659  OS << "0x";
660  for (int i = 7; i >= 0; i--)
661  OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
662 }
663 
664 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
665  int CPUTopSavedRegOff) {
666  OS << "\t.mask \t";
667  printHex32(CPUBitmask, OS);
668  OS << ',' << CPUTopSavedRegOff << '\n';
669 }
670 
671 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
672  int FPUTopSavedRegOff) {
673  OS << "\t.fmask\t";
674  printHex32(FPUBitmask, OS);
675  OS << "," << FPUTopSavedRegOff << '\n';
676 }
677 
679  OS << "\t.cpload\t$"
680  << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
682 }
683 
685  OS << "\t.cplocal\t$"
686  << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
688 }
689 
691  int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
692  const MCSubtargetInfo *STI) {
693  MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
694  OS << "\t.cprestore\t" << Offset << "\n";
695  return true;
696 }
697 
699  int RegOrOffset,
700  const MCSymbol &Sym,
701  bool IsReg) {
702  OS << "\t.cpsetup\t$"
703  << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
704 
705  if (IsReg)
706  OS << "$"
708  else
709  OS << RegOrOffset;
710 
711  OS << ", ";
712 
713  OS << Sym.getName();
715 }
716 
718  bool SaveLocationIsRegister) {
719  OS << "\t.cpreturn";
721 }
722 
726  OS << "\t.module\tsoftfloat\n";
727  else
728  OS << "\t.module\tfp=" << ABIFlagsSection.getFpABIString(FpABI) << "\n";
729 }
730 
734 
735  OS << "\t.set\tfp=";
736  OS << ABIFlagsSection.getFpABIString(Value) << "\n";
737 }
738 
741 
742  OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
743 }
744 
747  OS << "\t.set\toddspreg\n";
748 }
749 
752  OS << "\t.set\tnooddspreg\n";
753 }
754 
756  OS << "\t.module\tsoftfloat\n";
757 }
758 
760  OS << "\t.module\thardfloat\n";
761 }
762 
764  OS << "\t.module\tmt\n";
765 }
766 
768  OS << "\t.module\tcrc\n";
769 }
770 
772  OS << "\t.module\tnocrc\n";
773 }
774 
776  OS << "\t.module\tvirt\n";
777 }
778 
780  OS << "\t.module\tnovirt\n";
781 }
782 
784  OS << "\t.module\tginv\n";
785 }
786 
788  OS << "\t.module\tnoginv\n";
789 }
790 
791 // This part is for ELF object output.
793  const MCSubtargetInfo &STI)
794  : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
796 
797  // It's possible that MCObjectFileInfo isn't fully initialized at this point
798  // due to an initialization order problem where LLVMTargetMachine creates the
799  // target streamer before TargetLoweringObjectFile calls
800  // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
801  // covers all cases so this statement covers most cases and direct object
802  // emission must call setPic() once MCObjectFileInfo has been initialized. The
803  // cases we don't handle here are covered by MipsAsmPrinter.
805 
806  const FeatureBitset &Features = STI.getFeatureBits();
807 
808  // Set the header flags that we can in the constructor.
809  // FIXME: This is a fairly terrible hack. We set the rest
810  // of these in the destructor. The problem here is two-fold:
811  //
812  // a: Some of the eflags can be set/reset by directives.
813  // b: There aren't any usage paths that initialize the ABI
814  // pointer until after we initialize either an assembler
815  // or the target machine.
816  // We can fix this by making the target streamer construct
817  // the ABI, but this is fraught with wide ranging dependency
818  // issues as well.
819  unsigned EFlags = MCA.getELFHeaderEFlags();
820 
821  // FIXME: Fix a dependency issue by instantiating the ABI object to some
822  // default based off the triple. The triple doesn't describe the target
823  // fully, but any external user of the API that uses the MCTargetStreamer
824  // would otherwise crash on assertion failure.
825 
826  ABI = MipsABIInfo(
827  STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
828  STI.getTargetTriple().getArch() == Triple::ArchType::mips
829  ? MipsABIInfo::O32()
830  : MipsABIInfo::N64());
831 
832  // Architecture
833  if (Features[Mips::FeatureMips64r6])
834  EFlags |= ELF::EF_MIPS_ARCH_64R6;
835  else if (Features[Mips::FeatureMips64r2] ||
836  Features[Mips::FeatureMips64r3] ||
837  Features[Mips::FeatureMips64r5])
838  EFlags |= ELF::EF_MIPS_ARCH_64R2;
839  else if (Features[Mips::FeatureMips64])
840  EFlags |= ELF::EF_MIPS_ARCH_64;
841  else if (Features[Mips::FeatureMips5])
842  EFlags |= ELF::EF_MIPS_ARCH_5;
843  else if (Features[Mips::FeatureMips4])
844  EFlags |= ELF::EF_MIPS_ARCH_4;
845  else if (Features[Mips::FeatureMips3])
846  EFlags |= ELF::EF_MIPS_ARCH_3;
847  else if (Features[Mips::FeatureMips32r6])
848  EFlags |= ELF::EF_MIPS_ARCH_32R6;
849  else if (Features[Mips::FeatureMips32r2] ||
850  Features[Mips::FeatureMips32r3] ||
851  Features[Mips::FeatureMips32r5])
852  EFlags |= ELF::EF_MIPS_ARCH_32R2;
853  else if (Features[Mips::FeatureMips32])
854  EFlags |= ELF::EF_MIPS_ARCH_32;
855  else if (Features[Mips::FeatureMips2])
856  EFlags |= ELF::EF_MIPS_ARCH_2;
857  else
858  EFlags |= ELF::EF_MIPS_ARCH_1;
859 
860  // Machine
861  if (Features[Mips::FeatureCnMips])
862  EFlags |= ELF::EF_MIPS_MACH_OCTEON;
863 
864  // Other options.
865  if (Features[Mips::FeatureNaN2008])
866  EFlags |= ELF::EF_MIPS_NAN2008;
867 
868  MCA.setELFHeaderEFlags(EFlags);
869 }
870 
872  auto *Symbol = cast<MCSymbolELF>(S);
874  uint8_t Type = Symbol->getType();
875  if (Type != ELF::STT_FUNC)
876  return;
877 
878  if (isMicroMipsEnabled())
879  Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
880 }
881 
884  const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
885 
886  // .bss, .text and .data are always at least 16-byte aligned.
887  MCSection &TextSection = *OFI.getTextSection();
888  MCA.registerSection(TextSection);
889  MCSection &DataSection = *OFI.getDataSection();
890  MCA.registerSection(DataSection);
891  MCSection &BSSSection = *OFI.getBSSSection();
892  MCA.registerSection(BSSSection);
893 
894  TextSection.setAlignment(std::max(16u, TextSection.getAlignment()));
895  DataSection.setAlignment(std::max(16u, DataSection.getAlignment()));
896  BSSSection.setAlignment(std::max(16u, BSSSection.getAlignment()));
897 
898  if (RoundSectionSizes) {
899  // Make sections sizes a multiple of the alignment. This is useful for
900  // verifying the output of IAS against the output of other assemblers but
901  // it's not necessary to produce a correct object and increases section
902  // size.
903  MCStreamer &OS = getStreamer();
904  for (MCSection &S : MCA) {
905  MCSectionELF &Section = static_cast<MCSectionELF &>(S);
906 
907  unsigned Alignment = Section.getAlignment();
908  if (Alignment) {
909  OS.SwitchSection(&Section);
910  if (Section.UseCodeAlign())
911  OS.EmitCodeAlignment(Alignment, Alignment);
912  else
913  OS.EmitValueToAlignment(Alignment, 0, 1, Alignment);
914  }
915  }
916  }
917 
918  const FeatureBitset &Features = STI.getFeatureBits();
919 
920  // Update e_header flags. See the FIXME and comment above in
921  // the constructor for a full rundown on this.
922  unsigned EFlags = MCA.getELFHeaderEFlags();
923 
924  // ABI
925  // N64 does not require any ABI bits.
926  if (getABI().IsO32())
927  EFlags |= ELF::EF_MIPS_ABI_O32;
928  else if (getABI().IsN32())
929  EFlags |= ELF::EF_MIPS_ABI2;
930 
931  if (Features[Mips::FeatureGP64Bit]) {
932  if (getABI().IsO32())
933  EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
934  } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
935  EFlags |= ELF::EF_MIPS_32BITMODE;
936 
937  // -mplt is not implemented but we should act as if it was
938  // given.
939  if (!Features[Mips::FeatureNoABICalls])
940  EFlags |= ELF::EF_MIPS_CPIC;
941 
942  if (Pic)
944 
945  MCA.setELFHeaderEFlags(EFlags);
946 
947  // Emit all the option records.
948  // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
949  // .reginfo.
950  MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
951  MEF.EmitMipsOptionRecords();
952 
954 }
955 
957  auto *Symbol = cast<MCSymbolELF>(S);
958  // If on rhs is micromips symbol then mark Symbol as microMips.
959  if (Value->getKind() != MCExpr::SymbolRef)
960  return;
961  const auto &RhsSym = cast<MCSymbolELF>(
962  static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
963 
964  if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
965  return;
966 
967  Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
968 }
969 
971  return static_cast<MCELFStreamer &>(Streamer);
972 }
973 
975  MicroMipsEnabled = true;
977 }
978 
980  MicroMipsEnabled = false;
982 }
983 
986  unsigned Flags = MCA.getELFHeaderEFlags();
987  Flags |= ELF::EF_MIPS_MICROMIPS;
988  MCA.setELFHeaderEFlags(Flags);
989 }
990 
993  unsigned Flags = MCA.getELFHeaderEFlags();
994  Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
995  MCA.setELFHeaderEFlags(Flags);
997 }
998 
1001  unsigned Flags = MCA.getELFHeaderEFlags();
1002  Flags |= ELF::EF_MIPS_NOREORDER;
1003  MCA.setELFHeaderEFlags(Flags);
1005 }
1006 
1009  MCContext &Context = MCA.getContext();
1010  MCStreamer &OS = getStreamer();
1011 
1012  MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
1013 
1014  MCSymbol *Sym = Context.getOrCreateSymbol(Name);
1015  const MCSymbolRefExpr *ExprRef =
1017 
1018  MCA.registerSection(*Sec);
1019  Sec->setAlignment(4);
1020 
1021  OS.PushSection();
1022 
1023  OS.SwitchSection(Sec);
1024 
1025  OS.EmitValueImpl(ExprRef, 4);
1026 
1027  OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
1028  OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4); // reg_offset
1029 
1030  OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
1031  OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4); // fpreg_offset
1032 
1033  OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
1034  OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4); // frame_reg
1035  OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4); // return_reg
1036 
1037  // The .end directive marks the end of a procedure. Invalidate
1038  // the information gathered up until this point.
1039  GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1040 
1041  OS.PopSection();
1042 
1043  // .end also implicitly sets the size.
1044  MCSymbol *CurPCSym = Context.createTempSymbol();
1045  OS.EmitLabel(CurPCSym);
1048  ExprRef, Context);
1049 
1050  // The ELFObjectWriter can determine the absolute size as it has access to
1051  // the layout information of the assembly file, so a size expression rather
1052  // than an absolute value is ok here.
1053  static_cast<MCSymbolELF *>(Sym)->setSize(Size);
1054 }
1055 
1057  GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1058 
1059  // .ent also acts like an implicit '.type symbol, STT_FUNC'
1060  static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
1061 }
1062 
1065  unsigned Flags = MCA.getELFHeaderEFlags();
1067  MCA.setELFHeaderEFlags(Flags);
1068 }
1069 
1072  unsigned Flags = MCA.getELFHeaderEFlags();
1073  Flags |= ELF::EF_MIPS_NAN2008;
1074  MCA.setELFHeaderEFlags(Flags);
1075 }
1076 
1079  unsigned Flags = MCA.getELFHeaderEFlags();
1080  Flags &= ~ELF::EF_MIPS_NAN2008;
1081  MCA.setELFHeaderEFlags(Flags);
1082 }
1083 
1086  unsigned Flags = MCA.getELFHeaderEFlags();
1087  // This option overrides other PIC options like -KPIC.
1088  Pic = false;
1089  Flags &= ~ELF::EF_MIPS_PIC;
1090  MCA.setELFHeaderEFlags(Flags);
1091 }
1092 
1095  unsigned Flags = MCA.getELFHeaderEFlags();
1096  Pic = true;
1097  // NOTE: We are following the GAS behaviour here which means the directive
1098  // 'pic2' also sets the CPIC bit in the ELF header. This is different from
1099  // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
1100  // EF_MIPS_CPIC to be mutually exclusive.
1102  MCA.setELFHeaderEFlags(Flags);
1103 }
1104 
1107  MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1109 }
1110 
1111 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
1112  unsigned ReturnReg_) {
1114  const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
1115 
1116  FrameInfoSet = true;
1117  FrameReg = RegInfo->getEncodingValue(StackReg);
1118  FrameOffset = StackSize;
1119  ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
1120 }
1121 
1122 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
1123  int CPUTopSavedRegOff) {
1124  GPRInfoSet = true;
1125  GPRBitMask = CPUBitmask;
1126  GPROffset = CPUTopSavedRegOff;
1127 }
1128 
1129 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
1130  int FPUTopSavedRegOff) {
1131  FPRInfoSet = true;
1132  FPRBitMask = FPUBitmask;
1133  FPROffset = FPUTopSavedRegOff;
1134 }
1135 
1137  // .cpload $reg
1138  // This directive expands to:
1139  // lui $gp, %hi(_gp_disp)
1140  // addui $gp, $gp, %lo(_gp_disp)
1141  // addu $gp, $gp, $reg
1142  // when support for position independent code is enabled.
1143  if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1144  return;
1145 
1146  // There's a GNU extension controlled by -mno-shared that allows
1147  // locally-binding symbols to be accessed using absolute addresses.
1148  // This is currently not supported. When supported -mno-shared makes
1149  // .cpload expand to:
1150  // lui $gp, %hi(__gnu_local_gp)
1151  // addiu $gp, $gp, %lo(__gnu_local_gp)
1152 
1153  StringRef SymName("_gp_disp");
1155  MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
1156  MCA.registerSymbol(*GP_Disp);
1157 
1158  MCInst TmpInst;
1159  TmpInst.setOpcode(Mips::LUi);
1161  const MCExpr *HiSym = MipsMCExpr::create(
1164  MCA.getContext()),
1165  MCA.getContext());
1166  TmpInst.addOperand(MCOperand::createExpr(HiSym));
1167  getStreamer().EmitInstruction(TmpInst, STI);
1168 
1169  TmpInst.clear();
1170 
1171  TmpInst.setOpcode(Mips::ADDiu);
1174  const MCExpr *LoSym = MipsMCExpr::create(
1177  MCA.getContext()),
1178  MCA.getContext());
1179  TmpInst.addOperand(MCOperand::createExpr(LoSym));
1180  getStreamer().EmitInstruction(TmpInst, STI);
1181 
1182  TmpInst.clear();
1183 
1184  TmpInst.setOpcode(Mips::ADDu);
1187  TmpInst.addOperand(MCOperand::createReg(RegNo));
1188  getStreamer().EmitInstruction(TmpInst, STI);
1189 
1191 }
1192 
1194  if (Pic)
1196 }
1197 
1199  int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
1200  const MCSubtargetInfo *STI) {
1201  MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1202  // .cprestore offset
1203  // When PIC mode is enabled and the O32 ABI is used, this directive expands
1204  // to:
1205  // sw $gp, offset($sp)
1206  // and adds a corresponding LW after every JAL.
1207 
1208  // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1209  // is used in non-PIC mode.
1210  if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1211  return true;
1212 
1213  // Store the $gp on the stack.
1214  emitStoreWithImmOffset(Mips::SW, GPReg, Mips::SP, Offset, GetATReg, IDLoc,
1215  STI);
1216  return true;
1217 }
1218 
1220  int RegOrOffset,
1221  const MCSymbol &Sym,
1222  bool IsReg) {
1223  // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1224  if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1225  return;
1226 
1228 
1230  MCInst Inst;
1231 
1232  // Either store the old $gp in a register or on the stack
1233  if (IsReg) {
1234  // move $save, $gpreg
1235  emitRRR(Mips::OR64, RegOrOffset, GPReg, Mips::ZERO, SMLoc(), &STI);
1236  } else {
1237  // sd $gpreg, offset($sp)
1238  emitRRI(Mips::SD, GPReg, Mips::SP, RegOrOffset, SMLoc(), &STI);
1239  }
1240 
1241  if (getABI().IsN32()) {
1242  MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
1243  const MipsMCExpr *HiExpr = MipsMCExpr::create(
1245  MCA.getContext());
1246  const MipsMCExpr *LoExpr = MipsMCExpr::create(
1248  MCA.getContext());
1249 
1250  // lui $gp, %hi(__gnu_local_gp)
1251  emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1252 
1253  // addiu $gp, $gp, %lo(__gnu_local_gp)
1254  emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1255  &STI);
1256 
1257  return;
1258  }
1259 
1260  const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
1262  MCA.getContext());
1263  const MipsMCExpr *LoExpr = MipsMCExpr::createGpOff(
1265  MCA.getContext());
1266 
1267  // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1268  emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1269 
1270  // addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1271  emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1272  &STI);
1273 
1274  // daddu $gp, $gp, $funcreg
1275  emitRRR(Mips::DADDu, GPReg, GPReg, RegNo, SMLoc(), &STI);
1276 }
1277 
1279  bool SaveLocationIsRegister) {
1280  // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1281  if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1282  return;
1283 
1284  MCInst Inst;
1285  // Either restore the old $gp from a register or on the stack
1286  if (SaveLocationIsRegister) {
1287  Inst.setOpcode(Mips::OR);
1289  Inst.addOperand(MCOperand::createReg(SaveLocation));
1290  Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1291  } else {
1292  Inst.setOpcode(Mips::LD);
1294  Inst.addOperand(MCOperand::createReg(Mips::SP));
1295  Inst.addOperand(MCOperand::createImm(SaveLocation));
1296  }
1297  getStreamer().EmitInstruction(Inst, STI);
1298 
1300 }
1301 
1304  MCContext &Context = MCA.getContext();
1305  MCStreamer &OS = getStreamer();
1306  MCSectionELF *Sec = Context.getELFSection(
1307  ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
1308  MCA.registerSection(*Sec);
1309  Sec->setAlignment(8);
1310  OS.SwitchSection(Sec);
1311 
1312  OS << ABIFlagsSection;
1313 }
void emitDirectiveEnd(StringRef Name) override
virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff)
void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc, const MCSubtargetInfo *STI)
void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:255
Instances of this class represent a uniqued identifier for a section in the current translation unit...
Definition: MCSection.h:38
virtual void emitDirectiveModuleGINV()
void emitDirectiveModuleSoftFloat() override
void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI)
void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg) override
void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVMContext & Context
bool UseCodeAlign() const override
Return true if a .align directive should use "optimized nops" to fill instead of 0s.
virtual void emitDirectiveOptionPic2()
void emitDirectiveCpLocal(unsigned RegNo) override
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:331
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void clear()
Definition: MCInst.h:188
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
void emitDirectiveSetNoMicroMips() override
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
void emitAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, bool Is64Bit, const MCSubtargetInfo *STI)
Target specific streamer interface.
Definition: MCStreamer.h:83
void emitDirectiveCpreturn(unsigned SaveLocation, bool SaveLocationIsRegister) override
void setAlignment(unsigned Value)
Definition: MCSection.h:121
An efficient, type-erasing, non-owning reference to a callable.
Definition: STLExtras.h:116
virtual void emitDirectiveSetNoReorder()
virtual void emitDirectiveModuleHardFloat()
void registerSymbol(const MCSymbol &Symbol, bool *Created=nullptr)
void PushSection()
Save the current and previous section on the section stack.
Definition: MCStreamer.h:365
virtual void emitDirectiveModuleNoGINV()
void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value) override
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:305
void emitGPRestore(int Offset, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit the $gp restore operation for .cprestore.
block Block Frequency true
virtual void EmitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Emit the expression Value into the output as a native integer of the given Size bytes.
MipsTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
bool emitDirectiveCpRestore(int Offset, function_ref< unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) override
Emit a .cprestore directive.
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:960
void emitDirectiveCpLoad(unsigned RegNo) override
const Triple & getTargetTriple() const
unsigned getAlignment() const
Definition: MCSection.h:120
virtual void emitDirectiveSetMips32R3()
const MipsABIInfo & getABI() const
MCContext & getContext() const
Definition: MCAssembler.h:284
virtual void emitDirectiveSetMicroMips()
virtual void emitDirectiveSetMips3()
void emitDirectiveCpLocal(unsigned RegNo) override
void emitFrame(unsigned StackReg, unsigned StackSize, unsigned ReturnReg) override
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
void emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg, unsigned BaseReg, int64_t Offset, unsigned TmpReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit a load instruction with an immediate offset.
const FeatureBitset & getFeatureBits() const
virtual void emitFrame(unsigned StackReg, unsigned StackSize, unsigned ReturnReg)
virtual void emitDirectiveSetMips0()
virtual void emitDirectiveSetSoftFloat()
virtual void emitDirectiveSetNoMacro()
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
bool registerSection(MCSection &Section)
virtual void emitDirectiveEnd(StringRef Name)
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:173
MCSection * getBSSSection() const
MCSection * getDataSection() const
virtual void emitDirectiveSetMips32R6()
void createPendingLabelRelocs()
Mark labels as microMIPS, if necessary for the subtarget.
void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override
virtual void emitDirectiveSetMips1()
virtual void emitDirectiveModuleOddSPReg()
Context object for machine code objects.
Definition: MCContext.h:64
void emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI)
virtual void emitDirectiveModuleSoftFloat()
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:554
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:296
MipsABIFlagsSection ABIFlagsSection
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
void emitLabel(MCSymbol *Symbol) override
virtual void emitDirectiveSetOddSPReg()
virtual void emitDirectiveSetMips64R2()
virtual void EmitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers...
Definition: MCStreamer.cpp:128
virtual void emitDirectiveSetNoOddSPReg()
void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg) override
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc, const MCSubtargetInfo *STI)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
Streaming machine code generation interface.
Definition: MCStreamer.h:188
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:223
virtual void emitDirectiveSetMips4()
Container class for subtarget features.
static const MipsMCExpr * createGpOff(MipsExprKind Kind, const MCExpr *Expr, MCContext &Ctx)
Definition: MipsMCExpr.cpp:32
static bool hasShortDelaySlot(MCInst &Inst)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
virtual void emitDirectiveSetNoMicroMips()
StringRef getFpABIString(FpABIKind Value)
virtual void emitDirectiveModuleVirt()
virtual void emitDirectiveSetMips16()
virtual void SwitchSection(MCSection *Section, const MCExpr *Subsection=nullptr)
Set the current section where code is being emitted to Section.
static MipsABIInfo O32()
Definition: MipsABIInfo.h:34
MCAssembler & getAssembler()
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:30
virtual void emitDirectiveSetMacro()
void emitDirectiveCpreturn(unsigned SaveLocation, bool SaveLocationIsRegister) override
void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc, const MCSubtargetInfo *STI)
virtual void emitDirectiveCpLoad(unsigned RegNo)
virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value=0, unsigned ValueSize=1, unsigned MaxBytesToEmit=0)
Emit some number of copies of Value until the byte alignment ByteAlignment is reached.
void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, const MCSubtargetInfo *STI)
const MCObjectFileInfo * getObjectFileInfo() const
Definition: MCContext.h:314
virtual void emitDirectiveSetArch(StringRef Arch)
virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff)
unsigned getELFHeaderEFlags() const
ELF e_header flags.
Definition: MCAssembler.h:254
virtual void emitDirectiveSetNoCRC()
virtual void emitDirectiveSetMips32R5()
virtual void emitDirectiveSetMips32R2()
void setLoc(SMLoc loc)
Definition: MCInst.h:176
void emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg, unsigned BaseReg, MCOperand &HiOperand, MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit a load instruction with an symbol offset.
virtual void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value)
void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, SMLoc IDLoc, const MCSubtargetInfo *STI)
virtual void emitDirectiveAbiCalls()
void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override
virtual void emitDirectiveSetMips64R6()
void emitDirectiveEnt(const MCSymbol &Symbol) override
MCStreamer & getStreamer()
Definition: MCStreamer.h:91
void emitDirectiveEnt(const MCSymbol &Symbol) override
virtual void emitDirectiveModuleNoVirt()
void setOpcode(unsigned Op)
Definition: MCInst.h:170
virtual void emitDirectiveCpLocal(unsigned RegNo)
virtual void emitDirectiveOptionPic0()
void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override
Emit the given Instruction into the current section.
void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount, SMLoc IDLoc, const MCSubtargetInfo *STI)
ExprKind getKind() const
Definition: MCExpr.h:72
void emitAssignment(MCSymbol *Symbol, const MCExpr *Value) override
virtual void emitDirectiveSetNoGINV()
virtual void EmitCodeAlignment(unsigned ByteAlignment, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
void emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc, const MCSubtargetInfo *STI)
MCStreamer & Streamer
Definition: MCStreamer.h:85
virtual void emitDirectiveSetNoMips16()
void emitDirectiveSetNoOddSPReg() override
void emitDirectiveSetAtWithArg(unsigned RegNo) override
void emitDirectiveEnd(StringRef Name) override
MipsTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
void EmitMipsOptionRecords()
Emits all the option records stored up until the point it&#39;s called.
virtual void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg)
static const MipsMCExpr * create(MipsExprKind Kind, const MCExpr *Expr, MCContext &Ctx)
Definition: MipsMCExpr.cpp:27
virtual void emitDirectiveSetNoVirt()
void emitStoreWithImmOffset(unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset, function_ref< unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit a store instruction with an offset.
virtual void emitDirectiveSetMips64R3()
virtual void emitDirectiveSetMips64R5()
void emitDirectiveCpLoad(unsigned RegNo) override
virtual void emitDirectiveEnt(const MCSymbol &Symbol)
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
virtual void emitDirectiveSetHardFloat()
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:127
virtual void emitDirectiveSetMips64()
virtual bool emitDirectiveCpRestore(int Offset, function_ref< unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
virtual void emitDirectiveSetMips5()
virtual void emitDirectiveSetMips2()
Generic base class for all target subtargets.
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:27
References to labels and assigned expressions.
Definition: MCExpr.h:40
uint32_t Size
Definition: Profile.cpp:46
void emitDirectiveSetNoMicroMips() override
void emitFrame(unsigned StackReg, unsigned StackSize, unsigned ReturnReg) override
void emitDirectiveSetArch(StringRef Arch) override
void emitDirectiveModuleOddSPReg() override
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:204
void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm, SMLoc IDLoc, const MCSubtargetInfo *STI)
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:107
void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2, SMLoc IDLoc, const MCSubtargetInfo *STI)
MCSection * getTextSection() const
bool PopSection()
Restore the current and previous section from the section stack.
Definition: MCStreamer.h:374
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
Definition: MCContext.h:406
virtual void emitDirectiveSetReorder()
static const char * getRegisterName(unsigned RegNo)
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:312
LLVM Value Representation.
Definition: Value.h:72
virtual void emitDirectiveCpreturn(unsigned SaveLocation, bool SaveLocationIsRegister)
llvm::Optional< MipsABIInfo > ABI
virtual void emitDirectiveNaNLegacy()
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:351
void emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
virtual void emitDirectiveSetMips32()
virtual void emitDirectiveSetNoMsa()
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
virtual void emitDirectiveModuleNoCRC()
bool isPositionIndependent() const
static void printHex32(unsigned Value, raw_ostream &OS)
Represents a location in source code.
Definition: SMLoc.h:23
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
bool emitDirectiveCpRestore(int Offset, function_ref< unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) override
virtual void emitDirectiveSetAtWithArg(unsigned RegNo)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
static MipsABIInfo N64()
Definition: MipsABIInfo.h:36
void emitDirectiveModuleHardFloat() override
void emitStoreWithSymOffset(unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand, MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit a store instruction with an symbol offset.