LLVM  10.0.0svn
MipsTargetStreamer.cpp
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1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Mips specific target streamer methods.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsTargetStreamer.h"
14 #include "MipsInstPrinter.h"
16 #include "MipsELFStreamer.h"
17 #include "MipsMCExpr.h"
18 #include "MipsMCTargetDesc.h"
19 #include "MipsTargetObjectFile.h"
20 #include "llvm/BinaryFormat/ELF.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCSectionELF.h"
24 #include "llvm/MC/MCSymbolELF.h"
28 
29 using namespace llvm;
30 
31 namespace {
32 static cl::opt<bool> RoundSectionSizes(
33  "mips-round-section-sizes", cl::init(false),
34  cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
35 } // end anonymous namespace
36 
37 static bool isMipsR6(const MCSubtargetInfo *STI) {
38  return STI->getFeatureBits()[Mips::FeatureMips32r6] ||
39  STI->getFeatureBits()[Mips::FeatureMips64r6];
40 }
41 
42 static bool isMicroMips(const MCSubtargetInfo *STI) {
43  return STI->getFeatureBits()[Mips::FeatureMicroMips];
44 }
45 
47  : MCTargetStreamer(S), GPReg(Mips::GP), ModuleDirectiveAllowed(true) {
49 }
72 }
82 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
83  unsigned ReturnReg) {}
84 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
85 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
86 }
89 }
110 }
113 }
119  // .cplocal $reg
120  // This directive forces to use the alternate register for context pointer.
121  // For example
122  // .cplocal $4
123  // jal foo
124  // expands to
125  // ld $25, %call16(foo)($4)
126  // jalr $25
127 
128  if (!getABI().IsN32() && !getABI().IsN64())
129  return;
130 
131  GPReg = RegNo;
132 
134 }
136  int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
137  const MCSubtargetInfo *STI) {
139  return true;
140 }
141 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
142  const MCSymbol &Sym, bool IsReg) {
143 }
144 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
145  bool SaveLocationIsRegister) {}
146 
148 
151  report_fatal_error("+nooddspreg is only valid for O32");
152 }
165 }
169 }
170 
171 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
172  const MCSubtargetInfo *STI) {
173  MCInst TmpInst;
174  TmpInst.setOpcode(Opcode);
175  TmpInst.addOperand(MCOperand::createReg(Reg0));
176  TmpInst.setLoc(IDLoc);
177  getStreamer().EmitInstruction(TmpInst, *STI);
178 }
179 
180 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
181  SMLoc IDLoc, const MCSubtargetInfo *STI) {
182  MCInst TmpInst;
183  TmpInst.setOpcode(Opcode);
184  TmpInst.addOperand(MCOperand::createReg(Reg0));
185  TmpInst.addOperand(Op1);
186  TmpInst.setLoc(IDLoc);
187  getStreamer().EmitInstruction(TmpInst, *STI);
188 }
189 
190 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
191  SMLoc IDLoc, const MCSubtargetInfo *STI) {
192  emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
193 }
194 
195 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
196  SMLoc IDLoc, const MCSubtargetInfo *STI) {
197  emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
198 }
199 
200 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
201  SMLoc IDLoc, const MCSubtargetInfo *STI) {
202  MCInst TmpInst;
203  TmpInst.setOpcode(Opcode);
204  TmpInst.addOperand(MCOperand::createImm(Imm1));
205  TmpInst.addOperand(MCOperand::createImm(Imm2));
206  TmpInst.setLoc(IDLoc);
207  getStreamer().EmitInstruction(TmpInst, *STI);
208 }
209 
210 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
211  MCOperand Op2, SMLoc IDLoc,
212  const MCSubtargetInfo *STI) {
213  MCInst TmpInst;
214  TmpInst.setOpcode(Opcode);
215  TmpInst.addOperand(MCOperand::createReg(Reg0));
216  TmpInst.addOperand(MCOperand::createReg(Reg1));
217  TmpInst.addOperand(Op2);
218  TmpInst.setLoc(IDLoc);
219  getStreamer().EmitInstruction(TmpInst, *STI);
220 }
221 
222 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
223  unsigned Reg2, SMLoc IDLoc,
224  const MCSubtargetInfo *STI) {
225  emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
226 }
227 
228 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
229  unsigned Reg2, MCOperand Op3, SMLoc IDLoc,
230  const MCSubtargetInfo *STI) {
231  MCInst TmpInst;
232  TmpInst.setOpcode(Opcode);
233  TmpInst.addOperand(MCOperand::createReg(Reg0));
234  TmpInst.addOperand(MCOperand::createReg(Reg1));
235  TmpInst.addOperand(MCOperand::createReg(Reg2));
236  TmpInst.addOperand(Op3);
237  TmpInst.setLoc(IDLoc);
238  getStreamer().EmitInstruction(TmpInst, *STI);
239 }
240 
241 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
242  int16_t Imm, SMLoc IDLoc,
243  const MCSubtargetInfo *STI) {
244  emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
245 }
246 
247 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
248  unsigned Reg1, int16_t Imm0, int16_t Imm1,
249  int16_t Imm2, SMLoc IDLoc,
250  const MCSubtargetInfo *STI) {
251  MCInst TmpInst;
252  TmpInst.setOpcode(Opcode);
253  TmpInst.addOperand(MCOperand::createReg(Reg0));
254  TmpInst.addOperand(MCOperand::createReg(Reg1));
255  TmpInst.addOperand(MCOperand::createImm(Imm0));
256  TmpInst.addOperand(MCOperand::createImm(Imm1));
257  TmpInst.addOperand(MCOperand::createImm(Imm2));
258  TmpInst.setLoc(IDLoc);
259  getStreamer().EmitInstruction(TmpInst, *STI);
260 }
261 
262 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
263  unsigned TrgReg, bool Is64Bit,
264  const MCSubtargetInfo *STI) {
265  emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
266  STI);
267 }
268 
269 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
270  int16_t ShiftAmount, SMLoc IDLoc,
271  const MCSubtargetInfo *STI) {
272  if (ShiftAmount >= 32) {
273  emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
274  return;
275  }
276 
277  emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
278 }
279 
281  const MCSubtargetInfo *STI) {
282  if (hasShortDelaySlot)
283  emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
284  else
285  emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
286 }
287 
289  if (isMicroMips(STI))
290  emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
291  else
292  emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
293 }
294 
295 /// Emit the $gp restore operation for .cprestore.
297  const MCSubtargetInfo *STI) {
298  emitLoadWithImmOffset(Mips::LW, GPReg, Mips::SP, Offset, GPReg, IDLoc, STI);
299 }
300 
301 /// Emit a store instruction with an immediate offset.
303  unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
304  function_ref<unsigned()> GetATReg, SMLoc IDLoc,
305  const MCSubtargetInfo *STI) {
306  if (isInt<16>(Offset)) {
307  emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
308  return;
309  }
310 
311  // sw $8, offset($8) => lui $at, %hi(offset)
312  // add $at, $at, $8
313  // sw $8, %lo(offset)($at)
314 
315  unsigned ATReg = GetATReg();
316  if (!ATReg)
317  return;
318 
319  unsigned LoOffset = Offset & 0x0000ffff;
320  unsigned HiOffset = (Offset & 0xffff0000) >> 16;
321 
322  // If msb of LoOffset is 1(negative number) we must increment HiOffset
323  // to account for the sign-extension of the low part.
324  if (LoOffset & 0x8000)
325  HiOffset++;
326 
327  // Generate the base address in ATReg.
328  emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
329  if (BaseReg != Mips::ZERO)
330  emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
331  // Emit the store with the adjusted base and offset.
332  emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
333 }
334 
335 /// Emit a store instruction with an symbol offset.
336 void MipsTargetStreamer::emitSCWithSymOffset(unsigned Opcode, unsigned SrcReg,
337  unsigned BaseReg,
338  MCOperand &HiOperand,
339  MCOperand &LoOperand,
340  unsigned ATReg, SMLoc IDLoc,
341  const MCSubtargetInfo *STI) {
342  // sc $8, sym => lui $at, %hi(sym)
343  // sc $8, %lo(sym)($at)
344 
345  // Generate the base address in ATReg.
346  emitRX(Mips::LUi, ATReg, HiOperand, IDLoc, STI);
347  if (!isMicroMips(STI) && isMipsR6(STI)) {
348  // For non-micromips r6 offset for 'sc' is not in the lower 16 bits so we
349  // put it in 'at'.
350  // sc $8, sym => lui $at, %hi(sym)
351  // addiu $at, $at, %lo(sym)
352  // sc $8, 0($at)
353  emitRRX(Mips::ADDiu, ATReg, ATReg, LoOperand, IDLoc, STI);
354  MCOperand Offset = MCOperand::createImm(0);
355  // Emit the store with the adjusted base and offset.
356  emitRRRX(Opcode, SrcReg, SrcReg, ATReg, Offset, IDLoc, STI);
357  } else {
358  if (BaseReg != Mips::ZERO)
359  emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
360  // Emit the store with the adjusted base and offset.
361  emitRRRX(Opcode, SrcReg, SrcReg, ATReg, LoOperand, IDLoc, STI);
362  }
363 }
364 
365 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
366 /// permitted to be the same register iff DstReg is distinct from BaseReg and
367 /// DstReg is a GPR. It is the callers responsibility to identify such cases
368 /// and pass the appropriate register in TmpReg.
369 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
370  unsigned BaseReg, int64_t Offset,
371  unsigned TmpReg, SMLoc IDLoc,
372  const MCSubtargetInfo *STI) {
373  if (isInt<16>(Offset)) {
374  emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
375  return;
376  }
377 
378  // 1) lw $8, offset($9) => lui $8, %hi(offset)
379  // add $8, $8, $9
380  // lw $8, %lo(offset)($9)
381  // 2) lw $8, offset($8) => lui $at, %hi(offset)
382  // add $at, $at, $8
383  // lw $8, %lo(offset)($at)
384 
385  unsigned LoOffset = Offset & 0x0000ffff;
386  unsigned HiOffset = (Offset & 0xffff0000) >> 16;
387 
388  // If msb of LoOffset is 1(negative number) we must increment HiOffset
389  // to account for the sign-extension of the low part.
390  if (LoOffset & 0x8000)
391  HiOffset++;
392 
393  // Generate the base address in TmpReg.
394  emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
395  if (BaseReg != Mips::ZERO)
396  emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
397  // Emit the load with the adjusted base and offset.
398  emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
399 }
400 
403  : MipsTargetStreamer(S), OS(OS) {}
404 
406  OS << "\t.set\tmicromips\n";
408 }
409 
411  OS << "\t.set\tnomicromips\n";
413 }
414 
416  OS << "\t.set\tmips16\n";
418 }
419 
421  OS << "\t.set\tnomips16\n";
423 }
424 
426  OS << "\t.set\treorder\n";
428 }
429 
431  OS << "\t.set\tnoreorder\n";
433 }
434 
436  OS << "\t.set\tmacro\n";
438 }
439 
441  OS << "\t.set\tnomacro\n";
443 }
444 
446  OS << "\t.set\tmsa\n";
448 }
449 
451  OS << "\t.set\tnomsa\n";
453 }
454 
456  OS << "\t.set\tmt\n";
458 }
459 
461  OS << "\t.set\tnomt\n";
463 }
464 
466  OS << "\t.set\tcrc\n";
468 }
469 
471  OS << "\t.set\tnocrc\n";
473 }
474 
476  OS << "\t.set\tvirt\n";
478 }
479 
481  OS << "\t.set\tnovirt\n";
483 }
484 
486  OS << "\t.set\tginv\n";
488 }
489 
491  OS << "\t.set\tnoginv\n";
493 }
494 
496  OS << "\t.set\tat\n";
498 }
499 
501  OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
503 }
504 
506  OS << "\t.set\tnoat\n";
508 }
509 
511  OS << "\t.end\t" << Name << '\n';
512 }
513 
515  OS << "\t.ent\t" << Symbol.getName() << '\n';
516 }
517 
518 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
519 
520 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
521 
523  OS << "\t.nan\tlegacy\n";
524 }
525 
527  OS << "\t.option\tpic0\n";
528 }
529 
531  OS << "\t.option\tpic2\n";
532 }
533 
536  OS << "\t.insn\n";
537 }
538 
539 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
540  unsigned ReturnReg) {
541  OS << "\t.frame\t$"
542  << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
543  << StackSize << ",$"
544  << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
545 }
546 
548  OS << "\t.set arch=" << Arch << "\n";
550 }
551 
553  OS << "\t.set\tmips0\n";
555 }
556 
558  OS << "\t.set\tmips1\n";
560 }
561 
563  OS << "\t.set\tmips2\n";
565 }
566 
568  OS << "\t.set\tmips3\n";
570 }
571 
573  OS << "\t.set\tmips4\n";
575 }
576 
578  OS << "\t.set\tmips5\n";
580 }
581 
583  OS << "\t.set\tmips32\n";
585 }
586 
588  OS << "\t.set\tmips32r2\n";
590 }
591 
593  OS << "\t.set\tmips32r3\n";
595 }
596 
598  OS << "\t.set\tmips32r5\n";
600 }
601 
603  OS << "\t.set\tmips32r6\n";
605 }
606 
608  OS << "\t.set\tmips64\n";
610 }
611 
613  OS << "\t.set\tmips64r2\n";
615 }
616 
618  OS << "\t.set\tmips64r3\n";
620 }
621 
623  OS << "\t.set\tmips64r5\n";
625 }
626 
628  OS << "\t.set\tmips64r6\n";
630 }
631 
633  OS << "\t.set\tdsp\n";
635 }
636 
638  OS << "\t.set\tdspr2\n";
640 }
641 
643  OS << "\t.set\tnodsp\n";
645 }
646 
648  OS << "\t.set\tpop\n";
650 }
651 
653  OS << "\t.set\tpush\n";
655 }
656 
658  OS << "\t.set\tsoftfloat\n";
660 }
661 
663  OS << "\t.set\thardfloat\n";
665 }
666 
667 // Print a 32 bit hex number with all numbers.
668 static void printHex32(unsigned Value, raw_ostream &OS) {
669  OS << "0x";
670  for (int i = 7; i >= 0; i--)
671  OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
672 }
673 
674 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
675  int CPUTopSavedRegOff) {
676  OS << "\t.mask \t";
677  printHex32(CPUBitmask, OS);
678  OS << ',' << CPUTopSavedRegOff << '\n';
679 }
680 
681 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
682  int FPUTopSavedRegOff) {
683  OS << "\t.fmask\t";
684  printHex32(FPUBitmask, OS);
685  OS << "," << FPUTopSavedRegOff << '\n';
686 }
687 
689  OS << "\t.cpload\t$"
690  << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
692 }
693 
695  OS << "\t.cplocal\t$"
696  << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
698 }
699 
701  int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
702  const MCSubtargetInfo *STI) {
703  MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
704  OS << "\t.cprestore\t" << Offset << "\n";
705  return true;
706 }
707 
709  int RegOrOffset,
710  const MCSymbol &Sym,
711  bool IsReg) {
712  OS << "\t.cpsetup\t$"
713  << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
714 
715  if (IsReg)
716  OS << "$"
718  else
719  OS << RegOrOffset;
720 
721  OS << ", ";
722 
723  OS << Sym.getName();
725 }
726 
728  bool SaveLocationIsRegister) {
729  OS << "\t.cpreturn";
731 }
732 
736  OS << "\t.module\tsoftfloat\n";
737  else
738  OS << "\t.module\tfp=" << ABIFlagsSection.getFpABIString(FpABI) << "\n";
739 }
740 
744 
745  OS << "\t.set\tfp=";
746  OS << ABIFlagsSection.getFpABIString(Value) << "\n";
747 }
748 
751 
752  OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
753 }
754 
757  OS << "\t.set\toddspreg\n";
758 }
759 
762  OS << "\t.set\tnooddspreg\n";
763 }
764 
766  OS << "\t.module\tsoftfloat\n";
767 }
768 
770  OS << "\t.module\thardfloat\n";
771 }
772 
774  OS << "\t.module\tmt\n";
775 }
776 
778  OS << "\t.module\tcrc\n";
779 }
780 
782  OS << "\t.module\tnocrc\n";
783 }
784 
786  OS << "\t.module\tvirt\n";
787 }
788 
790  OS << "\t.module\tnovirt\n";
791 }
792 
794  OS << "\t.module\tginv\n";
795 }
796 
798  OS << "\t.module\tnoginv\n";
799 }
800 
801 // This part is for ELF object output.
803  const MCSubtargetInfo &STI)
804  : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
806 
807  // It's possible that MCObjectFileInfo isn't fully initialized at this point
808  // due to an initialization order problem where LLVMTargetMachine creates the
809  // target streamer before TargetLoweringObjectFile calls
810  // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
811  // covers all cases so this statement covers most cases and direct object
812  // emission must call setPic() once MCObjectFileInfo has been initialized. The
813  // cases we don't handle here are covered by MipsAsmPrinter.
815 
816  const FeatureBitset &Features = STI.getFeatureBits();
817 
818  // Set the header flags that we can in the constructor.
819  // FIXME: This is a fairly terrible hack. We set the rest
820  // of these in the destructor. The problem here is two-fold:
821  //
822  // a: Some of the eflags can be set/reset by directives.
823  // b: There aren't any usage paths that initialize the ABI
824  // pointer until after we initialize either an assembler
825  // or the target machine.
826  // We can fix this by making the target streamer construct
827  // the ABI, but this is fraught with wide ranging dependency
828  // issues as well.
829  unsigned EFlags = MCA.getELFHeaderEFlags();
830 
831  // FIXME: Fix a dependency issue by instantiating the ABI object to some
832  // default based off the triple. The triple doesn't describe the target
833  // fully, but any external user of the API that uses the MCTargetStreamer
834  // would otherwise crash on assertion failure.
835 
836  ABI = MipsABIInfo(
837  STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
838  STI.getTargetTriple().getArch() == Triple::ArchType::mips
839  ? MipsABIInfo::O32()
840  : MipsABIInfo::N64());
841 
842  // Architecture
843  if (Features[Mips::FeatureMips64r6])
844  EFlags |= ELF::EF_MIPS_ARCH_64R6;
845  else if (Features[Mips::FeatureMips64r2] ||
846  Features[Mips::FeatureMips64r3] ||
847  Features[Mips::FeatureMips64r5])
848  EFlags |= ELF::EF_MIPS_ARCH_64R2;
849  else if (Features[Mips::FeatureMips64])
850  EFlags |= ELF::EF_MIPS_ARCH_64;
851  else if (Features[Mips::FeatureMips5])
852  EFlags |= ELF::EF_MIPS_ARCH_5;
853  else if (Features[Mips::FeatureMips4])
854  EFlags |= ELF::EF_MIPS_ARCH_4;
855  else if (Features[Mips::FeatureMips3])
856  EFlags |= ELF::EF_MIPS_ARCH_3;
857  else if (Features[Mips::FeatureMips32r6])
858  EFlags |= ELF::EF_MIPS_ARCH_32R6;
859  else if (Features[Mips::FeatureMips32r2] ||
860  Features[Mips::FeatureMips32r3] ||
861  Features[Mips::FeatureMips32r5])
862  EFlags |= ELF::EF_MIPS_ARCH_32R2;
863  else if (Features[Mips::FeatureMips32])
864  EFlags |= ELF::EF_MIPS_ARCH_32;
865  else if (Features[Mips::FeatureMips2])
866  EFlags |= ELF::EF_MIPS_ARCH_2;
867  else
868  EFlags |= ELF::EF_MIPS_ARCH_1;
869 
870  // Machine
871  if (Features[Mips::FeatureCnMips])
872  EFlags |= ELF::EF_MIPS_MACH_OCTEON;
873 
874  // Other options.
875  if (Features[Mips::FeatureNaN2008])
876  EFlags |= ELF::EF_MIPS_NAN2008;
877 
878  MCA.setELFHeaderEFlags(EFlags);
879 }
880 
882  auto *Symbol = cast<MCSymbolELF>(S);
884  uint8_t Type = Symbol->getType();
885  if (Type != ELF::STT_FUNC)
886  return;
887 
888  if (isMicroMipsEnabled())
889  Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
890 }
891 
894  const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
895 
896  // .bss, .text and .data are always at least 16-byte aligned.
897  MCSection &TextSection = *OFI.getTextSection();
898  MCA.registerSection(TextSection);
899  MCSection &DataSection = *OFI.getDataSection();
900  MCA.registerSection(DataSection);
901  MCSection &BSSSection = *OFI.getBSSSection();
902  MCA.registerSection(BSSSection);
903 
904  TextSection.setAlignment(
905  llvm::Align(std::max(16u, TextSection.getAlignment())));
906  DataSection.setAlignment(
907  llvm::Align(std::max(16u, DataSection.getAlignment())));
908  BSSSection.setAlignment(
909  llvm::Align(std::max(16u, BSSSection.getAlignment())));
910 
911  if (RoundSectionSizes) {
912  // Make sections sizes a multiple of the alignment. This is useful for
913  // verifying the output of IAS against the output of other assemblers but
914  // it's not necessary to produce a correct object and increases section
915  // size.
916  MCStreamer &OS = getStreamer();
917  for (MCSection &S : MCA) {
918  MCSectionELF &Section = static_cast<MCSectionELF &>(S);
919 
920  unsigned Alignment = Section.getAlignment();
921  if (Alignment) {
922  OS.SwitchSection(&Section);
923  if (Section.UseCodeAlign())
924  OS.EmitCodeAlignment(Alignment, Alignment);
925  else
926  OS.EmitValueToAlignment(Alignment, 0, 1, Alignment);
927  }
928  }
929  }
930 
931  const FeatureBitset &Features = STI.getFeatureBits();
932 
933  // Update e_header flags. See the FIXME and comment above in
934  // the constructor for a full rundown on this.
935  unsigned EFlags = MCA.getELFHeaderEFlags();
936 
937  // ABI
938  // N64 does not require any ABI bits.
939  if (getABI().IsO32())
940  EFlags |= ELF::EF_MIPS_ABI_O32;
941  else if (getABI().IsN32())
942  EFlags |= ELF::EF_MIPS_ABI2;
943 
944  if (Features[Mips::FeatureGP64Bit]) {
945  if (getABI().IsO32())
946  EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
947  } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
948  EFlags |= ELF::EF_MIPS_32BITMODE;
949 
950  // -mplt is not implemented but we should act as if it was
951  // given.
952  if (!Features[Mips::FeatureNoABICalls])
953  EFlags |= ELF::EF_MIPS_CPIC;
954 
955  if (Pic)
957 
958  MCA.setELFHeaderEFlags(EFlags);
959 
960  // Emit all the option records.
961  // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
962  // .reginfo.
963  MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
964  MEF.EmitMipsOptionRecords();
965 
967 }
968 
970  auto *Symbol = cast<MCSymbolELF>(S);
971  // If on rhs is micromips symbol then mark Symbol as microMips.
972  if (Value->getKind() != MCExpr::SymbolRef)
973  return;
974  const auto &RhsSym = cast<MCSymbolELF>(
975  static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
976 
977  if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
978  return;
979 
980  Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
981 }
982 
984  return static_cast<MCELFStreamer &>(Streamer);
985 }
986 
988  MicroMipsEnabled = true;
990 }
991 
993  MicroMipsEnabled = false;
995 }
996 
999  unsigned Flags = MCA.getELFHeaderEFlags();
1000  Flags |= ELF::EF_MIPS_MICROMIPS;
1001  MCA.setELFHeaderEFlags(Flags);
1002 }
1003 
1006  unsigned Flags = MCA.getELFHeaderEFlags();
1007  Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
1008  MCA.setELFHeaderEFlags(Flags);
1010 }
1011 
1014  unsigned Flags = MCA.getELFHeaderEFlags();
1015  Flags |= ELF::EF_MIPS_NOREORDER;
1016  MCA.setELFHeaderEFlags(Flags);
1018 }
1019 
1022  MCContext &Context = MCA.getContext();
1023  MCStreamer &OS = getStreamer();
1024 
1025  MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
1026 
1027  MCSymbol *Sym = Context.getOrCreateSymbol(Name);
1028  const MCSymbolRefExpr *ExprRef =
1030 
1031  MCA.registerSection(*Sec);
1032  Sec->setAlignment(llvm::Align(4));
1033 
1034  OS.PushSection();
1035 
1036  OS.SwitchSection(Sec);
1037 
1038  OS.EmitValueImpl(ExprRef, 4);
1039 
1040  OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
1041  OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4); // reg_offset
1042 
1043  OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
1044  OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4); // fpreg_offset
1045 
1046  OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
1047  OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4); // frame_reg
1048  OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4); // return_reg
1049 
1050  // The .end directive marks the end of a procedure. Invalidate
1051  // the information gathered up until this point.
1052  GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1053 
1054  OS.PopSection();
1055 
1056  // .end also implicitly sets the size.
1057  MCSymbol *CurPCSym = Context.createTempSymbol();
1058  OS.EmitLabel(CurPCSym);
1061  ExprRef, Context);
1062 
1063  // The ELFObjectWriter can determine the absolute size as it has access to
1064  // the layout information of the assembly file, so a size expression rather
1065  // than an absolute value is ok here.
1066  static_cast<MCSymbolELF *>(Sym)->setSize(Size);
1067 }
1068 
1070  GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1071 
1072  // .ent also acts like an implicit '.type symbol, STT_FUNC'
1073  static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
1074 }
1075 
1078  unsigned Flags = MCA.getELFHeaderEFlags();
1080  MCA.setELFHeaderEFlags(Flags);
1081 }
1082 
1085  unsigned Flags = MCA.getELFHeaderEFlags();
1086  Flags |= ELF::EF_MIPS_NAN2008;
1087  MCA.setELFHeaderEFlags(Flags);
1088 }
1089 
1092  unsigned Flags = MCA.getELFHeaderEFlags();
1093  Flags &= ~ELF::EF_MIPS_NAN2008;
1094  MCA.setELFHeaderEFlags(Flags);
1095 }
1096 
1099  unsigned Flags = MCA.getELFHeaderEFlags();
1100  // This option overrides other PIC options like -KPIC.
1101  Pic = false;
1102  Flags &= ~ELF::EF_MIPS_PIC;
1103  MCA.setELFHeaderEFlags(Flags);
1104 }
1105 
1108  unsigned Flags = MCA.getELFHeaderEFlags();
1109  Pic = true;
1110  // NOTE: We are following the GAS behaviour here which means the directive
1111  // 'pic2' also sets the CPIC bit in the ELF header. This is different from
1112  // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
1113  // EF_MIPS_CPIC to be mutually exclusive.
1115  MCA.setELFHeaderEFlags(Flags);
1116 }
1117 
1120  MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1122 }
1123 
1124 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
1125  unsigned ReturnReg_) {
1127  const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
1128 
1129  FrameInfoSet = true;
1130  FrameReg = RegInfo->getEncodingValue(StackReg);
1131  FrameOffset = StackSize;
1132  ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
1133 }
1134 
1135 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
1136  int CPUTopSavedRegOff) {
1137  GPRInfoSet = true;
1138  GPRBitMask = CPUBitmask;
1139  GPROffset = CPUTopSavedRegOff;
1140 }
1141 
1142 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
1143  int FPUTopSavedRegOff) {
1144  FPRInfoSet = true;
1145  FPRBitMask = FPUBitmask;
1146  FPROffset = FPUTopSavedRegOff;
1147 }
1148 
1150  // .cpload $reg
1151  // This directive expands to:
1152  // lui $gp, %hi(_gp_disp)
1153  // addui $gp, $gp, %lo(_gp_disp)
1154  // addu $gp, $gp, $reg
1155  // when support for position independent code is enabled.
1156  if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1157  return;
1158 
1159  // There's a GNU extension controlled by -mno-shared that allows
1160  // locally-binding symbols to be accessed using absolute addresses.
1161  // This is currently not supported. When supported -mno-shared makes
1162  // .cpload expand to:
1163  // lui $gp, %hi(__gnu_local_gp)
1164  // addiu $gp, $gp, %lo(__gnu_local_gp)
1165 
1166  StringRef SymName("_gp_disp");
1168  MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
1169  MCA.registerSymbol(*GP_Disp);
1170 
1171  MCInst TmpInst;
1172  TmpInst.setOpcode(Mips::LUi);
1174  const MCExpr *HiSym = MipsMCExpr::create(
1177  MCA.getContext()),
1178  MCA.getContext());
1179  TmpInst.addOperand(MCOperand::createExpr(HiSym));
1180  getStreamer().EmitInstruction(TmpInst, STI);
1181 
1182  TmpInst.clear();
1183 
1184  TmpInst.setOpcode(Mips::ADDiu);
1187  const MCExpr *LoSym = MipsMCExpr::create(
1190  MCA.getContext()),
1191  MCA.getContext());
1192  TmpInst.addOperand(MCOperand::createExpr(LoSym));
1193  getStreamer().EmitInstruction(TmpInst, STI);
1194 
1195  TmpInst.clear();
1196 
1197  TmpInst.setOpcode(Mips::ADDu);
1200  TmpInst.addOperand(MCOperand::createReg(RegNo));
1201  getStreamer().EmitInstruction(TmpInst, STI);
1202 
1204 }
1205 
1207  if (Pic)
1209 }
1210 
1212  int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
1213  const MCSubtargetInfo *STI) {
1214  MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1215  // .cprestore offset
1216  // When PIC mode is enabled and the O32 ABI is used, this directive expands
1217  // to:
1218  // sw $gp, offset($sp)
1219  // and adds a corresponding LW after every JAL.
1220 
1221  // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1222  // is used in non-PIC mode.
1223  if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1224  return true;
1225 
1226  // Store the $gp on the stack.
1227  emitStoreWithImmOffset(Mips::SW, GPReg, Mips::SP, Offset, GetATReg, IDLoc,
1228  STI);
1229  return true;
1230 }
1231 
1233  int RegOrOffset,
1234  const MCSymbol &Sym,
1235  bool IsReg) {
1236  // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1237  if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1238  return;
1239 
1241 
1243  MCInst Inst;
1244 
1245  // Either store the old $gp in a register or on the stack
1246  if (IsReg) {
1247  // move $save, $gpreg
1248  emitRRR(Mips::OR64, RegOrOffset, GPReg, Mips::ZERO, SMLoc(), &STI);
1249  } else {
1250  // sd $gpreg, offset($sp)
1251  emitRRI(Mips::SD, GPReg, Mips::SP, RegOrOffset, SMLoc(), &STI);
1252  }
1253 
1254  if (getABI().IsN32()) {
1255  MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
1256  const MipsMCExpr *HiExpr = MipsMCExpr::create(
1258  MCA.getContext());
1259  const MipsMCExpr *LoExpr = MipsMCExpr::create(
1261  MCA.getContext());
1262 
1263  // lui $gp, %hi(__gnu_local_gp)
1264  emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1265 
1266  // addiu $gp, $gp, %lo(__gnu_local_gp)
1267  emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1268  &STI);
1269 
1270  return;
1271  }
1272 
1273  const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
1275  MCA.getContext());
1276  const MipsMCExpr *LoExpr = MipsMCExpr::createGpOff(
1278  MCA.getContext());
1279 
1280  // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1281  emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1282 
1283  // addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1284  emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1285  &STI);
1286 
1287  // daddu $gp, $gp, $funcreg
1288  emitRRR(Mips::DADDu, GPReg, GPReg, RegNo, SMLoc(), &STI);
1289 }
1290 
1292  bool SaveLocationIsRegister) {
1293  // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1294  if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1295  return;
1296 
1297  MCInst Inst;
1298  // Either restore the old $gp from a register or on the stack
1299  if (SaveLocationIsRegister) {
1300  Inst.setOpcode(Mips::OR);
1302  Inst.addOperand(MCOperand::createReg(SaveLocation));
1303  Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1304  } else {
1305  Inst.setOpcode(Mips::LD);
1307  Inst.addOperand(MCOperand::createReg(Mips::SP));
1308  Inst.addOperand(MCOperand::createImm(SaveLocation));
1309  }
1310  getStreamer().EmitInstruction(Inst, STI);
1311 
1313 }
1314 
1317  MCContext &Context = MCA.getContext();
1318  MCStreamer &OS = getStreamer();
1319  MCSectionELF *Sec = Context.getELFSection(
1320  ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
1321  MCA.registerSection(*Sec);
1322  Sec->setAlignment(llvm::Align(8));
1323  OS.SwitchSection(Sec);
1324 
1325  OS << ABIFlagsSection;
1326 }
void emitDirectiveEnd(StringRef Name) override
virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff)
void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc, const MCSubtargetInfo *STI)
void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:255
Instances of this class represent a uniqued identifier for a section in the current translation unit...
Definition: MCSection.h:39
virtual void emitDirectiveModuleGINV()
void emitDirectiveModuleSoftFloat() override
void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI)
void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg) override
void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVMContext & Context
bool UseCodeAlign() const override
Return true if a .align directive should use "optimized nops" to fill instead of 0s.
virtual void emitDirectiveOptionPic2()
void emitDirectiveCpLocal(unsigned RegNo) override
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:327
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void clear()
Definition: MCInst.h:188
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
void emitDirectiveSetNoMicroMips() override
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
void emitAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, bool Is64Bit, const MCSubtargetInfo *STI)
Target specific streamer interface.
Definition: MCStreamer.h:85
void emitDirectiveCpreturn(unsigned SaveLocation, bool SaveLocationIsRegister) override
An efficient, type-erasing, non-owning reference to a callable.
Definition: STLExtras.h:104
virtual void emitDirectiveSetNoReorder()
virtual void emitDirectiveModuleHardFloat()
void registerSymbol(const MCSymbol &Symbol, bool *Created=nullptr)
void PushSection()
Save the current and previous section on the section stack.
Definition: MCStreamer.h:367
virtual void emitDirectiveModuleNoGINV()
void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value) override
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:305
void emitGPRestore(int Offset, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit the $gp restore operation for .cprestore.
block Block Frequency true
virtual void EmitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Emit the expression Value into the output as a native integer of the given Size bytes.
MipsTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
bool emitDirectiveCpRestore(int Offset, function_ref< unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) override
Emit a .cprestore directive.
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
void emitDirectiveCpLoad(unsigned RegNo) override
const Triple & getTargetTriple() const
unsigned getAlignment() const
Definition: MCSection.h:121
virtual void emitDirectiveSetMips32R3()
const MipsABIInfo & getABI() const
MCContext & getContext() const
Definition: MCAssembler.h:284
virtual void emitDirectiveSetMicroMips()
virtual void emitDirectiveSetMips3()
void emitDirectiveCpLocal(unsigned RegNo) override
void emitFrame(unsigned StackReg, unsigned StackSize, unsigned ReturnReg) override
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
void emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg, unsigned BaseReg, int64_t Offset, unsigned TmpReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit a load instruction with an immediate offset.
const FeatureBitset & getFeatureBits() const
virtual void emitFrame(unsigned StackReg, unsigned StackSize, unsigned ReturnReg)
virtual void emitDirectiveSetMips0()
virtual void emitDirectiveSetSoftFloat()
virtual void emitDirectiveSetNoMacro()
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
bool registerSection(MCSection &Section)
virtual void emitDirectiveEnd(StringRef Name)
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:169
MCSection * getBSSSection() const
MCSection * getDataSection() const
virtual void emitDirectiveSetMips32R6()
void createPendingLabelRelocs()
Mark labels as microMIPS, if necessary for the subtarget.
void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override
virtual void emitDirectiveSetMips1()
virtual void emitDirectiveModuleOddSPReg()
Context object for machine code objects.
Definition: MCContext.h:65
void emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI)
virtual void emitDirectiveModuleSoftFloat()
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:550
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:296
void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, MCOperand Op3, SMLoc IDLoc, const MCSubtargetInfo *STI)
MipsABIFlagsSection ABIFlagsSection
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
void emitLabel(MCSymbol *Symbol) override
virtual void emitDirectiveSetOddSPReg()
virtual void emitDirectiveSetMips64R2()
virtual void EmitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers...
Definition: MCStreamer.cpp:130
virtual void emitDirectiveSetNoOddSPReg()
void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg) override
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc, const MCSubtargetInfo *STI)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
Streaming machine code generation interface.
Definition: MCStreamer.h:190
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:225
virtual void emitDirectiveSetMips4()
Container class for subtarget features.
static const MipsMCExpr * createGpOff(MipsExprKind Kind, const MCExpr *Expr, MCContext &Ctx)
Definition: MipsMCExpr.cpp:32
static bool hasShortDelaySlot(MCInst &Inst)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
virtual void emitDirectiveSetNoMicroMips()
StringRef getFpABIString(FpABIKind Value)
virtual void emitDirectiveModuleVirt()
virtual void emitDirectiveSetMips16()
virtual void SwitchSection(MCSection *Section, const MCExpr *Subsection=nullptr)
Set the current section where code is being emitted to Section.
static MipsABIInfo O32()
Definition: MipsABIInfo.h:34
MCAssembler & getAssembler()
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:30
virtual void emitDirectiveSetMacro()
void emitDirectiveCpreturn(unsigned SaveLocation, bool SaveLocationIsRegister) override
void setAlignment(llvm::Align Value)
Definition: MCSection.h:122
void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc, const MCSubtargetInfo *STI)
virtual void emitDirectiveCpLoad(unsigned RegNo)
virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value=0, unsigned ValueSize=1, unsigned MaxBytesToEmit=0)
Emit some number of copies of Value until the byte alignment ByteAlignment is reached.
void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, const MCSubtargetInfo *STI)
const MCObjectFileInfo * getObjectFileInfo() const
Definition: MCContext.h:322
virtual void emitDirectiveSetArch(StringRef Arch)
virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff)
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
unsigned getELFHeaderEFlags() const
ELF e_header flags.
Definition: MCAssembler.h:254
virtual void emitDirectiveSetNoCRC()
virtual void emitDirectiveSetMips32R5()
virtual void emitDirectiveSetMips32R2()
void setLoc(SMLoc loc)
Definition: MCInst.h:176
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
virtual void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value)
void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, SMLoc IDLoc, const MCSubtargetInfo *STI)
virtual void emitDirectiveAbiCalls()
void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override
virtual void emitDirectiveSetMips64R6()
void emitDirectiveEnt(const MCSymbol &Symbol) override
MCStreamer & getStreamer()
Definition: MCStreamer.h:93
void emitDirectiveEnt(const MCSymbol &Symbol) override
virtual void emitDirectiveModuleNoVirt()
void setOpcode(unsigned Op)
Definition: MCInst.h:170
virtual void emitDirectiveCpLocal(unsigned RegNo)
virtual void emitDirectiveOptionPic0()
void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override
Emit the given Instruction into the current section.
void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount, SMLoc IDLoc, const MCSubtargetInfo *STI)
ExprKind getKind() const
Definition: MCExpr.h:68
void emitAssignment(MCSymbol *Symbol, const MCExpr *Value) override
virtual void emitDirectiveSetNoGINV()
virtual void EmitCodeAlignment(unsigned ByteAlignment, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
void emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc, const MCSubtargetInfo *STI)
MCStreamer & Streamer
Definition: MCStreamer.h:87
virtual void emitDirectiveSetNoMips16()
void emitDirectiveSetNoOddSPReg() override
void emitDirectiveSetAtWithArg(unsigned RegNo) override
void emitDirectiveEnd(StringRef Name) override
static bool isMipsR6(const MCSubtargetInfo *STI)
MipsTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
void EmitMipsOptionRecords()
Emits all the option records stored up until the point it&#39;s called.
virtual void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg)
static const MipsMCExpr * create(MipsExprKind Kind, const MCExpr *Expr, MCContext &Ctx)
Definition: MipsMCExpr.cpp:27
virtual void emitDirectiveSetNoVirt()
void emitStoreWithImmOffset(unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset, function_ref< unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit a store instruction with an offset.
virtual void emitDirectiveSetMips64R3()
virtual void emitDirectiveSetMips64R5()
void emitDirectiveCpLoad(unsigned RegNo) override
virtual void emitDirectiveEnt(const MCSymbol &Symbol)
virtual void emitDirectiveSetHardFloat()
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:129
virtual bool emitDirectiveCpRestore(int Offset, function_ref< unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
virtual void emitDirectiveSetMips5()
virtual void emitDirectiveSetMips2()
Generic base class for all target subtargets.
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:27
References to labels and assigned expressions.
Definition: MCExpr.h:40
uint32_t Size
Definition: Profile.cpp:46
void emitDirectiveSetNoMicroMips() override
void emitFrame(unsigned StackReg, unsigned StackSize, unsigned ReturnReg) override
void emitDirectiveSetArch(StringRef Arch) override
void emitDirectiveModuleOddSPReg() override
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:204
void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm, SMLoc IDLoc, const MCSubtargetInfo *STI)
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:107
void emitSCWithSymOffset(unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand, MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit a store instruction with an symbol offset.
void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2, SMLoc IDLoc, const MCSubtargetInfo *STI)
MCSection * getTextSection() const
bool PopSection()
Restore the current and previous section from the section stack.
Definition: MCStreamer.h:376
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
Definition: MCContext.h:424
virtual void emitDirectiveSetReorder()
static const char * getRegisterName(unsigned RegNo)
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:320
LLVM Value Representation.
Definition: Value.h:73
virtual void emitDirectiveCpreturn(unsigned SaveLocation, bool SaveLocationIsRegister)
llvm::Optional< MipsABIInfo > ABI
virtual void emitDirectiveNaNLegacy()
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:399
void emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
virtual void emitDirectiveSetMips32()
virtual void emitDirectiveSetNoMsa()
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
virtual void emitDirectiveModuleNoCRC()
bool isPositionIndependent() const
static void printHex32(unsigned Value, raw_ostream &OS)
Represents a location in source code.
Definition: SMLoc.h:23
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
bool emitDirectiveCpRestore(int Offset, function_ref< unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) override
virtual void emitDirectiveSetAtWithArg(unsigned RegNo)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
static MipsABIInfo N64()
Definition: MipsABIInfo.h:36
void emitDirectiveModuleHardFloat() override
static bool isMicroMips(const MCSubtargetInfo *STI)