LLVM  14.0.0git
TargetSubtargetInfo.cpp
Go to the documentation of this file.
1 //===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file describes the general parts of a Subtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 
15 using namespace llvm;
16 
18  const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
20  const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
21  const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC,
22  const unsigned *FP)
23  : MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {}
24 
26 
28  return true;
29 }
30 
32  return false;
33 }
34 
36  return false;
37 }
38 
40  return enableMachineScheduler();
41 }
42 
44  CodeGenOpt::Level OptLevel) const {
45  return true;
46 }
47 
49  return false;
50 }
51 
54 }
55 
58 }
59 
61  return false;
62 }
63 
CmpMode::FP
@ FP
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::TargetSubtargetInfo::enablePostRAScheduler
virtual bool enablePostRAScheduler() const
True if the subtarget should run a scheduler after register allocation.
Definition: TargetSubtargetInfo.cpp:52
llvm::MCSubtargetInfo::getSchedModel
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
Definition: MCSubtargetInfo.h:162
llvm::TargetSubtargetInfo::enableRALocalReassignment
virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const
True if the subtarget should run the local reassignment heuristic of the register allocator.
Definition: TargetSubtargetInfo.cpp:43
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::X86II::PD
@ PD
Definition: X86BaseInfo.h:782
llvm::TargetSubtargetInfo::mirFileLoaded
virtual void mirFileLoaded(MachineFunction &MF) const
This is called after a .mir file was loaded.
Definition: TargetSubtargetInfo.cpp:64
llvm::MCWriteProcResEntry
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:63
llvm::MCSchedModel::PostRAScheduler
bool PostRAScheduler
Definition: MCSchedule.h:300
llvm::TargetSubtargetInfo::~TargetSubtargetInfo
~TargetSubtargetInfo() override
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::TargetSubtargetInfo::enableIndirectBrExpand
virtual bool enableIndirectBrExpand() const
True if the subtarget should run the indirectbr expansion pass.
Definition: TargetSubtargetInfo.cpp:31
llvm::TargetSubtargetInfo::enablePostRAMachineScheduler
virtual bool enablePostRAMachineScheduler() const
True if the subtarget should run a machine scheduler after register allocation.
Definition: TargetSubtargetInfo.cpp:56
llvm::MCWriteLatencyEntry
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:77
llvm::TargetSubtargetInfo::enableAdvancedRASplitCost
virtual bool enableAdvancedRASplitCost() const
True if the subtarget should consider the cost of local intervals created by a split candidate when c...
Definition: TargetSubtargetInfo.cpp:48
llvm::SystemZISD::OC
@ OC
Definition: SystemZISelLowering.h:122
RA
SI optimize exec mask operations pre RA
Definition: SIOptimizeExecMaskingPreRA.cpp:71
llvm::TargetSubtargetInfo::useAA
virtual bool useAA() const
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
Definition: TargetSubtargetInfo.cpp:60
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
TargetSubtargetInfo.h
llvm::TargetSubtargetInfo::enableJoinGlobalCopies
virtual bool enableJoinGlobalCopies() const
True if the subtarget should enable joining global copies.
Definition: TargetSubtargetInfo.cpp:39
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::InstrStage
These values represent a non-pipelined step in the execution of an instruction.
Definition: MCInstrItineraries.h:58
llvm::MCReadAdvanceEntry
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:94
llvm::TargetSubtargetInfo::TargetSubtargetInfo
TargetSubtargetInfo()=delete
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::TargetSubtargetInfo::enableMachineScheduler
virtual bool enableMachineScheduler() const
True if the subtarget should run MachineScheduler after aggressive coalescing.
Definition: TargetSubtargetInfo.cpp:35
llvm::TargetSubtargetInfo::enableAtomicExpand
virtual bool enableAtomicExpand() const
True if the subtarget should run the atomic expansion pass.
Definition: TargetSubtargetInfo.cpp:27