LLVM 20.0.0git
TargetSubtargetInfo.cpp
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1//===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file describes the general parts of a Subtarget.
10//
11//===----------------------------------------------------------------------===//
12
14
15using namespace llvm;
16
18 const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
20 const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
21 const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC,
22 const unsigned *FP)
23 : MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {}
24
26
28 return true;
29}
30
32 return false;
33}
34
36 return false;
37}
38
41}
42
44 CodeGenOptLevel OptLevel) const {
45 return true;
46}
47
50}
51
54}
55
57 return false;
58}
59
SI optimize exec mask operations pre RA
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Generic base class for all target subtargets.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
virtual bool enableJoinGlobalCopies() const
True if the subtarget should enable joining global copies.
virtual bool enableIndirectBrExpand() const
True if the subtarget should run the indirectbr expansion pass.
virtual bool enableRALocalReassignment(CodeGenOptLevel OptLevel) const
True if the subtarget should run the local reassignment heuristic of the register allocator.
virtual bool enableMachineScheduler() const
True if the subtarget should run MachineScheduler after aggressive coalescing.
virtual bool useAA() const
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
virtual void mirFileLoaded(MachineFunction &MF) const
This is called after a .mir file was loaded.
virtual bool enablePostRAMachineScheduler() const
True if the subtarget should run a machine scheduler after register allocation.
virtual bool enableAtomicExpand() const
True if the subtarget should run the atomic expansion pass.
virtual bool enablePostRAScheduler() const
True if the subtarget should run a scheduler after register allocation.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
These values represent a non-pipelined step in the execution of an instruction.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:103
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:86
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:63