LLVM  16.0.0git
X86CallLowering.cpp
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1 //===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86CallLowering.h"
16 #include "X86CallingConv.h"
17 #include "X86ISelLowering.h"
18 #include "X86InstrInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/CodeGen/Analysis.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/Value.h"
43 #include "llvm/MC/MCRegisterInfo.h"
46 #include <cassert>
47 #include <cstdint>
48 
49 using namespace llvm;
50 
52  : CallLowering(&TLI) {}
53 
54 namespace {
55 
56 struct X86OutgoingValueAssigner : public CallLowering::OutgoingValueAssigner {
57 private:
58  uint64_t StackSize = 0;
59  unsigned NumXMMRegs = 0;
60 
61 public:
62  uint64_t getStackSize() { return StackSize; }
63  unsigned getNumXmmRegs() { return NumXMMRegs; }
64 
65  X86OutgoingValueAssigner(CCAssignFn *AssignFn_)
66  : CallLowering::OutgoingValueAssigner(AssignFn_) {}
67 
68  bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
69  CCValAssign::LocInfo LocInfo,
71  CCState &State) override {
72  bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
73  StackSize = State.getNextStackOffset();
74 
75  static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
76  X86::XMM3, X86::XMM4, X86::XMM5,
77  X86::XMM6, X86::XMM7};
78  if (!Info.IsFixed)
79  NumXMMRegs = State.getFirstUnallocated(XMMArgRegs);
80 
81  return Res;
82  }
83 };
84 
85 struct X86OutgoingValueHandler : public CallLowering::OutgoingValueHandler {
86  X86OutgoingValueHandler(MachineIRBuilder &MIRBuilder,
88  : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB),
89  DL(MIRBuilder.getMF().getDataLayout()),
90  STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}
91 
92  Register getStackAddress(uint64_t Size, int64_t Offset,
93  MachinePointerInfo &MPO,
94  ISD::ArgFlagsTy Flags) override {
95  LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
96  LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
97  auto SPReg =
98  MIRBuilder.buildCopy(p0, STI.getRegisterInfo()->getStackRegister());
99 
100  auto OffsetReg = MIRBuilder.buildConstant(SType, Offset);
101 
102  auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
103 
104  MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
105  return AddrReg.getReg(0);
106  }
107 
108  void assignValueToReg(Register ValVReg, Register PhysReg,
109  CCValAssign VA) override {
110  MIB.addUse(PhysReg, RegState::Implicit);
111  Register ExtReg = extendRegister(ValVReg, VA);
112  MIRBuilder.buildCopy(PhysReg, ExtReg);
113  }
114 
115  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
116  MachinePointerInfo &MPO, CCValAssign &VA) override {
117  MachineFunction &MF = MIRBuilder.getMF();
118  Register ExtReg = extendRegister(ValVReg, VA);
119 
120  auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, MemTy,
121  inferAlignFromPtrInfo(MF, MPO));
122  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
123  }
124 
125 protected:
126  MachineInstrBuilder &MIB;
127  const DataLayout &DL;
128  const X86Subtarget &STI;
129 };
130 
131 } // end anonymous namespace
132 
134  MachineFunction &MF, CallingConv::ID CallConv,
135  SmallVectorImpl<CallLowering::BaseArgInfo> &Outs, bool IsVarArg) const {
138  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
139  return checkReturn(CCInfo, Outs, RetCC_X86);
140 }
141 
143  const Value *Val, ArrayRef<Register> VRegs,
144  FunctionLoweringInfo &FLI) const {
145  assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
146  "Return value without a vreg");
147  MachineFunction &MF = MIRBuilder.getMF();
148  auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
149  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
150  bool Is64Bit = STI.is64Bit();
151 
152  if (!FLI.CanLowerReturn) {
153  insertSRetStores(MIRBuilder, Val->getType(), VRegs, FLI.DemoteRegister);
154  MIRBuilder.buildCopy(Is64Bit ? X86::RAX : X86::EAX, FLI.DemoteRegister);
155  } else if (!VRegs.empty()) {
156  const Function &F = MF.getFunction();
158  const DataLayout &DL = MF.getDataLayout();
159 
160  ArgInfo OrigRetInfo(VRegs, Val->getType(), 0);
161  setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
162 
163  SmallVector<ArgInfo, 4> SplitRetInfos;
164  splitToValueTypes(OrigRetInfo, SplitRetInfos, DL, F.getCallingConv());
165 
166  X86OutgoingValueAssigner Assigner(RetCC_X86);
167  X86OutgoingValueHandler Handler(MIRBuilder, MRI, MIB);
168  if (!determineAndHandleAssignments(Handler, Assigner, SplitRetInfos,
169  MIRBuilder, F.getCallingConv(),
170  F.isVarArg()))
171  return false;
172  }
173 
174  MIRBuilder.insertInstr(MIB);
175  return true;
176 }
177 
178 namespace {
179 
180 struct X86IncomingValueHandler : public CallLowering::IncomingValueHandler {
181  X86IncomingValueHandler(MachineIRBuilder &MIRBuilder,
183  : IncomingValueHandler(MIRBuilder, MRI),
184  DL(MIRBuilder.getMF().getDataLayout()) {}
185 
186  Register getStackAddress(uint64_t Size, int64_t Offset,
187  MachinePointerInfo &MPO,
188  ISD::ArgFlagsTy Flags) override {
189  auto &MFI = MIRBuilder.getMF().getFrameInfo();
190 
191  // Byval is assumed to be writable memory, but other stack passed arguments
192  // are not.
193  const bool IsImmutable = !Flags.isByVal();
194 
195  int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
196  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
197 
198  return MIRBuilder
199  .buildFrameIndex(LLT::pointer(0, DL.getPointerSizeInBits(0)), FI)
200  .getReg(0);
201  }
202 
203  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
204  MachinePointerInfo &MPO, CCValAssign &VA) override {
205  MachineFunction &MF = MIRBuilder.getMF();
206  auto *MMO = MF.getMachineMemOperand(
208  inferAlignFromPtrInfo(MF, MPO));
209  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
210  }
211 
212  void assignValueToReg(Register ValVReg, Register PhysReg,
213  CCValAssign VA) override {
214  markPhysRegUsed(PhysReg);
215  IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
216  }
217 
218  /// How the physical register gets marked varies between formal
219  /// parameters (it's a basic-block live-in), and a call instruction
220  /// (it's an implicit-def of the BL).
221  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
222 
223 protected:
224  const DataLayout &DL;
225 };
226 
227 struct FormalArgHandler : public X86IncomingValueHandler {
229  : X86IncomingValueHandler(MIRBuilder, MRI) {}
230 
231  void markPhysRegUsed(unsigned PhysReg) override {
232  MIRBuilder.getMRI()->addLiveIn(PhysReg);
233  MIRBuilder.getMBB().addLiveIn(PhysReg);
234  }
235 };
236 
237 struct CallReturnHandler : public X86IncomingValueHandler {
239  MachineInstrBuilder &MIB)
240  : X86IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
241 
242  void markPhysRegUsed(unsigned PhysReg) override {
243  MIB.addDef(PhysReg, RegState::Implicit);
244  }
245 
246 protected:
247  MachineInstrBuilder &MIB;
248 };
249 
250 } // end anonymous namespace
251 
253  const Function &F,
255  FunctionLoweringInfo &FLI) const {
256  MachineFunction &MF = MIRBuilder.getMF();
258  auto DL = MF.getDataLayout();
259 
260  SmallVector<ArgInfo, 8> SplitArgs;
261 
262  if (!FLI.CanLowerReturn)
263  insertSRetIncomingArgument(F, SplitArgs, FLI.DemoteRegister, MRI, DL);
264 
265  // TODO: handle variadic function
266  if (F.isVarArg())
267  return false;
268 
269  unsigned Idx = 0;
270  for (const auto &Arg : F.args()) {
271  // TODO: handle not simple cases.
272  if (Arg.hasAttribute(Attribute::ByVal) ||
273  Arg.hasAttribute(Attribute::InReg) ||
274  Arg.hasAttribute(Attribute::StructRet) ||
275  Arg.hasAttribute(Attribute::SwiftSelf) ||
276  Arg.hasAttribute(Attribute::SwiftError) ||
277  Arg.hasAttribute(Attribute::Nest) || VRegs[Idx].size() > 1)
278  return false;
279 
280  ArgInfo OrigArg(VRegs[Idx], Arg.getType(), Idx);
281  setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
282  splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
283  Idx++;
284  }
285 
286  if (SplitArgs.empty())
287  return true;
288 
289  MachineBasicBlock &MBB = MIRBuilder.getMBB();
290  if (!MBB.empty())
291  MIRBuilder.setInstr(*MBB.begin());
292 
293  X86OutgoingValueAssigner Assigner(CC_X86);
294  FormalArgHandler Handler(MIRBuilder, MRI);
295  if (!determineAndHandleAssignments(Handler, Assigner, SplitArgs, MIRBuilder,
296  F.getCallingConv(), F.isVarArg()))
297  return false;
298 
299  // Move back to the end of the basic block.
300  MIRBuilder.setMBB(MBB);
301 
302  return true;
303 }
304 
306  CallLoweringInfo &Info) const {
307  MachineFunction &MF = MIRBuilder.getMF();
308  const Function &F = MF.getFunction();
310  const DataLayout &DL = F.getParent()->getDataLayout();
311  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
312  const TargetInstrInfo &TII = *STI.getInstrInfo();
313  const X86RegisterInfo *TRI = STI.getRegisterInfo();
314 
315  // Handle only Linux C, X86_64_SysV calling conventions for now.
316  if (!STI.isTargetLinux() || !(Info.CallConv == CallingConv::C ||
317  Info.CallConv == CallingConv::X86_64_SysV))
318  return false;
319 
320  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
321  auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
322 
323  // Create a temporarily-floating call instruction so we can add the implicit
324  // uses of arg registers.
325  bool Is64Bit = STI.is64Bit();
326  unsigned CallOpc = Info.Callee.isReg()
327  ? (Is64Bit ? X86::CALL64r : X86::CALL32r)
328  : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32);
329 
330  auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc)
331  .add(Info.Callee)
332  .addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
333 
334  SmallVector<ArgInfo, 8> SplitArgs;
335  for (const auto &OrigArg : Info.OrigArgs) {
336 
337  // TODO: handle not simple cases.
338  if (OrigArg.Flags[0].isByVal())
339  return false;
340 
341  if (OrigArg.Regs.size() > 1)
342  return false;
343 
344  splitToValueTypes(OrigArg, SplitArgs, DL, Info.CallConv);
345  }
346  // Do the actual argument marshalling.
347  X86OutgoingValueAssigner Assigner(CC_X86);
348  X86OutgoingValueHandler Handler(MIRBuilder, MRI, MIB);
349  if (!determineAndHandleAssignments(Handler, Assigner, SplitArgs, MIRBuilder,
350  Info.CallConv, Info.IsVarArg))
351  return false;
352 
353  bool IsFixed = Info.OrigArgs.empty() ? true : Info.OrigArgs.back().IsFixed;
354  if (STI.is64Bit() && !IsFixed && !STI.isCallingConvWin64(Info.CallConv)) {
355  // From AMD64 ABI document:
356  // For calls that may call functions that use varargs or stdargs
357  // (prototype-less calls or calls to functions containing ellipsis (...) in
358  // the declaration) %al is used as hidden argument to specify the number
359  // of SSE registers used. The contents of %al do not need to match exactly
360  // the number of registers, but must be an ubound on the number of SSE
361  // registers used and is in the range 0 - 8 inclusive.
362 
363  MIRBuilder.buildInstr(X86::MOV8ri)
364  .addDef(X86::AL)
365  .addImm(Assigner.getNumXmmRegs());
367  }
368 
369  // Now we can add the actual call instruction to the correct basic block.
370  MIRBuilder.insertInstr(MIB);
371 
372  // If Callee is a reg, since it is used by a target specific
373  // instruction, it must have a register class matching the
374  // constraint of that instruction.
375  if (Info.Callee.isReg())
377  MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
378  *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
379  0));
380 
381  // Finally we can copy the returned value back into its virtual-register. In
382  // symmetry with the arguments, the physical register must be an
383  // implicit-define of the call instruction.
384 
385  if (Info.CanLowerReturn && !Info.OrigRet.Ty->isVoidTy()) {
386  if (Info.OrigRet.Regs.size() > 1)
387  return false;
388 
389  SplitArgs.clear();
390  SmallVector<Register, 8> NewRegs;
391 
392  splitToValueTypes(Info.OrigRet, SplitArgs, DL, Info.CallConv);
393 
394  X86OutgoingValueAssigner Assigner(RetCC_X86);
395  CallReturnHandler Handler(MIRBuilder, MRI, MIB);
396  if (!determineAndHandleAssignments(Handler, Assigner, SplitArgs, MIRBuilder,
397  Info.CallConv, Info.IsVarArg))
398  return false;
399 
400  if (!NewRegs.empty())
401  MIRBuilder.buildMerge(Info.OrigRet.Regs[0], NewRegs);
402  }
403 
404  CallSeqStart.addImm(Assigner.getStackSize())
405  .addImm(0 /* see getFrameTotalSize */)
406  .addImm(0 /* see getFrameAdjustment */);
407 
408  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
409  MIRBuilder.buildInstr(AdjStackUp)
410  .addImm(Assigner.getStackSize())
411  .addImm(0 /* NumBytesForCalleeToPop */);
412 
413  if (!Info.CanLowerReturn)
414  insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs,
415  Info.DemoteRegister, Info.DemoteStackIndex);
416 
417  return true;
418 }
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:959
ValueTypes.h
LowLevelType.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::AArch64CC::AL
@ AL
Definition: AArch64BaseInfo.h:269
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
X86CallLowering.h
X86Subtarget.h
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:60
llvm::X86Subtarget::isTargetLinux
bool isTargetLinux() const
Definition: X86Subtarget.h:281
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:95
llvm::X86Subtarget::getInstrInfo
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:128
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::MachineIRBuilder::getMRI
MachineRegisterInfo * getMRI()
Getter for MRI.
Definition: MachineIRBuilder.h:289
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:454
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:144
MachineBasicBlock.h
llvm::X86CallLowering::X86CallLowering
X86CallLowering(const X86TargetLowering &TLI)
Definition: X86CallLowering.cpp:51
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1793
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:321
llvm::X86CallLowering::lowerCall
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: X86CallLowering.cpp:305
llvm::CallLowering::OutgoingValueHandler
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
Definition: CallLowering.h:333
TargetInstrInfo.h
llvm::CallLowering::splitToValueTypes
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
Definition: CallLowering.cpp:250
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:39
llvm::MachineIRBuilder::setInstr
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
Definition: MachineIRBuilder.h:342
MachineIRBuilder.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::FunctionLoweringInfo::CanLowerReturn
bool CanLowerReturn
CanLowerReturn - true iff the function's return value can be lowered to registers.
Definition: FunctionLoweringInfo.h:62
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::X86CallLowering::lowerReturn
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
Definition: X86CallLowering.cpp:142
MachineRegisterInfo.h
MachineValueType.h
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::FunctionLoweringInfo::DemoteRegister
Register DemoteRegister
DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg allocated to hold a pointer to ...
Definition: FunctionLoweringInfo.h:69
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::MachineIRBuilder::setMBB
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
Definition: MachineIRBuilder.h:333
FunctionLoweringInfo.h
llvm::CallLowering::ArgInfo
Definition: CallLowering.h:62
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::X86Subtarget::getRegisterInfo
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:138
Utils.h
llvm::RetCC_X86
bool RetCC_X86(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
llvm::FormalArgHandler
Definition: M68kCallLowering.h:66
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::CallLowering::OutgoingValueAssigner
Definition: CallLowering.h:223
llvm::CallingConv::C
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:271
llvm::CallLowering::IncomingValueHandler
Base class for ValueHandlers used for arguments coming into the current function, or for return value...
Definition: CallLowering.h:318
llvm::X86TargetLowering
Definition: X86ISelLowering.h:959
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
LowLevelTypeImpl.h
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:175
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:49
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:433
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:33
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:221
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::CallLowering::checkReturn
bool checkReturn(CCState &CCInfo, SmallVectorImpl< BaseArgInfo > &Outs, CCAssignFn *Fn) const
Definition: CallLowering.cpp:937
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:712
llvm::CallingConv::X86_64_SysV
@ X86_64_SysV
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:148
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
Analysis.h
MCRegisterInfo.h
ArrayRef.h
llvm::X86CallLowering::canLowerReturn
bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv, SmallVectorImpl< BaseArgInfo > &Outs, bool IsVarArg) const override
This hook must be implemented to check whether the return values described by Outs can fit into the r...
Definition: X86CallLowering.cpp:133
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:296
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::N86::EAX
@ EAX
Definition: X86MCTargetDesc.h:51
llvm::TargetSubtargetInfo::getRegBankInfo
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
Definition: TargetSubtargetInfo.h:131
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:383
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:197
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
DataLayout.h
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:43
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::CallLowering::insertSRetLoads
void insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg, int FI) const
Load the returned value from the stack into virtual registers in VRegs.
Definition: CallLowering.cpp:832
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:288
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::X86CallLowering::lowerFormalArguments
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
Definition: X86CallLowering.cpp:252
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:404
llvm::CallLowering::insertSRetIncomingArgument
void insertSRetIncomingArgument(const Function &F, SmallVectorImpl< ArgInfo > &SplitArgs, Register &DemoteReg, MachineRegisterInfo &MRI, const DataLayout &DL) const
Insert the hidden sret ArgInfo to the beginning of SplitArgs.
Definition: CallLowering.cpp:893
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
Attributes.h
llvm::CCState::getFirstUnallocated
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
Definition: CallingConvLower.h:334
llvm::CallLowering::insertSRetStores
void insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg) const
Store the return value given by VRegs into stack starting at the offset specified in DemoteReg.
Definition: CallLowering.cpp:862
X86CallingConv.h
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
CallingConvLower.h
llvm::CallLowering::ValueHandler::MRI
MachineRegisterInfo & MRI
Definition: CallLowering.h:231
llvm::X86Subtarget::isCallingConvWin64
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:328
MachineFrameInfo.h
llvm::ARCISD::RET
@ RET
Definition: ARCISelLowering.h:52
llvm::CC_X86
bool CC_X86(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
Function.h
llvm::CCState::getNextStackOffset
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Definition: CallingConvLower.h:262
llvm::CallLowering::CallLoweringInfo
Definition: CallLowering.h:102
X86ISelLowering.h
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:614
llvm::CallLowering::ValueHandler::MIRBuilder
MachineIRBuilder & MIRBuilder
Definition: CallLowering.h:230
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
X86RegisterInfo.h
SmallVector.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1019
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
MachineInstrBuilder.h
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:56
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:54
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:285
llvm::MachineIRBuilder::buildMerge
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
Definition: MachineIRBuilder.cpp:600
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:277
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
MachineOperand.h
llvm::CallReturnHandler
Definition: M68kCallLowering.h:71
MachineFunction.h
X86InstrInfo.h
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
Value.h
llvm::CallReturnHandler::CallReturnHandler
CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder &MIB)
Definition: M68kCallLowering.h:72
llvm::CallLowering
Definition: CallLowering.h:44
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1032
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AttributeList::FirstArgIndex
@ FirstArgIndex
Definition: Attributes.h:435
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:483
llvm::FormalArgHandler::FormalArgHandler
FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
Definition: M68kCallLowering.h:67
llvm::CallLowering::determineAndHandleAssignments
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=None) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
Definition: CallLowering.cpp:562
llvm::X86RegisterInfo
Definition: X86RegisterInfo.h:24
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::CallLowering::setArgFlags
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Definition: CallLowering.cpp:192