LLVM  10.0.0svn
MipsRegisterBankInfo.cpp
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1 //===- MipsRegisterBankInfo.cpp ---------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the RegisterBankInfo class for Mips.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsRegisterBankInfo.h"
14 #include "MipsInstrInfo.h"
19 
20 #define GET_TARGET_REGBANK_IMPL
21 
22 #include "MipsGenRegisterBank.inc"
23 
24 namespace llvm {
25 namespace Mips {
31 };
32 
34  {0, 32, GPRBRegBank},
35  {0, 32, FPRBRegBank},
36  {0, 64, FPRBRegBank}
37 };
38 
41  GPRIdx = 1,
42  SPRIdx = 4,
43  DPRIdx = 7
44 };
45 
47  // invalid
48  {nullptr, 0},
49  // up to 3 operands in GPRs
50  {&PartMappings[PMI_GPR - PMI_Min], 1},
51  {&PartMappings[PMI_GPR - PMI_Min], 1},
52  {&PartMappings[PMI_GPR - PMI_Min], 1},
53  // up to 3 ops operands FPRs - single precission
54  {&PartMappings[PMI_SPR - PMI_Min], 1},
55  {&PartMappings[PMI_SPR - PMI_Min], 1},
56  {&PartMappings[PMI_SPR - PMI_Min], 1},
57  // up to 3 ops operands FPRs - double precission
58  {&PartMappings[PMI_DPR - PMI_Min], 1},
59  {&PartMappings[PMI_DPR - PMI_Min], 1},
61 };
62 
63 } // end namespace Mips
64 } // end namespace llvm
65 
66 using namespace llvm;
67 
70 
72  const TargetRegisterClass &RC) const {
73  using namespace Mips;
74 
75  switch (RC.getID()) {
76  case Mips::GPR32RegClassID:
77  case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID:
78  case Mips::GPRMM16MovePPairFirstRegClassID:
79  case Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID:
80  case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID:
81  case Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID:
82  case Mips::SP32RegClassID:
83  case Mips::GP32RegClassID:
84  return getRegBank(Mips::GPRBRegBankID);
85  case Mips::FGRCCRegClassID:
86  case Mips::FGR32RegClassID:
87  case Mips::FGR64RegClassID:
88  case Mips::AFGR64RegClassID:
89  return getRegBank(Mips::FPRBRegBankID);
90  default:
91  llvm_unreachable("Register class not supported");
92  }
93 }
94 
95 // Instructions where all register operands are floating point.
96 static bool isFloatingPointOpcode(unsigned Opc) {
97  switch (Opc) {
98  case TargetOpcode::G_FCONSTANT:
99  case TargetOpcode::G_FADD:
100  case TargetOpcode::G_FSUB:
101  case TargetOpcode::G_FMUL:
102  case TargetOpcode::G_FDIV:
103  case TargetOpcode::G_FABS:
104  case TargetOpcode::G_FSQRT:
105  case TargetOpcode::G_FCEIL:
106  case TargetOpcode::G_FFLOOR:
107  case TargetOpcode::G_FPEXT:
108  case TargetOpcode::G_FPTRUNC:
109  return true;
110  default:
111  return false;
112  }
113 }
114 
115 // Instructions where use operands are floating point registers.
116 // Def operands are general purpose.
117 static bool isFloatingPointOpcodeUse(unsigned Opc) {
118  switch (Opc) {
119  case TargetOpcode::G_FPTOSI:
120  case TargetOpcode::G_FPTOUI:
121  case TargetOpcode::G_FCMP:
122  case Mips::MFC1:
124  case Mips::ExtractElementF64_64:
125  return true;
126  default:
127  return isFloatingPointOpcode(Opc);
128  }
129 }
130 
131 // Instructions where def operands are floating point registers.
132 // Use operands are general purpose.
133 static bool isFloatingPointOpcodeDef(unsigned Opc) {
134  switch (Opc) {
135  case TargetOpcode::G_SITOFP:
136  case TargetOpcode::G_UITOFP:
137  case Mips::MTC1:
138  case Mips::BuildPairF64:
139  case Mips::BuildPairF64_64:
140  return true;
141  default:
142  return isFloatingPointOpcode(Opc);
143  }
144 }
145 
146 static bool isAmbiguous(unsigned Opc) {
147  switch (Opc) {
148  case TargetOpcode::G_LOAD:
149  case TargetOpcode::G_STORE:
150  case TargetOpcode::G_PHI:
151  case TargetOpcode::G_SELECT:
152  return true;
153  default:
154  return false;
155  }
156 }
157 
158 void MipsRegisterBankInfo::AmbiguousRegDefUseContainer::addDefUses(
160  assert(!MRI.getType(Reg).isPointer() &&
161  "Pointers are gprb, they should not be considered as ambiguous.\n");
162  for (MachineInstr &UseMI : MRI.use_instructions(Reg)) {
163  MachineInstr *NonCopyInstr = skipCopiesOutgoing(&UseMI);
164  // Copy with many uses.
165  if (NonCopyInstr->getOpcode() == TargetOpcode::COPY &&
166  !Register::isPhysicalRegister(NonCopyInstr->getOperand(0).getReg()))
167  addDefUses(NonCopyInstr->getOperand(0).getReg(), MRI);
168  else
169  DefUses.push_back(skipCopiesOutgoing(&UseMI));
170  }
171 }
172 
173 void MipsRegisterBankInfo::AmbiguousRegDefUseContainer::addUseDef(
174  Register Reg, const MachineRegisterInfo &MRI) {
175  assert(!MRI.getType(Reg).isPointer() &&
176  "Pointers are gprb, they should not be considered as ambiguous.\n");
177  MachineInstr *DefMI = MRI.getVRegDef(Reg);
178  UseDefs.push_back(skipCopiesIncoming(DefMI));
179 }
180 
181 MachineInstr *
182 MipsRegisterBankInfo::AmbiguousRegDefUseContainer::skipCopiesOutgoing(
183  MachineInstr *MI) const {
184  const MachineFunction &MF = *MI->getParent()->getParent();
185  const MachineRegisterInfo &MRI = MF.getRegInfo();
186  MachineInstr *Ret = MI;
187  while (Ret->getOpcode() == TargetOpcode::COPY &&
189  MRI.hasOneUse(Ret->getOperand(0).getReg())) {
190  Ret = &(*MRI.use_instr_begin(Ret->getOperand(0).getReg()));
191  }
192  return Ret;
193 }
194 
195 MachineInstr *
196 MipsRegisterBankInfo::AmbiguousRegDefUseContainer::skipCopiesIncoming(
197  MachineInstr *MI) const {
198  const MachineFunction &MF = *MI->getParent()->getParent();
199  const MachineRegisterInfo &MRI = MF.getRegInfo();
200  MachineInstr *Ret = MI;
201  while (Ret->getOpcode() == TargetOpcode::COPY &&
203  Ret = MRI.getVRegDef(Ret->getOperand(1).getReg());
204  return Ret;
205 }
206 
207 MipsRegisterBankInfo::AmbiguousRegDefUseContainer::AmbiguousRegDefUseContainer(
208  const MachineInstr *MI) {
209  assert(isAmbiguous(MI->getOpcode()) &&
210  "Not implemented for non Ambiguous opcode.\n");
211 
212  const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
213 
214  if (MI->getOpcode() == TargetOpcode::G_LOAD)
215  addDefUses(MI->getOperand(0).getReg(), MRI);
216 
217  if (MI->getOpcode() == TargetOpcode::G_STORE)
218  addUseDef(MI->getOperand(0).getReg(), MRI);
219 
220  if (MI->getOpcode() == TargetOpcode::G_PHI) {
221  addDefUses(MI->getOperand(0).getReg(), MRI);
222 
223  for (unsigned i = 1; i < MI->getNumOperands(); i += 2)
224  addUseDef(MI->getOperand(i).getReg(), MRI);
225  }
226 
227  if (MI->getOpcode() == TargetOpcode::G_SELECT) {
228  addDefUses(MI->getOperand(0).getReg(), MRI);
229 
230  addUseDef(MI->getOperand(2).getReg(), MRI);
231  addUseDef(MI->getOperand(3).getReg(), MRI);
232  }
233 }
234 
235 bool MipsRegisterBankInfo::TypeInfoForMF::visit(
236  const MachineInstr *MI, const MachineInstr *WaitingForTypeOfMI) {
237  assert(isAmbiguous(MI->getOpcode()) && "Visiting non-Ambiguous opcode.\n");
238  if (wasVisited(MI))
239  return true; // InstType has already been determined for MI.
240 
241  startVisit(MI);
242  AmbiguousRegDefUseContainer DefUseContainer(MI);
243 
244  // Visit instructions where MI's DEF operands are USED.
245  if (visitAdjacentInstrs(MI, DefUseContainer.getDefUses(), true))
246  return true;
247 
248  // Visit instructions that DEFINE MI's USE operands.
249  if (visitAdjacentInstrs(MI, DefUseContainer.getUseDefs(), false))
250  return true;
251 
252  // All MI's adjacent instructions, are ambiguous.
253  if (!WaitingForTypeOfMI) {
254  // This is chain of ambiguous instructions.
255  setTypes(MI, InstType::Ambiguous);
256  return true;
257  }
258  // Excluding WaitingForTypeOfMI, MI is either connected to chains of ambiguous
259  // instructions or has no other adjacent instructions. Anyway InstType could
260  // not be determined. There could be unexplored path from some of
261  // WaitingForTypeOfMI's adjacent instructions to an instruction with only one
262  // mapping available.
263  // We are done with this branch, add MI to WaitingForTypeOfMI's WaitingQueue,
264  // this way when WaitingForTypeOfMI figures out its InstType same InstType
265  // will be assigned to all instructions in this branch.
266  addToWaitingQueue(WaitingForTypeOfMI, MI);
267  return false;
268 }
269 
270 bool MipsRegisterBankInfo::TypeInfoForMF::visitAdjacentInstrs(
271  const MachineInstr *MI, SmallVectorImpl<MachineInstr *> &AdjacentInstrs,
272  bool isDefUse) {
273  while (!AdjacentInstrs.empty()) {
274  MachineInstr *AdjMI = AdjacentInstrs.pop_back_val();
275 
276  if (isDefUse ? isFloatingPointOpcodeUse(AdjMI->getOpcode())
277  : isFloatingPointOpcodeDef(AdjMI->getOpcode())) {
278  setTypes(MI, InstType::FloatingPoint);
279  return true;
280  }
281 
282  // Determine InstType from register bank of phys register that is
283  // 'isDefUse ? def : use' of this copy.
284  if (AdjMI->getOpcode() == TargetOpcode::COPY) {
285  setTypesAccordingToPhysicalRegister(MI, AdjMI, isDefUse ? 0 : 1);
286  return true;
287  }
288 
289  // Defaults to integer instruction. Includes G_MERGE_VALUES and
290  // G_UNMERGE_VALUES.
291  if (!isAmbiguous(AdjMI->getOpcode())) {
292  setTypes(MI, InstType::Integer);
293  return true;
294  }
295 
296  // When AdjMI was visited first, MI has to continue to explore remaining
297  // adjacent instructions and determine InstType without visiting AdjMI.
298  if (!wasVisited(AdjMI) ||
299  getRecordedTypeForInstr(AdjMI) != InstType::NotDetermined) {
300  if (visit(AdjMI, MI)) {
301  // InstType is successfully determined and is same as for AdjMI.
302  setTypes(MI, getRecordedTypeForInstr(AdjMI));
303  return true;
304  }
305  }
306  }
307  return false;
308 }
309 
310 void MipsRegisterBankInfo::TypeInfoForMF::setTypes(const MachineInstr *MI,
311  InstType InstTy) {
312  changeRecordedTypeForInstr(MI, InstTy);
313  for (const MachineInstr *WaitingInstr : getWaitingQueueFor(MI)) {
314  setTypes(WaitingInstr, InstTy);
315  }
316 }
317 
318 void MipsRegisterBankInfo::TypeInfoForMF::setTypesAccordingToPhysicalRegister(
319  const MachineInstr *MI, const MachineInstr *CopyInst, unsigned Op) {
321  "Copies of non physical registers should not be considered here.\n");
322 
323  const MachineFunction &MF = *CopyInst->getMF();
324  const MachineRegisterInfo &MRI = MF.getRegInfo();
325  const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
326  const RegisterBankInfo &RBI =
327  *CopyInst->getMF()->getSubtarget().getRegBankInfo();
328  const RegisterBank *Bank =
329  RBI.getRegBank(CopyInst->getOperand(Op).getReg(), MRI, TRI);
330 
331  if (Bank == &Mips::FPRBRegBank)
332  setTypes(MI, InstType::FloatingPoint);
333  else if (Bank == &Mips::GPRBRegBank)
334  setTypes(MI, InstType::Integer);
335  else
336  llvm_unreachable("Unsupported register bank.\n");
337 }
338 
339 MipsRegisterBankInfo::InstType
340 MipsRegisterBankInfo::TypeInfoForMF::determineInstType(const MachineInstr *MI) {
341  visit(MI, nullptr);
342  return getRecordedTypeForInstr(MI);
343 }
344 
345 void MipsRegisterBankInfo::TypeInfoForMF::cleanupIfNewFunction(
346  llvm::StringRef FunctionName) {
347  if (MFName != FunctionName) {
348  MFName = FunctionName;
349  WaitingQueues.clear();
350  Types.clear();
351  }
352 }
353 
356 
357  static TypeInfoForMF TI;
358 
359  // Reset TI internal data when MF changes.
360  TI.cleanupIfNewFunction(MI.getMF()->getName());
361 
362  unsigned Opc = MI.getOpcode();
363  const MachineFunction &MF = *MI.getParent()->getParent();
364  const MachineRegisterInfo &MRI = MF.getRegInfo();
365 
366  if (MI.getOpcode() != TargetOpcode::G_PHI) {
367  const RegisterBankInfo::InstructionMapping &Mapping =
369  if (Mapping.isValid())
370  return Mapping;
371  }
372 
373  using namespace TargetOpcode;
374 
375  unsigned NumOperands = MI.getNumOperands();
376  const ValueMapping *OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
377  unsigned MappingID = DefaultMappingID;
378  const unsigned CustomMappingID = 1;
379 
380  switch (Opc) {
381  case G_TRUNC:
382  case G_ADD:
383  case G_SUB:
384  case G_MUL:
385  case G_UMULH:
386  case G_ZEXTLOAD:
387  case G_SEXTLOAD:
388  case G_GEP:
389  case G_INTTOPTR:
390  case G_PTRTOINT:
391  case G_AND:
392  case G_OR:
393  case G_XOR:
394  case G_SHL:
395  case G_ASHR:
396  case G_LSHR:
397  case G_SDIV:
398  case G_UDIV:
399  case G_SREM:
400  case G_UREM:
401  OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
402  break;
403  case G_LOAD: {
404  unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
405  InstType InstTy = InstType::Integer;
406  if (!MRI.getType(MI.getOperand(0).getReg()).isPointer()) {
407  InstTy = TI.determineInstType(&MI);
408  }
409 
410  if (InstTy == InstType::FloatingPoint ||
411  (Size == 64 && InstTy == InstType::Ambiguous)) { // fprb
412  OperandsMapping =
416  break;
417  } else { // gprb
418  OperandsMapping =
422  if (Size == 64)
423  MappingID = CustomMappingID;
424  }
425 
426  break;
427  }
428  case G_STORE: {
429  unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
430  InstType InstTy = InstType::Integer;
431  if (!MRI.getType(MI.getOperand(0).getReg()).isPointer()) {
432  InstTy = TI.determineInstType(&MI);
433  }
434 
435  if (InstTy == InstType::FloatingPoint ||
436  (Size == 64 && InstTy == InstType::Ambiguous)) { // fprb
437  OperandsMapping =
441  break;
442  } else { // gprb
443  OperandsMapping =
447  if (Size == 64)
448  MappingID = CustomMappingID;
449  }
450  break;
451  }
452  case G_PHI: {
453  unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
454  InstType InstTy = InstType::Integer;
455  if (!MRI.getType(MI.getOperand(0).getReg()).isPointer()) {
456  InstTy = TI.determineInstType(&MI);
457  }
458 
459  // PHI is copylike and should have one regbank in mapping for def register.
460  if (InstTy == InstType::Integer && Size == 64) { // fprb
461  OperandsMapping =
463  return getInstructionMapping(CustomMappingID, /*Cost=*/1, OperandsMapping,
464  /*NumOperands=*/1);
465  }
466  // Use default handling for PHI, i.e. set reg bank of def operand to match
467  // register banks of use operands.
468  const RegisterBankInfo::InstructionMapping &Mapping =
470  return Mapping;
471  }
472  case G_SELECT: {
473  unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
474  InstType InstTy = InstType::Integer;
475  if (!MRI.getType(MI.getOperand(0).getReg()).isPointer()) {
476  InstTy = TI.determineInstType(&MI);
477  }
478 
479  if (InstTy == InstType::FloatingPoint ||
480  (Size == 64 && InstTy == InstType::Ambiguous)) { // fprb
481  const RegisterBankInfo::ValueMapping *Bank =
482  Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
484  OperandsMapping = getOperandsMapping(
485  {Bank, &Mips::ValueMappings[Mips::GPRIdx], Bank, Bank});
486  break;
487  } else { // gprb
488  const RegisterBankInfo::ValueMapping *Bank =
489  Size <= 32 ? &Mips::ValueMappings[Mips::GPRIdx]
491  OperandsMapping = getOperandsMapping(
492  {Bank, &Mips::ValueMappings[Mips::GPRIdx], Bank, Bank});
493  if (Size == 64)
494  MappingID = CustomMappingID;
495  }
496  break;
497  }
498  case G_UNMERGE_VALUES: {
501  &Mips::ValueMappings[Mips::DPRIdx]});
502  MappingID = CustomMappingID;
503  break;
504  }
505  case G_MERGE_VALUES: {
508  &Mips::ValueMappings[Mips::GPRIdx]});
509  MappingID = CustomMappingID;
510  break;
511  }
512  case G_FADD:
513  case G_FSUB:
514  case G_FMUL:
515  case G_FDIV:
516  case G_FABS:
517  case G_FSQRT:{
518  unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
519  assert((Size == 32 || Size == 64) && "Unsupported floating point size");
520  OperandsMapping = Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
522  break;
523  }
524  case G_FCONSTANT: {
525  unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
526  assert((Size == 32 || Size == 64) && "Unsupported floating point size");
527  const RegisterBankInfo::ValueMapping *FPRValueMapping =
528  Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
530  OperandsMapping = getOperandsMapping({FPRValueMapping, nullptr});
531  break;
532  }
533  case G_FCMP: {
534  unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
535  assert((Size == 32 || Size == 64) && "Unsupported floating point size");
536  const RegisterBankInfo::ValueMapping *FPRValueMapping =
537  Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
539  OperandsMapping =
541  FPRValueMapping, FPRValueMapping});
542  break;
543  }
544  case G_FPEXT:
547  break;
548  case G_FPTRUNC:
551  break;
552  case G_FPTOSI: {
553  unsigned SizeFP = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
554  assert((MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 32) &&
555  "Unsupported integer size");
556  assert((SizeFP == 32 || SizeFP == 64) && "Unsupported floating point size");
557  OperandsMapping = getOperandsMapping({
559  SizeFP == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
561  });
562  break;
563  }
564  case G_SITOFP: {
565  unsigned SizeInt = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
566  unsigned SizeFP = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
567  (void)SizeInt;
568  assert((SizeInt == 32) && "Unsupported integer size");
569  assert((SizeFP == 32 || SizeFP == 64) && "Unsupported floating point size");
570  OperandsMapping =
574  break;
575  }
576  case G_CONSTANT:
577  case G_FRAME_INDEX:
578  case G_GLOBAL_VALUE:
579  case G_JUMP_TABLE:
580  case G_BRCOND:
581  OperandsMapping =
583  break;
584  case G_BRJT:
585  OperandsMapping =
588  break;
589  case G_ICMP:
590  OperandsMapping =
593  &Mips::ValueMappings[Mips::GPRIdx]});
594  break;
595  default:
597  }
598 
599  return getInstructionMapping(MappingID, /*Cost=*/1, OperandsMapping,
600  NumOperands);
601 }
602 
604 namespace {
605 class InstManager : public GISelChangeObserver {
606  InstListTy &InstList;
607 
608 public:
609  InstManager(InstListTy &Insts) : InstList(Insts) {}
610 
611  void createdInstr(MachineInstr &MI) override { InstList.insert(&MI); }
612  void erasingInstr(MachineInstr &MI) override {}
613  void changingInstr(MachineInstr &MI) override {}
614  void changedInstr(MachineInstr &MI) override {}
615 };
616 } // end anonymous namespace
617 
618 /// Here we have to narrowScalar s64 operands to s32, combine away
619 /// G_MERGE/G_UNMERGE and erase instructions that became dead in the process.
620 /// We manually assign 32 bit gprb to register operands of all new instructions
621 /// that got created in the process since they will not end up in RegBankSelect
622 /// loop. Careful not to delete instruction after MI i.e. MI.getIterator()++.
624  const OperandsMapper &OpdMapper) const {
625  MachineInstr &MI = OpdMapper.getMI();
626  InstListTy NewInstrs;
627  MachineIRBuilder B(MI);
628  MachineFunction *MF = MI.getMF();
629  MachineRegisterInfo &MRI = OpdMapper.getMRI();
630 
631  InstManager NewInstrObserver(NewInstrs);
632  GISelObserverWrapper WrapperObserver(&NewInstrObserver);
633  LegalizerHelper Helper(*MF, WrapperObserver, B);
634  LegalizationArtifactCombiner ArtCombiner(
635  B, MF->getRegInfo(), *MF->getSubtarget().getLegalizerInfo());
636 
637  switch (MI.getOpcode()) {
638  case TargetOpcode::G_LOAD:
639  case TargetOpcode::G_STORE:
640  case TargetOpcode::G_PHI:
641  case TargetOpcode::G_SELECT: {
642  Helper.narrowScalar(MI, 0, LLT::scalar(32));
643  // Handle new instructions.
644  while (!NewInstrs.empty()) {
645  MachineInstr *NewMI = NewInstrs.pop_back_val();
646  // This is new G_UNMERGE that was created during narrowScalar and will
647  // not be considered for regbank selection. RegBankSelect for mips
648  // visits/makes corresponding G_MERGE first. Combine them here.
649  if (NewMI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES) {
651  ArtCombiner.tryCombineMerges(*NewMI, DeadInstrs);
652  for (MachineInstr *DeadMI : DeadInstrs)
653  DeadMI->eraseFromParent();
654  }
655  // This G_MERGE will be combined away when its corresponding G_UNMERGE
656  // gets regBankSelected.
657  else if (NewMI->getOpcode() == TargetOpcode::G_MERGE_VALUES)
658  continue;
659  else
660  // Manually set register banks for all register operands to 32 bit gprb.
661  for (auto Op : NewMI->operands()) {
662  if (Op.isReg()) {
663  assert(MRI.getType(Op.getReg()).getSizeInBits() == 32 &&
664  "Only 32 bit gprb is handled here.\n");
665  MRI.setRegBank(Op.getReg(), getRegBank(Mips::GPRBRegBankID));
666  }
667  }
668  }
669  return;
670  }
671  case TargetOpcode::G_UNMERGE_VALUES: {
673  ArtCombiner.tryCombineMerges(MI, DeadInstrs);
674  for (MachineInstr *DeadMI : DeadInstrs)
675  DeadMI->eraseFromParent();
676  return;
677  }
678  default:
679  break;
680  }
681 
682  return applyDefaultMapping(OpdMapper);
683 }
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End...
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
RegisterBankInfo::ValueMapping ValueMappings[]
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
bool empty() const
Definition: GISelWorkList.h:42
unsigned Reg
MachineRegisterInfo & getMRI() const
The MachineRegisterInfo we used to realize the mapping.
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
unsigned const TargetRegisterInfo * TRI
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:461
LegalityPredicate isPointer(unsigned TypeIdx)
True iff the specified type index is a pointer (with any address space).
static bool isFloatingPointOpcodeUse(unsigned Opc)
static bool isFloatingPointOpcode(unsigned Opc)
Holds all the information related to register banks.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
static bool isFloatingPointOpcodeDef(unsigned Opc)
unsigned getID() const
Return the register class ID number.
static bool isAmbiguous(unsigned Opc)
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
This file declares the targeting of the RegisterBankInfo class for Mips.
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
virtual const LegalizerInfo * getLegalizerInfo() const
Abstract class that contains various methods for clients to notify about changes. ...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineInstrBuilder & UseMI
Helper struct that represents how a value is partially mapped into a register.
Helper class to build MachineInstr.
use_instr_iterator use_instr_begin(unsigned RegNo) const
RegisterBankInfo::PartialMapping PartMappings[]
void applyMappingImpl(const OperandsMapper &OpdMapper) const override
Here we have to narrowScalar s64 operands to s32, combine away G_MERGE/G_UNMERGE and erase instructio...
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isValid() const
Check whether this object is valid.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
MachineInstrBuilder MachineInstrBuilder & DefMI
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:374
MachineInstr * pop_back_val()
void insert(MachineInstr *I)
Add the specified instruction to the worklist if it isn&#39;t already in it.
Definition: GISelWorkList.h:78
This class implements the register bank concept.
Definition: RegisterBank.h:28
Helper struct that represents how a value is mapped through different register banks.
bool isPointer() const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
uint32_t Size
Definition: Profile.cpp:46
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)
Legalize an instruction by reducing the width of the underlying scalar type.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MipsRegisterBankInfo(const TargetRegisterInfo &TRI)
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
Simple wrapper observer that takes several observers, and calls each one for each event...
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const override
Get a register bank that covers RC.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19