21 #define GET_TARGET_REGBANK_IMPL
23 #include "MipsGenRegisterBank.inc"
84 case Mips::GPR32RegClassID:
85 case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID:
86 case Mips::GPRMM16MovePPairFirstRegClassID:
87 case Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID:
88 case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID:
89 case Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID:
90 case Mips::SP32RegClassID:
91 case Mips::GP32RegClassID:
93 case Mips::FGRCCRegClassID:
94 case Mips::FGR32RegClassID:
95 case Mips::FGR64RegClassID:
96 case Mips::AFGR64RegClassID:
97 case Mips::MSA128BRegClassID:
98 case Mips::MSA128HRegClassID:
99 case Mips::MSA128WRegClassID:
100 case Mips::MSA128DRegClassID:
110 case TargetOpcode::G_FCONSTANT:
111 case TargetOpcode::G_FADD:
112 case TargetOpcode::G_FSUB:
113 case TargetOpcode::G_FMUL:
114 case TargetOpcode::G_FDIV:
115 case TargetOpcode::G_FABS:
116 case TargetOpcode::G_FSQRT:
117 case TargetOpcode::G_FCEIL:
118 case TargetOpcode::G_FFLOOR:
119 case TargetOpcode::G_FPEXT:
120 case TargetOpcode::G_FPTRUNC:
131 case TargetOpcode::G_FPTOSI:
132 case TargetOpcode::G_FPTOUI:
133 case TargetOpcode::G_FCMP:
144 case TargetOpcode::G_SITOFP:
145 case TargetOpcode::G_UITOFP:
153 if (
MI->getOpcode() == TargetOpcode::G_LOAD ||
154 MI->getOpcode() == TargetOpcode::G_STORE) {
155 auto MMO = *
MI->memoperands_begin();
158 MMO->getAlign() < MMO->getSize()))
166 case TargetOpcode::G_LOAD:
167 case TargetOpcode::G_STORE:
168 case TargetOpcode::G_PHI:
169 case TargetOpcode::G_SELECT:
170 case TargetOpcode::G_IMPLICIT_DEF:
171 case TargetOpcode::G_UNMERGE_VALUES:
172 case TargetOpcode::G_MERGE_VALUES:
179 void MipsRegisterBankInfo::AmbiguousRegDefUseContainer::addDefUses(
182 "Pointers are gprb, they should not be considered as ambiguous.\n");
186 if (NonCopyInstr->
getOpcode() == TargetOpcode::COPY &&
190 DefUses.push_back(skipCopiesOutgoing(&
UseMI));
194 void MipsRegisterBankInfo::AmbiguousRegDefUseContainer::addUseDef(
197 "Pointers are gprb, they should not be considered as ambiguous.\n");
199 UseDefs.push_back(skipCopiesIncoming(
DefMI));
203 MipsRegisterBankInfo::AmbiguousRegDefUseContainer::skipCopiesOutgoing(
208 while (
Ret->getOpcode() == TargetOpcode::COPY &&
217 MipsRegisterBankInfo::AmbiguousRegDefUseContainer::skipCopiesIncoming(
222 while (
Ret->getOpcode() == TargetOpcode::COPY &&
228 MipsRegisterBankInfo::AmbiguousRegDefUseContainer::AmbiguousRegDefUseContainer(
231 "Not implemented for non Ambiguous opcode.\n");
235 if (
MI->getOpcode() == TargetOpcode::G_LOAD)
236 addDefUses(
MI->getOperand(0).getReg(),
MRI);
238 if (
MI->getOpcode() == TargetOpcode::G_STORE)
239 addUseDef(
MI->getOperand(0).getReg(),
MRI);
241 if (
MI->getOpcode() == TargetOpcode::G_PHI) {
242 addDefUses(
MI->getOperand(0).getReg(),
MRI);
244 for (
unsigned i = 1;
i <
MI->getNumOperands();
i += 2)
245 addUseDef(
MI->getOperand(
i).getReg(),
MRI);
248 if (
MI->getOpcode() == TargetOpcode::G_SELECT) {
249 addDefUses(
MI->getOperand(0).getReg(),
MRI);
251 addUseDef(
MI->getOperand(2).getReg(),
MRI);
252 addUseDef(
MI->getOperand(3).getReg(),
MRI);
255 if (
MI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
256 addDefUses(
MI->getOperand(0).getReg(),
MRI);
258 if (
MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES)
259 addUseDef(
MI->getOperand(
MI->getNumOperands() - 1).getReg(),
MRI);
261 if (
MI->getOpcode() == TargetOpcode::G_MERGE_VALUES)
262 addDefUses(
MI->getOperand(0).getReg(),
MRI);
265 bool MipsRegisterBankInfo::TypeInfoForMF::visit(
267 InstType &AmbiguousTy) {
273 AmbiguousRegDefUseContainer DefUseContainer(
MI);
276 setTypes(
MI, Integer);
280 if (AmbiguousTy == InstType::Ambiguous &&
281 (
MI->getOpcode() == TargetOpcode::G_MERGE_VALUES ||
282 MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES))
283 AmbiguousTy = InstType::AmbiguousWithMergeOrUnmerge;
286 if (visitAdjacentInstrs(
MI, DefUseContainer.getDefUses(),
true, AmbiguousTy))
290 if (visitAdjacentInstrs(
MI, DefUseContainer.getUseDefs(),
false, AmbiguousTy))
294 if (!WaitingForTypeOfMI) {
296 setTypes(
MI, AmbiguousTy);
307 addToWaitingQueue(WaitingForTypeOfMI,
MI);
311 bool MipsRegisterBankInfo::TypeInfoForMF::visitAdjacentInstrs(
313 bool isDefUse, InstType &AmbiguousTy) {
314 while (!AdjacentInstrs.empty()) {
319 setTypes(
MI, InstType::FloatingPoint);
325 if (AdjMI->
getOpcode() == TargetOpcode::COPY) {
326 setTypesAccordingToPhysicalRegister(
MI, AdjMI, isDefUse ? 0 : 1);
332 if ((!isDefUse && AdjMI->
getOpcode() == TargetOpcode::G_UNMERGE_VALUES) ||
333 (isDefUse && AdjMI->
getOpcode() == TargetOpcode::G_MERGE_VALUES) ||
341 if (!wasVisited(AdjMI) ||
342 getRecordedTypeForInstr(AdjMI) != InstType::NotDetermined) {
343 if (visit(AdjMI,
MI, AmbiguousTy)) {
345 setTypes(
MI, getRecordedTypeForInstr(AdjMI));
353 void MipsRegisterBankInfo::TypeInfoForMF::setTypes(
const MachineInstr *
MI,
355 changeRecordedTypeForInstr(
MI, InstTy);
357 setTypes(WaitingInstr, InstTy);
361 void MipsRegisterBankInfo::TypeInfoForMF::setTypesAccordingToPhysicalRegister(
364 "Copies of non physical registers should not be considered here.\n");
374 if (Bank == &Mips::FPRBRegBank)
375 setTypes(
MI, InstType::FloatingPoint);
376 else if (Bank == &Mips::GPRBRegBank)
382 MipsRegisterBankInfo::InstType
383 MipsRegisterBankInfo::TypeInfoForMF::determineInstType(
const MachineInstr *
MI) {
384 InstType DefaultAmbiguousType = InstType::Ambiguous;
385 visit(
MI,
nullptr, DefaultAmbiguousType);
386 return getRecordedTypeForInstr(
MI);
389 void MipsRegisterBankInfo::TypeInfoForMF::cleanupIfNewFunction(
391 if (MFName != FunctionName) {
392 MFName = std::string(FunctionName);
393 WaitingQueues.clear();
398 static const MipsRegisterBankInfo::ValueMapping *
401 "MSA mapping not available on target without MSA.");
414 static const MipsRegisterBankInfo::ValueMapping *
426 static TypeInfoForMF TI;
429 TI.cleanupIfNewFunction(
MI.getMF()->getName());
431 unsigned Opc =
MI.getOpcode();
435 if (
MI.getOpcode() != TargetOpcode::G_PHI) {
442 using namespace TargetOpcode;
444 unsigned NumOperands =
MI.getNumOperands();
499 if (Op0Size == 128) {
506 InstTy = TI.determineInstType(&
MI);
508 if (isFloatingPoint_32or64(InstTy, Op0Size) ||
509 isAmbiguous_64(InstTy, Op0Size)) {
513 assert((isInteger_32(InstTy, Op0Size) ||
514 isAmbiguous_32(InstTy, Op0Size) ||
515 isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) &&
516 "Unexpected Inst type");
526 InstTy = TI.determineInstType(&
MI);
529 if (isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) {
532 TI.clearTypeInfoData(&
MI);
536 assert((isInteger_32(InstTy, Op0Size) ||
537 isFloatingPoint_32or64(InstTy, Op0Size) ||
538 isAmbiguous_32or64(InstTy, Op0Size)) &&
539 "Unexpected Inst type");
546 InstTy = TI.determineInstType(&
MI);
547 if (isFloatingPoint_32or64(InstTy, Op0Size) ||
548 isAmbiguous_64(InstTy, Op0Size)) {
554 assert((isInteger_32(InstTy, Op0Size) ||
555 isAmbiguous_32(InstTy, Op0Size) ||
556 isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) &&
557 "Unexpected Inst type");
565 case G_IMPLICIT_DEF: {
567 InstTy = TI.determineInstType(&
MI);
569 if (isFloatingPoint_32or64(InstTy, Op0Size))
572 assert((isInteger_32(InstTy, Op0Size) ||
573 isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) &&
574 "Unexpected Inst type");
578 case G_UNMERGE_VALUES: {
579 assert(
MI.getNumOperands() == 3 &&
"Unsupported G_UNMERGE_VALUES");
581 InstTy = TI.determineInstType(&
MI);
582 assert((isAmbiguousWithMergeOrUnmerge_64(InstTy, Op3Size) ||
583 isFloatingPoint_64(InstTy, Op3Size)) &&
584 "Unexpected Inst type");
588 if (isAmbiguousWithMergeOrUnmerge_64(InstTy, Op3Size))
592 case G_MERGE_VALUES: {
593 InstTy = TI.determineInstType(&
MI);
594 assert((isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size) ||
595 isFloatingPoint_64(InstTy, Op0Size)) &&
596 "Unexpected Inst type");
600 if (isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size))
633 assert((Op0Size == 32) &&
"Unsupported integer size");
641 "Unsupported integer size");
669 TI.clearTypeInfoData(&
MI);
680 InstManager(
InstListTy &Insts) : InstList(Insts) {}
692 switch (
MI.getOpcode()) {
693 case TargetOpcode::G_STORE:
696 case TargetOpcode::G_CONSTANT:
697 case TargetOpcode::G_LOAD:
698 case TargetOpcode::G_SELECT:
699 case TargetOpcode::G_PHI:
700 case TargetOpcode::G_IMPLICIT_DEF: {
705 case TargetOpcode::G_PTR_ADD: {
721 UpdatedDefs, Observer);
723 DeadMI->eraseFromParent();
734 InstManager NewInstrObserver(NewInstrs);
739 switch (
MI.getOpcode()) {
740 case TargetOpcode::G_LOAD:
741 case TargetOpcode::G_STORE:
742 case TargetOpcode::G_PHI:
743 case TargetOpcode::G_SELECT:
744 case TargetOpcode::G_IMPLICIT_DEF: {
747 while (!NewInstrs.
empty()) {
752 if (
auto *Unmerge = dyn_cast<GUnmerge>(NewMI))
756 else if (NewMI->
getOpcode() == TargetOpcode::G_MERGE_VALUES)
764 case TargetOpcode::G_UNMERGE_VALUES: