LLVM  14.0.0git
VERegisterInfo.cpp
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1 //===-- VERegisterInfo.cpp - VE Register Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the VE implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "VERegisterInfo.h"
14 #include "VE.h"
15 #include "VESubtarget.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/IR/Type.h"
25 #include "llvm/Support/Debug.h"
27 
28 using namespace llvm;
29 
30 #define GET_REGINFO_TARGET_DESC
31 #include "VEGenRegisterInfo.inc"
32 
33 // VE uses %s10 == %lp to keep return address
35 
36 const MCPhysReg *
38  switch (MF->getFunction().getCallingConv()) {
39  case CallingConv::Fast:
40  // Being explicit (same as standard CC).
41  default:
42  return CSR_SaveList;
44  return CSR_preserve_all_SaveList;
45  }
46 }
47 
49  CallingConv::ID CC) const {
50  switch (CC) {
51  case CallingConv::Fast:
52  // Being explicit (same as standard CC).
53  default:
54  return CSR_RegMask;
56  return CSR_preserve_all_RegMask;
57  }
58 }
59 
61  return CSR_NoRegs_RegMask;
62 }
63 
65  BitVector Reserved(getNumRegs());
66 
67  const Register ReservedRegs[] = {
68  VE::SX8, // Stack limit
69  VE::SX9, // Frame pointer
70  VE::SX10, // Link register (return address)
71  VE::SX11, // Stack pointer
72 
73  // FIXME: maybe not need to be reserved
74  VE::SX12, // Outer register
75  VE::SX13, // Id register for dynamic linker
76 
77  VE::SX14, // Thread pointer
78  VE::SX15, // Global offset table register
79  VE::SX16, // Procedure linkage table register
80  VE::SX17, // Linkage-area register
81  // sx18-sx33 are callee-saved registers
82  // sx34-sx63 are temporary registers
83  };
84 
85  for (auto R : ReservedRegs)
86  for (MCRegAliasIterator ItAlias(R, this, true); ItAlias.isValid();
87  ++ItAlias)
88  Reserved.set(*ItAlias);
89 
90  // Reserve constant registers.
91  Reserved.set(VE::VM0);
92  Reserved.set(VE::VMP0);
93 
94  return Reserved;
95 }
96 
98  switch (PhysReg) {
99  case VE::VM0:
100  case VE::VMP0:
101  return true;
102  default:
103  return false;
104  }
105 }
106 
107 const TargetRegisterClass *
109  unsigned Kind) const {
110  return &VE::I64RegClass;
111 }
112 
113 static unsigned offsetToDisp(MachineInstr &MI) {
114  // Default offset in instruction's operands (reg+reg+imm).
115  unsigned OffDisp = 2;
116 
117 #define RRCAS_multi_cases(NAME) NAME##rir : case NAME##rii
118 
119  {
120  using namespace llvm::VE;
121  switch (MI.getOpcode()) {
122  case RRCAS_multi_cases(TS1AML):
123  case RRCAS_multi_cases(TS1AMW):
124  case RRCAS_multi_cases(CASL):
125  case RRCAS_multi_cases(CASW):
126  // These instructions use AS format (reg+imm).
127  OffDisp = 1;
128  break;
129  }
130  }
131 #undef RRCAS_multi_cases
132 
133  return OffDisp;
134 }
135 
137  MachineInstr &MI, const DebugLoc &dl,
138  unsigned FIOperandNum, int Offset, Register FrameReg) {
139  // Replace frame index with a frame pointer reference directly.
140  // VE has 32 bit offset field, so no need to expand a target instruction.
141  // Directly encode it.
142  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
143  MI.getOperand(FIOperandNum + offsetToDisp(MI)).ChangeToImmediate(Offset);
144 }
145 
147  int SPAdj, unsigned FIOperandNum,
148  RegScavenger *RS) const {
149  assert(SPAdj == 0 && "Unexpected");
150 
151  MachineInstr &MI = *II;
152  DebugLoc dl = MI.getDebugLoc();
153  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
154  MachineFunction &MF = *MI.getParent()->getParent();
155  const VEFrameLowering *TFI = getFrameLowering(MF);
156 
157  Register FrameReg;
158  int Offset;
159  Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg).getFixed();
160 
161  Offset += MI.getOperand(FIOperandNum + offsetToDisp(MI)).getImm();
162 
163  if (MI.getOpcode() == VE::STQrii) {
164  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
165  Register SrcReg = MI.getOperand(3).getReg();
166  Register SrcHiReg = getSubReg(SrcReg, VE::sub_even);
167  Register SrcLoReg = getSubReg(SrcReg, VE::sub_odd);
168  // VE stores HiReg to 8(addr) and LoReg to 0(addr)
169  MachineInstr *StMI = BuildMI(*MI.getParent(), II, dl, TII.get(VE::STrii))
170  .addReg(FrameReg)
171  .addImm(0)
172  .addImm(0)
173  .addReg(SrcLoReg);
174  replaceFI(MF, II, *StMI, dl, 0, Offset, FrameReg);
175  MI.setDesc(TII.get(VE::STrii));
176  MI.getOperand(3).setReg(SrcHiReg);
177  Offset += 8;
178  } else if (MI.getOpcode() == VE::LDQrii) {
179  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
180  Register DestReg = MI.getOperand(0).getReg();
181  Register DestHiReg = getSubReg(DestReg, VE::sub_even);
182  Register DestLoReg = getSubReg(DestReg, VE::sub_odd);
183  // VE loads HiReg from 8(addr) and LoReg from 0(addr)
184  MachineInstr *StMI =
185  BuildMI(*MI.getParent(), II, dl, TII.get(VE::LDrii), DestLoReg)
186  .addReg(FrameReg)
187  .addImm(0)
188  .addImm(0);
189  replaceFI(MF, II, *StMI, dl, 1, Offset, FrameReg);
190  MI.setDesc(TII.get(VE::LDrii));
191  MI.getOperand(0).setReg(DestHiReg);
192  Offset += 8;
193  }
194 
195  replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FrameReg);
196 }
197 
199  return VE::SX9;
200 }
llvm::VERegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: VERegisterInfo.cpp:37
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::VERegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: VERegisterInfo.cpp:60
llvm::VERegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: VERegisterInfo.cpp:198
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
ErrorHandling.h
offsetToDisp
static unsigned offsetToDisp(MachineInstr &MI)
Definition: VERegisterInfo.cpp:113
TargetInstrInfo.h
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
STLExtras.h
MachineRegisterInfo.h
CommandLine.h
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::VERegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const override
Definition: VERegisterInfo.cpp:97
BitVector.h
llvm::BitVector
Definition: BitVector.h:74
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Type.h
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::VERegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: VERegisterInfo.cpp:146
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:239
llvm::RegScavenger
Definition: RegisterScavenging.h:34
VERegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::VEFrameLowering
Definition: VEFrameLowering.h:23
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
VEGenRegisterInfo
llvm::MachineFunction
Definition: MachineFunction.h:230
uint32_t
llvm::StackOffset::getFixed
static StackOffset getFixed(ScalarTy Fixed)
Definition: TypeSize.h:143
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
uint16_t
MachineFrameInfo.h
VE.h
llvm::VERegisterInfo::VERegisterInfo
VERegisterInfo()
Definition: VERegisterInfo.cpp:34
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:805
llvm::CallingConv::PreserveAll
@ PreserveAll
Definition: CallingConv.h:70
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
VESubtarget.h
llvm::VE
Definition: VEFixupKinds.h:15
llvm::VERegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
Definition: VERegisterInfo.cpp:48
llvm::VERegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: VERegisterInfo.cpp:64
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
MachineFunction.h
llvm::MachineInstrBundleIterator
MachineBasicBlock iterator that automatically skips over MIs that are inside bundles (i....
Definition: MachineInstrBundleIterator.h:108
llvm::VERegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind) const override
Definition: VERegisterInfo.cpp:108
replaceFI
static void replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II, MachineInstr &MI, const DebugLoc &dl, unsigned FIOperandNum, int Offset, Register FrameReg)
Definition: VERegisterInfo.cpp:136
RRCAS_multi_cases
#define RRCAS_multi_cases(NAME)
Debug.h
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
llvm::VEFrameLowering::getFrameIndexReference
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
Definition: VEFrameLowering.cpp:444