30 #define GET_REGINFO_TARGET_DESC 31 #include "VEGenRegisterInfo.inc" 44 return CSR_preserve_all_SaveList;
56 return CSR_preserve_all_RegMask;
61 return CSR_NoRegs_RegMask;
85 for (
auto R : ReservedRegs)
88 Reserved.
set(*ItAlias);
91 Reserved.
set(VE::VM0);
92 Reserved.
set(VE::VMP0);
109 unsigned Kind)
const {
110 return &VE::I64RegClass;
115 unsigned OffDisp = 2;
117 #define RRCAS_multi_cases(NAME) NAME##rir : case NAME##rii 121 switch (
MI.getOpcode()) {
131 #undef RRCAS_multi_cases 142 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg,
false);
147 int SPAdj,
unsigned FIOperandNum,
149 assert(SPAdj == 0 &&
"Unexpected");
153 int FrameIndex =
MI.getOperand(FIOperandNum).getIndex();
163 if (
MI.getOpcode() == VE::STQrii) {
166 Register SrcHiReg = getSubReg(SrcReg, VE::sub_even);
167 Register SrcLoReg = getSubReg(SrcReg, VE::sub_odd);
175 MI.setDesc(
TII.get(VE::STrii));
176 MI.getOperand(3).setReg(SrcHiReg);
178 }
else if (
MI.getOpcode() == VE::LDQrii) {
181 Register DestHiReg = getSubReg(DestReg, VE::sub_even);
182 Register DestLoReg = getSubReg(DestReg, VE::sub_odd);
185 BuildMI(*
MI.getParent(), II, dl,
TII.get(VE::LDrii), DestLoReg)
190 MI.setDesc(
TII.get(VE::LDrii));
191 MI.getOperand(0).setReg(DestHiReg);
const uint32_t * getNoPreservedMask() const override
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
Wrapper class representing physical registers. Should be passed by value.
BitVector getReservedRegs(const MachineFunction &MF) const override
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
This class represents lattice values for constants.
Function & getFunction()
Return the LLVM function that this machine code represents.
Register getFrameRegister(const MachineFunction &MF) const override
#define RRCAS_multi_cases(NAME)
static StackOffset getFixed(ScalarTy Fixed)
const HexagonInstrInfo * TII
static unsigned offsetToDisp(MachineInstr &MI)
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
virtual const TargetInstrInfo * getInstrInfo() const
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCRegAliasIterator enumerates all registers aliasing Reg.
static void replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II, MachineInstr &MI, const DebugLoc &dl, unsigned FIOperandNum, int Offset, Register FrameReg)
bool isConstantPhysReg(MCRegister PhysReg) const override
Fast - This calling convention attempts to make calls as fast as possible (e.g.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Representation of each machine instruction.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Wrapper class representing virtual and physical registers.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind) const override