31 #define DEBUG_TYPE "arm-pseudo"
35 cl::desc(
"Verify machine code after expanding ARM pseudos"));
37 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
72 unsigned Opc,
bool IsExt);
110 unsigned StrexOp,
unsigned UxtOp,
125 void ARMExpandPseudo::TransferImpOps(
MachineInstr &OldMI,
131 assert(MO.isReg() && MO.getReg());
144 enum NEONRegSpacing {
155 struct NEONLdStTableEntry {
160 bool hasWritebackOperand;
169 bool copyAllListRegs;
172 bool operator<(
const NEONLdStTableEntry &TE)
const {
173 return PseudoOpc <
TE.PseudoOpc;
175 friend bool operator<(
const NEONLdStTableEntry &TE,
unsigned PseudoOpc) {
176 return TE.PseudoOpc < PseudoOpc;
179 const NEONLdStTableEntry &TE) {
180 return PseudoOpc <
TE.PseudoOpc;
186 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16,
true,
false,
false, EvenDblSpc, 1, 4 ,
true},
187 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD,
true,
true,
true, EvenDblSpc, 1, 4 ,
true},
188 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32,
true,
false,
false, EvenDblSpc, 1, 2 ,
true},
189 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD,
true,
true,
true, EvenDblSpc, 1, 2 ,
true},
190 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8,
true,
false,
false, EvenDblSpc, 1, 8 ,
true},
191 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD,
true,
true,
true, EvenDblSpc, 1, 8 ,
true},
193 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q,
true,
false,
false, SingleSpc, 4, 4 ,
false},
194 { ARM::VLD1d16QPseudoWB_fixed, ARM::VLD1d16Qwb_fixed,
true,
true,
false, SingleSpc, 4, 4 ,
false},
195 { ARM::VLD1d16QPseudoWB_register, ARM::VLD1d16Qwb_register,
true,
true,
true, SingleSpc, 4, 4 ,
false},
196 { ARM::VLD1d16TPseudo, ARM::VLD1d16T,
true,
false,
false, SingleSpc, 3, 4 ,
false},
197 { ARM::VLD1d16TPseudoWB_fixed, ARM::VLD1d16Twb_fixed,
true,
true,
false, SingleSpc, 3, 4 ,
false},
198 { ARM::VLD1d16TPseudoWB_register, ARM::VLD1d16Twb_register,
true,
true,
true, SingleSpc, 3, 4 ,
false},
200 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q,
true,
false,
false, SingleSpc, 4, 2 ,
false},
201 { ARM::VLD1d32QPseudoWB_fixed, ARM::VLD1d32Qwb_fixed,
true,
true,
false, SingleSpc, 4, 2 ,
false},
202 { ARM::VLD1d32QPseudoWB_register, ARM::VLD1d32Qwb_register,
true,
true,
true, SingleSpc, 4, 2 ,
false},
203 { ARM::VLD1d32TPseudo, ARM::VLD1d32T,
true,
false,
false, SingleSpc, 3, 2 ,
false},
204 { ARM::VLD1d32TPseudoWB_fixed, ARM::VLD1d32Twb_fixed,
true,
true,
false, SingleSpc, 3, 2 ,
false},
205 { ARM::VLD1d32TPseudoWB_register, ARM::VLD1d32Twb_register,
true,
true,
true, SingleSpc, 3, 2 ,
false},
207 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q,
true,
false,
false, SingleSpc, 4, 1 ,
false},
208 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed,
true,
true,
false, SingleSpc, 4, 1 ,
false},
209 { ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register,
true,
true,
true, SingleSpc, 4, 1 ,
false},
210 { ARM::VLD1d64TPseudo, ARM::VLD1d64T,
true,
false,
false, SingleSpc, 3, 1 ,
false},
211 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed,
true,
true,
false, SingleSpc, 3, 1 ,
false},
212 { ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register,
true,
true,
true, SingleSpc, 3, 1 ,
false},
214 { ARM::VLD1d8QPseudo, ARM::VLD1d8Q,
true,
false,
false, SingleSpc, 4, 8 ,
false},
215 { ARM::VLD1d8QPseudoWB_fixed, ARM::VLD1d8Qwb_fixed,
true,
true,
false, SingleSpc, 4, 8 ,
false},
216 { ARM::VLD1d8QPseudoWB_register, ARM::VLD1d8Qwb_register,
true,
true,
true, SingleSpc, 4, 8 ,
false},
217 { ARM::VLD1d8TPseudo, ARM::VLD1d8T,
true,
false,
false, SingleSpc, 3, 8 ,
false},
218 { ARM::VLD1d8TPseudoWB_fixed, ARM::VLD1d8Twb_fixed,
true,
true,
false, SingleSpc, 3, 8 ,
false},
219 { ARM::VLD1d8TPseudoWB_register, ARM::VLD1d8Twb_register,
true,
true,
true, SingleSpc, 3, 8 ,
false},
221 { ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q,
true,
false,
false, SingleHighQSpc, 4, 4 ,
false},
222 { ARM::VLD1q16HighQPseudo_UPD, ARM::VLD1d16Qwb_fixed,
true,
true,
true, SingleHighQSpc, 4, 4 ,
false},
223 { ARM::VLD1q16HighTPseudo, ARM::VLD1d16T,
true,
false,
false, SingleHighTSpc, 3, 4 ,
false},
224 { ARM::VLD1q16HighTPseudo_UPD, ARM::VLD1d16Twb_fixed,
true,
true,
true, SingleHighTSpc, 3, 4 ,
false},
225 { ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed,
true,
true,
true, SingleLowSpc, 4, 4 ,
false},
226 { ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed,
true,
true,
true, SingleLowSpc, 3, 4 ,
false},
228 { ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q,
true,
false,
false, SingleHighQSpc, 4, 2 ,
false},
229 { ARM::VLD1q32HighQPseudo_UPD, ARM::VLD1d32Qwb_fixed,
true,
true,
true, SingleHighQSpc, 4, 2 ,
false},
230 { ARM::VLD1q32HighTPseudo, ARM::VLD1d32T,
true,
false,
false, SingleHighTSpc, 3, 2 ,
false},
231 { ARM::VLD1q32HighTPseudo_UPD, ARM::VLD1d32Twb_fixed,
true,
true,
true, SingleHighTSpc, 3, 2 ,
false},
232 { ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed,
true,
true,
true, SingleLowSpc, 4, 2 ,
false},
233 { ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed,
true,
true,
true, SingleLowSpc, 3, 2 ,
false},
235 { ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q,
true,
false,
false, SingleHighQSpc, 4, 1 ,
false},
236 { ARM::VLD1q64HighQPseudo_UPD, ARM::VLD1d64Qwb_fixed,
true,
true,
true, SingleHighQSpc, 4, 1 ,
false},
237 { ARM::VLD1q64HighTPseudo, ARM::VLD1d64T,
true,
false,
false, SingleHighTSpc, 3, 1 ,
false},
238 { ARM::VLD1q64HighTPseudo_UPD, ARM::VLD1d64Twb_fixed,
true,
true,
true, SingleHighTSpc, 3, 1 ,
false},
239 { ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed,
true,
true,
true, SingleLowSpc, 4, 1 ,
false},
240 { ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed,
true,
true,
true, SingleLowSpc, 3, 1 ,
false},
242 { ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q,
true,
false,
false, SingleHighQSpc, 4, 8 ,
false},
243 { ARM::VLD1q8HighQPseudo_UPD, ARM::VLD1d8Qwb_fixed,
true,
true,
true, SingleHighQSpc, 4, 8 ,
false},
244 { ARM::VLD1q8HighTPseudo, ARM::VLD1d8T,
true,
false,
false, SingleHighTSpc, 3, 8 ,
false},
245 { ARM::VLD1q8HighTPseudo_UPD, ARM::VLD1d8Twb_fixed,
true,
true,
true, SingleHighTSpc, 3, 8 ,
false},
246 { ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed,
true,
true,
true, SingleLowSpc, 4, 8 ,
false},
247 { ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed,
true,
true,
true, SingleLowSpc, 3, 8 ,
false},
249 { ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2,
true,
false,
false, EvenDblSpc, 2, 4 ,
false},
250 { ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2,
true,
false,
false, OddDblSpc, 2, 4 ,
false},
251 { ARM::VLD2DUPq16OddPseudoWB_fixed, ARM::VLD2DUPd16x2wb_fixed,
true,
true,
false, OddDblSpc, 2, 4 ,
false},
252 { ARM::VLD2DUPq16OddPseudoWB_register, ARM::VLD2DUPd16x2wb_register,
true,
true,
true, OddDblSpc, 2, 4 ,
false},
253 { ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2,
true,
false,
false, EvenDblSpc, 2, 2 ,
false},
254 { ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2,
true,
false,
false, OddDblSpc, 2, 2 ,
false},
255 { ARM::VLD2DUPq32OddPseudoWB_fixed, ARM::VLD2DUPd32x2wb_fixed,
true,
true,
false, OddDblSpc, 2, 2 ,
false},
256 { ARM::VLD2DUPq32OddPseudoWB_register, ARM::VLD2DUPd32x2wb_register,
true,
true,
true, OddDblSpc, 2, 2 ,
false},
257 { ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2,
true,
false,
false, EvenDblSpc, 2, 8 ,
false},
258 { ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2,
true,
false,
false, OddDblSpc, 2, 8 ,
false},
259 { ARM::VLD2DUPq8OddPseudoWB_fixed, ARM::VLD2DUPd8x2wb_fixed,
true,
true,
false, OddDblSpc, 2, 8 ,
false},
260 { ARM::VLD2DUPq8OddPseudoWB_register, ARM::VLD2DUPd8x2wb_register,
true,
true,
true, OddDblSpc, 2, 8 ,
false},
262 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16,
true,
false,
false, SingleSpc, 2, 4 ,
true},
263 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD,
true,
true,
true, SingleSpc, 2, 4 ,
true},
264 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32,
true,
false,
false, SingleSpc, 2, 2 ,
true},
265 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD,
true,
true,
true, SingleSpc, 2, 2 ,
true},
266 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8,
true,
false,
false, SingleSpc, 2, 8 ,
true},
267 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD,
true,
true,
true, SingleSpc, 2, 8 ,
true},
268 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16,
true,
false,
false, EvenDblSpc, 2, 4 ,
true},
269 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD,
true,
true,
true, EvenDblSpc, 2, 4 ,
true},
270 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32,
true,
false,
false, EvenDblSpc, 2, 2 ,
true},
271 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD,
true,
true,
true, EvenDblSpc, 2, 2 ,
true},
273 { ARM::VLD2q16Pseudo, ARM::VLD2q16,
true,
false,
false, SingleSpc, 4, 4 ,
false},
274 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed,
true,
true,
false, SingleSpc, 4, 4 ,
false},
275 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register,
true,
true,
true, SingleSpc, 4, 4 ,
false},
276 { ARM::VLD2q32Pseudo, ARM::VLD2q32,
true,
false,
false, SingleSpc, 4, 2 ,
false},
277 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed,
true,
true,
false, SingleSpc, 4, 2 ,
false},
278 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register,
true,
true,
true, SingleSpc, 4, 2 ,
false},
279 { ARM::VLD2q8Pseudo, ARM::VLD2q8,
true,
false,
false, SingleSpc, 4, 8 ,
false},
280 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed,
true,
true,
false, SingleSpc, 4, 8 ,
false},
281 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register,
true,
true,
true, SingleSpc, 4, 8 ,
false},
283 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16,
true,
false,
false, SingleSpc, 3, 4,
true},
284 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD,
true,
true,
true, SingleSpc, 3, 4,
true},
285 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32,
true,
false,
false, SingleSpc, 3, 2,
true},
286 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD,
true,
true,
true, SingleSpc, 3, 2,
true},
287 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8,
true,
false,
false, SingleSpc, 3, 8,
true},
288 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD,
true,
true,
true, SingleSpc, 3, 8,
true},
289 { ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16,
true,
false,
false, EvenDblSpc, 3, 4 ,
true},
290 { ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16,
true,
false,
false, OddDblSpc, 3, 4 ,
true},
291 { ARM::VLD3DUPq16OddPseudo_UPD, ARM::VLD3DUPq16_UPD,
true,
true,
true, OddDblSpc, 3, 4 ,
true},
292 { ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32,
true,
false,
false, EvenDblSpc, 3, 2 ,
true},
293 { ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32,
true,
false,
false, OddDblSpc, 3, 2 ,
true},
294 { ARM::VLD3DUPq32OddPseudo_UPD, ARM::VLD3DUPq32_UPD,
true,
true,
true, OddDblSpc, 3, 2 ,
true},
295 { ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8,
true,
false,
false, EvenDblSpc, 3, 8 ,
true},
296 { ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8,
true,
false,
false, OddDblSpc, 3, 8 ,
true},
297 { ARM::VLD3DUPq8OddPseudo_UPD, ARM::VLD3DUPq8_UPD,
true,
true,
true, OddDblSpc, 3, 8 ,
true},
299 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16,
true,
false,
false, SingleSpc, 3, 4 ,
true},
300 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD,
true,
true,
true, SingleSpc, 3, 4 ,
true},
301 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32,
true,
false,
false, SingleSpc, 3, 2 ,
true},
302 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD,
true,
true,
true, SingleSpc, 3, 2 ,
true},
303 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8,
true,
false,
false, SingleSpc, 3, 8 ,
true},
304 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD,
true,
true,
true, SingleSpc, 3, 8 ,
true},
305 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16,
true,
false,
false, EvenDblSpc, 3, 4 ,
true},
306 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD,
true,
true,
true, EvenDblSpc, 3, 4 ,
true},
307 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32,
true,
false,
false, EvenDblSpc, 3, 2 ,
true},
308 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD,
true,
true,
true, EvenDblSpc, 3, 2 ,
true},
310 { ARM::VLD3d16Pseudo, ARM::VLD3d16,
true,
false,
false, SingleSpc, 3, 4 ,
true},
311 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD,
true,
true,
true, SingleSpc, 3, 4 ,
true},
312 { ARM::VLD3d32Pseudo, ARM::VLD3d32,
true,
false,
false, SingleSpc, 3, 2 ,
true},
313 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD,
true,
true,
true, SingleSpc, 3, 2 ,
true},
314 { ARM::VLD3d8Pseudo, ARM::VLD3d8,
true,
false,
false, SingleSpc, 3, 8 ,
true},
315 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD,
true,
true,
true, SingleSpc, 3, 8 ,
true},
317 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD,
true,
true,
true, EvenDblSpc, 3, 4 ,
true},
318 { ARM::VLD3q16oddPseudo, ARM::VLD3q16,
true,
false,
false, OddDblSpc, 3, 4 ,
true},
319 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD,
true,
true,
true, OddDblSpc, 3, 4 ,
true},
320 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD,
true,
true,
true, EvenDblSpc, 3, 2 ,
true},
321 { ARM::VLD3q32oddPseudo, ARM::VLD3q32,
true,
false,
false, OddDblSpc, 3, 2 ,
true},
322 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD,
true,
true,
true, OddDblSpc, 3, 2 ,
true},
323 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD,
true,
true,
true, EvenDblSpc, 3, 8 ,
true},
324 { ARM::VLD3q8oddPseudo, ARM::VLD3q8,
true,
false,
false, OddDblSpc, 3, 8 ,
true},
325 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD,
true,
true,
true, OddDblSpc, 3, 8 ,
true},
327 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16,
true,
false,
false, SingleSpc, 4, 4,
true},
328 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD,
true,
true,
true, SingleSpc, 4, 4,
true},
329 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32,
true,
false,
false, SingleSpc, 4, 2,
true},
330 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD,
true,
true,
true, SingleSpc, 4, 2,
true},
331 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8,
true,
false,
false, SingleSpc, 4, 8,
true},
332 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD,
true,
true,
true, SingleSpc, 4, 8,
true},
333 { ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16,
true,
false,
false, EvenDblSpc, 4, 4 ,
true},
334 { ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16,
true,
false,
false, OddDblSpc, 4, 4 ,
true},
335 { ARM::VLD4DUPq16OddPseudo_UPD, ARM::VLD4DUPq16_UPD,
true,
true,
true, OddDblSpc, 4, 4 ,
true},
336 { ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32,
true,
false,
false, EvenDblSpc, 4, 2 ,
true},
337 { ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32,
true,
false,
false, OddDblSpc, 4, 2 ,
true},
338 { ARM::VLD4DUPq32OddPseudo_UPD, ARM::VLD4DUPq32_UPD,
true,
true,
true, OddDblSpc, 4, 2 ,
true},
339 { ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8,
true,
false,
false, EvenDblSpc, 4, 8 ,
true},
340 { ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8,
true,
false,
false, OddDblSpc, 4, 8 ,
true},
341 { ARM::VLD4DUPq8OddPseudo_UPD, ARM::VLD4DUPq8_UPD,
true,
true,
true, OddDblSpc, 4, 8 ,
true},
343 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16,
true,
false,
false, SingleSpc, 4, 4 ,
true},
344 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD,
true,
true,
true, SingleSpc, 4, 4 ,
true},
345 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32,
true,
false,
false, SingleSpc, 4, 2 ,
true},
346 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD,
true,
true,
true, SingleSpc, 4, 2 ,
true},
347 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8,
true,
false,
false, SingleSpc, 4, 8 ,
true},
348 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD,
true,
true,
true, SingleSpc, 4, 8 ,
true},
349 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16,
true,
false,
false, EvenDblSpc, 4, 4 ,
true},
350 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD,
true,
true,
true, EvenDblSpc, 4, 4 ,
true},
351 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32,
true,
false,
false, EvenDblSpc, 4, 2 ,
true},
352 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD,
true,
true,
true, EvenDblSpc, 4, 2 ,
true},
354 { ARM::VLD4d16Pseudo, ARM::VLD4d16,
true,
false,
false, SingleSpc, 4, 4 ,
true},
355 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD,
true,
true,
true, SingleSpc, 4, 4 ,
true},
356 { ARM::VLD4d32Pseudo, ARM::VLD4d32,
true,
false,
false, SingleSpc, 4, 2 ,
true},
357 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD,
true,
true,
true, SingleSpc, 4, 2 ,
true},
358 { ARM::VLD4d8Pseudo, ARM::VLD4d8,
true,
false,
false, SingleSpc, 4, 8 ,
true},
359 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD,
true,
true,
true, SingleSpc, 4, 8 ,
true},
361 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD,
true,
true,
true, EvenDblSpc, 4, 4 ,
true},
362 { ARM::VLD4q16oddPseudo, ARM::VLD4q16,
true,
false,
false, OddDblSpc, 4, 4 ,
true},
363 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD,
true,
true,
true, OddDblSpc, 4, 4 ,
true},
364 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD,
true,
true,
true, EvenDblSpc, 4, 2 ,
true},
365 { ARM::VLD4q32oddPseudo, ARM::VLD4q32,
true,
false,
false, OddDblSpc, 4, 2 ,
true},
366 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD,
true,
true,
true, OddDblSpc, 4, 2 ,
true},
367 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD,
true,
true,
true, EvenDblSpc, 4, 8 ,
true},
368 { ARM::VLD4q8oddPseudo, ARM::VLD4q8,
true,
false,
false, OddDblSpc, 4, 8 ,
true},
369 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD,
true,
true,
true, OddDblSpc, 4, 8 ,
true},
371 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16,
false,
false,
false, EvenDblSpc, 1, 4 ,
true},
372 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD,
false,
true,
true, EvenDblSpc, 1, 4 ,
true},
373 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32,
false,
false,
false, EvenDblSpc, 1, 2 ,
true},
374 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD,
false,
true,
true, EvenDblSpc, 1, 2 ,
true},
375 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8,
false,
false,
false, EvenDblSpc, 1, 8 ,
true},
376 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD,
false,
true,
true, EvenDblSpc, 1, 8 ,
true},
378 { ARM::VST1d16QPseudo, ARM::VST1d16Q,
false,
false,
false, SingleSpc, 4, 4 ,
false},
379 { ARM::VST1d16QPseudoWB_fixed, ARM::VST1d16Qwb_fixed,
false,
true,
false, SingleSpc, 4, 4 ,
false},
380 { ARM::VST1d16QPseudoWB_register, ARM::VST1d16Qwb_register,
false,
true,
true, SingleSpc, 4, 4 ,
false},
381 { ARM::VST1d16TPseudo, ARM::VST1d16T,
false,
false,
false, SingleSpc, 3, 4 ,
false},
382 { ARM::VST1d16TPseudoWB_fixed, ARM::VST1d16Twb_fixed,
false,
true,
false, SingleSpc, 3, 4 ,
false},
383 { ARM::VST1d16TPseudoWB_register, ARM::VST1d16Twb_register,
false,
true,
true, SingleSpc, 3, 4 ,
false},
385 { ARM::VST1d32QPseudo, ARM::VST1d32Q,
false,
false,
false, SingleSpc, 4, 2 ,
false},
386 { ARM::VST1d32QPseudoWB_fixed, ARM::VST1d32Qwb_fixed,
false,
true,
false, SingleSpc, 4, 2 ,
false},
387 { ARM::VST1d32QPseudoWB_register, ARM::VST1d32Qwb_register,
false,
true,
true, SingleSpc, 4, 2 ,
false},
388 { ARM::VST1d32TPseudo, ARM::VST1d32T,
false,
false,
false, SingleSpc, 3, 2 ,
false},
389 { ARM::VST1d32TPseudoWB_fixed, ARM::VST1d32Twb_fixed,
false,
true,
false, SingleSpc, 3, 2 ,
false},
390 { ARM::VST1d32TPseudoWB_register, ARM::VST1d32Twb_register,
false,
true,
true, SingleSpc, 3, 2 ,
false},
392 { ARM::VST1d64QPseudo, ARM::VST1d64Q,
false,
false,
false, SingleSpc, 4, 1 ,
false},
393 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed,
false,
true,
false, SingleSpc, 4, 1 ,
false},
394 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register,
false,
true,
true, SingleSpc, 4, 1 ,
false},
395 { ARM::VST1d64TPseudo, ARM::VST1d64T,
false,
false,
false, SingleSpc, 3, 1 ,
false},
396 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed,
false,
true,
false, SingleSpc, 3, 1 ,
false},
397 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register,
false,
true,
true, SingleSpc, 3, 1 ,
false},
399 { ARM::VST1d8QPseudo, ARM::VST1d8Q,
false,
false,
false, SingleSpc, 4, 8 ,
false},
400 { ARM::VST1d8QPseudoWB_fixed, ARM::VST1d8Qwb_fixed,
false,
true,
false, SingleSpc, 4, 8 ,
false},
401 { ARM::VST1d8QPseudoWB_register, ARM::VST1d8Qwb_register,
false,
true,
true, SingleSpc, 4, 8 ,
false},
402 { ARM::VST1d8TPseudo, ARM::VST1d8T,
false,
false,
false, SingleSpc, 3, 8 ,
false},
403 { ARM::VST1d8TPseudoWB_fixed, ARM::VST1d8Twb_fixed,
false,
true,
false, SingleSpc, 3, 8 ,
false},
404 { ARM::VST1d8TPseudoWB_register, ARM::VST1d8Twb_register,
false,
true,
true, SingleSpc, 3, 8 ,
false},
406 { ARM::VST1q16HighQPseudo, ARM::VST1d16Q,
false,
false,
false, SingleHighQSpc, 4, 4 ,
false},
407 { ARM::VST1q16HighQPseudo_UPD, ARM::VST1d16Qwb_fixed,
false,
true,
true, SingleHighQSpc, 4, 8 ,
false},
408 { ARM::VST1q16HighTPseudo, ARM::VST1d16T,
false,
false,
false, SingleHighTSpc, 3, 4 ,
false},
409 { ARM::VST1q16HighTPseudo_UPD, ARM::VST1d16Twb_fixed,
false,
true,
true, SingleHighTSpc, 3, 4 ,
false},
410 { ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed,
false,
true,
true, SingleLowSpc, 4, 4 ,
false},
411 { ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed,
false,
true,
true, SingleLowSpc, 3, 4 ,
false},
413 { ARM::VST1q32HighQPseudo, ARM::VST1d32Q,
false,
false,
false, SingleHighQSpc, 4, 2 ,
false},
414 { ARM::VST1q32HighQPseudo_UPD, ARM::VST1d32Qwb_fixed,
false,
true,
true, SingleHighQSpc, 4, 8 ,
false},
415 { ARM::VST1q32HighTPseudo, ARM::VST1d32T,
false,
false,
false, SingleHighTSpc, 3, 2 ,
false},
416 { ARM::VST1q32HighTPseudo_UPD, ARM::VST1d32Twb_fixed,
false,
true,
true, SingleHighTSpc, 3, 2 ,
false},
417 { ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed,
false,
true,
true, SingleLowSpc, 4, 2 ,
false},
418 { ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed,
false,
true,
true, SingleLowSpc, 3, 2 ,
false},
420 { ARM::VST1q64HighQPseudo, ARM::VST1d64Q,
false,
false,
false, SingleHighQSpc, 4, 1 ,
false},
421 { ARM::VST1q64HighQPseudo_UPD, ARM::VST1d64Qwb_fixed,
false,
true,
true, SingleHighQSpc, 4, 8 ,
false},
422 { ARM::VST1q64HighTPseudo, ARM::VST1d64T,
false,
false,
false, SingleHighTSpc, 3, 1 ,
false},
423 { ARM::VST1q64HighTPseudo_UPD, ARM::VST1d64Twb_fixed,
false,
true,
true, SingleHighTSpc, 3, 1 ,
false},
424 { ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed,
false,
true,
true, SingleLowSpc, 4, 1 ,
false},
425 { ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed,
false,
true,
true, SingleLowSpc, 3, 1 ,
false},
427 { ARM::VST1q8HighQPseudo, ARM::VST1d8Q,
false,
false,
false, SingleHighQSpc, 4, 8 ,
false},
428 { ARM::VST1q8HighQPseudo_UPD, ARM::VST1d8Qwb_fixed,
false,
true,
true, SingleHighQSpc, 4, 8 ,
false},
429 { ARM::VST1q8HighTPseudo, ARM::VST1d8T,
false,
false,
false, SingleHighTSpc, 3, 8 ,
false},
430 { ARM::VST1q8HighTPseudo_UPD, ARM::VST1d8Twb_fixed,
false,
true,
true, SingleHighTSpc, 3, 8 ,
false},
431 { ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed,
false,
true,
true, SingleLowSpc, 4, 8 ,
false},
432 { ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed,
false,
true,
true, SingleLowSpc, 3, 8 ,
false},
434 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16,
false,
false,
false, SingleSpc, 2, 4 ,
true},
435 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD,
false,
true,
true, SingleSpc, 2, 4 ,
true},
436 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32,
false,
false,
false, SingleSpc, 2, 2 ,
true},
437 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD,
false,
true,
true, SingleSpc, 2, 2 ,
true},
438 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8,
false,
false,
false, SingleSpc, 2, 8 ,
true},
439 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD,
false,
true,
true, SingleSpc, 2, 8 ,
true},
440 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16,
false,
false,
false, EvenDblSpc, 2, 4,
true},
441 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD,
false,
true,
true, EvenDblSpc, 2, 4,
true},
442 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32,
false,
false,
false, EvenDblSpc, 2, 2,
true},
443 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD,
false,
true,
true, EvenDblSpc, 2, 2,
true},
445 { ARM::VST2q16Pseudo, ARM::VST2q16,
false,
false,
false, SingleSpc, 4, 4 ,
false},
446 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed,
false,
true,
false, SingleSpc, 4, 4 ,
false},
447 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register,
false,
true,
true, SingleSpc, 4, 4 ,
false},
448 { ARM::VST2q32Pseudo, ARM::VST2q32,
false,
false,
false, SingleSpc, 4, 2 ,
false},
449 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed,
false,
true,
false, SingleSpc, 4, 2 ,
false},
450 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register,
false,
true,
true, SingleSpc, 4, 2 ,
false},
451 { ARM::VST2q8Pseudo, ARM::VST2q8,
false,
false,
false, SingleSpc, 4, 8 ,
false},
452 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed,
false,
true,
false, SingleSpc, 4, 8 ,
false},
453 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register,
false,
true,
true, SingleSpc, 4, 8 ,
false},
455 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16,
false,
false,
false, SingleSpc, 3, 4 ,
true},
456 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD,
false,
true,
true, SingleSpc, 3, 4 ,
true},
457 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32,
false,
false,
false, SingleSpc, 3, 2 ,
true},
458 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD,
false,
true,
true, SingleSpc, 3, 2 ,
true},
459 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8,
false,
false,
false, SingleSpc, 3, 8 ,
true},
460 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD,
false,
true,
true, SingleSpc, 3, 8 ,
true},
461 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16,
false,
false,
false, EvenDblSpc, 3, 4,
true},
462 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD,
false,
true,
true, EvenDblSpc, 3, 4,
true},
463 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32,
false,
false,
false, EvenDblSpc, 3, 2,
true},
464 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD,
false,
true,
true, EvenDblSpc, 3, 2,
true},
466 { ARM::VST3d16Pseudo, ARM::VST3d16,
false,
false,
false, SingleSpc, 3, 4 ,
true},
467 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD,
false,
true,
true, SingleSpc, 3, 4 ,
true},
468 { ARM::VST3d32Pseudo, ARM::VST3d32,
false,
false,
false, SingleSpc, 3, 2 ,
true},
469 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD,
false,
true,
true, SingleSpc, 3, 2 ,
true},
470 { ARM::VST3d8Pseudo, ARM::VST3d8,
false,
false,
false, SingleSpc, 3, 8 ,
true},
471 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD,
false,
true,
true, SingleSpc, 3, 8 ,
true},
473 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD,
false,
true,
true, EvenDblSpc, 3, 4 ,
true},
474 { ARM::VST3q16oddPseudo, ARM::VST3q16,
false,
false,
false, OddDblSpc, 3, 4 ,
true},
475 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD,
false,
true,
true, OddDblSpc, 3, 4 ,
true},
476 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD,
false,
true,
true, EvenDblSpc, 3, 2 ,
true},
477 { ARM::VST3q32oddPseudo, ARM::VST3q32,
false,
false,
false, OddDblSpc, 3, 2 ,
true},
478 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD,
false,
true,
true, OddDblSpc, 3, 2 ,
true},
479 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD,
false,
true,
true, EvenDblSpc, 3, 8 ,
true},
480 { ARM::VST3q8oddPseudo, ARM::VST3q8,
false,
false,
false, OddDblSpc, 3, 8 ,
true},
481 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD,
false,
true,
true, OddDblSpc, 3, 8 ,
true},
483 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16,
false,
false,
false, SingleSpc, 4, 4 ,
true},
484 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD,
false,
true,
true, SingleSpc, 4, 4 ,
true},
485 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32,
false,
false,
false, SingleSpc, 4, 2 ,
true},
486 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD,
false,
true,
true, SingleSpc, 4, 2 ,
true},
487 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8,
false,
false,
false, SingleSpc, 4, 8 ,
true},
488 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD,
false,
true,
true, SingleSpc, 4, 8 ,
true},
489 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16,
false,
false,
false, EvenDblSpc, 4, 4,
true},
490 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD,
false,
true,
true, EvenDblSpc, 4, 4,
true},
491 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32,
false,
false,
false, EvenDblSpc, 4, 2,
true},
492 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD,
false,
true,
true, EvenDblSpc, 4, 2,
true},
494 { ARM::VST4d16Pseudo, ARM::VST4d16,
false,
false,
false, SingleSpc, 4, 4 ,
true},
495 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD,
false,
true,
true, SingleSpc, 4, 4 ,
true},
496 { ARM::VST4d32Pseudo, ARM::VST4d32,
false,
false,
false, SingleSpc, 4, 2 ,
true},
497 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD,
false,
true,
true, SingleSpc, 4, 2 ,
true},
498 { ARM::VST4d8Pseudo, ARM::VST4d8,
false,
false,
false, SingleSpc, 4, 8 ,
true},
499 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD,
false,
true,
true, SingleSpc, 4, 8 ,
true},
501 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD,
false,
true,
true, EvenDblSpc, 4, 4 ,
true},
502 { ARM::VST4q16oddPseudo, ARM::VST4q16,
false,
false,
false, OddDblSpc, 4, 4 ,
true},
503 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD,
false,
true,
true, OddDblSpc, 4, 4 ,
true},
504 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD,
false,
true,
true, EvenDblSpc, 4, 2 ,
true},
505 { ARM::VST4q32oddPseudo, ARM::VST4q32,
false,
false,
false, OddDblSpc, 4, 2 ,
true},
506 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD,
false,
true,
true, OddDblSpc, 4, 2 ,
true},
507 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD,
false,
true,
true, EvenDblSpc, 4, 8 ,
true},
508 { ARM::VST4q8oddPseudo, ARM::VST4q8,
false,
false,
false, OddDblSpc, 4, 8 ,
true},
509 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD,
false,
true,
true, OddDblSpc, 4, 8 ,
true}
517 static std::atomic<bool> TableChecked(
false);
518 if (!TableChecked.load(std::memory_order_relaxed)) {
520 TableChecked.store(
true, std::memory_order_relaxed);
535 unsigned &D1,
unsigned &D2,
unsigned &D3) {
536 if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) {
541 }
else if (RegSpc == SingleHighQSpc) {
546 }
else if (RegSpc == SingleHighTSpc) {
551 }
else if (RegSpc == EvenDblSpc) {
557 assert(RegSpc == OddDblSpc &&
"unknown register spacing");
573 assert(TableEntry && TableEntry->IsLoad &&
"NEONLdStTable lookup failed");
574 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
575 unsigned NumRegs = TableEntry->NumRegs;
578 TII->get(TableEntry->RealOpc));
581 bool DstIsDead =
MI.getOperand(OpIdx).isDead();
582 Register DstReg =
MI.getOperand(OpIdx++).getReg();
584 bool IsVLD2DUP = TableEntry->RealOpc == ARM::VLD2DUPd8x2 ||
585 TableEntry->RealOpc == ARM::VLD2DUPd16x2 ||
586 TableEntry->RealOpc == ARM::VLD2DUPd32x2 ||
587 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed ||
588 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed ||
589 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed ||
590 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_register ||
591 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_register ||
592 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_register;
595 unsigned SubRegIndex;
596 if (RegSpc == EvenDblSpc) {
597 SubRegIndex = ARM::dsub_0;
599 assert(RegSpc == OddDblSpc &&
"Unexpected spacing!");
600 SubRegIndex = ARM::dsub_1;
604 &ARM::DPairSpcRegClass);
607 unsigned D0, D1, D2, D3;
610 if (NumRegs > 1 && TableEntry->copyAllListRegs)
612 if (NumRegs > 2 && TableEntry->copyAllListRegs)
614 if (NumRegs > 3 && TableEntry->copyAllListRegs)
618 if (TableEntry->isUpdating)
619 MIB.add(
MI.getOperand(OpIdx++));
622 MIB.add(
MI.getOperand(OpIdx++));
623 MIB.add(
MI.getOperand(OpIdx++));
626 if (TableEntry->hasWritebackOperand) {
635 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed ||
636 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed ||
637 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed ||
638 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed ||
639 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed ||
640 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed ||
641 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed ||
642 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed ||
643 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed ||
644 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed ||
645 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed) {
647 "A fixed writing-back pseudo instruction provides an offset "
657 unsigned SrcOpIdx = 0;
659 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc ||
660 RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc ||
661 RegSpc == SingleHighTSpc)
666 MIB.add(
MI.getOperand(OpIdx++));
667 MIB.add(
MI.getOperand(OpIdx++));
678 TransferImpOps(
MI, MIB, MIB);
681 MIB.cloneMemRefs(
MI);
682 MI.eraseFromParent();
694 assert(TableEntry && !TableEntry->IsLoad &&
"NEONLdStTable lookup failed");
695 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
696 unsigned NumRegs = TableEntry->NumRegs;
699 TII->get(TableEntry->RealOpc));
701 if (TableEntry->isUpdating)
702 MIB.
add(
MI.getOperand(OpIdx++));
705 MIB.
add(
MI.getOperand(OpIdx++));
706 MIB.
add(
MI.getOperand(OpIdx++));
708 if (TableEntry->hasWritebackOperand) {
717 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed ||
718 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed ||
719 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed ||
720 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed ||
721 TableEntry->RealOpc == ARM::VST1d8Twb_fixed ||
722 TableEntry->RealOpc == ARM::VST1d16Twb_fixed ||
723 TableEntry->RealOpc == ARM::VST1d32Twb_fixed ||
724 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) {
726 "A fixed writing-back pseudo instruction provides an offset "
733 bool SrcIsKill =
MI.getOperand(OpIdx).isKill();
734 bool SrcIsUndef =
MI.getOperand(OpIdx).isUndef();
735 Register SrcReg =
MI.getOperand(OpIdx++).getReg();
736 unsigned D0, D1, D2, D3;
739 if (NumRegs > 1 && TableEntry->copyAllListRegs)
741 if (NumRegs > 2 && TableEntry->copyAllListRegs)
743 if (NumRegs > 3 && TableEntry->copyAllListRegs)
747 MIB.add(
MI.getOperand(OpIdx++));
748 MIB.add(
MI.getOperand(OpIdx++));
750 if (SrcIsKill && !SrcIsUndef)
751 MIB->addRegisterKilled(SrcReg,
TRI,
true);
752 else if (!SrcIsUndef)
754 TransferImpOps(
MI, MIB, MIB);
757 MIB.cloneMemRefs(
MI);
758 MI.eraseFromParent();
770 assert(TableEntry &&
"NEONLdStTable lookup failed");
771 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
772 unsigned NumRegs = TableEntry->NumRegs;
773 unsigned RegElts = TableEntry->RegElts;
776 TII->get(TableEntry->RealOpc));
780 unsigned Lane =
MI.getOperand(
MI.getDesc().getNumOperands() - 3).getImm();
783 assert(RegSpc != OddDblSpc &&
"unexpected register spacing for VLD/VST-lane");
784 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
788 assert(Lane < RegElts &&
"out of range lane for VLD/VST-lane");
790 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
792 bool DstIsDead =
false;
793 if (TableEntry->IsLoad) {
794 DstIsDead =
MI.getOperand(OpIdx).isDead();
795 DstReg =
MI.getOperand(OpIdx++).getReg();
806 if (TableEntry->isUpdating)
807 MIB.add(
MI.getOperand(OpIdx++));
810 MIB.add(
MI.getOperand(OpIdx++));
811 MIB.add(
MI.getOperand(OpIdx++));
813 if (TableEntry->hasWritebackOperand)
814 MIB.add(
MI.getOperand(OpIdx++));
818 if (!TableEntry->IsLoad)
824 MIB.addReg(D0, SrcFlags);
826 MIB.addReg(D1, SrcFlags);
828 MIB.addReg(D2, SrcFlags);
830 MIB.addReg(D3, SrcFlags);
837 MIB.add(
MI.getOperand(OpIdx++));
838 MIB.add(
MI.getOperand(OpIdx++));
843 if (TableEntry->IsLoad)
846 TransferImpOps(
MI, MIB, MIB);
848 MIB.cloneMemRefs(
MI);
849 MI.eraseFromParent();
855 unsigned Opc,
bool IsExt) {
864 MIB.
add(
MI.getOperand(OpIdx++));
870 bool SrcIsKill =
MI.getOperand(OpIdx).isKill();
871 Register SrcReg =
MI.getOperand(OpIdx++).getReg();
872 unsigned D0, D1, D2, D3;
881 MIB.
add(
MI.getOperand(OpIdx++));
882 MIB.
add(
MI.getOperand(OpIdx++));
886 TransferImpOps(
MI, MIB, MIB);
887 MI.eraseFromParent();
895 MI.getOpcode() == ARM::MQQPRStore ||
MI.getOpcode() == ARM::MQQQQPRStore
906 MIB.
add(
MI.getOperand(1));
912 if (
MI.getOpcode() == ARM::MQQQQPRStore ||
913 MI.getOpcode() == ARM::MQQQQPRLoad) {
920 if (NewOpc == ARM::VSTMDIA)
923 TransferImpOps(
MI, MIB, MIB);
925 MI.eraseFromParent();
974 unsigned Opcode =
MI.getOpcode();
978 bool DstIsDead =
MI.getOperand(0).isDead();
979 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
985 if (!STI->hasV6T2Ops() &&
986 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
988 assert(!STI->isTargetWindows() &&
"Windows on ARM requires ARMv7+");
990 assert (MO.
isImm() &&
"MOVi32imm w/ non-immediate source operand!");
991 unsigned ImmVal = (unsigned)MO.
getImm();
992 unsigned SOImmValV1 = 0, SOImmValV2 = 0;
1008 SOImmValV1 = ~(-SOImmValV1);
1011 unsigned MIFlags =
MI.getFlags();
1012 LO16 = LO16.
addImm(SOImmValV1);
1013 HI16 = HI16.
addImm(SOImmValV2);
1022 TransferImpOps(
MI, LO16, HI16);
1023 MI.eraseFromParent();
1027 unsigned LO16Opc = 0;
1028 unsigned HI16Opc = 0;
1029 unsigned MIFlags =
MI.getFlags();
1030 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
1031 LO16Opc = ARM::t2MOVi16;
1032 HI16Opc = ARM::t2MOVTi16;
1034 LO16Opc = ARM::MOVi16;
1035 HI16Opc = ARM::MOVTi16;
1049 unsigned Lo16 =
Imm & 0xffff;
1050 unsigned Hi16 = (
Imm >> 16) & 0xffff;
1051 LO16 = LO16.
addImm(Lo16);
1052 HI16 = HI16.
addImm(Hi16);
1076 if (RequiresBundling)
1081 TransferImpOps(
MI, LO16, HI16);
1082 MI.eraseFromParent();
1092 const std::initializer_list<unsigned> &Regs,
1096 if (!
Op.isReg() || !
Op.isUse())
1098 OpRegs.push_back(
Op.getReg());
1103 std::back_inserter(ClearRegs));
1106 void ARMExpandPseudo::CMSEClearGPRegs(
1109 unsigned ClobberReg) {
1111 if (STI->hasV8_1MMainlineOps()) {
1115 for (
unsigned R : ClearRegs)
1122 for (
unsigned Reg : ClearRegs) {
1123 if (
Reg == ClobberReg)
1131 .
addImm(STI->hasDSP() ? 0xc00 : 0x800)
1150 if ((
Reg >= ARM::Q0 &&
Reg <= ARM::Q7) ||
1151 (
Reg >= ARM::D0 &&
Reg <= ARM::D15) ||
1152 (
Reg >= ARM::S0 &&
Reg <= ARM::S31))
1157 if (
Reg >= ARM::Q0 &&
Reg <= ARM::Q7) {
1158 int R =
Reg - ARM::Q0;
1159 ClearRegs.
reset(R * 4, (R + 1) * 4);
1160 }
else if (
Reg >= ARM::D0 &&
Reg <= ARM::D15) {
1161 int R =
Reg - ARM::D0;
1162 ClearRegs.
reset(R * 2, (R + 1) * 2);
1163 }
else if (
Reg >= ARM::S0 &&
Reg <= ARM::S31) {
1164 ClearRegs[
Reg - ARM::S0] =
false;
1176 if (STI->hasV8_1MMainlineOps())
1177 return CMSEClearFPRegsV81(
MBB,
MBBI, ClearRegs);
1179 return CMSEClearFPRegsV8(
MBB,
MBBI, ClearRegs);
1188 if (!STI->hasFPRegs())
1198 if (STI->hasMinSize()) {
1199 ClearBB = DoneBB = &
MBB;
1220 if (
Reg == ARM::NoRegister ||
Reg == ARM::LR)
1246 for (
unsigned D = 0;
D < 8;
D++) {
1248 if (ClearRegs[
D * 2 + 0] && ClearRegs[
D * 2 + 1]) {
1249 unsigned Reg = ARM::D0 +
D;
1256 if (ClearRegs[
D * 2 + 0]) {
1257 unsigned Reg = ARM::S0 +
D * 2;
1263 if (ClearRegs[
D * 2 + 1]) {
1264 unsigned Reg = ARM::S0 +
D * 2 + 1;
1301 int Start = -1, End = -1;
1302 for (
int S = 0,
E = ClearRegs.
size();
S !=
E; ++
S) {
1303 if (ClearRegs[
S] &&
S == End + 1) {
1312 while (++Start <= End)
1323 while (++Start <= End)
1331 void ARMExpandPseudo::CMSESaveClearFPRegs(
1334 if (STI->hasV8_1MMainlineOps())
1335 CMSESaveClearFPRegsV81(
MBB,
MBBI,
DL, LiveRegs);
1336 else if (STI->hasV8MMainlineOps())
1337 CMSESaveClearFPRegsV8(
MBB,
MBBI,
DL, LiveRegs, ScratchRegs);
1341 void ARMExpandPseudo::CMSESaveClearFPRegsV8(
1346 assert(!ScratchRegs.empty());
1347 unsigned SpareReg = ScratchRegs.front();
1356 std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs;
1357 std::vector<unsigned> NonclearedFPRegs;
1359 if (
Op.isReg() &&
Op.isUse()) {
1365 if (ScratchRegs.size() >= 2) {
1368 ClearedFPRegs.emplace_back(
Reg, SaveReg1, SaveReg2);
1377 NonclearedFPRegs.push_back(
Reg);
1380 if (ScratchRegs.size() >= 1) {
1382 ClearedFPRegs.emplace_back(
Reg, SaveReg, 0);
1389 NonclearedFPRegs.push_back(
Reg);
1395 bool passesFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty());
1398 assert(STI->hasFPRegs() &&
"Subtarget needs fpregs");
1405 for (
auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1,
1406 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7})
1411 for (
const auto &Regs : ClearedFPRegs) {
1412 unsigned Reg, SaveReg1, SaveReg2;
1413 std::tie(
Reg, SaveReg1, SaveReg2) = Regs;
1425 for (
unsigned Reg : NonclearedFPRegs) {
1427 if (STI->isLittle()) {
1488 if (!DefFP && ClearRegs.
count() == ClearRegs.
size()) {
1499 for (
auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1,
1500 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7})
1509 for (
int Reg = ARM::S16;
Reg <= ARM::S31; ++
Reg)
1513 (void)CMSEClearFPRegsV81(
MBB,
MBBI, ClearRegs);
1524 void ARMExpandPseudo::CMSERestoreFPRegs(
1527 if (STI->hasV8_1MMainlineOps())
1528 CMSERestoreFPRegsV81(
MBB,
MBBI,
DL, AvailableRegs);
1529 else if (STI->hasV8MMainlineOps())
1530 CMSERestoreFPRegsV8(
MBB,
MBBI,
DL, AvailableRegs);
1533 void ARMExpandPseudo::CMSERestoreFPRegsV8(
1538 unsigned ScratchReg = ARM::NoRegister;
1539 if (STI->fixCMSE_CVE_2021_35465())
1543 std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs;
1544 std::vector<unsigned> NonclearedFPRegs;
1546 if (
Op.isReg() &&
Op.isDef()) {
1552 if (AvailableRegs.size() >= 2) {
1555 ClearedFPRegs.emplace_back(
Reg, SaveReg1, SaveReg2);
1564 NonclearedFPRegs.push_back(
Reg);
1567 if (AvailableRegs.size() >= 1) {
1569 ClearedFPRegs.emplace_back(
Reg, SaveReg, 0);
1576 NonclearedFPRegs.push_back(
Reg);
1582 bool returnsFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty());
1585 assert(STI->hasFPRegs() &&
"Subtarget needs fpregs");
1588 for (
unsigned Reg : NonclearedFPRegs) {
1609 if (STI->fixCMSE_CVE_2021_35465()) {
1629 if (STI->hasFPRegs())
1642 for (
const auto &Regs : ClearedFPRegs) {
1643 unsigned Reg, SaveReg1, SaveReg2;
1644 std::tie(
Reg, SaveReg1, SaveReg2) = Regs;
1668 if ((
Reg >= ARM::Q0 &&
Reg <= ARM::Q7) ||
1669 (
Reg >= ARM::D0 &&
Reg <= ARM::D15) ||
1670 (
Reg >= ARM::S0 &&
Reg <= ARM::S31))
1676 void ARMExpandPseudo::CMSERestoreFPRegsV81(
1680 if (STI->fixCMSE_CVE_2021_35465()) {
1709 for (
int Reg = ARM::S16;
Reg <= ARM::S31; ++
Reg)
1719 unsigned LdrexOp,
unsigned StrexOp,
1722 bool IsThumb = STI->isThumb();
1726 Register TempReg =
MI.getOperand(1).getReg();
1729 assert(!
MI.getOperand(2).isUndef() &&
"cannot handle undef");
1730 Register AddrReg =
MI.getOperand(2).getReg();
1731 Register DesiredReg =
MI.getOperand(3).getReg();
1735 assert(STI->hasV8MBaselineOps() &&
1736 "CMP_SWAP not expected to be custom expanded for Thumb1");
1737 assert((UxtOp == 0 || UxtOp == ARM::tUXTB || UxtOp == ARM::tUXTH) &&
1738 "ARMv8-M.baseline does not have t2UXTB/t2UXTH");
1740 "DesiredReg used for UXT op must be tGPR");
1749 MF->
insert(++LoadCmpBB->getIterator(), StoreBB);
1750 MF->
insert(++StoreBB->getIterator(), DoneBB);
1769 if (LdrexOp == ARM::t2LDREX)
1773 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
1778 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
1783 LoadCmpBB->addSuccessor(DoneBB);
1784 LoadCmpBB->addSuccessor(StoreBB);
1793 if (StrexOp == ARM::t2STREX)
1797 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
1806 StoreBB->addSuccessor(LoadCmpBB);
1807 StoreBB->addSuccessor(DoneBB);
1815 MI.eraseFromParent();
1823 StoreBB->clearLiveIns();
1825 LoadCmpBB->clearLiveIns();
1835 unsigned Flags,
bool IsThumb,
1840 MIB.
addReg(RegLo, Flags);
1841 MIB.
addReg(RegHi, Flags);
1850 bool IsThumb = STI->isThumb();
1854 Register TempReg =
MI.getOperand(1).getReg();
1857 assert(!
MI.getOperand(2).isUndef() &&
"cannot handle undef");
1858 Register AddrReg =
MI.getOperand(2).getReg();
1859 Register DesiredReg =
MI.getOperand(3).getReg();
1861 New.setIsKill(
false);
1874 MF->
insert(++LoadCmpBB->getIterator(), StoreBB);
1875 MF->
insert(++StoreBB->getIterator(), DoneBB);
1882 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
1888 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
1899 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
1904 LoadCmpBB->addSuccessor(DoneBB);
1905 LoadCmpBB->addSuccessor(StoreBB);
1911 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
1917 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
1926 StoreBB->addSuccessor(LoadCmpBB);
1927 StoreBB->addSuccessor(DoneBB);
1935 MI.eraseFromParent();
1943 StoreBB->clearLiveIns();
1945 LoadCmpBB->clearLiveIns();
1971 for (
int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >=
ARM::R4; --LoReg) {
1972 if (JumpReg == LoReg)
1990 if (JumpReg >=
ARM::R4 && JumpReg <= ARM::R7) {
2019 for (
int R = 0; R < 4; ++R) {
2027 for (
int R = 0; R < 4; ++R)
2043 unsigned Opcode =
MI.getOpcode();
2051 if (DstReg ==
MI.getOperand(3).getReg()) {
2053 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq;
2055 .
add(
MI.getOperand(0))
2056 .
add(
MI.getOperand(3))
2057 .
add(
MI.getOperand(2))
2058 .
add(
MI.getOperand(1))
2060 .
add(
MI.getOperand(5));
2061 }
else if (DstReg ==
MI.getOperand(2).getReg()) {
2063 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq;
2065 .
add(
MI.getOperand(0))
2066 .
add(
MI.getOperand(2))
2067 .
add(
MI.getOperand(3))
2068 .
add(
MI.getOperand(1))
2070 .
add(
MI.getOperand(5));
2073 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq;
2074 if (DstReg ==
MI.getOperand(1).getReg()) {
2076 .
add(
MI.getOperand(0))
2077 .
add(
MI.getOperand(1))
2078 .
add(
MI.getOperand(2))
2079 .
add(
MI.getOperand(3))
2081 .
add(
MI.getOperand(5));
2084 unsigned MoveOpc = Opcode == ARM::VBSPd ? ARM::VORRd : ARM::VORRq;
2089 .
add(
MI.getOperand(1))
2090 .
add(
MI.getOperand(1))
2092 .
add(
MI.getOperand(5));
2094 .
add(
MI.getOperand(0))
2098 .
add(
MI.getOperand(2))
2099 .
add(
MI.getOperand(3))
2101 .
add(
MI.getOperand(5));
2104 MI.eraseFromParent();
2108 case ARM::TCRETURNdi:
2109 case ARM::TCRETURNri: {
2111 if (
MBBI->getOpcode() == ARM::SEH_EpilogEnd)
2113 if (
MBBI->getOpcode() == ARM::SEH_Nop_Ret)
2116 "Can only insert epilog into returning blocks");
2117 unsigned RetOpcode =
MBBI->getOpcode();
2124 if (
MBBI->getOpcode() == ARM::SEH_EpilogEnd)
2126 if (
MBBI->getOpcode() == ARM::SEH_Nop_Ret)
2131 if (RetOpcode == ARM::TCRETURNdi) {
2137 ? ((STI->isTargetMachO() || NeedsWinCFI) ? ARM::tTAILJMPd
2153 }
else if (RetOpcode == ARM::TCRETURNri) {
2155 STI->isThumb() ? ARM::tTAILJMPr
2156 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4);
2162 auto NewMI = std::prev(
MBBI);
2163 for (
unsigned i = 2,
e =
MBBI->getNumOperands();
i !=
e; ++
i)
2164 NewMI->addOperand(
MBBI->getOperand(
i));
2168 if (
MI.isCandidateForCallSiteEntry())
2169 MI.getMF()->moveCallSiteInfo(&
MI, &*NewMI);
2175 case ARM::tBXNS_RET: {
2178 if (!STI->hasV8_1MMainlineOps() && AFI->shouldSignReturnAddress())
2183 if (STI->hasV8_1MMainlineOps()) {
2186 TII->get(ARM::VLDR_FPCXTNS_post), ARM::SP)
2191 if (AFI->shouldSignReturnAddress())
2197 return !Op.isReg() || Op.getReg() != ARM::R12;
2201 *
MBBI, {ARM::R0, ARM::R1,
ARM::R2, ARM::R3, ARM::R12}, ClearRegs);
2202 CMSEClearGPRegs(AfterBB, AfterBB.
end(),
MBBI->getDebugLoc(), ClearRegs,
2207 TII->get(ARM::tBXNS))
2212 MI.eraseFromParent();
2215 case ARM::tBLXNS_CALL: {
2230 AFI->isThumb1OnlyFunction());
2235 ARM::R5,
ARM::R6, ARM::R7, ARM::R8, ARM::R9,
2236 ARM::R10, ARM::R11, ARM::R12},
2238 auto OriginalClearRegs = ClearRegs;
2242 unsigned ScratchReg = ClearRegs.front();
2245 if (AFI->isThumb2Function()) {
2266 CMSESaveClearFPRegs(
MBB,
MBBI,
DL, LiveRegs,
2268 CMSEClearGPRegs(
MBB,
MBBI,
DL, ClearRegs, JumpReg);
2277 if (
MI.isCandidateForCallSiteEntry())
2280 CMSERestoreFPRegs(
MBB,
MBBI,
DL, OriginalClearRegs);
2284 MI.eraseFromParent();
2289 case ARM::VMOVDcc: {
2290 unsigned newOpc = Opcode != ARM::VMOVDcc ? ARM::VMOVS : ARM::VMOVD;
2292 MI.getOperand(1).getReg())
2293 .
add(
MI.getOperand(2))
2295 .
add(
MI.getOperand(4))
2298 MI.eraseFromParent();
2303 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
2305 MI.getOperand(1).getReg())
2306 .
add(
MI.getOperand(2))
2308 .
add(
MI.getOperand(4))
2312 MI.eraseFromParent();
2315 case ARM::MOVCCsi: {
2317 (
MI.getOperand(1).getReg()))
2318 .
add(
MI.getOperand(2))
2321 .
add(
MI.getOperand(5))
2325 MI.eraseFromParent();
2328 case ARM::MOVCCsr: {
2330 (
MI.getOperand(1).getReg()))
2331 .
add(
MI.getOperand(2))
2332 .
add(
MI.getOperand(3))
2335 .
add(
MI.getOperand(6))
2339 MI.eraseFromParent();
2342 case ARM::t2MOVCCi16:
2343 case ARM::MOVCCi16: {
2344 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
2346 MI.getOperand(1).getReg())
2349 .
add(
MI.getOperand(4))
2351 MI.eraseFromParent();
2356 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
2358 MI.getOperand(1).getReg())
2361 .
add(
MI.getOperand(4))
2365 MI.eraseFromParent();
2370 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
2372 MI.getOperand(1).getReg())
2375 .
add(
MI.getOperand(4))
2379 MI.eraseFromParent();
2382 case ARM::t2MOVCClsl:
2383 case ARM::t2MOVCClsr:
2384 case ARM::t2MOVCCasr:
2385 case ARM::t2MOVCCror: {
2388 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri;
break;
2389 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri;
break;
2390 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri;
break;
2391 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri;
break;
2395 MI.getOperand(1).getReg())
2396 .
add(
MI.getOperand(2))
2399 .
add(
MI.getOperand(5))
2402 MI.eraseFromParent();
2405 case ARM::Int_eh_sjlj_dispatchsetup: {
2414 int32_t NumBytes = AFI->getFramePtrSpillOffset();
2417 "base pointer without frame pointer?");
2419 if (AFI->isThumb2Function()) {
2422 }
else if (AFI->isThumbFunction()) {
2424 FramePtr, -NumBytes, *
TII, RI);
2431 if (RI.hasStackRealignment(MF)) {
2434 assert (!AFI->isThumb1OnlyFunction());
2437 "The BIC instruction cannot encode "
2438 "immediates larger than 256 with all lower "
2440 unsigned bicOpc = AFI->isThumbFunction() ?
2441 ARM::t2BICri : ARM::BICri;
2449 MI.eraseFromParent();
2453 case ARM::MOVsrl_flag:
2454 case ARM::MOVsra_flag: {
2457 MI.getOperand(0).getReg())
2458 .
add(
MI.getOperand(1))
2463 MI.eraseFromParent();
2470 MI.getOperand(0).getReg())
2471 .
add(
MI.getOperand(1))
2475 TransferImpOps(
MI, MIB, MIB);
2476 MI.eraseFromParent();
2481 const bool Thumb = Opcode == ARM::tTPsoft;
2485 if (STI->genLongCalls()) {
2487 unsigned PCLabelID = AFI->createPICLabelUId();
2490 "__aeabi_read_tp", PCLabelID, 0);
2494 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12),
Reg)
2515 TransferImpOps(
MI, MIB, MIB);
2517 if (
MI.isCandidateForCallSiteEntry())
2519 MI.eraseFromParent();
2522 case ARM::tLDRpci_pic:
2523 case ARM::t2LDRpci_pic: {
2524 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
2525 ? ARM::tLDRpci : ARM::t2LDRpci;
2527 bool DstIsDead =
MI.getOperand(0).isDead();
2530 .
add(
MI.getOperand(1))
2537 .
add(
MI.getOperand(2));
2538 TransferImpOps(
MI, MIB1, MIB2);
2539 MI.eraseFromParent();
2543 case ARM::LDRLIT_ga_abs:
2544 case ARM::LDRLIT_ga_pcrel:
2545 case ARM::LDRLIT_ga_pcrel_ldr:
2546 case ARM::tLDRLIT_ga_abs:
2547 case ARM::t2LDRLIT_ga_pcrel:
2548 case ARM::tLDRLIT_ga_pcrel: {
2550 bool DstIsDead =
MI.getOperand(0).isDead();
2554 bool IsARM = Opcode != ARM::tLDRLIT_ga_pcrel &&
2555 Opcode != ARM::tLDRLIT_ga_abs &&
2556 Opcode != ARM::t2LDRLIT_ga_pcrel;
2558 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
2559 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
2560 if (Opcode == ARM::t2LDRLIT_ga_pcrel)
2561 LDRLITOpc = ARM::t2LDRpci;
2562 unsigned PICAddOpc =
2564 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
2569 unsigned ARMPCLabelIndex = 0;
2573 unsigned PCAdj = IsARM ? 8 : 4;
2577 ARMPCLabelIndex = AFI->createPICLabelUId();
2596 .
addImm(ARMPCLabelIndex);
2602 MI.eraseFromParent();
2605 case ARM::MOV_ga_pcrel:
2606 case ARM::MOV_ga_pcrel_ldr:
2607 case ARM::t2MOV_ga_pcrel: {
2609 unsigned LabelId = AFI->createPICLabelUId();
2611 bool DstIsDead =
MI.getOperand(0).isDead();
2615 bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
2616 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
2617 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
2620 unsigned PICAddOpc = isARM
2621 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
2624 TII->get(LO16Opc), DstReg)
2634 TII->get(PICAddOpc))
2639 if (Opcode == ARM::MOV_ga_pcrel_ldr)
2642 TransferImpOps(
MI, MIB1, MIB3);
2643 MI.eraseFromParent();
2647 case ARM::MOVi32imm:
2648 case ARM::MOVCCi32imm:
2649 case ARM::t2MOVi32imm:
2650 case ARM::t2MOVCCi32imm:
2654 case ARM::SUBS_PC_LR: {
2658 .
add(
MI.getOperand(0))
2659 .
add(
MI.getOperand(1))
2660 .
add(
MI.getOperand(2))
2662 TransferImpOps(
MI, MIB, MIB);
2663 MI.eraseFromParent();
2666 case ARM::VLDMQIA: {
2667 unsigned NewOpc = ARM::VLDMDIA;
2673 bool DstIsDead =
MI.getOperand(OpIdx).isDead();
2674 Register DstReg =
MI.getOperand(OpIdx++).getReg();
2677 MIB.
add(
MI.getOperand(OpIdx++));
2680 MIB.
add(
MI.getOperand(OpIdx++));
2681 MIB.
add(
MI.getOperand(OpIdx++));
2691 TransferImpOps(
MI, MIB, MIB);
2693 MI.eraseFromParent();
2697 case ARM::VSTMQIA: {
2698 unsigned NewOpc = ARM::VSTMDIA;
2704 bool SrcIsKill =
MI.getOperand(OpIdx).isKill();
2705 Register SrcReg =
MI.getOperand(OpIdx++).getReg();
2712 MIB.
add(
MI.getOperand(OpIdx++));
2713 MIB.
add(
MI.getOperand(OpIdx++));
2724 TransferImpOps(
MI, MIB, MIB);
2726 MI.eraseFromParent();
2730 case ARM::VLD2q8Pseudo:
2731 case ARM::VLD2q16Pseudo:
2732 case ARM::VLD2q32Pseudo:
2733 case ARM::VLD2q8PseudoWB_fixed:
2734 case ARM::VLD2q16PseudoWB_fixed:
2735 case ARM::VLD2q32PseudoWB_fixed:
2736 case ARM::VLD2q8PseudoWB_register:
2737 case ARM::VLD2q16PseudoWB_register:
2738 case ARM::VLD2q32PseudoWB_register:
2739 case ARM::VLD3d8Pseudo:
2740 case ARM::VLD3d16Pseudo:
2741 case ARM::VLD3d32Pseudo:
2742 case ARM::VLD1d8TPseudo:
2743 case ARM::VLD1d8TPseudoWB_fixed:
2744 case ARM::VLD1d8TPseudoWB_register:
2745 case ARM::VLD1d16TPseudo:
2746 case ARM::VLD1d16TPseudoWB_fixed:
2747 case ARM::VLD1d16TPseudoWB_register:
2748 case ARM::VLD1d32TPseudo:
2749 case ARM::VLD1d32TPseudoWB_fixed:
2750 case ARM::VLD1d32TPseudoWB_register:
2751 case ARM::VLD1d64TPseudo:
2752 case ARM::VLD1d64TPseudoWB_fixed:
2753 case ARM::VLD1d64TPseudoWB_register:
2754 case ARM::VLD3d8Pseudo_UPD:
2755 case ARM::VLD3d16Pseudo_UPD:
2756 case ARM::VLD3d32Pseudo_UPD:
2757 case ARM::VLD3q8Pseudo_UPD:
2758 case ARM::VLD3q16Pseudo_UPD:
2759 case ARM::VLD3q32Pseudo_UPD:
2760 case ARM::VLD3q8oddPseudo:
2761 case ARM::VLD3q16oddPseudo:
2762 case ARM::VLD3q32oddPseudo:
2763 case ARM::VLD3q8oddPseudo_UPD:
2764 case ARM::VLD3q16oddPseudo_UPD:
2765 case ARM::VLD3q32oddPseudo_UPD:
2766 case ARM::VLD4d8Pseudo:
2767 case ARM::VLD4d16Pseudo:
2768 case ARM::VLD4d32Pseudo:
2769 case ARM::VLD1d8QPseudo:
2770 case ARM::VLD1d8QPseudoWB_fixed:
2771 case ARM::VLD1d8QPseudoWB_register:
2772 case ARM::VLD1d16QPseudo:
2773 case ARM::VLD1d16QPseudoWB_fixed:
2774 case ARM::VLD1d16QPseudoWB_register:
2775 case ARM::VLD1d32QPseudo:
2776 case ARM::VLD1d32QPseudoWB_fixed:
2777 case ARM::VLD1d32QPseudoWB_register:
2778 case ARM::VLD1d64QPseudo:
2779 case ARM::VLD1d64QPseudoWB_fixed:
2780 case ARM::VLD1d64QPseudoWB_register:
2781 case ARM::VLD1q8HighQPseudo:
2782 case ARM::VLD1q8HighQPseudo_UPD:
2783 case ARM::VLD1q8LowQPseudo_UPD:
2784 case ARM::VLD1q8HighTPseudo:
2785 case ARM::VLD1q8HighTPseudo_UPD:
2786 case ARM::VLD1q8LowTPseudo_UPD:
2787 case ARM::VLD1q16HighQPseudo:
2788 case ARM::VLD1q16HighQPseudo_UPD:
2789 case ARM::VLD1q16LowQPseudo_UPD:
2790 case ARM::VLD1q16HighTPseudo:
2791 case ARM::VLD1q16HighTPseudo_UPD:
2792 case ARM::VLD1q16LowTPseudo_UPD:
2793 case ARM::VLD1q32HighQPseudo:
2794 case ARM::VLD1q32HighQPseudo_UPD:
2795 case ARM::VLD1q32LowQPseudo_UPD:
2796 case ARM::VLD1q32HighTPseudo:
2797 case ARM::VLD1q32HighTPseudo_UPD:
2798 case ARM::VLD1q32LowTPseudo_UPD:
2799 case ARM::VLD1q64HighQPseudo:
2800 case ARM::VLD1q64HighQPseudo_UPD:
2801 case ARM::VLD1q64LowQPseudo_UPD:
2802 case ARM::VLD1q64HighTPseudo:
2803 case ARM::VLD1q64HighTPseudo_UPD:
2804 case ARM::VLD1q64LowTPseudo_UPD:
2805 case ARM::VLD4d8Pseudo_UPD:
2806 case ARM::VLD4d16Pseudo_UPD:
2807 case ARM::VLD4d32Pseudo_UPD:
2808 case ARM::VLD4q8Pseudo_UPD:
2809 case ARM::VLD4q16Pseudo_UPD:
2810 case ARM::VLD4q32Pseudo_UPD:
2811 case ARM::VLD4q8oddPseudo:
2812 case ARM::VLD4q16oddPseudo:
2813 case ARM::VLD4q32oddPseudo:
2814 case ARM::VLD4q8oddPseudo_UPD:
2815 case ARM::VLD4q16oddPseudo_UPD:
2816 case ARM::VLD4q32oddPseudo_UPD:
2817 case ARM::VLD3DUPd8Pseudo:
2818 case ARM::VLD3DUPd16Pseudo:
2819 case ARM::VLD3DUPd32Pseudo:
2820 case ARM::VLD3DUPd8Pseudo_UPD:
2821 case ARM::VLD3DUPd16Pseudo_UPD:
2822 case ARM::VLD3DUPd32Pseudo_UPD:
2823 case ARM::VLD4DUPd8Pseudo:
2824 case ARM::VLD4DUPd16Pseudo:
2825 case ARM::VLD4DUPd32Pseudo:
2826 case ARM::VLD4DUPd8Pseudo_UPD:
2827 case ARM::VLD4DUPd16Pseudo_UPD:
2828 case ARM::VLD4DUPd32Pseudo_UPD:
2829 case ARM::VLD2DUPq8EvenPseudo:
2830 case ARM::VLD2DUPq8OddPseudo:
2831 case ARM::VLD2DUPq16EvenPseudo:
2832 case ARM::VLD2DUPq16OddPseudo:
2833 case ARM::VLD2DUPq32EvenPseudo:
2834 case ARM::VLD2DUPq32OddPseudo:
2835 case ARM::VLD2DUPq8OddPseudoWB_fixed:
2836 case ARM::VLD2DUPq8OddPseudoWB_register:
2837 case ARM::VLD2DUPq16OddPseudoWB_fixed:
2838 case ARM::VLD2DUPq16OddPseudoWB_register:
2839 case ARM::VLD2DUPq32OddPseudoWB_fixed:
2840 case ARM::VLD2DUPq32OddPseudoWB_register:
2841 case ARM::VLD3DUPq8EvenPseudo:
2842 case ARM::VLD3DUPq8OddPseudo:
2843 case ARM::VLD3DUPq16EvenPseudo:
2844 case ARM::VLD3DUPq16OddPseudo:
2845 case ARM::VLD3DUPq32EvenPseudo:
2846 case ARM::VLD3DUPq32OddPseudo:
2847 case ARM::VLD3DUPq8OddPseudo_UPD:
2848 case ARM::VLD3DUPq16OddPseudo_UPD:
2849 case ARM::VLD3DUPq32OddPseudo_UPD:
2850 case ARM::VLD4DUPq8EvenPseudo:
2851 case ARM::VLD4DUPq8OddPseudo:
2852 case ARM::VLD4DUPq16EvenPseudo:
2853 case ARM::VLD4DUPq16OddPseudo:
2854 case ARM::VLD4DUPq32EvenPseudo:
2855 case ARM::VLD4DUPq32OddPseudo:
2856 case ARM::VLD4DUPq8OddPseudo_UPD:
2857 case ARM::VLD4DUPq16OddPseudo_UPD:
2858 case ARM::VLD4DUPq32OddPseudo_UPD:
2862 case ARM::VST2q8Pseudo:
2863 case ARM::VST2q16Pseudo:
2864 case ARM::VST2q32Pseudo:
2865 case ARM::VST2q8PseudoWB_fixed:
2866 case ARM::VST2q16PseudoWB_fixed:
2867 case ARM::VST2q32PseudoWB_fixed:
2868 case ARM::VST2q8PseudoWB_register:
2869 case ARM::VST2q16PseudoWB_register:
2870 case ARM::VST2q32PseudoWB_register:
2871 case ARM::VST3d8Pseudo:
2872 case ARM::VST3d16Pseudo:
2873 case ARM::VST3d32Pseudo:
2874 case ARM::VST1d8TPseudo:
2875 case ARM::VST1d8TPseudoWB_fixed:
2876 case ARM::VST1d8TPseudoWB_register:
2877 case ARM::VST1d16TPseudo:
2878 case ARM::VST1d16TPseudoWB_fixed:
2879 case ARM::VST1d16TPseudoWB_register:
2880 case ARM::VST1d32TPseudo:
2881 case ARM::VST1d32TPseudoWB_fixed:
2882 case ARM::VST1d32TPseudoWB_register:
2883 case ARM::VST1d64TPseudo:
2884 case ARM::VST1d64TPseudoWB_fixed:
2885 case ARM::VST1d64TPseudoWB_register:
2886 case ARM::VST3d8Pseudo_UPD:
2887 case ARM::VST3d16Pseudo_UPD:
2888 case ARM::VST3d32Pseudo_UPD:
2889 case ARM::VST3q8Pseudo_UPD:
2890 case ARM::VST3q16Pseudo_UPD:
2891 case ARM::VST3q32Pseudo_UPD:
2892 case ARM::VST3q8oddPseudo:
2893 case ARM::VST3q16oddPseudo:
2894 case ARM::VST3q32oddPseudo:
2895 case ARM::VST3q8oddPseudo_UPD:
2896 case ARM::VST3q16oddPseudo_UPD:
2897 case ARM::VST3q32oddPseudo_UPD:
2898 case ARM::VST4d8Pseudo:
2899 case ARM::VST4d16Pseudo:
2900 case ARM::VST4d32Pseudo:
2901 case ARM::VST1d8QPseudo:
2902 case ARM::VST1d8QPseudoWB_fixed:
2903 case ARM::VST1d8QPseudoWB_register:
2904 case ARM::VST1d16QPseudo:
2905 case ARM::VST1d16QPseudoWB_fixed:
2906 case ARM::VST1d16QPseudoWB_register:
2907 case ARM::VST1d32QPseudo:
2908 case ARM::VST1d32QPseudoWB_fixed:
2909 case ARM::VST1d32QPseudoWB_register:
2910 case ARM::VST1d64QPseudo:
2911 case ARM::VST1d64QPseudoWB_fixed:
2912 case ARM::VST1d64QPseudoWB_register:
2913 case ARM::VST4d8Pseudo_UPD:
2914 case ARM::VST4d16Pseudo_UPD:
2915 case ARM::VST4d32Pseudo_UPD:
2916 case ARM::VST1q8HighQPseudo:
2917 case ARM::VST1q8LowQPseudo_UPD:
2918 case ARM::VST1q8HighTPseudo:
2919 case ARM::VST1q8LowTPseudo_UPD:
2920 case ARM::VST1q16HighQPseudo:
2921 case ARM::VST1q16LowQPseudo_UPD:
2922 case ARM::VST1q16HighTPseudo:
2923 case ARM::VST1q16LowTPseudo_UPD:
2924 case ARM::VST1q32HighQPseudo:
2925 case ARM::VST1q32LowQPseudo_UPD:
2926 case ARM::VST1q32HighTPseudo:
2927 case ARM::VST1q32LowTPseudo_UPD:
2928 case ARM::VST1q64HighQPseudo:
2929 case ARM::VST1q64LowQPseudo_UPD:
2930 case ARM::VST1q64HighTPseudo:
2931 case ARM::VST1q64LowTPseudo_UPD:
2932 case ARM::VST1q8HighTPseudo_UPD:
2933 case ARM::VST1q16HighTPseudo_UPD:
2934 case ARM::VST1q32HighTPseudo_UPD:
2935 case ARM::VST1q64HighTPseudo_UPD:
2936 case ARM::VST1q8HighQPseudo_UPD:
2937 case ARM::VST1q16HighQPseudo_UPD:
2938 case ARM::VST1q32HighQPseudo_UPD:
2939 case ARM::VST1q64HighQPseudo_UPD:
2940 case ARM::VST4q8Pseudo_UPD:
2941 case ARM::VST4q16Pseudo_UPD:
2942 case ARM::VST4q32Pseudo_UPD:
2943 case ARM::VST4q8oddPseudo:
2944 case ARM::VST4q16oddPseudo:
2945 case ARM::VST4q32oddPseudo:
2946 case ARM::VST4q8oddPseudo_UPD:
2947 case ARM::VST4q16oddPseudo_UPD:
2948 case ARM::VST4q32oddPseudo_UPD:
2952 case ARM::VLD1LNq8Pseudo:
2953 case ARM::VLD1LNq16Pseudo:
2954 case ARM::VLD1LNq32Pseudo:
2955 case ARM::VLD1LNq8Pseudo_UPD:
2956 case ARM::VLD1LNq16Pseudo_UPD:
2957 case ARM::VLD1LNq32Pseudo_UPD:
2958 case ARM::VLD2LNd8Pseudo:
2959 case ARM::VLD2LNd16Pseudo:
2960 case ARM::VLD2LNd32Pseudo:
2961 case ARM::VLD2LNq16Pseudo:
2962 case ARM::VLD2LNq32Pseudo:
2963 case ARM::VLD2LNd8Pseudo_UPD:
2964 case ARM::VLD2LNd16Pseudo_UPD:
2965 case ARM::VLD2LNd32Pseudo_UPD:
2966 case ARM::VLD2LNq16Pseudo_UPD:
2967 case ARM::VLD2LNq32Pseudo_UPD:
2968 case ARM::VLD3LNd8Pseudo:
2969 case ARM::VLD3LNd16Pseudo:
2970 case ARM::VLD3LNd32Pseudo:
2971 case ARM::VLD3LNq16Pseudo:
2972 case ARM::VLD3LNq32Pseudo:
2973 case ARM::VLD3LNd8Pseudo_UPD:
2974 case ARM::VLD3LNd16Pseudo_UPD:
2975 case ARM::VLD3LNd32Pseudo_UPD:
2976 case ARM::VLD3LNq16Pseudo_UPD:
2977 case ARM::VLD3LNq32Pseudo_UPD:
2978 case ARM::VLD4LNd8Pseudo:
2979 case ARM::VLD4LNd16Pseudo:
2980 case ARM::VLD4LNd32Pseudo:
2981 case ARM::VLD4LNq16Pseudo:
2982 case ARM::VLD4LNq32Pseudo:
2983 case ARM::VLD4LNd8Pseudo_UPD:
2984 case ARM::VLD4LNd16Pseudo_UPD:
2985 case ARM::VLD4LNd32Pseudo_UPD:
2986 case ARM::VLD4LNq16Pseudo_UPD:
2987 case ARM::VLD4LNq32Pseudo_UPD:
2988 case ARM::VST1LNq8Pseudo:
2989 case ARM::VST1LNq16Pseudo:
2990 case ARM::VST1LNq32Pseudo:
2991 case ARM::VST1LNq8Pseudo_UPD:
2992 case ARM::VST1LNq16Pseudo_UPD:
2993 case ARM::VST1LNq32Pseudo_UPD:
2994 case ARM::VST2LNd8Pseudo:
2995 case ARM::VST2LNd16Pseudo:
2996 case ARM::VST2LNd32Pseudo:
2997 case ARM::VST2LNq16Pseudo:
2998 case ARM::VST2LNq32Pseudo:
2999 case ARM::VST2LNd8Pseudo_UPD:
3000 case ARM::VST2LNd16Pseudo_UPD:
3001 case ARM::VST2LNd32Pseudo_UPD:
3002 case ARM::VST2LNq16Pseudo_UPD:
3003 case ARM::VST2LNq32Pseudo_UPD:
3004 case ARM::VST3LNd8Pseudo:
3005 case ARM::VST3LNd16Pseudo:
3006 case ARM::VST3LNd32Pseudo:
3007 case ARM::VST3LNq16Pseudo:
3008 case ARM::VST3LNq32Pseudo:
3009 case ARM::VST3LNd8Pseudo_UPD:
3010 case ARM::VST3LNd16Pseudo_UPD:
3011 case ARM::VST3LNd32Pseudo_UPD:
3012 case ARM::VST3LNq16Pseudo_UPD:
3013 case ARM::VST3LNq32Pseudo_UPD:
3014 case ARM::VST4LNd8Pseudo:
3015 case ARM::VST4LNd16Pseudo:
3016 case ARM::VST4LNd32Pseudo:
3017 case ARM::VST4LNq16Pseudo:
3018 case ARM::VST4LNq32Pseudo:
3019 case ARM::VST4LNd8Pseudo_UPD:
3020 case ARM::VST4LNd16Pseudo_UPD:
3021 case ARM::VST4LNd32Pseudo_UPD:
3022 case ARM::VST4LNq16Pseudo_UPD:
3023 case ARM::VST4LNq32Pseudo_UPD:
3027 case ARM::VTBL3Pseudo: ExpandVTBL(
MBBI, ARM::VTBL3,
false);
return true;
3028 case ARM::VTBL4Pseudo: ExpandVTBL(
MBBI, ARM::VTBL4,
false);
return true;
3029 case ARM::VTBX3Pseudo: ExpandVTBL(
MBBI, ARM::VTBX3,
true);
return true;
3030 case ARM::VTBX4Pseudo: ExpandVTBL(
MBBI, ARM::VTBX4,
true);
return true;
3032 case ARM::MQQPRLoad:
3033 case ARM::MQQPRStore:
3034 case ARM::MQQQQPRLoad:
3035 case ARM::MQQQQPRStore:
3036 ExpandMQQPRLoadStore(
MBBI);
3039 case ARM::tCMP_SWAP_8:
3041 return ExpandCMP_SWAP(
MBB,
MBBI, ARM::t2LDREXB, ARM::t2STREXB, ARM::tUXTB,
3043 case ARM::tCMP_SWAP_16:
3045 return ExpandCMP_SWAP(
MBB,
MBBI, ARM::t2LDREXH, ARM::t2STREXH, ARM::tUXTH,
3048 case ARM::CMP_SWAP_8:
3052 case ARM::CMP_SWAP_16:
3056 case ARM::CMP_SWAP_32:
3058 return ExpandCMP_SWAP(
MBB,
MBBI, ARM::t2LDREX, ARM::t2STREX, 0,
3061 return ExpandCMP_SWAP(
MBB,
MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
3063 case ARM::CMP_SWAP_64:
3064 return ExpandCMP_SWAP_64(
MBB,
MBBI, NextMBBI);
3066 case ARM::tBL_PUSHLR:
3067 case ARM::BL_PUSHLR: {
3068 const bool Thumb = Opcode == ARM::tBL_PUSHLR;
3070 assert(
Reg == ARM::LR &&
"expect LR register!");
3094 MI.eraseFromParent();
3102 for (
unsigned i = 0;
i <
MI.getNumOperands(); ++
i)
3103 MIB.
add(
MI.getOperand(
i));
3104 if (
MI.isCandidateForCallSiteEntry())
3107 Bundler.append(MIB);
3108 Bundler.append(
BuildMI(MF,
MI.getDebugLoc(),
TII->get(ARM::t2BTI)));
3110 MI.eraseFromParent();
3114 case ARM::STOREDUAL: {
3115 Register PairReg =
MI.getOperand(0).getReg();
3128 MI.eraseFromParent();
3149 TII = STI->getInstrInfo();
3150 TRI = STI->getRegisterInfo();
3153 LLVM_DEBUG(
dbgs() <<
"********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n"
3154 <<
"********** Function: " << MF.
getName() <<
'\n');
3160 MF.verify(
this,
"After expanding ARM pseudo instructions.");
3162 LLVM_DEBUG(
dbgs() <<
"***************************************************\n");
3169 return new ARMExpandPseudo();