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23 #define GET_INSTRINFO_CTOR_DTOR
24 #include "BPFGenInstrInfo.inc"
35 if (BPF::GPRRegClass.
contains(DestReg, SrcReg))
38 else if (BPF::GPR32RegClass.
contains(DestReg, SrcReg))
49 uint64_t Alignment =
MI->getOperand(3).getImm();
50 Register ScratchReg =
MI->getOperand(4).getReg();
53 unsigned LdOpc, StOpc;
76 unsigned IterationNum = CopyLen >>
Log2_64(Alignment);
77 for(
unsigned I = 0;
I < IterationNum; ++
I) {
86 unsigned BytesLeft = CopyLen & (
Alignment - 1);
88 bool Hanging4Byte = BytesLeft & 0x4;
89 bool Hanging2Byte = BytesLeft & 0x2;
90 bool Hanging1Byte = BytesLeft & 0x1;
126 Register SrcReg,
bool IsKill,
int FI,
131 DL =
I->getDebugLoc();
133 if (RC == &BPF::GPRRegClass)
138 else if (RC == &BPF::GPR32RegClass)
154 DL =
I->getDebugLoc();
156 if (RC == &BPF::GPRRegClass)
158 else if (RC == &BPF::GPR32RegClass)
168 bool AllowModify)
const {
174 if (
I->isDebugInstr())
179 if (!isUnpredicatedTerminator(*
I))
188 if (
I->getOpcode() == BPF::JMP) {
190 TBB =
I->getOperand(0).getMBB();
202 I->eraseFromParent();
208 TBB =
I->getOperand(0).getMBB();
223 int *BytesAdded)
const {
224 assert(!BytesAdded &&
"code size not handled");
227 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
231 assert(!FBB &&
"Unconditional branch with multiple successors!");
240 int *BytesRemoved)
const {
241 assert(!BytesRemoved &&
"code size not handled");
248 if (
I->isDebugInstr())
250 if (
I->getOpcode() != BPF::JMP)
253 I->eraseFromParent();
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
return AArch64::GPR64RegClass contains(Reg)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned const TargetRegisterInfo * TRI
bool expandPostRAPseudo(MachineInstr &MI) const override
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
@ Kill
The last use of a register.
const MachineInstrBuilder & addFrameIndex(int Idx) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Representation of each machine instruction.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
SmallVector< MachineOperand, 4 > Cond
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Wrapper class representing virtual and physical registers.
Should compile to something r4 addze r3 instead we get
@ Define
Register definition.
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
unsigned getKillRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Wrapper class representing physical registers. Should be passed by value.