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38 #define DEBUG_TYPE "xcore-reg-info"
40 #define GET_REGINFO_TARGET_DESC
41 #include "XCoreGenRegisterInfo.inc"
53 return val < (1 << 6);
57 return val < (1 << 16);
63 unsigned Reg,
unsigned FrameReg,
int Offset ) {
68 switch (
MI.getOpcode()) {
94 unsigned Reg,
unsigned FrameReg,
96 assert(RS &&
"requiresRegisterScavenging failed");
104 switch (
MI.getOpcode()) {
136 switch (
MI.getOpcode()) {
139 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
145 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
152 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
164 assert(RS &&
"requiresRegisterScavenging failed");
168 unsigned OpCode =
MI.getOpcode();
170 unsigned ScratchBase;
171 if (OpCode==XCore::STWFI) {
213 static const MCPhysReg CalleeSavedRegs[] = {
215 XCore::R8, XCore::R9, XCore::R10,
218 static const MCPhysReg CalleeSavedRegsFP[] = {
220 XCore::R8, XCore::R9,
225 return CalleeSavedRegsFP;
226 return CalleeSavedRegs;
237 if (TFI->
hasFP(MF)) {
255 int SPAdj,
unsigned FIOperandNum,
257 assert(SPAdj == 0 &&
"Unexpected");
284 if (
MI.isDebugValue()) {
285 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg,
false );
286 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(
Offset);
291 Offset +=
MI.getOperand(FIOperandNum + 1).getImm();
292 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
302 if (TFI->
hasFP(MF)) {
323 return TFI->
hasFP(MF) ? XCore::R10 : XCore::SP;
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
virtual const TargetInstrInfo * getInstrInfo() const
return AArch64::GPR64RegClass contains(Reg)
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
BitVector getReservedRegs(const MachineFunction &MF) const override
Reg
All possible values of the reg field in the ModR/M byte.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
static bool needsFrameMoves(const MachineFunction &MF)
Return whether to emit frame moves.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Register scavengeRegister(const TargetRegisterClass *RC, MachineBasicBlock::iterator I, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available and do the appropriate bookkeeping.
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The initial backend is deliberately restricted to z10 We should add support for later architectures at some point If an asm ties an i32 r result to an i64 the input will be treated as an leaving the upper bits uninitialised For i64 store i32 val
Representation of each machine instruction.
static void InsertSPImmInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, int Offset)
Register getFrameRegister(const MachineFunction &MF) const override
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static void InsertFPConstInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset, RegScavenger *RS)
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static bool isImmU6(unsigned val)
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store load store see def memrix16 in PPCInstrInfo td Load Store Vector load store outs ins lxsdx set load store with conversion from to DP
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Wrapper class representing virtual and physical registers.
static bool isImmU16(unsigned val)
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
static bool isImmUs(unsigned val)
static void InsertFPImmInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset)
@ Kill
The last use of a register.
unsigned getKillRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static void InsertSPConstInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, int Offset, RegScavenger *RS)
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool useFPForScavengingIndex(const MachineFunction &MF) const override