LLVM  14.0.0git
XCoreInstrInfo.h
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1 //===-- XCoreInstrInfo.h - XCore Instruction Information --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the XCore implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
14 #define LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
15 
16 #include "XCoreRegisterInfo.h"
18 
19 #define GET_INSTRINFO_HEADER
20 #include "XCoreGenInstrInfo.inc"
21 
22 namespace llvm {
23 
25  const XCoreRegisterInfo RI;
26  virtual void anchor();
27 public:
29 
30  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
31  /// such, whenever a client has an instance of instruction info, it should
32  /// always be able to get register info as well (through this method).
33  ///
34  const TargetRegisterInfo &getRegisterInfo() const { return RI; }
35 
36  /// isLoadFromStackSlot - If the specified machine instruction is a direct
37  /// load from a stack slot, return the virtual or physical register number of
38  /// the destination along with the FrameIndex of the loaded stack slot. If
39  /// not, return 0. This predicate must return 0 if the instruction has
40  /// any side effects other than loading from the stack slot.
41  unsigned isLoadFromStackSlot(const MachineInstr &MI,
42  int &FrameIndex) const override;
43 
44  /// isStoreToStackSlot - If the specified machine instruction is a direct
45  /// store to a stack slot, return the virtual or physical register number of
46  /// the source reg along with the FrameIndex of the loaded stack slot. If
47  /// not, return 0. This predicate must return 0 if the instruction has
48  /// any side effects other than storing to the stack slot.
49  unsigned isStoreToStackSlot(const MachineInstr &MI,
50  int &FrameIndex) const override;
51 
53  MachineBasicBlock *&FBB,
55  bool AllowModify) const override;
56 
59  const DebugLoc &DL,
60  int *BytesAdded = nullptr) const override;
61 
63  int *BytesRemoved = nullptr) const override;
64 
66  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
67  bool KillSrc) const override;
68 
71  Register SrcReg, bool isKill, int FrameIndex,
72  const TargetRegisterClass *RC,
73  const TargetRegisterInfo *TRI) const override;
74 
77  Register DestReg, int FrameIndex,
78  const TargetRegisterClass *RC,
79  const TargetRegisterInfo *TRI) const override;
80 
82  SmallVectorImpl<MachineOperand> &Cond) const override;
83 
84  // Emit code before MBBI to load immediate value into physical register Reg.
85  // Returns an iterator to the new instruction.
88  unsigned Reg, uint64_t Value) const;
89 };
90 
91 }
92 
93 #endif
llvm::XCoreInstrInfo::loadImmediate
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
Definition: XCoreInstrInfo.cpp:426
XCoreRegisterInfo.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm::XCoreInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: XCoreInstrInfo.cpp:358
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::XCoreInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: XCoreInstrInfo.cpp:331
llvm::XCoreInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
analyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
Definition: XCoreInstrInfo.cpp:189
llvm::XCoreInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
Definition: XCoreInstrInfo.cpp:82
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
TargetInstrInfo.h
llvm::XCoreInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: XCoreInstrInfo.cpp:306
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::XCoreInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: XCoreInstrInfo.cpp:271
llvm::XCoreInstrInfo
Definition: XCoreInstrInfo.h:24
llvm::XCoreRegisterInfo
Definition: XCoreRegisterInfo.h:23
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::XCoreInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: XCoreInstrInfo.cpp:381
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::XCoreInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
Definition: XCoreInstrInfo.cpp:62
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::XCoreInstrInfo::getRegisterInfo
const TargetRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: XCoreInstrInfo.h:34
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
XCoreGenInstrInfo
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::XCoreInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: XCoreInstrInfo.cpp:403
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::XCoreInstrInfo::XCoreInstrInfo
XCoreInstrInfo()
Definition: XCoreInstrInfo.cpp:48
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23