LLVM 22.0.0git
XCoreInstrInfo.h
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1//===-- XCoreInstrInfo.h - XCore Instruction Information --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the XCore implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
14#define LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
15
16#include "XCoreRegisterInfo.h"
18
19#define GET_INSTRINFO_HEADER
20#include "XCoreGenInstrInfo.inc"
21
22namespace llvm {
23class XCoreSubtarget;
24
26 const XCoreRegisterInfo RI;
27 virtual void anchor();
28public:
29 explicit XCoreInstrInfo(const XCoreSubtarget &ST);
30
31 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
32 /// such, whenever a client has an instance of instruction info, it should
33 /// always be able to get register info as well (through this method).
34 ///
35 const TargetRegisterInfo &getRegisterInfo() const { return RI; }
36
37 /// isLoadFromStackSlot - If the specified machine instruction is a direct
38 /// load from a stack slot, return the virtual or physical register number of
39 /// the destination along with the FrameIndex of the loaded stack slot. If
40 /// not, return 0. This predicate must return 0 if the instruction has
41 /// any side effects other than loading from the stack slot.
43 int &FrameIndex) const override;
44
45 /// isStoreToStackSlot - If the specified machine instruction is a direct
46 /// store to a stack slot, return the virtual or physical register number of
47 /// the source reg along with the FrameIndex of the loaded stack slot. If
48 /// not, return 0. This predicate must return 0 if the instruction has
49 /// any side effects other than storing to the stack slot.
51 int &FrameIndex) const override;
52
56 bool AllowModify) const override;
57
60 const DebugLoc &DL,
61 int *BytesAdded = nullptr) const override;
62
64 int *BytesRemoved = nullptr) const override;
65
67 const DebugLoc &DL, Register DestReg, Register SrcReg,
68 bool KillSrc, bool RenamableDest = false,
69 bool RenamableSrc = false) const override;
70
73 bool isKill, int FrameIndex, const TargetRegisterClass *RC,
74 const TargetRegisterInfo *TRI, Register VReg,
75 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
76
79 int FrameIndex, const TargetRegisterClass *RC,
80 const TargetRegisterInfo *TRI, Register VReg,
81 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
82
85
86 // Emit code before MBBI to load immediate value into physical register Reg.
87 // Returns an iterator to the new instruction.
90 unsigned Reg, uint64_t Value) const;
91};
92
93}
94
95#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition MD5.cpp:58
Register Reg
Register const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
A debug info location.
Definition DebugLoc.h:124
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
Wrapper class representing virtual and physical registers.
Definition Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
Definition Value.h:75
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
analyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
const TargetRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
XCoreInstrInfo(const XCoreSubtarget &ST)
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
This is an optimization pass for GlobalISel generic memory operations.