#include "Target/XCore/XCoreInstrInfo.h"

Inheritance diagram for llvm::XCoreInstrInfo:

Public Member Functions
	XCoreInstrInfo (const XCoreSubtarget &ST)
const TargetRegisterInfo &	getRegisterInfo () const
	getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Register	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
	isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.
Register	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
	isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.
bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
	analyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g.
unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock TBB, MachineBasicBlock FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
MachineBasicBlock::iterator	loadImmediate (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const

Detailed Description

Definition at line 25 of file XCoreInstrInfo.h.

Constructor & Destructor Documentation

◆ XCoreInstrInfo()

XCoreInstrInfo::XCoreInstrInfo ( const XCoreSubtarget & ST )

explicit

Definition at line 45 of file XCoreInstrInfo.cpp.

Member Function Documentation

◆ analyzeBranch()

bool XCoreInstrInfo::analyzeBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *&	TBB,
		MachineBasicBlock *&	FBB,
		SmallVectorImpl< MachineOperand > &	Cond,
		bool	AllowModify ) const

override

analyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g.

it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:

If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null.
If this block ends with only an unconditional branch, it sets TBB to be the destination block.
If this block ends with an conditional branch and it falls through to an successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
If this block ends with an conditional branch and an unconditional block, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.

Note that removeBranch and insertBranch must be implemented to support cases where this method returns success.

Definition at line 185 of file XCoreInstrInfo.cpp.

References Cond, llvm::XCore::COND_INVALID, llvm::MachineOperand::CreateImm(), GetCondFromBranchOpc(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, IsBR_JT(), IsBRU(), MBB, and TBB.

◆ copyPhysReg()

void XCoreInstrInfo::copyPhysReg	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		Register	DestReg,
		Register	SrcReg,
		bool	KillSrc,
		bool	RenamableDest = false,
		bool	RenamableSrc = false ) const

override

Definition at line 327 of file XCoreInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::get(), llvm::getKillRegState(), I, llvm_unreachable, and MBB.

◆ getRegisterInfo()

const TargetRegisterInfo & llvm::XCoreInstrInfo::getRegisterInfo ( ) const

inline

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 35 of file XCoreInstrInfo.h.

◆ insertBranch()

unsigned XCoreInstrInfo::insertBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *	TBB,
		MachineBasicBlock *	FBB,
		ArrayRef< MachineOperand >	Cond,
		const DebugLoc &	DL,
		int *	BytesAdded = nullptr ) const

override

Definition at line 267 of file XCoreInstrInfo.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), Cond, DL, llvm::get(), GetCondBranchFromCond(), llvm::getImm(), getReg(), MBB, Opc, and TBB.

◆ isLoadFromStackSlot()

Register XCoreInstrInfo::isLoadFromStackSlot	(	const MachineInstr &	MI,
		int &	FrameIndex ) const

override

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Definition at line 58 of file XCoreInstrInfo.cpp.

References isZeroImm(), and MI.

◆ isStoreToStackSlot()

Register XCoreInstrInfo::isStoreToStackSlot	(	const MachineInstr &	MI,
		int &	FrameIndex ) const

override

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Definition at line 78 of file XCoreInstrInfo.cpp.

References isZeroImm(), and MI.

◆ loadImmediate()

MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		unsigned	Reg,
		uint64_t	Value ) const

Definition at line 422 of file XCoreInstrInfo.cpp.

References llvm::MachineInstrBuilder::addConstantPoolIndex(), llvm::MachineInstrBuilder::addImm(), llvm::bit_width(), llvm::BuildMI(), llvm::CallingConv::C, llvm::get(), llvm::MachineInstrBuilder::getInstr(), llvm::Type::getInt32Ty(), isImmMskBitp(), isImmU16(), isImmU6(), MBB, MI, and N.

◆ loadRegFromStackSlot()

void XCoreInstrInfo::loadRegFromStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		Register	DestReg,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI,
		Register	VReg,
		MachineInstr::MIFlag	Flags = MachineInstr::NoFlags ) const

override

Definition at line 376 of file XCoreInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::BuildMI(), DL, llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), I, MBB, llvm::MachineMemOperand::MOLoad, and TRI.

◆ removeBranch()

unsigned XCoreInstrInfo::removeBranch	(	MachineBasicBlock &	MBB,
		int *	BytesRemoved = nullptr ) const

override

Definition at line 302 of file XCoreInstrInfo.cpp.

References assert(), I, IsBRU(), IsCondBranch(), and MBB.

◆ reverseBranchCondition()

bool XCoreInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > & Cond ) const

override

Definition at line 398 of file XCoreInstrInfo.cpp.

References assert(), Cond, llvm::getImm(), and GetOppositeBranchCondition().

◆ storeRegToStackSlot()

void XCoreInstrInfo::storeRegToStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		Register	SrcReg,
		bool	isKill,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI,
		Register	VReg,
		MachineInstr::MIFlag	Flags = MachineInstr::NoFlags ) const

override

Definition at line 355 of file XCoreInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), I, MBB, llvm::MachineMemOperand::MOStore, and TRI.

The documentation for this class was generated from the following files:

lib/Target/XCore/XCoreInstrInfo.h
lib/Target/XCore/XCoreInstrInfo.cpp

Public Member Functions

Detailed Description

Constructor & Destructor Documentation

◆ XCoreInstrInfo()

Member Function Documentation

◆ analyzeBranch()

◆ copyPhysReg()

◆ getRegisterInfo()

◆ insertBranch()

◆ isLoadFromStackSlot()

◆ isStoreToStackSlot()

◆ loadImmediate()

◆ loadRegFromStackSlot()

◆ removeBranch()

◆ reverseBranchCondition()

◆ storeRegToStackSlot()