LLVM  14.0.0git
XCoreInstrInfo.cpp
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1 //===-- XCoreInstrInfo.cpp - XCore Instruction Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the XCore implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "XCoreInstrInfo.h"
14 #include "XCore.h"
16 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/IR/Constants.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/TargetRegistry.h"
25 #include "llvm/Support/Debug.h"
27 
28 using namespace llvm;
29 
30 #define GET_INSTRINFO_CTOR_DTOR
31 #include "XCoreGenInstrInfo.inc"
32 
33 namespace llvm {
34 namespace XCore {
35 
36  // XCore Condition Codes
37  enum CondCode {
41  };
42 }
43 }
44 
45 // Pin the vtable to this file.
46 void XCoreInstrInfo::anchor() {}
47 
49  : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
50  RI() {
51 }
52 
53 static bool isZeroImm(const MachineOperand &op) {
54  return op.isImm() && op.getImm() == 0;
55 }
56 
57 /// isLoadFromStackSlot - If the specified machine instruction is a direct
58 /// load from a stack slot, return the virtual or physical register number of
59 /// the destination along with the FrameIndex of the loaded stack slot. If
60 /// not, return 0. This predicate must return 0 if the instruction has
61 /// any side effects other than loading from the stack slot.
63  int &FrameIndex) const {
64  int Opcode = MI.getOpcode();
65  if (Opcode == XCore::LDWFI)
66  {
67  if ((MI.getOperand(1).isFI()) && // is a stack slot
68  (MI.getOperand(2).isImm()) && // the imm is zero
69  (isZeroImm(MI.getOperand(2)))) {
70  FrameIndex = MI.getOperand(1).getIndex();
71  return MI.getOperand(0).getReg();
72  }
73  }
74  return 0;
75 }
76 
77  /// isStoreToStackSlot - If the specified machine instruction is a direct
78  /// store to a stack slot, return the virtual or physical register number of
79  /// the source reg along with the FrameIndex of the loaded stack slot. If
80  /// not, return 0. This predicate must return 0 if the instruction has
81  /// any side effects other than storing to the stack slot.
83  int &FrameIndex) const {
84  int Opcode = MI.getOpcode();
85  if (Opcode == XCore::STWFI)
86  {
87  if ((MI.getOperand(1).isFI()) && // is a stack slot
88  (MI.getOperand(2).isImm()) && // the imm is zero
89  (isZeroImm(MI.getOperand(2)))) {
90  FrameIndex = MI.getOperand(1).getIndex();
91  return MI.getOperand(0).getReg();
92  }
93  }
94  return 0;
95 }
96 
97 //===----------------------------------------------------------------------===//
98 // Branch Analysis
99 //===----------------------------------------------------------------------===//
100 
101 static inline bool IsBRU(unsigned BrOpc) {
102  return BrOpc == XCore::BRFU_u6
103  || BrOpc == XCore::BRFU_lu6
104  || BrOpc == XCore::BRBU_u6
105  || BrOpc == XCore::BRBU_lu6;
106 }
107 
108 static inline bool IsBRT(unsigned BrOpc) {
109  return BrOpc == XCore::BRFT_ru6
110  || BrOpc == XCore::BRFT_lru6
111  || BrOpc == XCore::BRBT_ru6
112  || BrOpc == XCore::BRBT_lru6;
113 }
114 
115 static inline bool IsBRF(unsigned BrOpc) {
116  return BrOpc == XCore::BRFF_ru6
117  || BrOpc == XCore::BRFF_lru6
118  || BrOpc == XCore::BRBF_ru6
119  || BrOpc == XCore::BRBF_lru6;
120 }
121 
122 static inline bool IsCondBranch(unsigned BrOpc) {
123  return IsBRF(BrOpc) || IsBRT(BrOpc);
124 }
125 
126 static inline bool IsBR_JT(unsigned BrOpc) {
127  return BrOpc == XCore::BR_JT
128  || BrOpc == XCore::BR_JT32;
129 }
130 
131 /// GetCondFromBranchOpc - Return the XCore CC that matches
132 /// the correspondent Branch instruction opcode.
133 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
134 {
135  if (IsBRT(BrOpc)) {
136  return XCore::COND_TRUE;
137  } else if (IsBRF(BrOpc)) {
138  return XCore::COND_FALSE;
139  } else {
140  return XCore::COND_INVALID;
141  }
142 }
143 
144 /// GetCondBranchFromCond - Return the Branch instruction
145 /// opcode that matches the cc.
146 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
147 {
148  switch (CC) {
149  default: llvm_unreachable("Illegal condition code!");
150  case XCore::COND_TRUE : return XCore::BRFT_lru6;
151  case XCore::COND_FALSE : return XCore::BRFF_lru6;
152  }
153 }
154 
155 /// GetOppositeBranchCondition - Return the inverse of the specified
156 /// condition, e.g. turning COND_E to COND_NE.
158 {
159  switch (CC) {
160  default: llvm_unreachable("Illegal condition code!");
161  case XCore::COND_TRUE : return XCore::COND_FALSE;
162  case XCore::COND_FALSE : return XCore::COND_TRUE;
163  }
164 }
165 
166 /// analyzeBranch - Analyze the branching code at the end of MBB, returning
167 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
168 /// implemented for a target). Upon success, this returns false and returns
169 /// with the following information in various cases:
170 ///
171 /// 1. If this block ends with no branches (it just falls through to its succ)
172 /// just return false, leaving TBB/FBB null.
173 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
174 /// the destination block.
175 /// 3. If this block ends with an conditional branch and it falls through to
176 /// an successor block, it sets TBB to be the branch destination block and a
177 /// list of operands that evaluate the condition. These
178 /// operands can be passed to other TargetInstrInfo methods to create new
179 /// branches.
180 /// 4. If this block ends with an conditional branch and an unconditional
181 /// block, it returns the 'true' destination in TBB, the 'false' destination
182 /// in FBB, and a list of operands that evaluate the condition. These
183 /// operands can be passed to other TargetInstrInfo methods to create new
184 /// branches.
185 ///
186 /// Note that removeBranch and insertBranch must be implemented to support
187 /// cases where this method returns success.
188 ///
190  MachineBasicBlock *&TBB,
191  MachineBasicBlock *&FBB,
193  bool AllowModify) const {
194  // If the block has no terminators, it just falls into the block after it.
196  if (I == MBB.end())
197  return false;
198 
199  if (!isUnpredicatedTerminator(*I))
200  return false;
201 
202  // Get the last instruction in the block.
203  MachineInstr *LastInst = &*I;
204 
205  // If there is only one terminator instruction, process it.
206  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
207  if (IsBRU(LastInst->getOpcode())) {
208  TBB = LastInst->getOperand(0).getMBB();
209  return false;
210  }
211 
212  XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
213  if (BranchCode == XCore::COND_INVALID)
214  return true; // Can't handle indirect branch.
215 
216  // Conditional branch
217  // Block ends with fall-through condbranch.
218 
219  TBB = LastInst->getOperand(1).getMBB();
220  Cond.push_back(MachineOperand::CreateImm(BranchCode));
221  Cond.push_back(LastInst->getOperand(0));
222  return false;
223  }
224 
225  // Get the instruction before it if it's a terminator.
226  MachineInstr *SecondLastInst = &*I;
227 
228  // If there are three terminators, we don't know what sort of block this is.
229  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
230  return true;
231 
232  unsigned SecondLastOpc = SecondLastInst->getOpcode();
233  XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
234 
235  // If the block ends with conditional branch followed by unconditional,
236  // handle it.
237  if (BranchCode != XCore::COND_INVALID
238  && IsBRU(LastInst->getOpcode())) {
239 
240  TBB = SecondLastInst->getOperand(1).getMBB();
241  Cond.push_back(MachineOperand::CreateImm(BranchCode));
242  Cond.push_back(SecondLastInst->getOperand(0));
243 
244  FBB = LastInst->getOperand(0).getMBB();
245  return false;
246  }
247 
248  // If the block ends with two unconditional branches, handle it. The second
249  // one is not executed, so remove it.
250  if (IsBRU(SecondLastInst->getOpcode()) &&
251  IsBRU(LastInst->getOpcode())) {
252  TBB = SecondLastInst->getOperand(0).getMBB();
253  I = LastInst;
254  if (AllowModify)
255  I->eraseFromParent();
256  return false;
257  }
258 
259  // Likewise if it ends with a branch table followed by an unconditional branch.
260  if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) {
261  I = LastInst;
262  if (AllowModify)
263  I->eraseFromParent();
264  return true;
265  }
266 
267  // Otherwise, can't handle this.
268  return true;
269 }
270 
272  MachineBasicBlock *TBB,
273  MachineBasicBlock *FBB,
275  const DebugLoc &DL,
276  int *BytesAdded) const {
277  // Shouldn't be a fall through.
278  assert(TBB && "insertBranch must not be told to insert a fallthrough");
279  assert((Cond.size() == 2 || Cond.size() == 0) &&
280  "Unexpected number of components!");
281  assert(!BytesAdded && "code size not handled");
282 
283  if (!FBB) { // One way branch.
284  if (Cond.empty()) {
285  // Unconditional branch
286  BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
287  } else {
288  // Conditional branch.
289  unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
290  BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
291  .addMBB(TBB);
292  }
293  return 1;
294  }
295 
296  // Two-way Conditional branch.
297  assert(Cond.size() == 2 && "Unexpected number of components!");
298  unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
299  BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
300  .addMBB(TBB);
301  BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
302  return 2;
303 }
304 
305 unsigned
307  assert(!BytesRemoved && "code size not handled");
308 
310  if (I == MBB.end())
311  return 0;
312 
313  if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))
314  return 0;
315 
316  // Remove the branch.
317  I->eraseFromParent();
318 
319  I = MBB.end();
320 
321  if (I == MBB.begin()) return 1;
322  --I;
323  if (!IsCondBranch(I->getOpcode()))
324  return 1;
325 
326  // Remove the branch.
327  I->eraseFromParent();
328  return 2;
329 }
330 
333  const DebugLoc &DL, MCRegister DestReg,
334  MCRegister SrcReg, bool KillSrc) const {
335  bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
336  bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);
337 
338  if (GRDest && GRSrc) {
339  BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
340  .addReg(SrcReg, getKillRegState(KillSrc))
341  .addImm(0);
342  return;
343  }
344 
345  if (GRDest && SrcReg == XCore::SP) {
346  BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
347  return;
348  }
349 
350  if (DestReg == XCore::SP && GRSrc) {
351  BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
352  .addReg(SrcReg, getKillRegState(KillSrc));
353  return;
354  }
355  llvm_unreachable("Impossible reg-to-reg copy");
356 }
357 
360  Register SrcReg, bool isKill,
361  int FrameIndex,
362  const TargetRegisterClass *RC,
363  const TargetRegisterInfo *TRI) const
364 {
365  DebugLoc DL;
366  if (I != MBB.end() && !I->isDebugInstr())
367  DL = I->getDebugLoc();
368  MachineFunction *MF = MBB.getParent();
369  const MachineFrameInfo &MFI = MF->getFrameInfo();
374  BuildMI(MBB, I, DL, get(XCore::STWFI))
375  .addReg(SrcReg, getKillRegState(isKill))
377  .addImm(0)
378  .addMemOperand(MMO);
379 }
380 
383  Register DestReg, int FrameIndex,
384  const TargetRegisterClass *RC,
385  const TargetRegisterInfo *TRI) const
386 {
387  DebugLoc DL;
388  if (I != MBB.end() && !I->isDebugInstr())
389  DL = I->getDebugLoc();
390  MachineFunction *MF = MBB.getParent();
391  const MachineFrameInfo &MFI = MF->getFrameInfo();
396  BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
398  .addImm(0)
399  .addMemOperand(MMO);
400 }
401 
402 bool XCoreInstrInfo::
404  assert((Cond.size() == 2) &&
405  "Invalid XCore branch condition!");
406  Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));
407  return false;
408 }
409 
410 static inline bool isImmU6(unsigned val) {
411  return val < (1 << 6);
412 }
413 
414 static inline bool isImmU16(unsigned val) {
415  return val < (1 << 16);
416 }
417 
418 static bool isImmMskBitp(unsigned val) {
419  if (!isMask_32(val)) {
420  return false;
421  }
422  int N = Log2_32(val) + 1;
423  return (N >= 1 && N <= 8) || N == 16 || N == 24 || N == 32;
424 }
425 
429  unsigned Reg, uint64_t Value) const {
430  DebugLoc dl;
431  if (MI != MBB.end() && !MI->isDebugInstr())
432  dl = MI->getDebugLoc();
433  if (isImmMskBitp(Value)) {
434  int N = Log2_32(Value) + 1;
435  return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg)
436  .addImm(N)
437  .getInstr();
438  }
439  if (isImmU16(Value)) {
440  int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
441  return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr();
442  }
444  const Constant *C = ConstantInt::get(
446  unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align(4));
447  return BuildMI(MBB, MI, dl, get(XCore::LDWCP_lru6), Reg)
449  .getInstr();
450 }
isImmMskBitp
static bool isImmMskBitp(unsigned val)
Definition: XCoreInstrInfo.cpp:418
llvm::XCoreInstrInfo::loadImmediate
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
Definition: XCoreInstrInfo.cpp:426
GetOppositeBranchCondition
static XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified condition, e.g.
Definition: XCoreInstrInfo.cpp:157
GetCondFromBranchOpc
static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
GetCondFromBranchOpc - Return the XCore CC that matches the correspondent Branch instruction opcode.
Definition: XCoreInstrInfo.cpp:133
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::XCoreInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: XCoreInstrInfo.cpp:358
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
IsBRU
static bool IsBRU(unsigned BrOpc)
Definition: XCoreInstrInfo.cpp:101
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:946
llvm::XCoreInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: XCoreInstrInfo.cpp:331
XCore.h
llvm::XCoreInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
analyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
Definition: XCoreInstrInfo.cpp:189
op
#define op(i)
IsBRF
static bool IsBRF(unsigned BrOpc)
Definition: XCoreInstrInfo.cpp:115
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:431
ErrorHandling.h
llvm::XCoreInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
Definition: XCoreInstrInfo.cpp:82
llvm::ConstantPool
Definition: ConstantPools.h:43
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:321
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::XCoreInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: XCoreInstrInfo.cpp:306
STLExtras.h
llvm::XCore::CondCode
CondCode
Definition: XCoreInstrInfo.cpp:37
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
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static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:241
isImmU6
static bool isImmU6(unsigned val)
Definition: XCoreInstrInfo.cpp:410
llvm::XCoreInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: XCoreInstrInfo.cpp:271
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
GetCondBranchFromCond
static unsigned GetCondBranchFromCond(XCore::CondCode CC)
GetCondBranchFromCond - Return the Branch instruction opcode that matches the cc.
Definition: XCoreInstrInfo.cpp:146
Constants.h
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:773
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
MCContext.h
XCoreInstrInfo.h
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:596
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MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
XCoreMachineFunctionInfo.h
llvm::ConstantInt::get
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:925
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::XCoreInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: XCoreInstrInfo.cpp:381
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
val
The initial backend is deliberately restricted to z10 We should add support for later architectures at some point If an asm ties an i32 r result to an i64 the input will be treated as an leaving the upper bits uninitialised For i64 store i32 val
Definition: README.txt:15
llvm::XCoreInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
Definition: XCoreInstrInfo.cpp:62
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:453
llvm::XCore::COND_INVALID
@ COND_INVALID
Definition: XCoreInstrInfo.cpp:40
llvm::MachineConstantPool
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
Definition: MachineConstantPool.h:117
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:467
MachineConstantPool.h
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:266
llvm::MachineFunction::getConstantPool
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
Definition: MachineFunction.h:666
assert
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llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:650
IsCondBranch
static bool IsCondBranch(unsigned BrOpc)
Definition: XCoreInstrInfo.cpp:122
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::isMask_32
constexpr bool isMask_32(uint32_t Value)
Return true if the argument is a non-empty sequence of ones starting at the least significant bit wit...
Definition: MathExtras.h:467
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:135
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:600
llvm::XCore::COND_TRUE
@ COND_TRUE
Definition: XCoreInstrInfo.cpp:38
isImmU16
static bool isImmU16(unsigned val)
Definition: XCoreInstrInfo.cpp:414
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
MachineFrameInfo.h
llvm::MachineInstrBuilder::addConstantPoolIndex
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:158
Function.h
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:137
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
IsBR_JT
static bool IsBR_JT(unsigned BrOpc)
Definition: XCoreInstrInfo.cpp:126
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1008
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
llvm::XCore::COND_FALSE
@ COND_FALSE
Definition: XCoreInstrInfo.cpp:39
isZeroImm
static bool isZeroImm(const MachineOperand &op)
Definition: XCoreInstrInfo.cpp:53
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
XCoreGenInstrInfo
IsBRT
static bool IsBRT(unsigned BrOpc)
Definition: XCoreInstrInfo.cpp:108
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::XCoreInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: XCoreInstrInfo.cpp:403
llvm::MachineInstrBundleIterator< MachineInstr >
TargetRegistry.h
llvm::XCoreInstrInfo::XCoreInstrInfo
XCoreInstrInfo()
Definition: XCoreInstrInfo.cpp:48
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::XCoreISD::BR_JT32
@ BR_JT32
Definition: XCoreISelLowering.h:74
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:572
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24