17#ifndef LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
18#define LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
26class MachineRegisterInfo;
51 if (UnifiedVGPRFile) {
64 return std::min(ST.getOccupancyWithNumSGPRs(
getSGPRNum()),
65 ST.getOccupancyWithNumVGPRs(
getVGPRNum(ST.hasGFX90AInsts())));
78 unsigned MaxOccupancy = std::numeric_limits<unsigned>::max())
const;
104 Res.Value[
I] = std::max(P1.Value[
I], P2.Value[
I]);
196 const LiveIntervals &LIS,
197 const MachineRegisterInfo &
MRI);
200 const LiveIntervals &LIS,
201 const MachineRegisterInfo &
MRI);
208template <
typename Range>
209DenseMap<MachineInstr*, GCNRPTracker::LiveRegSet>
211 std::vector<SlotIndex> Indexes;
212 Indexes.reserve(std::distance(R.begin(), R.end()));
215 auto SI = SII.getInstructionIndex(*
I);
216 Indexes.push_back(After ?
SI.getDeadSlot() :
SI.getBaseIndex());
223 for (
unsigned I = 0,
E =
MRI.getNumVirtRegs();
I !=
E; ++
I) {
229 if (!LI.findIndexesLiveAt(Indexes, std::back_inserter(LiveIdxs)))
231 if (!LI.hasSubRanges()) {
232 for (
auto SI : LiveIdxs)
233 LiveRegMap[SII.getInstructionFromIndex(
SI)][
Reg] =
234 MRI.getMaxLaneMaskForVReg(
Reg);
236 for (
const auto &S : LI.subranges()) {
239 S.findIndexesLiveAt(LiveIdxs, std::back_inserter(SRLiveIdxs));
240 for (
auto SI : SRLiveIdxs)
241 LiveRegMap[SII.getInstructionFromIndex(
SI)][
Reg] |= S.LaneMask;
250 MI.getParent()->getParent()->getRegInfo());
256 MI.getParent()->getParent()->getRegInfo());
259template <
typename Range>
263 for (
const auto &RM : LiveRegs)
271Printable
print(
const GCNRegPressure &RP,
const GCNSubtarget *ST =
nullptr);
274 const MachineRegisterInfo &
MRI);
278 const TargetRegisterInfo *
TRI);
unsigned const MachineRegisterInfo * MRI
static const Function * getParent(const Value *V)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
AMD GCN specific subclass of TargetSubtarget.
unsigned const TargetRegisterInfo * TRI
MachineBasicBlock::const_iterator getNext() const
GCNDownwardRPTracker(const LiveIntervals &LIS_)
bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs=nullptr)
const decltype(LiveRegs) & getLiveRegs() const
const MachineInstr * LastTrackedMI
decltype(LiveRegs) moveLiveRegs()
GCNRegPressure CurPressure
DenseMap< unsigned, LaneBitmask > LiveRegSet
GCNRPTracker(const LiveIntervals &LIS_)
GCNRegPressure MaxPressure
void reset(const MachineInstr &MI, const LiveRegSet *LiveRegsCopy, bool After)
const MachineInstr * getLastTrackedMI() const
decltype(MaxPressure) moveMaxPressure()
const MachineRegisterInfo * MRI
const LiveIntervals & LIS
GCNUpwardRPTracker(const LiveIntervals &LIS_)
void reset(const MachineInstr &MI, const LiveRegSet *LiveRegs=nullptr)
void recede(const MachineInstr &MI)
Module * getParent()
Get the module that this global value is contained inside of...
bool hasInterval(Register Reg) const
SlotIndexes * getSlotIndexes() const
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
LiveInterval & getInterval(Register Reg)
A set of live virtual registers and physical register units.
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Simple wrapper around std::function<void(raw_ostream&)>.
Wrapper class representing virtual and physical registers.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
LLVM Value Representation.
This is an optimization pass for GlobalISel generic memory operations.
bool isEqual(const GCNRPTracker::LiveRegSet &S1, const GCNRPTracker::LiveRegSet &S2)
GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI, Range &&LiveRegs)
GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
GCNRPTracker::LiveRegSet getLiveRegsAfter(const MachineInstr &MI, const LiveIntervals &LIS)
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
void sort(IteratorTy Start, IteratorTy End)
LaneBitmask getLiveLaneMask(unsigned Reg, SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
Printable reportMismatch(const GCNRPTracker::LiveRegSet &LISLR, const GCNRPTracker::LiveRegSet &TrackedL, const TargetRegisterInfo *TRI)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
DenseMap< MachineInstr *, GCNRPTracker::LiveRegSet > getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS)
creates a map MachineInstr -> LiveRegSet R - range of iterators on instructions After - upon entry or...
GCNRPTracker::LiveRegSet getLiveRegsBefore(const MachineInstr &MI, const LiveIntervals &LIS)
bool operator!=(const GCNRegPressure &O) const
unsigned getVGPRTuplesWeight() const
unsigned getOccupancy(const GCNSubtarget &ST) const
unsigned getVGPRNum(bool UnifiedVGPRFile) const
friend GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
void inc(unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask, const MachineRegisterInfo &MRI)
bool higherOccupancy(const GCNSubtarget &ST, const GCNRegPressure &O) const
unsigned getAGPRNum() const
unsigned getSGPRNum() const
bool less(const GCNSubtarget &ST, const GCNRegPressure &O, unsigned MaxOccupancy=std::numeric_limits< unsigned >::max()) const
unsigned getSGPRTuplesWeight() const
bool operator==(const GCNRegPressure &O) const
friend Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST)
static constexpr LaneBitmask getNone()