LLVM 19.0.0git
XtensaFrameLowering.cpp
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1//===- XtensaFrameLowering.cpp - Xtensa Frame Information -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Xtensa implementation of TargetFrameLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "XtensaFrameLowering.h"
14#include "XtensaInstrInfo.h"
15#include "XtensaSubtarget.h"
21#include "llvm/IR/Function.h"
22
23using namespace llvm;
24
26 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(4), 0,
27 Align(4)),
28 TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {}
29
31 const MachineFrameInfo &MFI = MF.getFrameInfo();
34}
35
37 MachineBasicBlock &MBB) const {
38 assert(&MBB == &MF.front() && "Shrink-wrapping not yet implemented");
41 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
42 MCRegister SP = Xtensa::SP;
44 MachineModuleInfo &MMI = MF.getMMI();
46
47 // First, compute final stack size.
48 uint64_t StackSize = MFI.getStackSize();
49 uint64_t PrevStackSize = StackSize;
50
51 // Round up StackSize to 16*N
52 StackSize += (16 - StackSize) & 0xf;
53
54 // No need to allocate space on the stack.
55 if (StackSize == 0 && !MFI.adjustsStack())
56 return;
57
58 // Adjust stack.
59 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
60
61 // emit ".cfi_def_cfa_offset StackSize"
62 unsigned CFIIndex =
63 MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize));
64 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
65 .addCFIIndex(CFIIndex);
66
67 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
68
69 if (!CSI.empty()) {
70 // Find the instruction past the last instruction that saves a
71 // callee-saved register to the stack. The callee-saved store
72 // instructions are placed at the begin of basic block, so
73 // iterate over instruction sequence and check that
74 // save instructions are placed correctly.
75 for (unsigned i = 0, e = CSI.size(); i < e; ++i) {
76#ifndef NDEBUG
77 const CalleeSavedInfo &Info = CSI[i];
78 int FI = Info.getFrameIdx();
79 int StoreFI = 0;
80
81 // Checking that the instruction is exactly as expected
82 bool IsStoreInst = false;
83 if (MBBI->getOpcode() == TargetOpcode::COPY && Info.isSpilledToReg()) {
84 Register DstReg = MBBI->getOperand(0).getReg();
85 Register Reg = MBBI->getOperand(1).getReg();
86 IsStoreInst = (Info.getDstReg() == DstReg) && (Info.getReg() == Reg);
87 } else {
88 Register Reg = TII.isStoreToStackSlot(*MBBI, StoreFI);
89 IsStoreInst = (Reg == Info.getReg()) && (StoreFI == FI);
90 }
91 assert(IsStoreInst &&
92 "Unexpected callee-saved register store instruction");
93#endif
94 ++MBBI;
95 }
96
97 // Iterate over list of callee-saved registers and emit .cfi_offset
98 // directives.
99 for (const auto &I : CSI) {
100 int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
101 Register Reg = I.getReg();
102
103 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
104 nullptr, MRI->getDwarfRegNum(Reg, 1), Offset));
105 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
106 .addCFIIndex(CFIIndex);
107 }
108 }
109
110 // if framepointer enabled, set it to point to the stack pointer.
111 if (hasFP(MF)) {
112 // Insert instruction "move $fp, $sp" at this location.
113 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::OR), FP)
114 .addReg(SP)
115 .addReg(SP)
117
118 // emit ".cfi_def_cfa_register $fp"
120 nullptr, MRI->getDwarfRegNum(FP, true)));
121 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
122 .addCFIIndex(CFIIndex);
123 }
124
125 if (StackSize != PrevStackSize) {
126 MFI.setStackSize(StackSize);
127
128 for (int i = MFI.getObjectIndexBegin(); i < MFI.getObjectIndexEnd(); i++) {
129 if (!MFI.isDeadObjectIndex(i)) {
130 int64_t SPOffset = MFI.getObjectOffset(i);
131
132 if (SPOffset < 0)
133 MFI.setObjectOffset(i, SPOffset - StackSize + PrevStackSize);
134 }
135 }
136 }
137}
138
140 MachineBasicBlock &MBB) const {
142 MachineFrameInfo &MFI = MF.getFrameInfo();
143 DebugLoc DL = MBBI->getDebugLoc();
144 MCRegister SP = Xtensa::SP;
145 MCRegister FP = TRI->getFrameRegister(MF);
146
147 // if framepointer enabled, restore the stack pointer.
148 if (hasFP(MF)) {
149 // We should place restore stack pointer instruction just before
150 // sequence of instructions which restores callee-saved registers.
151 // This sequence is placed at the end of the basic block,
152 // so we should find first instruction of the sequence.
154
155 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
156
157 // Find the first instruction at the end that restores a callee-saved
158 // register.
159 for (unsigned i = 0, e = CSI.size(); i < e; ++i) {
160 --I;
161#ifndef NDEBUG
162 const CalleeSavedInfo &Info = CSI[i];
163 int FI = Info.getFrameIdx();
164 int LoadFI = 0;
165
166 // Checking that the instruction is exactly as expected
167 bool IsRestoreInst = false;
168 if (I->getOpcode() == TargetOpcode::COPY && Info.isSpilledToReg()) {
169 Register Reg = I->getOperand(0).getReg();
170 Register DstReg = I->getOperand(1).getReg();
171 IsRestoreInst = (Info.getDstReg() == DstReg) && (Info.getReg() == Reg);
172 } else {
173 Register Reg = TII.isLoadFromStackSlot(*I, LoadFI);
174 IsRestoreInst = (Info.getReg() == Reg) && (LoadFI == FI);
175 }
176 assert(IsRestoreInst &&
177 "Unexpected callee-saved register restore instruction");
178#endif
179 }
180
181 BuildMI(MBB, I, DL, TII.get(Xtensa::OR), SP).addReg(FP).addReg(FP);
182 }
183
184 // Get the number of bytes from FrameInfo
185 uint64_t StackSize = MFI.getStackSize();
186
187 if (!StackSize)
188 return;
189
190 // Adjust stack.
191 TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
192}
193
198 MachineBasicBlock &EntryBlock = *(MF->begin());
199
200 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
201 // Add the callee-saved register as live-in. Do not add if the register is
202 // A0 and return address is taken, because it will be implemented in
203 // method XtensaTargetLowering::LowerRETURNADDR.
204 // It's killed at the spill, unless the register is RA and return address
205 // is taken.
206 Register Reg = CSI[i].getReg();
207 bool IsA0AndRetAddrIsTaken =
208 (Reg == Xtensa::A0) && MF->getFrameInfo().isReturnAddressTaken();
209 if (!IsA0AndRetAddrIsTaken)
210 EntryBlock.addLiveIn(Reg);
211
212 // Insert the spill to the stack frame.
213 bool IsKill = !IsA0AndRetAddrIsTaken;
214 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
215 TII.storeRegToStackSlot(EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(),
216 RC, TRI, Register());
217 }
218
219 return true;
220}
221
226}
227
228// Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions
232 const XtensaInstrInfo &TII =
233 *static_cast<const XtensaInstrInfo *>(MF.getSubtarget().getInstrInfo());
234
235 if (!hasReservedCallFrame(MF)) {
236 int64_t Amount = I->getOperand(0).getImm();
237
238 if (I->getOpcode() == Xtensa::ADJCALLSTACKDOWN)
239 Amount = -Amount;
240
241 TII.adjustStackPtr(Xtensa::SP, Amount, MBB, I);
242 }
243
244 return MBB.erase(I);
245}
246
248 BitVector &SavedRegs,
249 RegScavenger *RS) const {
250 unsigned FP = TRI->getFrameRegister(MF);
251
253
254 // Mark $fp as used if function has dedicated frame pointer.
255 if (hasFP(MF))
256 SavedRegs.set(FP);
257}
258
260 MachineFunction &MF, RegScavenger *RS) const {
261 // Set scavenging frame index if necessary.
262 MachineFrameInfo &MFI = MF.getFrameInfo();
263 uint64_t MaxSPOffset = MFI.estimateStackSize(MF);
264
265 if (isInt<12>(MaxSPOffset))
266 return;
267
268 const TargetRegisterClass &RC = Xtensa::ARRegClass;
269 unsigned Size = TRI->getSpillSize(RC);
270 Align Alignment = TRI->getSpillAlign(RC);
271 int FI = MF.getFrameInfo().CreateStackObject(Size, Alignment, false);
272
274}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
uint64_t Size
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
BitVector & set()
Definition: BitVector.h:351
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
A debug info location.
Definition: DebugLoc.h:33
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:565
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:600
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:573
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:414
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
bool isReturnAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void setStackSize(uint64_t Size)
Set the size of the stack.
int getObjectIndexBegin() const
Return the minimum frame object index.
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
unsigned addFrameInst(const MCCFIInstruction &Inst)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MachineModuleInfo & getMMI() const
const MachineBasicBlock & front() const
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
This class contains meta information specific to a module.
const MCContext & getContext() const
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Information about stack frame layout on the target.
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
TargetOptions Options
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetInstrInfo * getInstrInfo() const
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
void emitPrologue(MachineFunction &, MachineBasicBlock &) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
XtensaFrameLowering(const XtensaSubtarget &STI)
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
Adjust SP by Amount bytes.
Register getFrameRegister(const MachineFunction &MF) const override
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39