LLVM 20.0.0git
AVRFrameLowering.cpp
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1//===-- AVRFrameLowering.cpp - AVR Frame Information ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AVR implementation of TargetFrameLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AVRFrameLowering.h"
14
15#include "AVR.h"
16#include "AVRInstrInfo.h"
18#include "AVRTargetMachine.h"
20
26#include "llvm/IR/Function.h"
27
28namespace llvm {
29
31 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(1), -2) {}
32
34 const MachineFunction &MF) const {
35 // Always simplify call frame pseudo instructions, even when
36 // hasReservedCallFrame is false.
37 return true;
38}
39
41 // Reserve call frame memory in function prologue under the following
42 // conditions:
43 // - Y pointer is reserved to be the frame pointer.
44 // - The function does not contain variable sized objects.
45
46 const MachineFrameInfo &MFI = MF.getFrameInfo();
47 return hasFP(MF) && !MFI.hasVarSizedObjects();
48}
49
51 MachineBasicBlock &MBB) const {
53 DebugLoc DL = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
54 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
55 const AVRInstrInfo &TII = *STI.getInstrInfo();
58 bool HasFP = hasFP(MF);
59
60 // Interrupt handlers re-enable interrupts in function entry.
61 if (AFI->isInterruptHandler()) {
62 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs))
63 .addImm(0x07)
65 }
66
67 // Emit special prologue code to save R1, R0 and SREG in interrupt/signal
68 // handlers before saving any other registers.
69 if (AFI->isInterruptOrSignalHandler()) {
70 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
73
74 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), STI.getTmpRegister())
75 .addImm(STI.getIORegSREG())
77 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
80 if (!MRI.reg_empty(STI.getZeroRegister())) {
81 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
84 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr))
89 }
90 }
91
92 // Early exit if the frame pointer is not needed in this function.
93 if (!HasFP) {
94 return;
95 }
96
97 const MachineFrameInfo &MFI = MF.getFrameInfo();
98 unsigned FrameSize = MFI.getStackSize() - AFI->getCalleeSavedFrameSize();
99
100 // Skip the callee-saved push instructions.
101 while (
102 (MBBI != MBB.end()) && MBBI->getFlag(MachineInstr::FrameSetup) &&
103 (MBBI->getOpcode() == AVR::PUSHRr || MBBI->getOpcode() == AVR::PUSHWRr)) {
104 ++MBBI;
105 }
106
107 // Update Y with the new base value.
108 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28)
109 .addReg(AVR::SP)
111
112 // Mark the FramePtr as live-in in every block except the entry.
113 for (MachineBasicBlock &MBBJ : llvm::drop_begin(MF)) {
114 MBBJ.addLiveIn(AVR::R29R28);
115 }
116
117 if (!FrameSize) {
118 return;
119 }
120
121 // Reserve the necessary frame memory by doing FP -= <size>.
122 unsigned Opcode = (isUInt<6>(FrameSize) && STI.hasADDSUBIW()) ? AVR::SBIWRdK
123 : AVR::SUBIWRdK;
124
125 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
126 .addReg(AVR::R29R28, RegState::Kill)
127 .addImm(FrameSize)
129 // The SREG implicit def is dead.
130 MI->getOperand(3).setIsDead();
131
132 // Write back R29R28 to SP and temporarily disable interrupts.
133 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP)
134 .addReg(AVR::R29R28)
136}
137
140 const MachineRegisterInfo &MRI = MF.getRegInfo();
141
143
144 DebugLoc DL = MBBI->getDebugLoc();
145 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
146 const AVRInstrInfo &TII = *STI.getInstrInfo();
147
148 // Emit special epilogue code to restore R1, R0 and SREG in interrupt/signal
149 // handlers at the very end of the function, just before reti.
150 if (AFI->isInterruptOrSignalHandler()) {
151 if (!MRI.reg_empty(STI.getZeroRegister())) {
152 BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), STI.getZeroRegister());
153 }
154 BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), STI.getTmpRegister());
155 BuildMI(MBB, MBBI, DL, TII.get(AVR::OUTARr))
156 .addImm(STI.getIORegSREG())
158 BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), STI.getTmpRegister());
159 }
160}
161
163 MachineBasicBlock &MBB) const {
165
166 // Early exit if the frame pointer is not needed in this function except for
167 // signal/interrupt handlers where special code generation is required.
168 if (!hasFP(MF) && !AFI->isInterruptOrSignalHandler()) {
169 return;
170 }
171
172 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
173 assert(MBBI->getDesc().isReturn() &&
174 "Can only insert epilog into returning blocks");
175
176 DebugLoc DL = MBBI->getDebugLoc();
177 const MachineFrameInfo &MFI = MF.getFrameInfo();
178 unsigned FrameSize = MFI.getStackSize() - AFI->getCalleeSavedFrameSize();
179 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
180 const AVRInstrInfo &TII = *STI.getInstrInfo();
181
182 // Early exit if there is no need to restore the frame pointer.
183 if (!FrameSize && !MF.getFrameInfo().hasVarSizedObjects()) {
185 return;
186 }
187
188 // Skip the callee-saved pop instructions.
189 while (MBBI != MBB.begin()) {
190 MachineBasicBlock::iterator PI = std::prev(MBBI);
191 int Opc = PI->getOpcode();
192
193 if (Opc != AVR::POPRd && Opc != AVR::POPWRd && !PI->isTerminator()) {
194 break;
195 }
196
197 --MBBI;
198 }
199
200 if (FrameSize) {
201 unsigned Opcode;
202
203 // Select the optimal opcode depending on how big it is.
204 if (isUInt<6>(FrameSize) && STI.hasADDSUBIW()) {
205 Opcode = AVR::ADIWRdK;
206 } else {
207 Opcode = AVR::SUBIWRdK;
208 FrameSize = -FrameSize;
209 }
210
211 // Restore the frame pointer by doing FP += <size>.
212 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
213 .addReg(AVR::R29R28, RegState::Kill)
214 .addImm(FrameSize);
215 // The SREG implicit def is dead.
216 MI->getOperand(3).setIsDead();
217 }
218
219 // Write back R29R28 to SP and temporarily disable interrupts.
220 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP)
221 .addReg(AVR::R29R28, RegState::Kill);
222
224}
225
226// Return true if the specified function should have a dedicated frame
227// pointer register. This is true if the function meets any of the following
228// conditions:
229// - a register has been spilled
230// - has allocas
231// - input arguments are passed using the stack
232//
233// Notice that strictly this is not a frame pointer because it contains SP after
234// frame allocation instead of having the original SP in function entry.
237
238 return (FuncInfo->getHasSpills() || FuncInfo->getHasAllocas() ||
239 FuncInfo->getHasStackArgs() ||
241}
242
246 if (CSI.empty()) {
247 return false;
248 }
249
250 unsigned CalleeFrameSize = 0;
251 DebugLoc DL = MBB.findDebugLoc(MI);
252 MachineFunction &MF = *MBB.getParent();
253 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
254 const TargetInstrInfo &TII = *STI.getInstrInfo();
256
257 for (const CalleeSavedInfo &I : llvm::reverse(CSI)) {
258 Register Reg = I.getReg();
259 bool IsNotLiveIn = !MBB.isLiveIn(Reg);
260
261 // Check if Reg is a sub register of a 16-bit livein register, and then
262 // add it to the livein list.
263 if (IsNotLiveIn)
264 for (const auto &LiveIn : MBB.liveins())
265 if (STI.getRegisterInfo()->isSubRegister(LiveIn.PhysReg, Reg)) {
266 IsNotLiveIn = false;
267 MBB.addLiveIn(Reg);
268 break;
269 }
270
271 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
272 "Invalid register size");
273
274 // Add the callee-saved register as live-in only if it is not already a
275 // live-in register, this usually happens with arguments that are passed
276 // through callee-saved registers.
277 if (IsNotLiveIn) {
278 MBB.addLiveIn(Reg);
279 }
280
281 // Do not kill the register when it is an input argument.
282 BuildMI(MBB, MI, DL, TII.get(AVR::PUSHRr))
283 .addReg(Reg, getKillRegState(IsNotLiveIn))
285 ++CalleeFrameSize;
286 }
287
288 AVRFI->setCalleeSavedFrameSize(CalleeFrameSize);
289
290 return true;
291}
292
296 if (CSI.empty()) {
297 return false;
298 }
299
300 DebugLoc DL = MBB.findDebugLoc(MI);
301 const MachineFunction &MF = *MBB.getParent();
302 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
303 const TargetInstrInfo &TII = *STI.getInstrInfo();
304
305 for (const CalleeSavedInfo &CCSI : CSI) {
306 Register Reg = CCSI.getReg();
307
308 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
309 "Invalid register size");
310
311 BuildMI(MBB, MI, DL, TII.get(AVR::POPRd), Reg);
312 }
313
314 return true;
315}
316
317/// Replace pseudo store instructions that pass arguments through the stack with
318/// real instructions.
321 const TargetInstrInfo &TII) {
322 // Iterate through the BB until we hit a call instruction or we reach the end.
323 for (MachineInstr &MI :
325 if (MI.isCall())
326 break;
327
328 unsigned Opcode = MI.getOpcode();
329
330 // Only care of pseudo store instructions where SP is the base pointer.
331 if (Opcode != AVR::STDSPQRr && Opcode != AVR::STDWSPQRr)
332 continue;
333
334 assert(MI.getOperand(0).getReg() == AVR::SP &&
335 "SP is expected as base pointer");
336
337 // Replace this instruction with a regular store. Use Y as the base
338 // pointer since it is guaranteed to contain a copy of SP.
339 unsigned STOpc =
340 (Opcode == AVR::STDWSPQRr) ? AVR::STDWPtrQRr : AVR::STDPtrQRr;
341
342 MI.setDesc(TII.get(STOpc));
343 MI.getOperand(0).setReg(AVR::R31R30);
344 }
345}
346
350 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
351 const AVRInstrInfo &TII = *STI.getInstrInfo();
352
353 if (hasReservedCallFrame(MF)) {
354 return MBB.erase(MI);
355 }
356
357 DebugLoc DL = MI->getDebugLoc();
358 unsigned int Opcode = MI->getOpcode();
359 int Amount = TII.getFrameSize(*MI);
360
361 if (Amount == 0) {
362 return MBB.erase(MI);
363 }
364
365 assert(getStackAlign() == Align(1) && "Unsupported stack alignment");
366
367 if (Opcode == TII.getCallFrameSetupOpcode()) {
368 // Update the stack pointer.
369 // In many cases this can be done far more efficiently by pushing the
370 // relevant values directly to the stack. However, doing that correctly
371 // (in the right order, possibly skipping some empty space for undef
372 // values, etc) is tricky and thus left to be optimized in the future.
373 BuildMI(MBB, MI, DL, TII.get(AVR::SPREAD), AVR::R31R30).addReg(AVR::SP);
374
375 MachineInstr *New =
376 BuildMI(MBB, MI, DL, TII.get(AVR::SUBIWRdK), AVR::R31R30)
377 .addReg(AVR::R31R30, RegState::Kill)
378 .addImm(Amount);
379 New->getOperand(3).setIsDead();
380
381 BuildMI(MBB, MI, DL, TII.get(AVR::SPWRITE), AVR::SP).addReg(AVR::R31R30);
382
383 // Make sure the remaining stack stores are converted to real store
384 // instructions.
386 } else {
387 assert(Opcode == TII.getCallFrameDestroyOpcode());
388
389 // Note that small stack changes could be implemented more efficiently
390 // with a few pop instructions instead of the 8-9 instructions now
391 // required.
392
393 // Select the best opcode to adjust SP based on the offset size.
394 unsigned AddOpcode;
395
396 if (isUInt<6>(Amount) && STI.hasADDSUBIW()) {
397 AddOpcode = AVR::ADIWRdK;
398 } else {
399 AddOpcode = AVR::SUBIWRdK;
400 Amount = -Amount;
401 }
402
403 // Build the instruction sequence.
404 BuildMI(MBB, MI, DL, TII.get(AVR::SPREAD), AVR::R31R30).addReg(AVR::SP);
405
406 MachineInstr *New = BuildMI(MBB, MI, DL, TII.get(AddOpcode), AVR::R31R30)
407 .addReg(AVR::R31R30, RegState::Kill)
408 .addImm(Amount);
409 New->getOperand(3).setIsDead();
410
411 BuildMI(MBB, MI, DL, TII.get(AVR::SPWRITE), AVR::SP)
412 .addReg(AVR::R31R30, RegState::Kill);
413 }
414
415 return MBB.erase(MI);
416}
417
419 BitVector &SavedRegs,
420 RegScavenger *RS) const {
422
423 // If we have a frame pointer, the Y register needs to be saved as well.
424 if (hasFP(MF)) {
425 SavedRegs.set(AVR::R29);
426 SavedRegs.set(AVR::R28);
427 }
428}
429/// The frame analyzer pass.
430///
431/// Scans the function for allocas and used arguments
432/// that are passed through the stack.
434 static char ID;
436
438 const MachineFrameInfo &MFI = MF.getFrameInfo();
440
441 // If there are no fixed frame indexes during this stage it means there
442 // are allocas present in the function.
443 if (MFI.getNumObjects() != MFI.getNumFixedObjects()) {
444 // Check for the type of allocas present in the function. We only care
445 // about fixed size allocas so do not give false positives if only
446 // variable sized allocas are present.
447 for (unsigned i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
448 // Variable sized objects have size 0.
449 if (MFI.getObjectSize(i)) {
450 AFI->setHasAllocas(true);
451 break;
452 }
453 }
454 }
455
456 // If there are fixed frame indexes present, scan the function to see if
457 // they are really being used.
458 if (MFI.getNumFixedObjects() == 0) {
459 return false;
460 }
461
462 // Ok fixed frame indexes present, now scan the function to see if they
463 // are really being used, otherwise we can ignore them.
464 for (const MachineBasicBlock &BB : MF) {
465 for (const MachineInstr &MI : BB) {
466 int Opcode = MI.getOpcode();
467
468 if ((Opcode != AVR::LDDRdPtrQ) && (Opcode != AVR::LDDWRdPtrQ) &&
469 (Opcode != AVR::STDPtrQRr) && (Opcode != AVR::STDWPtrQRr) &&
470 (Opcode != AVR::FRMIDX)) {
471 continue;
472 }
473
474 for (const MachineOperand &MO : MI.operands()) {
475 if (!MO.isFI()) {
476 continue;
477 }
478
479 if (MFI.isFixedObjectIndex(MO.getIndex())) {
480 AFI->setHasStackArgs(true);
481 return false;
482 }
483 }
484 }
485 }
486
487 return false;
488 }
489
490 StringRef getPassName() const override { return "AVR Frame Analyzer"; }
491};
492
493char AVRFrameAnalyzer::ID = 0;
494
495/// Creates instance of the frame analyzer pass.
497
498} // end of namespace llvm
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override
canSimplifyCallFramePseudos - When possible, it's best to simplify the call frame pseudo ops before d...
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:66
Contains AVR-specific information for each MachineFunction.
void setCalleeSavedFrameSize(unsigned Bytes)
bool isInterruptOrSignalHandler() const
Checks if the function is some form of interrupt service routine.
A specific AVR target MCU.
Definition: AVRSubtarget.h:32
Register getTmpRegister() const
Definition: AVRSubtarget.h:91
Register getZeroRegister() const
Definition: AVRSubtarget.h:94
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:42
int getIORegSREG() const
Definition: AVRSubtarget.h:85
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:52
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
BitVector & set()
Definition: BitVector.h:351
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
A debug info location.
Definition: DebugLoc.h:33
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:310
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getNumObjects() const
Return the number of objects.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
unsigned getNumFixedObjects() const
Return the number of fixed objects.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Information about stack frame layout on the target.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
@ Define
Register definition.
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:329
static void fixStackStores(MachineBasicBlock &MBB, MachineBasicBlock::iterator StartMI, const TargetInstrInfo &TII)
Replace pseudo store instructions that pass arguments through the stack with real instructions.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:656
FunctionPass * createAVRFrameAnalyzerPass()
Creates instance of the frame analyzer pass.
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:419
unsigned getKillRegState(bool B)
static void restoreStatusRegister(MachineFunction &MF, MachineBasicBlock &MBB)
The frame analyzer pass.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39